Integrated circuit revision method, device, computer equipment, storage medium and computer program product
By positioning and rewriting logic redundant devices in integrated circuits, the problems of high cost and low efficiency in the prior art are solved, and a more efficient and economical integrated circuit modification is achieved.
Patent Information
- Application Number
- CN202411926788.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-25
- Publication Date
- 2025-04-04
AI Technical Summary
The existing integrated circuit modification method requires the configuration of spare devices in advance, resulting in higher cost and inefficient enough for smaller logic modifications.
By obtaining the layout information of the integrated circuit, determining the information of the logical redundant devices, and rewriting and updating these devices without the need to set up additional spare devices, thereby realizing the revision of the integrated circuit.
Improve the efficiency of integrated circuit revision and reduce the cost of revision design, especially in the case of small logic modifications.
Smart Images
Figure CN119761296A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of integrated circuit layout design, and in particular to an integrated circuit revision method, apparatus, computer equipment, storage medium and computer program product. Background Art
[0002] In recent years, electronic information technology has developed rapidly. Electronic technology, especially integrated circuit semiconductor technology, has become the hub of the information technology era. Integrated circuit technology has been developing rapidly for many years in accordance with Moore's Law. With the development of more complex functions and more advanced processing technologies, higher production costs have been brought about. Bugs are inevitable in complex designs. If the work of fixing bugs cannot be completed in the RTL stage, then ECO [Engineering Change Order] is required to fix bugs through the principle of local logic modification. ECO work is divided into pre-tapeline ECO and post-tapeline ECO. Pre-tapeline ECO mainly costs time, while post-tapeline ECO, at this time the mask has been made, and time and money costs are required, and the latter is often greater.
[0003] In the related technology, there are currently many ways to modify the design after tape-out, such as: using pre-placed spare logic cells [spare cells], using pre-placed dedicated ECO filler cells [ECO filler], using pre-placed dedicated ECO logic cells [ECO logic cells], etc. When choosing a method for modifying the design after tape-out, it is necessary to comprehensively consider the specific needs of the project, the complexity of the design, and the expected cost. Spare logic cells provide flexibility, ECO filler cells help with quick repairs, and dedicated ECO logic cells are functionally targeted.
[0004] However, the current integrated circuit revision method has the following technical problems:
[0005] Existing integrated circuit revision methods require pre-configuration of spare devices, which are then introduced by modifying the metal layer layout wiring. This method is suitable for complex logic modifications and revisions that can withstand higher costs, but often requires smaller logic modifications but higher costs. Summary of the invention
[0006] Based on this, it is necessary to provide an integrated circuit revision method, device, computer equipment, computer-readable storage medium and computer program product that can improve the revision efficiency of integrated circuits and reduce the cost of revision design in response to the above technical problems.
[0007] In a first aspect, the present application provides a method for redesigning an integrated circuit. The method comprises:
[0008] In response to a revision requirement of a target object, obtaining layout information of the target object;
[0009] Determine target device information in the target object according to the layout information, wherein the target device is a logic redundant device;
[0010] rewriting the target device based on the target device information;
[0011] The target object is updated in layout based on the rewritten target device to obtain a revised integrated circuit layout.
[0012] In one embodiment, determining target device information in the target object according to the layout information, wherein the target device is a logic redundant device, comprises:
[0013] If the logic redundant device does not exist in the original layout of the target object, determining the relevant logic devices associated with the revision requirement;
[0014] The layout of the target object is rewritten based on the related logic devices.
[0015] In one embodiment, after updating the layout of the target object based on the rewritten target device to obtain a revised integrated circuit layout, the method further includes:
[0016] Verify the revised integrated circuit layout, including Figure 1 Consistency testing, physical design rule testing, formal verification, and static timing analysis.
[0017] In one embodiment, the verifying the revised integrated circuit layout includes:
[0018] Inputting a test signal to the revised target object based on a preset test logic;
[0019] The stimulus signal returned by the target object is detected to obtain a verification result of the revised integrated circuit layout.
[0020] In one embodiment, in response to a revision requirement of a target object, obtaining layout information of the target object includes:
[0021] Obtaining the revision information;
[0022] The revision information is reversely processed based on a preset back-annotation logic to obtain the physical data that needs to be modified in the original layout of the target object.
[0023] In one embodiment, the method further comprises:
[0024] If there are several optional revision plans for the target object, the multiple revision plans are sorted based on a preset evaluation logic;
[0025] A target revision scheme is determined from the sorted revision schemes.
[0026] In a second aspect, the present application also provides an integrated circuit revision device. The device comprises:
[0027] A revision requirement module, used to obtain layout information of a target object in response to a revision requirement of the target object;
[0028] A device positioning module, used to determine target device information in the target object according to the layout information, wherein the target device is a logic redundant device;
[0029] A device rewriting module, used for rewriting the target device based on the target device information;
[0030] The revision writing module is used to update the layout of the target object based on the rewritten target device to obtain a revised integrated circuit layout.
[0031] In one embodiment, the device positioning module includes:
[0032] A related device module, used for determining the related logic devices associated with the revision requirement if the logic redundant device does not exist in the original layout of the target object;
[0033] A related device rewriting module is used to rewrite the layout of the target object based on the related logic devices.
[0034] In one embodiment, after the revision is written into the module, the method further comprises:
[0035] A revision verification module is used to verify the revised integrated circuit layout, the verification includes: Figure 1 Consistency testing, physical design rule testing, formal verification, and static timing analysis.
[0036] In one embodiment, the revision verification module includes:
[0037] A test signal module, used for inputting a test signal to the revised target object based on a preset test logic;
[0038] The feedback verification module is used to detect the excitation signal returned by the target object to obtain the verification result of the revised integrated circuit layout.
[0039] In one embodiment, the revision requirement module includes:
[0040] A revision trust module, used to obtain the revision information;
[0041] The reverse-annotation data module is used to reversely process the revision information based on a preset reverse-annotation logic to obtain the physical data that needs to be modified in the original layout of the target object.
[0042] In one embodiment, the device further comprises:
[0043] A parallel scheme module, used for sorting the multiple revision schemes based on a preset evaluation logic if there are several optional revision schemes in the target object;
[0044] The parallel screening module is used to determine the target revision scheme from the sorted revision schemes.
[0045] In a third aspect, the present application further provides a computer device, which includes a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the steps in the integrated circuit revision method described in any one of the embodiments in the first aspect are implemented.
[0046] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps in the integrated circuit revision method as described in any one of the embodiments in the first aspect are implemented.
[0047] In a fifth aspect, the present application further provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, the steps in the integrated circuit revision method described in any one of the embodiments in the first aspect are implemented.
[0048] The above-mentioned integrated circuit revision method, device, computer equipment, storage medium and computer program product can achieve the following beneficial effects corresponding to the technical problems in the background technology by deducing the technical features in the claims:
[0049] The present application provides an integrated circuit revision method, including obtaining the layout information of the target object in response to the revision demand of the target object; determining the target device information in the target object according to the layout information, wherein the target device is a logic redundant device; rewriting the target device based on the target device information; and updating the layout of the target object based on the rewritten target device to obtain a revised integrated circuit layout. In implementation, by finding, introducing, and modifying the redundant logic devices in the design, or modifying the logic of the original device, only a small amount of metal layers are used to complete the logic connection modification, thereby achieving the purpose of fixing the bug. Specifically, the device information in the target object can be determined through the layout information, so as to locate and analyze the logic redundant devices. By rewriting the logic redundant devices, the processing methods such as setting up additional spare devices are replaced, thereby improving the efficiency of the integrated circuit revision design, and on the other hand, reducing the implementation cost of the integrated circuit revision. BRIEF DESCRIPTION OF THE DRAWINGS
[0050] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.
[0051] Figure 1 A first flow chart of an integrated circuit revision method in one embodiment;
[0052] Figure 2 A second flow chart of an integrated circuit revision method in another embodiment;
[0053] Figure 3 A third flow chart of an integrated circuit revision method in another embodiment;
[0054] Figure 4 A fourth flow chart of an integrated circuit revision method in another embodiment;
[0055] Figure 5 A fifth flow chart of an integrated circuit revision method in another embodiment;
[0056] Figure 6 A sixth flow chart of an integrated circuit revision method in another embodiment;
[0057] Figure 7 is an overall flow chart of an integrated circuit revision method in one embodiment;
[0058] Figure 8A structural block diagram of an integrated circuit revision device in one embodiment;
[0059] Fig. 9 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION
[0060] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.
[0061] In the related technology, there are currently many ways to modify the design after tape-out, such as: using pre-placed spare logic cells [spare cells], using pre-placed dedicated ECO filler cells [ECO filler], using pre-placed dedicated ECO logic cells [ECO logic cells], etc. When choosing a method for modifying the design after tape-out, it is necessary to comprehensively consider the specific needs of the project, the complexity of the design, and the expected cost. Spare logic cells provide flexibility, ECO filler cells help with quick repairs, and dedicated ECO logic cells are functionally targeted.
[0062] However, the current integrated circuit revision method has the following technical problems:
[0063] Existing integrated circuit revision methods require pre-configuration of spare devices, which are then introduced by modifying the metal layer layout wiring. This method is suitable for complex logic modifications and revisions that can withstand higher costs, but often requires smaller logic modifications but higher costs.
[0064] Based on this, an embodiment of the present application provides a method for redesigning an integrated circuit.
[0065] In one embodiment, Figure 1 As shown, a method for redesigning an integrated circuit is provided. This embodiment uses the method applied to a terminal as an example for illustration. It can be understood that the method can also be applied to a server, and can also be applied to a system including a terminal and a server, and is implemented through the interaction between the terminal and the server. In this embodiment, the method includes the following steps:
[0066] Step 102: In response to a revision requirement of a target object, obtaining layout information of the target object;
[0067] Step 104: determining target device information in the target object according to the layout information, wherein the target device is a logic redundant device;
[0068] Step 106: rewriting the target device based on the target device information;
[0069] Step 108: updating the layout of the target object based on the rewritten target device to obtain a revised integrated circuit layout.
[0070] In the above integrated circuit revision method, reasonable deduction is performed in combination with the technical features in the embodiment, which can achieve the beneficial effect of solving the technical problems raised in the background technology:
[0071] The present application provides an integrated circuit revision method, including obtaining the layout information of the target object in response to the revision demand of the target object; determining the target device information in the target object according to the layout information, wherein the target device is a logic redundant device; rewriting the target device based on the target device information; and updating the layout of the target object based on the rewritten target device to obtain a revised integrated circuit layout. In implementation, by finding, introducing, and modifying the redundant logic devices in the design, or modifying the logic of the original device, only a small amount of metal layers are used to complete the logic connection modification, thereby achieving the purpose of fixing the bug. Specifically, the device information in the target object can be determined through the layout information, so as to locate and analyze the logic redundant devices. By rewriting the logic redundant devices, the processing methods such as setting up additional spare devices are replaced, thereby improving the efficiency of the integrated circuit revision design, and on the other hand, reducing the implementation cost of the integrated circuit revision.
[0072] In one embodiment, the Figure 2 As shown, step 103 includes:
[0073] Step 201: if the logic redundant device does not exist in the original layout of the target object, then determine the relevant logic devices associated with the revision requirement;
[0074] Step 203: rewriting the layout of the target object based on the relevant logic devices.
[0075] In this embodiment, when there are no redundant logic devices, relevant logic devices associated with the revision requirements can be determined, and rewriting processing can be performed through the relevant logic devices, which helps to improve the flexibility of the integrated circuit revision processing.
[0076] In one embodiment, the Figure 3 As shown, after step 107, the following further includes:
[0077] Step 301: Verify the revised integrated circuit layout, including Figure 1 Consistency testing, physical design rule testing, formal verification, and static timing analysis.
[0078] In this embodiment, the integrated circuit layout is verified after the revision is completed, and the feasibility verification of the revision process is achieved through a variety of verification logics, which helps to improve the stability of the revision process.
[0079] In one embodiment, the Figure 4 As shown, step 301 includes:
[0080] Step 401: inputting a test signal to the revised target object based on a preset test logic;
[0081] Step 403: Detect the stimulus signal returned by the target object to obtain a verification result of the revised integrated circuit layout.
[0082] In this embodiment, the revision verification of the integrated circuit layout is implemented by using the test signal, which helps to improve the efficiency of the revision verification.
[0083] In one embodiment, the Figure 5 As shown, in response to the revision requirement of the target object, obtaining the layout information of the target object includes:
[0084] Step 501: Obtain the revision information;
[0085] Step 503: reversely process the revision information based on a preset back-annotation logic to obtain the physical data that needs to be modified in the original layout of the target object.
[0086] In this embodiment, the transformation of revision information from an abstract logical concept to a concrete physical concept is achieved through back-labeling logic, which helps to improve the accuracy of revision design.
[0087] In one embodiment, the Figure 6 As shown, the method also includes:
[0088] Step 601: if there are several optional revision plans for the target object, sort the multiple revision plans based on a preset evaluation logic;
[0089] Step 603: Determine a target revision scheme from the sorted revision schemes.
[0090] In this embodiment, by sorting a plurality of revision schemes, it is helpful to select a revision scheme according to actual needs, and it is helpful to improve the flexibility of revision processing.
[0091] In a most specific embodiment, the method flow of an integrated circuit revision method provided by the present application can be as follows: Figure 7 shown.
[0092] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.
[0093] Based on the same inventive concept, the embodiment of the present application also provides an integrated circuit revision device for implementing the integrated circuit revision method involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in one or more embodiments of an integrated circuit revision device provided below can refer to the limitations of an integrated circuit revision method above, and will not be repeated here.
[0094] In one embodiment, Figure 8 As shown, an integrated circuit revision device is provided, comprising: a revision requirement module, a device positioning module, a device rewriting module and a revision writing module, wherein:
[0095] A revision requirement module, used to obtain layout information of a target object in response to a revision requirement of the target object;
[0096] A device positioning module, used to determine target device information in the target object according to the layout information, wherein the target device is a logic redundant device;
[0097] A device rewriting module, used for rewriting the target device based on the target device information;
[0098] The revision writing module is used to update the layout of the target object based on the rewritten target device to obtain a revised integrated circuit layout.
[0099] In one embodiment, the device positioning module includes:
[0100] A related device module, used for determining the related logic devices associated with the revision requirement if the logic redundant device does not exist in the original layout of the target object;
[0101] A related device rewriting module is used to rewrite the layout of the target object based on the related logic devices.
[0102] In one embodiment, after the revision is written into the module, the method further comprises:
[0103] A revision verification module is used to verify the revised integrated circuit layout, the verification includes: Figure 1 Consistency testing, physical design rule testing, formal verification, and static timing analysis.
[0104] In one embodiment, the revision verification module includes:
[0105] A test signal module, used for inputting a test signal to the revised target object based on a preset test logic;
[0106] The feedback verification module is used to detect the excitation signal returned by the target object to obtain the verification result of the revised integrated circuit layout.
[0107] In one embodiment, the revision requirement module includes:
[0108] A revision trust module, used to obtain the revision information;
[0109] The reverse-annotation data module is used to reversely process the revision information based on a preset reverse-annotation logic to obtain the physical data that needs to be modified in the original layout of the target object.
[0110] In one embodiment, the device further comprises:
[0111] A parallel scheme module, used for sorting the multiple revision schemes based on a preset evaluation logic if there are several optional revision schemes in the target object;
[0112] The parallel screening module is used to determine the target revision scheme from the sorted revision schemes.
[0113] Each module in the above integrated circuit revision device can be implemented in whole or in part by software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute the operations corresponding to each module.
[0114] In one embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as follows: Fig. 9As shown. The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit and an input device. The processor, the memory and the input / output interface are connected through a system bus, and the communication interface, the display unit and the input device are connected to the system bus through the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and the external device. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be realized through WIFI, a mobile cellular network, NFC (near field communication) or other technologies. When the computer program is executed by the processor, a method for revising an integrated circuit is implemented. The display unit of the computer device is used to form a visually visible picture, which can be a display screen, a projection device or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covering the display screen, or a button, trackball or touchpad set on the computer device shell, or an external keyboard, touchpad or mouse.
[0115] Those skilled in the art will understand that Fig. 9 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.
[0116] In one embodiment, a computer device is further provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps in the above method embodiments when executing the computer program.
[0117] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.
[0118] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.
[0119] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant laws, regulations and standards of relevant countries and regions.
[0120] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.
[0121] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0122] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the present application. It should be noted that, for a person of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.
Claims
1. A method for redesigning an integrated circuit, characterized in that: The method comprises: In response to a revision requirement of a target object, obtaining layout information of the target object; Determine target device information in the target object according to the layout information, wherein the target device is a logic redundant device; rewriting the target device based on the target device information; The target object is updated in layout based on the rewritten target device to obtain a revised integrated circuit layout.
2. The method according to claim 1, characterized in that Determining target device information in the target object according to the layout information, wherein the target device is a logic redundant device, comprises: If the logic redundant device does not exist in the original layout of the target object, determining the relevant logic devices associated with the revision requirement; The layout of the target object is rewritten based on the related logic devices.
3. The method according to claim 2, characterized in that After the target object is updated based on the rewritten target device to obtain a revised integrated circuit layout, the method further includes: The revised integrated circuit layout is verified, and the verification includes layout consistency detection, physical design rule detection, formal verification, and static timing analysis.
4. The method according to claim 1, characterized in that The verification of the revised integrated circuit layout includes: Inputting a test signal to the revised target object based on a preset test logic; The stimulus signal returned by the target object is detected to obtain a verification result of the revised integrated circuit layout.
5. The method according to any one of claims 1 to 4, characterized in that: In response to the revision requirement of the target object, obtaining the layout information of the target object includes: Obtaining the revision information; The revision information is reversely processed based on a preset back-annotation logic to obtain the physical data that needs to be modified in the original layout of the target object.
6. The method according to claim 1, characterized in that The method further comprises: If there are several optional revision plans for the target object, the multiple revision plans are sorted based on a preset evaluation logic; A target revision scheme is determined from the sorted revision schemes.
7. An integrated circuit revision device, characterized in that: The device comprises: A revision requirement module, used to obtain layout information of a target object in response to a revision requirement of the target object; A device positioning module, used to determine target device information in the target object according to the layout information, wherein the target device is a logic redundant device; A device rewriting module, used for rewriting the target device based on the target device information; The revision writing module is used to update the layout of the target object based on the rewritten target device to obtain a revised integrated circuit layout.
8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.
9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.
10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.