A FLASH device design method based on machine learning

Abstract

A FLASH device design method based on machine learning, the method comprising: step one, defining a 2T-FLASH unit structure; step two, in the process of establishing the 2T-FLASH unit, using a random number seed method to collect input data of a prediction model; step three, simulating the performance of the 2T-FLASH unit, and collecting output data of the prediction model; step four: determining the input and output of the prediction model to divide the training set and the test set, and performing the first training; step five, selecting and retaining the prediction model that converges to the expected level and the corresponding input and output, establishing a second data set, and performing the second training. Using machine learning to carry out simulation design of FLASH devices can greatly shorten the R&D cycle and reduce development costs, and also provide a technical basis for the tape-out of FLASH devices.

Description

Technical Field

[0001] The present application relates to the field of microelectronic integration technology, and in particular to a FLASH device design method based on machine learning. Background Art

[0002] Flash memory (FLASH) is an electrically erasable programmable read-only memory. Its core unit, FLASH devices, have the advantages of high-speed reading and writing, low power consumption and small size. It has the advantages of low power consumption, high integration, CMOS process compatibility, high reliability and radiation resistance. It is widely used in data storage, boot loading and firmware updates. It is also the core configuration unit for storage-computing integration and brain-like computing technologies in the post-Moore era.

[0003] With the development of emerging technologies such as artificial intelligence, 5G, and the Internet of Things, FLASH faces more demands and challenges. However, the tape-out iteration based on multiple adjustments of process parameters will not only greatly extend the FLASH device design cycle, but also cause a sharp increase in research and development costs. At present, although the research and development of FLASH devices based on simulation software has led the direction of research and development to a certain extent, it is the same as experimental design. It is difficult to traverse and integrate all influencing factors based on manual device simulation. Therefore, simulation design is also blind and time-consuming. Summary of the invention

[0004] The present application provides a FLASH device design method based on machine learning, which can be used to solve the technical problem of blindness in the machine learning simulation process.

[0005] The present application provides a FLASH device design method based on machine learning, the method comprising:

[0006] Step 1, define the 2T-FLASH unit structure;

[0007] Step 2: During the establishment of the 2T-FLASH unit, the random number seed method is used to collect input data for the prediction model;

[0008] Step 3: Perform 2T-FLASH unit performance simulation and collect output data of the prediction model;

[0009] Step 4: Determine the input and output of the prediction model, divide it into training set and test set, and conduct the first training;

[0010] Step 5: Screen and retain the prediction models that converge to the expected level and the corresponding input and output quantities, establish a second data set and conduct a second training.

[0011] The present application provides a method of machine learning, which learns from existing data, discovers the laws and trends in the data, and uses the established laws and trends to complete the prediction, classification and clustering of tasks, with the advantages of automated learning, high accuracy and strong adaptability. Therefore, the simulation design of FLASH devices based on machine learning can greatly shorten the R&D cycle and reduce the development cost, and also provide a technical basis for the tape-out of FLASH devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 The FLASH device development requirements and key parameters provided for the embodiments of this application;

[0013] Figure 2 A FLASH device modeling method provided in an embodiment of the present application;

[0014] Figure 3 An AI-assisted FLASH device simulation process is provided in an embodiment of the present application. DETAILED DESCRIPTION

[0015] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0016] The following first introduces the embodiments of the present application in conjunction with the accompanying drawings.

[0017] Machine learning learns from existing data, discovers patterns and trends in the data, and uses the established patterns and trends to complete task prediction, classification, and clustering. It has the advantages of automated learning, high accuracy, and strong adaptability. Therefore, the simulation design of FLASH devices based on machine learning can greatly shorten the R&D cycle and reduce the R&D cost, and also provide a technical basis for the tape-out of FLASH devices.

[0018] like Figure 1 As shown in the figure: as the device feature size gradually decreases, channel doping will cause drastic fluctuations in the threshold voltage of the FLASH device; at the same time, source and drain doping will also affect the threshold voltage of the FLASH device by affecting the channel potential and contact resistance of the device, both of which will seriously affect the performance of the circuit. In the case of fixed ion species, channel doping and source and drain doping optimization can be achieved by adjusting the injection energy and injection dose. FLASH device design and wafer verification based on process bias have the disadvantages of low development efficiency, long cycle and high cost, and it is difficult to traverse all process parameters and complete the full combination and arrangement of process parameters. Based on the 2T-FLASH unit structure, the present invention establishes its finite element model and performs performance simulation for the first time, and combines machine learning methods to propose a FLASH device design method to achieve accurate and efficient process parameter optimization and control.

[0019] like Figure 2 As shown: A FLASH device design method based on machine learning, wherein the 2T-FLASH unit process method mainly includes the following steps:

[0020] Step 1, define the 2T-FLASH unit structure;

[0021] Based on the designed 2T-FLASH unit structure, the size of the 2T-FLASH unit simulation model is defined, including a MOSFET, namely SG, and a FLASH transistor, namely CG, and the grid density is defined, and the grid is encrypted in the ion implantation or PN junction area in the simulation structure;

[0022] Step 2: During the establishment of the 2T-FLASH unit, the random number seed method is used to collect input data for the prediction model;

[0023] Step 21, using a high temperature oxide layer deposition process to prepare a MOSFET transistor oxide layer, performing threshold adjustment doping injection, and using a random number seed to generate energy and dose for threshold adjustment injection; using an etching process to remove the FLASH transistor oxide layer, combined with a low temperature thermal oxidation process, to prepare the FLASH transistor oxide layer;

[0024] Step 22, preparing a polysilicon layer by using an in-situ polysilicon doping process, forming a silicon dioxide-silicon nitride-silicon dioxide dielectric layer by depositing an oxide layer and silicon nitride on the polysilicon layer, preparing a polysilicon layer by using an ion implantation doping process, performing polysilicon doping implantation, and using a random number seed to generate the energy and dose of the polysilicon implantation;

[0025] Step 23, forming MOSFET and FLASH transistors through gate photolithography and etching process, performing source-drain injection of FLASH transistors, using random number seeds to generate energy and dose for source-drain injection of FLASH transistors, performing source-drain injection of MOSFET and FLASH transistors, using random number seeds to generate energy and dose for source-drain injection of MOSFET and FLASH transistors.

[0026] Step 3: Perform 2T-FLASH unit performance simulation and collect output data of the prediction model;

[0027] Step 31, interconnecting the MOSFET and FLASH transistors through a gate photolithography and etching process, and using a metal salicide process to form metal silicide on the heavily doped region and the top polysilicon of the gate, forming a layer of borophosphide silicon glass through chemical vapor deposition, locating the metal connection position, forming a through hole through etching, and forming a first metal connection layer through chemical vapor deposition and etching;

[0028] Step 32, using the Shockley-Reed-Hall and Poole-Frenkel models to simulate the performance of the 2T-FLASH unit, the erasing process uses the Nottheim tunneling method, by applying a negative pulse potential at the gate end and applying a positive potential to the other ports, completing the tunneling of electrons from the gate to the substrate, and the programming process uses the band-to-band tunneling induced hot electron injection method, by applying a negative pulse potential at the drain end and a positive potential at the gate end, and the other ports are set to zero potential, completing the tunneling of electrons to the floating gate;

[0029] Step 33, after the erasing process and the programming process, perform a 2T-FLASH unit transfer characteristic simulation, during which -0.1V is applied to the drain terminal, -3V is applied to the gate terminal of the MOSFET transistor, and a voltage scan of -8 to 15V is applied to the FLASH transistor, and the remaining ports are set to zero potential. Based on the 2T-FLASH unit transfer characteristic simulation results, the simulation results are divided into convergence and non-convergence, and for the convergence results, the threshold voltage of the FLASH transistor is recorded when the absolute value of the drain current is 100nA, including the erased state threshold voltage and the programmed state threshold voltage.

[0030] Step 4: Determine the input and output of the prediction model, divide it into training set and test set, and conduct the first training;

[0031] Step 41, constructing the energy and dose of the threshold adjustment injection, the energy and dose of the polysilicon injection, the energy and dose of the FLASH transistor source and drain injection, the MOSFET and FLASH transistor source and drain injection, the erased state threshold voltage and the programmed state threshold voltage as a data set, wherein the energy and dose of the threshold adjustment injection, the energy and dose of the polysilicon injection, the energy and dose of the FLASH transistor source and drain injection, the energy and dose of the MOSFET and FLASH transistor source and drain injection are input quantities, and the erased state threshold voltage and the programmed state threshold voltage are output quantities;

[0032] Step 42, dividing the data set into a training set and a test set in proportion, the training set is used for 2T-FLASH unit simulation model training and parameter adjustment, and the test set is used for final evaluation of the performance of the 2T-FLASH unit simulation model;

[0033] Step 43, in order to be able to pre-screen the randomly generated threshold adjustment injection energy and dose, polysilicon injection energy and dose, FLASH transistor source and drain injection energy and dose, MOSFET and FLASH transistor source and drain injection energy and dose, different classifiers that can identify parameter convergence are trained, and a confusion matrix is ​​established according to convergence and non-convergence, as shown in Table 1:

[0034] Table 12 T-FLASH unit confusion matrix

[0035]

[0036] In the table, true convergence TP: the model is predicted to converge and actually converges, the correct number of convergences;

[0037] False convergence FP: The model is predicted to converge, but actually diverges, false positives, incorrect convergence numbers;

[0038] True divergence TN: The predicted model is divergent and actually diverges, the correct number of divergences;

[0039] Fake FN: The model is predicted to be divergent, and actually converged, missed, and the number of divergences not found correctly.

[0040] Step 5: Screen and retain the prediction models that converge to the expected level and the corresponding input and output quantities, establish a second data set and conduct a second training.

[0041] Step 51, evaluating the advantages and disadvantages of different classifier models through the area under the receiver operating characteristic curve (ROC) AUC, selecting the best classifier, pre-screening the randomly generated input, and retaining the threshold adjustment injection energy and dose, polysilicon injection energy and dose, FLASH transistor source and drain injection energy and dose, MOSFET and FLASH transistor source and drain injection energy and dose that converge to the expected value as the input data of the second data set;

[0042] Step 52, normalizing the input data of the second data set and converting it into a value between 0 and 1; the normalization method adopts any one of Max-Min normalization, Z-score normalization, data type normalization, and standard deviation normalization;

[0043] Step 53, training the prediction model: Since the prediction accuracy of the neural network is affected by multiple factors, including data preprocessing method, network depth, and the number of neurons in each layer, the present invention obtains the average verification loss through repeated training and uses it as the model loss; wherein the data set is shuffled in each training to record each training loss and verification loss, and the value with the minimum verification loss in Epochs is used as the final loss of the model evaluation; at the same time, the verification loss is tested by changing the number of hidden units in each layer, and the number of neurons in each layer under the lowest loss is screened to achieve the best performance.

[0044] The data set is divided into training set, validation set and test set in proportion. According to the inferred optimal network depth and number of layer neurons, the mapping of injection energy and dose to erased state threshold voltage and programmed state threshold voltage is completed.

[0045] At the same time, the training data is reversely modeled to complete the mapping of the erased state threshold voltage and the programmed state threshold voltage to the injection energy and dose.

[0046] Specifically, based on the constructed neural network model, the erased state threshold voltage and programmed state threshold voltage of the 2T-FLASH cell are predicted according to the designed 2T-FLASH cell threshold adjustment injection energy and dose, polysilicon injection energy and dose, FLASH transistor source and drain injection energy and dose, MOSFET and FLASH transistor source and drain injection energy and dose parameters;

[0047] At the same time, according to the target erased state threshold voltage and programmed state threshold voltage of the 2T-FLASH cell, the threshold adjustment injection energy and dose, polysilicon injection energy and dose, FLASH transistor source and drain injection energy and dose, MOSFET and FLASH transistor source and drain injection energy and dose parameters are inferred.

[0048] The above-described embodiments of the present application do not constitute a limitation on the protection scope of the present application.

Claims

1. A FLASH device design method based on machine learning, characterized in that: The method comprises: Step 1, define the 2T-FLASH unit structure; Step 2: During the establishment of the 2T-FLASH unit, the random number seed method is used to collect input data for the prediction model; Step 3: Perform 2T-FLASH unit performance simulation and collect output data of the prediction model; Step 4: Determine the input and output of the prediction model, divide it into training set and test set, and conduct the first training; Step 5: Screen and retain the prediction models that converge to the expected level and the corresponding input and output quantities, establish a second data set and conduct a second training.

2. The method according to claim 1, characterized in that: Step 1: define the 2T-FLASH unit structure; including: Based on the designed 2T-FLASH unit structure, the size of the 2T-FLASH unit simulation model is defined, including a MOSFET, namely SG, and a FLASH transistor, namely CG, and the grid density is defined, and the grid is encrypted in the ion implantation or PN junction area in the simulation structure.

3. The method according to claim 1, characterized in that Step 2: During the establishment of the 2T-FLASH unit, the random number seed method is used to collect input data of the prediction model; including: Step 21, using a high temperature oxide layer deposition process to prepare a MOSFET transistor oxide layer, performing threshold adjustment doping injection, and using a random number seed to generate energy and dose for threshold adjustment injection; using an etching process to remove the FLASH transistor oxide layer, combined with a low temperature thermal oxidation process, to prepare the FLASH transistor oxide layer; Step 22, preparing a polysilicon layer by using an in-situ polysilicon doping process, forming a silicon dioxide-silicon nitride-silicon dioxide dielectric layer by depositing an oxide layer and silicon nitride on the polysilicon layer, preparing a polysilicon layer by using an ion implantation doping process, performing polysilicon doping implantation, and using a random number seed to generate the energy and dose of the polysilicon implantation; Step 23, forming MOSFET and FLASH transistors through gate photolithography and etching process, performing source-drain injection of FLASH transistors, using random number seeds to generate energy and dose for source-drain injection of FLASH transistors, performing source-drain injection of MOSFET and FLASH transistors, using random number seeds to generate energy and dose for source-drain injection of MOSFET and FLASH transistors.

4. The method according to claim 1, characterized in that Step 3: Perform 2T-FLASH unit performance simulation and collect output data of the prediction model; including: Step 31, interconnecting the MOSFET and FLASH transistors through a gate photolithography and etching process, and using a metal salicide process to form metal silicide on the heavily doped region and the top polysilicon of the gate, forming a layer of borophosphide silicon glass through chemical vapor deposition, locating the metal connection position, forming a through hole through etching, and forming a first metal connection layer through chemical vapor deposition and etching; Step 32, using the Shockley-Reed-Hall and Poole-Frenkel models to simulate the performance of the 2T-FLASH unit, the erasing process uses the Nottheim tunneling method, by applying a negative pulse potential at the gate end and applying a positive potential to the other ports, completing the tunneling of electrons from the gate to the substrate, and the programming process uses the band-to-band tunneling induced hot electron injection method, by applying a negative pulse potential at the drain end and a positive potential at the gate end, and the other ports are set to zero potential, completing the tunneling of electrons to the floating gate; Step 33, after the erasing process and the programming process, perform a 2T-FLASH unit transfer characteristic simulation, during which -0.1V is applied to the drain terminal, -3V is applied to the gate terminal of the MOSFET transistor, and a voltage scan of -8 to 15V is applied to the FLASH transistor, and the remaining ports are set to zero potential. Based on the 2T-FLASH unit transfer characteristic simulation results, the simulation results are divided into convergence and non-convergence, and for the convergence results, the threshold voltage of the FLASH transistor is recorded when the absolute value of the drain current is 100nA, including the erased state threshold voltage and the programmed state threshold voltage.

5. The method according to claim 1, characterized in that Step 4: Determine the input and output of the prediction model, divide it into training set and test set, and conduct the first training; include: Step 41, constructing the energy and dose of the threshold adjustment injection, the energy and dose of the polysilicon injection, the energy and dose of the FLASH transistor source and drain injection, the MOSFET and FLASH transistor source and drain injection, the erased state threshold voltage and the programmed state threshold voltage as a data set, wherein the energy and dose of the threshold adjustment injection, the energy and dose of the polysilicon injection, the energy and dose of the FLASH transistor source and drain injection, the energy and dose of the MOSFET and FLASH transistor source and drain injection are input quantities, and the erased state threshold voltage and the programmed state threshold voltage are output quantities; Step 42, dividing the data set into a training set and a test set in proportion, the training set is used for 2T-FLASH unit simulation model training and parameter adjustment, and the test set is used for final evaluation of the performance of the 2T-FLASH unit simulation model; Step 43, perform different classifier training that can identify parameter convergence, and establish a confusion matrix based on convergence and non-convergence, as shown in Table 1: Table 12 T-FLASH unit confusion matrix In the table, true convergence TP: the model is predicted to converge and actually converges, the correct number of convergences; False convergence FP: The model is predicted to converge, but actually diverges, false positives, incorrect convergence numbers; True divergence TN: The predicted model is divergent and actually diverges, the correct number of divergences; Fake FN: The model is predicted to be divergent, and actually converged, missed, and the number of divergences not found correctly.

6. The method according to claim 1, characterized in that Step 5: Screen and retain the prediction models that converge to the expected level and the corresponding input and output quantities, establish a second data set and conduct a second training, including: Step 51, evaluating the advantages and disadvantages of different classifier models through the area under the receiver operating characteristic curve (ROC) AUC, selecting the best classifier, pre-screening the randomly generated input, and retaining the threshold adjustment injection energy and dose, polysilicon injection energy and dose, FLASH transistor source and drain injection energy and dose, MOSFET and FLASH transistor source and drain injection energy and dose that converge to the expected value as the input data of the second data set; Step 52, normalizing the input data of the second data set and converting it into a value between 0 and 1; the normalization method adopts any one of Max-Min normalization, Z-score normalization, data type normalization, and standard deviation normalization; Step 53, training the prediction model: by repeated training for multiple times, the average validation loss is obtained and used as the model loss; in each training, the data set is shuffled to record each training loss and validation loss, and the value with the minimum validation loss in Epochs is used as the final loss of the model evaluation; at the same time, the validation loss is tested by changing the number of hidden units in each layer, and the number of neurons in each layer with the lowest loss is screened; The data set is divided into training set, validation set and test set in proportion. According to the inferred optimal network depth and number of layer neurons, the mapping of injection energy and dose to erased state threshold voltage and programmed state threshold voltage is completed. At the same time, the training data is reversely modeled to complete the mapping of the erased state threshold voltage and the programmed state threshold voltage to the injection energy and dose.

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