A method for generating Liberty library files for analog circuit interface timing
By configuring the system environment and using Perl scripts to generate Liberty library files, the problem of the generation of the simulated circuit interface timing Liberty library files in the prior art relying on transistor-level static timing analysis, realizing a simple and fast generation process, reducing design cost and system complexity.
Patent Information
- Application Number
- CN202411853655.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-16
- Publication Date
- 2025-04-04
AI Technical Summary
The prior art is difficult to generate the analog circuit interface timing Liberty library files simply and quickly, and it relies on transistor-level static timing analysis, resulting in large consumption of computing resources, high learning threshold, difficult interpretation of results, high design costs and increased system complexity.
By configuring the system environment, installing Perl tools and Library Compiler tools, collecting interface timing information of the simulated circuit, filling in the specified form, calling Perl scripts to generate three Liberty library files, Best, Typical and Worst, and using Library Compiler tools for format checking and database file generation.
The generation of analog circuit interface timing Liberty library files without relying on transistor-level static timing analysis is realized, which reduces the calculation amount and design cost, simplifies the operation process, and improves development efficiency and quality control capabilities.
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Figure CN119761331A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to chip design, and in particular to a method for generating a timing Liberty library file of an analog circuit interface. Background Art
[0002] The Liberty format is an open standard for integrated circuit library files, created and promoted by Synopsys. It can provide a unified interface for EDA tools to form Liberty library files, which is of great significance to chip design.
[0003] In chip design, Liberty library files are required for logic synthesis and static timing analysis. During logic synthesis, it can provide timing and power consumption characteristics for the basic units of the gate-level netlist and optimize the logic circuit; during static timing analysis, it can provide necessary timing information. Among them, the basic units include standard units and modules. The standard unit is a standard logic gate composed of transistors, such as AND, NOT, OR gates, etc.; the module is the circuit other than the standard unit, including digital circuits and analog circuits.
[0004] The Liberty library files of standard cells are provided by the chip foundry, while the Liberty library files of modules need to be generated by designers through specific tools and processes. Digital circuits can generate Liberty library files through the PrimeTime tool, while analog circuits are at the transistor level and require the Nanotime tool, which can perform static timing verification on transistor-level fully customized analog circuits and generate Liberty library files.
[0005] However, transistor-level static timing analysis is not part of the standard process for analog circuit design, and the Nanotime tool has many shortcomings: first, it consumes large amounts of computing resources, increasing design costs; second, it has a high learning threshold, increasing learning and time costs; third, it is difficult to interpret the results, which can easily lead to design decision errors; fourth, it relies on external tools and environments, increasing system complexity and maintenance costs; fifth, due to design cycle constraints, delays in analog circuit progress will affect SOC circuit development; and sixth, it requires the purchase of a license to use it, increasing design costs.
[0006] Therefore, it is necessary to generate Liberty library files for analog circuit interface timing, but there is a lack of a simple and fast method for generating Liberty library files that does not rely on transistor-level static timing analysis. Summary of the invention
[0007] 1. Technical issues to be solved
[0008] In view of the above-mentioned shortcomings of the prior art, the present invention provides a method for generating an analog circuit interface timing Liberty library file, which can effectively overcome the defects of the prior art that it is difficult to generate an analog circuit interface timing Liberty library file simply and quickly without relying on transistor-level static timing analysis.
[0009] (II) Technical solution
[0010] To achieve the above objectives, the present invention is implemented through the following technical solutions:
[0011] A method for generating a Liberty library file for an analog circuit interface timing sequence comprises the following steps:
[0012] S1. Configure the system environment, install tools and plug-ins, and add corresponding environment variables and path variables in the system configuration file;
[0013] S2. Collect the interface timing information of the analog circuit, and fill the interface timing information into the designated table position according to the preset requirements;
[0014] S3, placing the filled-in form in a location that supports Perl script reading;
[0015] S4, calling the Perl script, the Perl script generates three Liberty library files, Best, Typical and Worst, according to the filled-in form;
[0016] S5. Use the Library Compiler tool to check the format of the Liberty library file and generate a database file.
[0017] Preferably, in S1, the system environment is configured, tools and plug-ins are installed, and corresponding environment variables and path variables are added to the system configuration file, including:
[0018] Configure the system environment, install the Perl tool, Library Compiler tool, and Excel reading and writing plug-in, and add corresponding environment variables and path variables in the system configuration file.
[0019] Preferably, collecting the interface timing information of the analog circuit in S2 and filling the interface timing information into a designated table position according to preset requirements includes:
[0020] For signals with timing requirements, fill in the corresponding interface timing information in the specified table position according to the input interface / output interface, clock signal / data signal;
[0021] For data signals without timing requirements, directly fill in the corresponding interface timing information in the specified table position;
[0022] Among them, after filling in the interface timing information, you need to fill in the best, typical and worst values according to the process-voltage-temperature combination.
[0023] Preferably, for the signal with timing requirements, the corresponding interface timing information is filled in the designated table position according to the input interface / output interface, clock signal / data signal, including:
[0024] For input clock signals, you need to fill in the interface basic information table, interface other information table, and Input Clk min_pulse_width, Input Pin capacitance, and Input Pin transition constraint in the input interface timing information table;
[0025] For output clock signals, you need to fill in the interface basic information table, interface other information table, and Output Pin Transition and Output Pin capacitance constraint in the output interface timing information table;
[0026] For input data signals with timing requirements, you need to fill in the interface basic information table, interface other information table, as well as Input Pin capacitance, Input Pin transition constraint, Input Pin Setup / Hold time in the input interface timing information table and Related Pin, Related Pin Edge, Timing Type in the output interface timing information table;
[0027] For output data signals with timing requirements, you need to fill in the interface basic information table, interface other information table, and OutputPinDelay, Output PinTransition, OutputPincapacitance constraint, RelatedPin, RelatedPin Edge, and Timing Type in the output interface timing information table.
[0028] Preferably, for data signals without timing requirements, the corresponding interface timing information is directly filled in the designated table position, including:
[0029] For data signals without timing requirements, you need to fill in the interface basic information table and interface other information table;
[0030] Among them, for the clock signal and / or the data signal, the basic information table only needs to be filled in a separate sheet.
[0031] Preferably, the basic information table includes Process, Time_unit, Capacitance_unit, ss_corner, tt_corner, ff_corner, Module0 and Module1;
[0032] Process, fill in the process information. With the accumulation of projects, the basic information table of the same process module can be reused;
[0033] Time_unit and Capacitance_unit, fill in the unit information of the current process, which is consistent with the standard library provided by Foundry. All information in the basic information table is filled in with units of ns and pf. If it is inconsistent with the standard library provided by Foundry, the Perl script can handle the consistency;
[0034] ss_corner, tt_corner, and ff_corner, fill in the name of the process-voltage-temperature combination, which together with the module name constitutes the name of the Liberty library file, and fill in the voltage information and temperature information;
[0035] For Module0 and Module1, fill in the module names for which you want to generate Liberty library files.
[0036] Preferably, the interface basic information table includes InterfaceName and Direction;
[0037] InterfaceName, fill in the signal name information;
[0038] Direction, fill in the direction attribute information of the signal.
[0039] Preferably, the interface other information table includes Defaultvalue, PR Guideline and PG Info;
[0040] Defaultvalue, fill in the default value;
[0041] PR Guideline, fill in the layout and routing requirements;
[0042] PG Info, fill in the power ground;
[0043] Among them, the Perl script further generates a PG library file according to the interface other information table.
[0044] (III) Beneficial effects
[0045] Compared with the prior art, the method for generating a Liberty library file for an analog circuit interface timing provided by the present invention has the following beneficial effects:
[0046] 1) The Liberty library file can be generated by filling in the interface table template, which is more intuitive and less prone to errors. The Liberty library file can be provided before the circuit design is completed, so that the timing budget can be formulated as the design standard of the analog circuit in the early stage, reducing the design iteration;
[0047] 2) The Liberty library file can be generated by filling in the interface form template. This convenience is conducive to the rapid output of temporary versions and the determination of the final version. At the same time, the Excel backup function facilitates the tracing of historical versions, ensuring the accuracy of data and further improving development efficiency and quality control capabilities;
[0048] 3) The Liberty library file generated by the present invention not only contains timing information, but also contains information such as area and power consumption. It can also be converted into a database file using the Library Compiler tool and can be used as a standard library file in the front-end and back-end processes of chip design;
[0049] 4) Effectively reduce the amount of calculation and design costs, no license required, easy to operate;
[0050] 5) Simulators can obtain data through simulation without doing much extra work beyond design, thus ensuring design continuity;
[0051] 6) The generated files are highly readable, making it easier to control the design quality;
[0052] 7) Strong portability and shortened iteration cycle;
[0053] 8) The table method can reduce communication costs and improve overall efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0054] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0055] Figure 1 It is a schematic diagram of the process of the present invention. DETAILED DESCRIPTION
[0056] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0057] A method for generating a timing Liberty library file for an analog circuit interface, such as Figure 1 As shown, S1. Configure the system environment, install tools and plug-ins, and add corresponding environment variables and path variables in the system configuration file, including:
[0058] Configure the system environment, install the Perl tool, Library Compiler tool, and Excel reading and writing plug-in, and add corresponding environment variables and path variables in the system configuration file.
[0059] S2. Collect the interface timing information of the analog circuit and fill the interface timing information into the specified table position according to the preset requirements, including:
[0060] For signals with timing requirements, fill in the corresponding interface timing information in the specified table position according to the input interface / output interface, clock signal / data signal;
[0061] For data signals without timing requirements, directly fill in the corresponding interface timing information in the specified table position;
[0062] Among them, after filling in the interface timing information, you need to fill in the best, typical and worst values according to the process-voltage-temperature combination.
[0063] 1) For signals with timing requirements, fill in the corresponding interface timing information in the specified table position according to the input interface / output interface, clock signal / data signal, including:
[0064] For input clock signals, you need to fill in the interface basic information table, interface other information table, and Input Clk min_pulse_width, Input Pin capacitance, and Input Pin transition constraint in the input interface timing information table;
[0065] For output clock signals, you need to fill in the interface basic information table, interface other information table, and Output Pin Transition and Output Pin capacitance constraint in the output interface timing information table;
[0066] For input data signals with timing requirements, you need to fill in the interface basic information table, interface other information table, as well as Input Pin capacitance, Input Pin transition constraint, Input Pin Setup / Hold time in the input interface timing information table and Related Pin, Related Pin Edge, Timing Type in the output interface timing information table;
[0067] For output data signals with timing requirements, you need to fill in the interface basic information table, interface other information table, and OutputPinDelay, Output PinTransition, OutputPincapacitance constraint, RelatedPin, RelatedPin Edge, and Timing Type in the output interface timing information table.
[0068] 2) For data signals without timing requirements, directly fill in the corresponding interface timing information in the specified table position, including:
[0069] For data signals without timing requirements, you need to fill in the interface basic information table and interface other information table;
[0070] Among them, for the clock signal and / or the data signal, the basic information table only needs to be filled in a separate sheet.
[0071] A. In the technical solution of this application, the basic information table includes Process, Time_unit, Capacitance_unit, ss_corner, tt_corner, ff_corner, Module0 and Module1;
[0072] Process, fill in the process information. With the accumulation of projects, the basic information table of the same process module can be reused;
[0073] Time_unit and Capacitance_unit, fill in the unit information of the current process, which is consistent with the standard library provided by Foundry. All information in the basic information table is filled in with units of ns and pf. If it is inconsistent with the standard library provided by Foundry, the Perl script can handle the consistency;
[0074] ss_corner, tt_corner, and ff_corner, fill in the name of the process-voltage-temperature combination, which together with the module name constitutes the name of the Liberty library file, and fill in the voltage information and temperature information;
[0075] For Module0 and Module1, fill in the module names for which you want to generate Liberty library files.
[0076] The basic information table is shown in the following table:
[0077] Table 1 Basic information table
[0078]
[0079]
[0080] B. In the technical solution of this application, the basic interface information table includes Interface Name and Direction;
[0081] Interface Name, fill in the signal name information;
[0082] Direction, fill in the direction attribute information of the signal.
[0083] The basic information table of the interface is shown in the following table:
[0084] Table 2 Basic interface information
[0085] Interface Name Direction Description DATA input …
[0086] C. In the technical solution of this application, the input interface timing information table is shown in the following table:
[0087] Table 3 Input interface timing information table
[0088]
[0089] D. In the technical solution of this application, the output interface timing information table is shown in the following table:
[0090] Table 4 Output interface timing information table
[0091]
[0092] E. Other interface information tables include Default value, PR Guideline and PG Info;
[0093] Default value, fill in the default value;
[0094] PR Guideline, fill in the layout and routing requirements;
[0095] PG Info, fill in the power ground;
[0096] Among them, the Perl script further generates a PG library file according to the interface other information table.
[0097] The following table shows other interface information:
[0098] Table 5 Interface other information table
[0099] Default value PR Guideline PG Info 1’b0 Don’t touch AVDD / AVSS
[0100] S3. Place the filled-in form in a location that supports Perl script reading.
[0101] S4. Call the Perl script, which generates three Liberty library files, Best, Typical and Worst, according to the filled-in form.
[0102] S5. Use the Library Compiler tool to check the format of the Liberty library file and generate a database file.
[0103] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for generating a Liberty library file for an analog circuit interface timing sequence, characterized in that: The following steps are involved: S1. Configure the system environment, install tools and plug-ins, and add corresponding environment variables and path variables in the system configuration file; S2. Collect the interface timing information of the analog circuit, and fill the interface timing information into the designated table position according to the preset requirements; S3, placing the filled-in form in a location that supports Perl script reading; S4, calling the Perl script, the Perl script generates three Liberty library files, Best, Typical and Worst, according to the filled-in form; S5. Use the Library Compiler tool to check the format of the Liberty library file and generate a database file.
2. The method for generating a Liberty library file for an analog circuit interface timing according to claim 1, characterized in that: Configure the system environment in S1, install tools and plug-ins, and add corresponding environment variables and path variables in the system configuration file, including: Configure the system environment, install the Perl tool, Library Compiler tool, and Excel reading and writing plug-in, and add corresponding environment variables and path variables in the system configuration file.
3. The method for generating a Liberty library file of an analog circuit interface timing according to claim 1, characterized in that: S2 collects the interface timing information of the analog circuit and fills the interface timing information into the specified table position according to the preset requirements, including: For signals with timing requirements, fill in the corresponding interface timing information in the specified table position according to the input interface / output interface, clock signal / data signal; For data signals without timing requirements, directly fill in the corresponding interface timing information in the specified table position; Among them, after filling in the interface timing information, you need to fill in the best, typical and worst values according to the process-voltage-temperature combination.
4. The method for generating a Liberty library file for an analog circuit interface timing according to claim 3, characterized in that: For the signal with timing requirements, the corresponding interface timing information is filled in the designated table position according to the input interface / output interface, clock signal / data signal, including: For input clock signals, you need to fill in the Interface Basic Information Table, Interface Other Information Table, and Input Clk min_pulse_width, Input Pin capacitance, and InputPintransitionconstraint in the Input Interface Timing Information Table; For output clock signals, you need to fill in the interface basic information table, interface other information table, and Output Pin Transition and Output Pin capacitance constraint in the output interface timing information table; For input data signals with timing requirements, you need to fill in the interface basic information table, interface other information table, as well as Input Pin capacitance, Input Pin transition constraint, Input Pin Setup / Hold time in the input interface timing information table and Related Pin, Related Pin Edge, Timing Type in the output interface timing information table; For output data signals with timing requirements, you need to fill in the interface basic information table, interface other information table, and OutputPinDelay, Output PinTransition, OutputPin capacitanceconstraint, RelatedPin, RelatedPin Edge, and Timing Type in the output interface timing information table.
5. The method for generating a Liberty library file for an analog circuit interface timing according to claim 4, characterized in that: For data signals without timing requirements, the corresponding interface timing information is directly filled in the specified table position, including: For data signals without timing requirements, you need to fill in the interface basic information table and interface other information table; Among them, for the clock signal and / or the data signal, the basic information table only needs to be filled in a separate sheet.
6. The method for generating a Liberty library file for an analog circuit interface timing according to claim 5, characterized in that: The basic information table includes Process, Time_unit, Capacitance_unit, ss_corner, tt_corner, ff_corner, Module0 and Module1; Process, fill in the process information. With the accumulation of projects, the basic information table of the same process module can be reused; Time_unit and Capacitance_unit, fill in the unit information of the current process, which is consistent with the standard library provided by Foundry. All information in the basic information table is filled in with units of ns and pf. If it is inconsistent with the standard library provided by Foundry, the Perl script can handle the consistency; ss_corner, tt_corner, and ff_corner, fill in the name of the process-voltage-temperature combination, which together with the module name constitutes the name of the Liberty library file, and fill in the voltage information and temperature information; For Module0 and Module1, fill in the module names for which you want to generate Liberty library files.
7. The method for generating a Liberty library file for an analog circuit interface timing according to claim 5, characterized in that: The interface basic information table includes Interface Name and Direction; InterfaceName, fill in the signal name information; Direction, fill in the direction attribute information of the signal.
8. The method for generating a Liberty library file for an analog circuit interface timing according to claim 5, characterized in that: The interface other information table includes Default value, PR Guideline and PG Info; Defaultvalue, fill in the default value; PR Guideline, fill in the layout and routing requirements; PG Info, fill in the power ground; Among them, the Perl script further generates a PG library file according to the interface other information table.