Performance-driven logic optimization for logic synthesis

Abstract

The present technology includes performance-driven logic optimization for logic synthesis. A ground-truth dataset is generated based on technology mapping and static timing analysis of a set of gate-level netlists generated from a set of And-Inverter Graphs (AIGs). The ground-truth dataset is used to train a machine learning (ML) model to predict area and delay metrics. The trained ML model is used to predicted area and delay metrics for each AIG in another set of AIGs. A reward is calculated for each AIG in the other set of AIGs based on the predicted area and delay metrics. An AIG in the other set of AIGs having a smallest reward is selected as an optimal AIG. Technology mapping is performed on the optimal AIG to generate another gate-level netlist for use in one or more physical integrated circuit design processes.

Description

GDM 3.4-008

[0050] PERFORMANCE-DRIVEN LOGIC OPTIMIZATION FOR LOGIC SYNTHESISCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of and priority to U.S. Provisional Patent Application No. 63 / 686,883, filed August 26, 2024, the entire disclosure of which is incorporated by reference herein. BACKGROUND

[0002] Electronic design automation (EDA), also referred to as electronic computer-aided design (ECAD), refers to a process, and set of software tools, used for designing electronic systems, such as integrated circuits (ICs), printed circuit boards (PCBs), and the like. The EDA process encompasses a series of steps to design and implement digital circuits from high-level specifications to physical hardware. One such step in the EDA process is logic synthesis.

[0003] Logic sy nthesis is a process of converting an abstract specification of circuit behavior into a circuit design implementation in terms of logic gates. This involves transforming the abstract specification, such as a register-transfer level (RTL) description, into a netw ork of logic gates, such as a logic gate-level netlist, that can be physically implemented on an IC. The logic synthesis process also includes logic optimization and technology' mapping. Logic optimization involves optimizing the netlist based on design constraints and objectives, such as timing constraints and specific target implementation technology. Logic mapping involves selecting logical elements to implement the optimized netlist.

[0004] Objectives of the optimization process may include optimization of timing, area, and power of the resultant design. However, since accurate metrics, such as power, performance, and area (PPA) metrics, are only available after technology mapping is done, a common practice is to use proxy metrics to estimate the timing, area, and power metrics during logic optimization. For example, the node count of a netlist is often used to approximate the design area and the level count of the netlist is often used to approximate maximum delay. However, the correlation between level count and the maximum delay is not ideal or necessarily accurate. Therefore, using such proxy metrics during logical optimization may not yield the most optimal circuit designs in terms of, for example, PPA. Thus, such approaches can result in insufficient and / or ineffective solutions.SUMMARY

[0005] Aspects of the present technology employ a performance -driven logic optimization approach to iteratively refine logical optimization during logic synthesis. The present technology provides a new way to perform logical optimization that utilizes actual performance metrics of a technology -mapped netlist without requiring technology mapping and performance analysis to be performed on the netlist. Specifically, ground truth obtained post-mapping, for example, the area and timing of a mapped netlist. is incorporated into an objective function, such as a cost function or the like, that drives the optimization process. The ground-truth-based logic optimization runs technology mapping and static timing analysis (STA) in each iteration of an optimization problem flow, such as simulated annealing (SA), which could be computationally expensive depending on the size of the circuit. Thus, one aspect of the presentGDM 3.4-008

[0050] technology uses a faster, and more computationally efficient, machine learning (ML)-based logic optimization to achieve optimized netlists of similar quality, but with much shorter runtime and smaller resource expenditure.

[0006] Some embodiments include a computer-implemented method of And-Inverter Graph (AIG) optimization for logic synthesis. The method may include generating, by at least one processor, a groundtruth dataset based on technology mapping and static timing analysis of a set of gate-level netlists generated from a set of AIGs. The method may include training, by the at least one processor, a machine learning model to predict area and delay metrics based on tire ground-truth dataset. Tire method may include generating, by the at least one processor, predicted area and delay metrics for each AIG in another set of AIGs using the trained machine learning model. The method may include calculating, by the at least one processor, a reward value for each AIG in the other set of AIGs based on the predicted area and delay metrics. The method may include selecting, by the at least one processor, as an optimal AIG, one AIG from the other set of AIGs based on a comparison of the calculated reward values. The method may include providing, by the at least one processor, the optimal AIG to one or more physical integrated circuit design processes.

[0007] In some embodiments, selecting the one AIG comprises: selecting, by the at least one processor, as the optimal AIG, the one AIG from the other set of AIGs having a “best” reward value in comparison to other reward values of other AIGs in the other set of AIGs. In some embodiments, the best reward value may be a smallest reward value in comparison to the other reward values. In some embodiments, the best reward value may be a largest reward value in comparison to the other reward values.

[0008] In some embodiments, the method may include performing, by the at least one processor, technology mapping on the optimal AIG to generate another gate -level netlist for use in the one or more physical integrated circuit design processes.

[0009] In some embodiments, generating the ground-truth dataset comprises: obtaining, by the at least one processor, an initial AIG produced from a register-transfer level description; generating, by the at least one processor, the set of AIGs based on the initial AIG, wherein each AIG in the set of AIGs has a different structure than the initial AIG; generating, by the at least one processor, a set of gate-level netlists from each AIG, wherein each gate-level netlist in the set of gate-level netlists corresponds to a respective AIG in the set of set of AIGs; and deriving, by the at least one processor, delay and area metrics from each gate-level netlist.

[0010] In some embodiments, generating the ground-truth dataset further comprises: calculating, by the at least one processor, a reward value for each gate-level netlist based on the delay and area metrics; and storing, by the at least one processor, the calculated reward value in association with corresponding ones of the set of second AIGs.

[0011] In some embodiments, the reward value is a weighted sum of the delay metric and the area metric of the respective gate-level netlists.GDM 3.4-008

[0050]

[0012] In some embodiments, generating the ground-truth dataset further comprises: storing, by the at least one processor, the delay and area metrics of each gate-level netlist in association with corresponding ones of the set of AIGs.

[0013] In some embodiments, generating the set of AIGs based on the initial AIG comprises: applying, by the at least one processor, different random transformations to the initial AIG to produce different AIGs to be part of the set of AIGs.

[0014] In some embodiments, generating the set of AIGs based on the first AIG comprises: generating, by the at least one processor, at least two AIGs from the initial AIG in parallel.

[0015] In some embodiments, generating the set of gate-level netlists from each AIG comprises: performing, by the at least one processor, technology mapping on each AIG to produce corresponding gatelevel netlists in the set of gate-level netlists.

[0016] In some embodiments, deriving the delay metric and the area metric from each gate-level netlist comprises: performing, by the at least one processor, static timing analysis on each gate-level netlist.

[0017] In some embodiments, the method further comprises: extracting, by the at least one processor, a set of features from each AIG in the other set of AIGs; and operating, by the at least one processor, the trained machine learning model to generate the predicted area and delay metrics for each AIG in the other set of AIGs based on the extracted set of features.

[0018] Some embodiments include a computer-readable medium comprising computer-executable instructions stored thereon. The instructions, in response to execution by one or more processors of a computing system, cause the computing system to perform the computer-implemented method in any of the previously described embodiments. In some embodiments, the computer-readable medium is a non- transitory computer-readable medium.

[0019] Some embodiments include a computing system, comprising: at least one memory device configmed to store instructions for performing AIG optimization for logic synthesis; and at least one processor connected to the at least one memory device. The at least one processor is configured to execute the instructions to: generate a ground-truth dataset based on technology mapping and static timing analysis of a set of gate-level netlists generated from a set of AIGs; train a machine learning model to predict area and delay metrics based on the ground-truth dataset; generate predicted area and delay metrics for each AIG in another set of AIGs using the trained machine learning model; calculate a reward value for each AIG in the other set of AIGs based on the predicted area and delay metrics; select, as an optimal AIG, one AIG from the other set of AIGs based on a comparison of the calculated reward values; and provide the optimal AIG to one or more physical integrated circuit design processes.

[0020] In some embodiments, to select the one AIG, the at least one processor is configmed to execute the instructions to: select, as the optimal AIG, the one AIG from the other set of AIGs having a best reward value in comparison to other reward values of other AIGs in the other set of AIGs. In some embodiments, the best reward value may be a smallest reward value in comparison to the other reward values. In some embodiments, the best reward value may be a largest reward value in comparison to the other reward values.GDM 3.4-008

[0050]

[0021] In some embodiments, the at least one processor is configured to execute the instructions to perform technology mapping on the optimal AIG to generate another gate-level netlist for use in the one or more physical integrated circuit design processes.

[0022] In some embodiments, to generate the ground-truth dataset, the at least one processor is configured to execute the instructions to: obtain an initial AIG produced from a register-transfer level description; generate the set of AIGs based on the initial AIG, wherein each AIG in the set of AIGs has a different structure than the initial AIG; generate a set of gate-level netlists from each AIG, wherein each gate-level netlist in the set of gate-level netlists corresponds to a respective AIG in the set of set of AIGs; and derive delay and area metrics from each gate-level netlist.

[0023] In some embodiments, to generate the ground-truth dataset, the at least one processor is configured to execute the instructions to: calculate a reward value for each gate-level netlist based on the delay and area metrics, wherein the reward value is a weighted sum of the delay metric and the area metric of the respective gate-level netlists; and store the calculated reward value in association with corresponding ones of the set of second AIGs.

[0024] In some embodiments, to generate the ground-truth dataset, the at least one processor is configured to execute the instructions to: store the delay and area metrics of each gate-level netlist in association with corresponding ones of the set of AIGs.

[0025] In some embodiments, to generate the set of AIGs based on the initial AIG, the at least one processor is configured to execute the instructions to: apply different random transformations to the initial AIG to produce different AIGs to be part of the set of AIGs.

[0026] In some embodiments, to generate the set of AIGs based on the first AIG, the at least one processor is configured to execute the instructions to: generate at least two AIGs from the initial AIG in parallel.

[0027] In some embodiments, to generate the set of gate-level netlists from each AIG, the at least one processor is configmed to execute the instructions to: perform technology mapping on each AIG to produce corresponding gate-level netlists in the set of gate-level netlists.

[0028] In some embodiments, to derive the delay metric and the area metric from each gate-level netlist. the at least one processor is configured to execute the instructions to: perform static timing analysis on each gate-level netlist.

[0029] In some embodiments, the at least one processor is configmed to execute the instructions to: extract a set of features from each AIG in the other set of AIGs; and operate the trained machine learning model to generate tire predicted area and delay metrics for each AIG in the other set of AIGs based on the extracted set of features.

[0030] In some embodiments, the machine learning model is an extreme gradient boosting (XGBoost) model.BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Fig. 1 illustrates an example logic synthesis flow and baseline optimization flow for use with aspects of the present technology.GDM 3.4-008

[0050]

[0032] Fig. 2 illustrates a graph of AIG levels vs post-technology mapping delay in accordance with aspects of the present technology.

[0033] Figs. 3 A and 3B illustrate example AIGs generated based on node count and depth in accordance with aspects of the present technology.

[0034] Fig. 4A and 4B illustrate gate-level graphs of the AIGs of Figs. 3A and 3B in accordance with aspects of the present technology.

[0035] Fig. 5A illustrates an example performance-driven logic optimization flow in accordance with aspects of the present technology.

[0036] Fig. 5B illustrates example feature extraction techniques in accordance with aspects of the present technology.

[0037] Figs. 6A-B illustrate Pareto-front comparisons of AIGs generated using baseline and performance- driven logic optimization flows, in accordance with aspects of the present technology.

[0038] Figs. 7A and 7B illustrate runtime for PPA reward calculations in accordance with aspects of the present technology.

[0039] Figs. 8A, 8B, and 8C illustrate ground truth delay versus delay predictions in accordance with aspects of the present technology.

[0040] Fig. 9 illustrates predictive performance of various features used to predict delay for AIGs in accordance with aspects of the present technology.

[0041] Fig. 10 shows a comparison of Pareto-optimal fronts for the delay and area of a test design from the baseline, ground-truth-based, and ML-based flows in accordance with aspects of the present technology.

[0042] Figs. 11-12 illustrate an exemplary system in which aspects of the technology can be practiced.

[0043] Fig. 13 illustrates an example method in accordance with aspects of the present technology. DETAILED DESCRIPTION

[0044] The present technology enhances the optimization stage of logic synthesis, which includes two main stages: optimization and technology mapping. Traditionally, optimization may be performed using AIGs. The performance of an AIG is typically assessed by counting the number of nodes and the number of levels (depth) in the AIG. with fewer nodes and lower depth being associated with better area and performance. However, these metrics are coarse and do not always correlate well with the final performance characteristics of a corresponding technology -mapped netlist. For instance, two AIGs with identical node counts and depths may have vastly different structures, making it difficult to determine which AIG has superior performance characteristic based solely on the node count and depth metrics.

[0045] To address these limitations, aspects of the technology introduce an ML model to guide the optimization process by predicting area and delay metrics for individual AIGs. This allows for a more accurate and immediate assessment of AIG performance, bypassing the need for using technology mapping and timing analyses in an iterative process, which could be computationally expensive.

[0046] Tirus, aspects of the technology involve using machine learning predictions based on ground truth data to guide the optimization process. Obtaining ground truth data includes applying random transformsGDM 3.4-008

[0050] to an initial AIG to produce a plurality of new AIGs. Each of the new AIGs may be different than the initial AIG. Technology mapping is performed on each of the new AIGs to produce respective gate-level netlists. Static timing analysis is performed on each gate-level netlist to determine its actual delay and area. A reward function calculates a reward value for each gate-level netlist based on its actual delay and area. The reward values and / or the actual delay and area of each gate-level netlist is used as the ground truth data to train an ML model to predict delay and area based on AIG features. After the ML model is trained on the ground truth data, the ML model may be deployed into an optimization engine that attempts to optimize an AIG using the predicted area and delay.

[0047] Tire present technology is capable of discovering optimal AIG structures having better (shorter) delay and more efficient area characteristics in comparison to using conventional AIG optimization techniques. The machine learning models are able to predict delay and area with a high level of accuracy , which can replace computationally expensive EDA tool runs. Additionally, the present technology is capable of being plugged into existing AIG optimization frameworks, which allows for circuit designers to easily implement the present technology into their existing systems.1. Performance-driven Logic Optimization for Logic Synthesis

[0048] EDA is a process, and set of software tools, used for designing electronic systems, such as ICs, PCBs. and the like. The EDA process encompasses a series of steps to design and implement digital circuits from high-level specifications to physical hardware. The process mainly includes steps, such as system design or specification, logic design, logic synthesis, physical design, physical synthesis, physical verification, and tapeout. Additional or alternative steps / processes may be included in an EDA process in other implementations. As mentioned previously, logic synthesis is one step in the EDA circuit design process.

[0049] Fig. 1 depicts an example logic synthesis flow 100 in accordance with aspects of the present technology. Logic synthesis is a process of converting an abstract specification of circuit behavior into a circuit design implementation in terms of logic gates that can be physically implemented on an IC. In this example, the abstract specification are in the form of an RTL circuit description 110. The RTL description 110 may be expressed using a hardware description language (HDL), such as VHDL. Verilog, MyHDL. Clash, Chisel, and the like. The RTL description 110 defines the flow of data between registers and the logical operations performed on that data. Additionally or alternatively, the RTL description 110 may describe bitstreams for programmable logic devices (PLDs), such as programmable array logic (PAL), complex PLDs, field-programmable gate arrays (FPGAs), programmable Sy stem -on -Chip (SoC) platforms, and the like. The RTL description 110 may be generated using a high-level synthesis (HLS) tool. HLS tools automatically synthesize circuits specified using high-level programming languages, such as C, C++, SystemC, MATLAB, and the like, into a functionally -equivalent RTL hardware implementation, such as RTL description 110.

[0050] Tire logic sy nthesis flow 100 transforms, translates, or transcodes the RTL description 110 into gate-level descriptions, such as logic gate-level netlist 116. The output of the logic synthesis flow 100 (logicGDM 3.4-008

[0050] gate-level netlist 116) may be the input to a physical processing stage 120 of an EDA process (e.g., physical synthesis, etc ).

[0051] In this example, the logic synthesis flow 100 includes three stages: a logic translation stage performed by a translation engine 102, a logic optimization stage performed by an optimization engine 104. and a technology mapping stage performed by a technology mapping engine 106. The logic translation stage involves a translation engine 102 translating the RTL description 110 into a non-optimized logical netlist 112 based on, for example, technology libraries of standard cells, gates, and / or other logical components.

[0052] At the logic optimization stage, an optimization engine 104 optimizes the netlist 112 based on design constraints and objectives. For example, the synthesis constraints can include environment constraints, design constraints, and logic optimization constraints. The environment constraints include aspects of the external environment where the circuit is intended to operate, such as temperature, voltage, drive, load, and / or the like. The design constraints include design-related aspects of the circuit such as, for example, maximum transition time, maximum fan-out, minimum capacitance, maximum capacitance, and / or the like. The logic optimization constraints include constraints related to aspects of the optimization of the netlist 112, such as timing constraints and area constraints. The timing constraints may limit, for example, clock networks, timing paths, critical path delays, asynchronous logic timing, and the like. The area constraints may limit, for example, the maximum number of logic units and the like. To optimize netlist 112, the optimization engine 104 may be configmed to operate an optimization algorithm, which may operate according to baseline flow 104a. In the example of Fig. 1, the baseline flow 104a is a SA flow for A1G optimization in which a randomly selected sequence of transformations are applied to a given (current) AIG 140. and the new AIG depth and node count are used to evaluate the cost, such as reward 152. However, it should be noted that the baseline flow 104a could represent another optimization algorithm / flow. such as an evolutionary algorithm, genetic algorithm, Bayesian optimization algorithm, and / or other approach.

[0053] At the technology mapping stage, the technology mapping engine 106 selects logical elements to implement the optimized netlist 1 14. This may include, for example, selecting logic unit instances from the same or different technology7libraries to implement a gate-level logic netlist 116. The selection may be based on various constraints, such as time sequence or other timing constraints, PPA constraints (e.g., power consumption, performance in terms of speed and / or delay, and circuit area), logic unit characteristics, logical relationships, and the area of logic units provided by the technology libraries.

[0054] Tire netlists 112, 114. 116 are descriptions of the connectivity of an electronic circuit. Each netlist 112, 114, 116 is usually in the form of a logical data structure, such as an AIG. An AIG is a directed acyclic graph that represents a structural implementation of the logical functionality of a circuit or network. As the name suggests, an AIG usually comprises a network of AND gates and inverters. The embodiments discussed herein involve netlists in the form of AIGs, and thus, the optimization engine 104 may be considered as an AIG optimization engine 104. However, it should be understood that other logical dataGDM 3.4-008

[0050] structures, such as binary decision diagrams (BDD), sum-of-product forms (Soil), Boolean networks, and the like, could be used instead of AIGs in other implementations.

[0055] The AIG optimization engine 104 is to find an optimal AIG 114 that has the best performance in comparison from among a set of candidate AIGs. The optimization stage in logic synthesis has become an important factor affecting the feasibility of IC physical design. Most logical synthesis optimization engines analyze performance metrics, such as PPA, and the like, that are only available after technology7mapping 106 is completed, which may necessitate the use of an iteration loop 118 to further refine optimized netlists 114. However, such iterations can be computationally expensive in terms of computational resources.

[0056] One common optimization methodology to avoid such computationally taxing optimization involves using proxy metrics that can be obtained from an optimized AIG 114 to approximate the timing and area of an AIG 112, 114. According to such methodology , an AIG’s node count is ty pically used to approximate the design area of a circuit and the AIG’s level count is used to approximate maximum delay. This optimization methodology attempts to minimize AIG level and node count using, for example, SA, an evolutionary algorithm, a genetic algorithm, Bayesian optimization, or some other optimization algorithm.

[0057] For example, as shown by Fig. 1, the baseline optimization flow 104a involves providing a current AIG 140 to an AIG transformation function 142, which applies a randomly selected transfonnation to the current AIG 140 to produce a new AIG 144. The transformation may include any change to the arrangement or configuration of the current AIG 140 including, for example, node substitution (e.g.. randomly selecting one or more nodes in the AIG 140 and replace those node(s) with an equivalent but structurally different node or subgraph), node insertion (e.g., inserting one or more new nodes in the AIG 140 with one or more connections, which may also be randomly selected), node deletion (e.g., deleting one or more existing nodes in the AIG by removing the node(s) and connecting its inputs to its outputs or bypassing the node(s) entirely), edge rewiring (e.g.. randomly changing the connections (edges) between two or more nodes in the AIG 140, such as by rerouting the output of a node to feed into a different node or swapping the inputs of a node), subgraph replacement (e.g.. identifying a subgraph within the AIG 140 and replacing the identified subgraph with a different subgraph that implements the same or similar logical function, but having a different structure), node reordering (e.g., reordering the sequence of gates in a way that maintains logical equivalence, but changes the structure of the AIG 140, such as by rearranging the order in which one or more operations are performed without changing the overall logic), inversion pushing (e.g.. pushing inversion through one or more nodes in the AIG 140. such as by moving one or more inverters from a first side of a gate / node to a second side of the gate / node, or distributing one or more inverters across different parts of the AIG 140), balancing or rebalancing the AIG 140 (e.g., rearranging the structure of the AIG 140 to reduce or increase the number of levels (depth) in the AIG 140), and / or the like. Any additional or alternative methodology7of generating and applying transformations to AIGs 140 may be used.

[0058] A graph processor 146 performs graph processing on the new AIG 144 to identify or determine a depth (level count) and node count 148 for the new AIG 144. The graph processor 146 may use a suitable graph search or graph traversal algorithm (e.g., breadth-first search (BFS), depth-first search (DFS), etc.),GDM 3.4-008

[0050] topological sorting, levelization approaches, dynamic programming approaches, and / or the like. The depth and node count 148 is provided to a reward function 150. which uses the depth and node count 148 to calculate a reward value 152 for the new AIG 144. For example, the reward function 150 may calculate, as the reward value 152. a weighted sum or weighted average of the depth value and the node count. Then, an AIG selection function 154 decides whether to accept the new AIG 144 or not based on the reward value 152. For example, if the reward value 152 is a weighted sum or weighted average of the depth value and the node count and / or one or more other features, and the reward value 152 for the new AIG 144 is less (smaller) than a reward value of the current AIG 140, then the new AIG 144 may be selected; otherwise, the current AIG 140 is kept. In another example, if the reward value 152 is a weighted score based on the depth value, the node count, and / or one or more other features, and the reward value 152 for the new AIG 144 is more (larger) than a reward value of the current AIG 140, then the new AIG 144 may be selected; otherwise, the current AIG 140 is kept. In either case, the selected AIG (i.e., either the new AIG 144 or the current AIG 140) may be fed through the optimization process 104 again in an attempt to discover a more efficient AIG. This process may repeat for a predefined or configurable number of times. For example, in some SA implementations, the optimization process 104 may be repeated for about 1 million iterations. In other implementations, fewer or more iterations may be predefined or configured. Thus, the first tune that the optimization process 104 is run, the current AIG 140 may be the initial netlist 112 (or an AIG produced using the netlist 112). After the initiation run of the optimization engine 104, the current AIG 140 may be the new AIG 144 or the same, current AIG 144 based on which AIG is selected by the AIG selection function 154.

[0059] However, as shown by graph 200 of Fig. 2 and the example AIGs of Figs. 3A and 3B, the correlation between AIG level count and AIG maximum delay is not always ideal. Fig. 2 depicts a graph 200, which plots AIG level (x-axis) vs post-technology mapping delay (y-axis). Specifically, Fig. 2 plots the post-technology-mapping maximum delay against the number of levels, for a number of AIGs associated with a multiplier design. Each point (circle) in the graph 200 represents an individual AIG. Additionally, each point (circle) is color-coded based on the number of nodes (or elements) it contains (i.e.. its node count). The level of a node in an AIG is the length of the longest path from any primary input to that node, and thus, represents the number of logic stages (AND gates) that a signal must pass through to reach that node from an input. The overall depth of an AIG is the maximum level among all nodes. This corresponds to the longest path from any primary input to any primary output, indicating the circuit’ s critical path delay. The AIG depth (i.e., the maximum AIG level) is related to the critical path delay of the circuit, where a higher AIG level implies a longer critical path, which can lead to slower circuit performance. Reducing the number of AIG levels (or AIG depth) using techniques, such as logic balancing, node restructuring, and retiming, is a common goal in such optimization processes. In the example of Fig. 2, point 202 represents an optimal AIG (“AIG 202”) having the lowest maximum delay. However, the AIG represented by point 204 (“AIG 204”) has a greater maximum delay than AIG 202 even though AIG 204 has fewer AIG levels than AIG 202. For example, graph 200 shows that the correlation between maximumGDM 3.4-008

[0050] delay and the number of AIG levels, which may be referred to as the Pearson correlation coefficient, is only 0.74. Therefore, using AIG level as a proxy metric may not necessarily lead an AIG optimization algorithm to discover the true optimal AIG 114 having the best performance.

[0060] Figs. 3 A and 3B show a first AIG (“AIGl”) and a second AIG (“AIG2”), respectively. AIG1 and AIG2 were generated using the ABC logic synthesis system provided by Berkeley Logic Synthesis and Verification Group™. Both AIGs have a node count of 178 and an AIG depth of 14. However, AIGl has a different structure than the structure of AIG2. Therefore, it may not be possible to determine which AIG has better performance characteristics using node count and level count (or depth) alone.

[0061] Figs. 4A and 4B show the results of ruiming STA after technology mapping of AIGl and AIG2, respectively. Specifically, Fig. 4A shows a gatc-lcvcl graph of AIGl containing 178 logic nodes and 0 latches, and Fig. 4B shows a gate-level graph of AIG2 containing 150 logic nodes and 0 latches. The gatelevel graph in Fig. 4A has an area of 803.27 square micrometers (|im2) and a delay of 1.75 nanoseconds (ns) whereas the gate-level graph in Fig. 4B has an area of 770.74 pm2and a delay of 1.33 ns. Thus, AIG2 has better performance characteristics than AIGl even though AIGl and AIG2 have the same AIG node count and AIG depth.

[0062] To resolve the aforementioned issues, the present technology includes a performance-driven logic optimization process. Instead of relying on proxy metrics, the technology uses post-mapping metrics, such as post-mapping delay and area, to guide AIG optimization. As alluded to previously, the depth of an AIG (the maximum AIG level) does not necessarily lead to a most optimized AIG 114 with the actual optimal delay characteristics, and unawareness of the different structure of AIGs with same depth and node count. To overcome these challenges, a ‘ground truth’ obtained post-mapping (the actual area and timing of a mapped netlist 116) may be introduced into an objective function used to drive the AIG optimization algorithm. In some embodiments, a goal of the objective function may be defined to minimize post-mapping timing and area. The ground truth may be metrics obtained after technology mapping (e.g., area and delay. PPA. etc.), and these metrics may be used to drive the AIG optimization. However, ground-truth-based logic optimization may need to run technology mapping and STA in each iteration of the optimization flow, which may be computationally expensive or intensive. Therefore, the present technology includes a faster ML-based logic optimization flow to achieve AIGs of similar quality using a much smaller runtime and using fewer computational resources than existing optimization processes.1.1. Machine Learning Enhanced Logic Optimization

[0063] Fig. 5 A depicts an example performance-driven logic optimization flow 104x according to aspects of the present technology. The performance-driven logic optimization flow 104x includes a ground-truth flow 500a and an ML flow 500b. The ground-truth approach may be performed in certain scenarios according to one aspect of the technology, while the ML approach may be performed in other scenarios according to another aspect of the technology. Specifically, the ground-truth flow 500a is used to determine or obtain accurate post-mapping PPA, and the ML flow 500b uses the ground truth generated by the groundtruth flow 500a (i.e., the post-mapping PPA) to generate predicted PPA that is used to drive AIGGDM 3.4-008

[0050] optimization. Using PPA predicted by an ML model, such as ML model 566, as a reward, such as reward value 552, for logic optimization leads to circuit designs with better PPA in comparison to baseline AIG optimization flows that solely rely on proxy metrics, such as depth and node count.

[0064] Referring to the ground-truth flow 500a. the AIG transformer 142 transforms a current AIG 140a into a new AIG 514 in the same or similar manner as discussed previously. The AIG 140a may have the same or different structure than the AIG 140 of Fig. 1. The new AIG 514 is provided to a technology mapping engine 506. The technology mapping engine 506 generates a gate-level netlist 516 based on the new AIG 514. The gate-level netlist 516 represents a synthesized circuit. The technology mapping engine 506 may perform technology mapping in the same or similar maimer as discussed previously with respect to the technology mapping engine 106.

[0065] In various embodiments, the technology mapping engine 506 may be configured to optimize the gate-level netlist 516 based on PPA characteristics and / or constraints. For example, with respect to power consumption of PPA, the technology mapping engine 506 may aim to choose gates that meet performance and area constraints while minimizing power consumption. Where different gate implementations in the technology' library have vary ing power characteristics, this may include selecting loyv-power gates or reducing the syvitching activity of gates in non-critical paths. In another example, the technology mapping engine 506 may implement the logic in a way that meets or exceeds specified performance targets and / or meets delay targets by optimizing critical paths, choosing faster gates, and / or reducing logic depth. In yet another example, the technology mapping engine 506 may be configured to minimize the area by selecting smaller gates or minimizing the number of gates in the netlist 516, while still meeting the power and performance requirements.

[0066] The gate-level netlist 516 is provided to an STA engine 508. which performs STA on the gate-level netlist 516 to determine delay and area metrics 518 for the gate-level netlist 516. For example, the STA engine 508 may use timing models from libraries that provide delay information for each gate under various conditions. The STA engine 508 constructs a timing graph from the gate-level netlist 516 and evaluates the propagation delays across various paths in the circuit. Each path's delay is calculated by summing the delays of individual gates and interconnects, considering input transition times and output loads. The STA engine 508 may also provide insights into the area of the circuit, as it evaluates the impact of gate sizing and placement on both delay and area.

[0067] The delay and area metrics 518 may be provided to the reyvard function 550. The reward function 550 uses the area and delay 518 of the mapped netlist 516 for the ne v AIG 514 to compute a cost value (e.g., reyvard 552), which is used to guide the optimization. The reyvard function 550 may add yveights to each metric, such as adding a first weight to the delay metric and adding a second weight to the area metric, and then summing the yveighted metrics to yield a single reward 552. The first and second weights may be the same value or different values.

[0068] Tire reward value 552 may be stored by a storage function 554 in a database 556 as part of a groundtruth dataset 558. The database 556 may be a relational or non-relational database. In various embodiments,GDM 3.4-008

[0050] the ground-truth dataset 558 may comprise each generated AIG 514 stored in association with a corresponding reward value 552, corresponding delay and area metrics 518, and / or corresponding gatelevel netlists 516. Any other data and / or metadata generated during or after the ground-truth flow 500a may be stored as part of the dataset 558 such as, for example, transforms used by the transformer 142, circuit type(s), one or more identifiers, one or more pointers, date / time that data is generated, and / or the like.

[0069] For example, each record in the dataset 558 may include a field storing an AIG 514, a field storing its reward 552. a field for the calculated delay metric, a field for the calculated area metric, a field for the gate-level netlists 516, and / or zero or more other fields for any other type of data or metadata related to the AIG 514. In some implementations, the delay and area metrics 518 may be used for model training, and in such implementations, the delay and area metrics 518 may be stored without being provided to the reward function 550. As discussed in more detail infra, the ground-truth dataset 558 may be used for training an ML model, such as ML model 566, to predict delay and area metrics for AIGs, such as AIGs 544. Thus, in some embodiments, various features of the AIGs 514, such as those listed in tables 1 and 2 shown infra, may be extracted and stored as part of the ground-truth dataset 558.

[0070] It should be noted that multiple instances of the ground-truth flow 500a can operate in parallel, significantly reducing the overall execution time for the optimization stage. In a baseline AIG optimization flow, such as baseline flow 104a. one AIG serves as an initial AIG 140, which is transfonned into a new AIG 144. The AIG selection function 154 then determines whether this new AIG 144 should be the starting point for the next iteration based on its reward value 152. For example, if the reward 152 of the new AIG 144 is better than that of the current AIG 140, it becomes the starting point for the next iteration. Otherwise, the current AIG 140 is reused. As a result, the baseline flow 104a generates only one new AIG 144 per iteration, and thus, the baseline flow 104a is a sequential, iterative process. It should be noted that a “better” reward 152 in this example may refer to a smaller value, such as when the reward 152 is calculated as a weighted sum of AIG depth and node count. This is because, as alluded to previously, according to the typical optimization methodologies. AIGs having a smaller AIG depth and / or a smaller node count are typically considered to be more efficient than AIGs with larger AIG depths and / or node counts.

[0071] In contrast, the ground-truth flow 500a can generate multiple new AIGs 514 simultaneously, as it does not require a comparison of the rewards 552 of the new AIGs 514 and current AIG 140a and it does not make a selection of an optimal AIG. In other words, the ground-truth flow 500a is not required to be an iterative or sequential process. This allows the AIG transformer 142 to apply different random transformations to the same current AIG 140a, producing multiple distinct new AIGs 514 that can be run through the ground-truth flow 500a. Although it is not a requirement, the ground-truth flow 500a could be configured as an iterative or sequential process similar to the baseline flow 104a, if desired.

[0072] After a desired amount of ground-truth data 558 has been collected, the ML flow 500b may be used to train an ML model 566 to predict area and delay values based on a set of features 562. After the ML model 566 is trained and validated, the model 566 may be used to provide predicted delay and predicted area 568 to the reward function 550 for AIG selection 154.GDM 3.4-008

[0050]

[0073] Before the training phase, data preparation may take place where the ground-truth dataset 558 may be split into a training dataset and testing dataset. For example, 70-80% of the ground-truth dataset 558 may be used for training the model 558, while the remaining 20-30% may be reserved for testing and evaluating the model’s 558 performance. In some implementations, the ground-truth flow 500a may rim on the order of 100,000 iterations (or more or less) to gather a training dataset comprising 70,000 to 80,000 samples (or more or less) and a testing dataset comprising 20,000 to 30,000 samples (or more or less). Each sample may comprise a record and / or extracted features from the dataset 558. For example, each sample may include a reward value 552 that is used to label a corresponding AIG 514. In another example, each sample may include area and delay metrics 518, which are used to label for a corresponding AIG 514. In yet another example, any of combination of features listed in table 1 and / or table 2 (infra) may be used as labels for a corresponding AIG 514. In various embodiments, the extracted features may include AIG features and gate-level features. The features used for training may be collected in the same or similar manner as discussed infra with respect to feature extractor 560 and features 562.

[0074] During the training phase, a training algorithm may train the ML model 566 to find patterns in the training dataset based on the labels and / or features. In various embodiments, the ML model 566 may be a gradient boosting decision tree (GBDT) model, such as an extreme gradient boosting (XGBoost) model that may be implemented using the XGBoost library, which is an ensemble learning algorithm based on gradient boosting.

[0075] Training the XGBoost model, such as ML model 566, involves an iterative process designed to optimize predictions by minimizing an objective function. XGBoost is an ensemble learning technique that combines the predictions of multiple weak models to produce a strong prediction. The weak models are shallow decision trees, which are trained using gradient boosting. At each iteration, the XGBoost algorithm fits a decision tree to the residuals of the previous iteration. The residuals represent the errors made by the previous decision tree in the previous iteration, or the differences between the actual values and predicted values for each sample in the training dataset. The decision trees in XGBoost are trained using an objective function, which may be a loss function that quantifies the error between the model’s predictions and the actual target values in the training dataset. The objective function may also include a regularization term that controls the complexity of the model to avoid overfitting.

[0076] For example, training the XGBoost model may start with an initial prediction, such as an average or mean of some or all target values in the training dataset. In each iteration of the training process, a decision tree is built to correct the errors of decision trees generated during previous iterations. This may be done by calculating the gradients of the loss function, which represent how much the predictions need to change to reduce the error or loss. A new decision tree is built that is fit to the calculated gradients, effectively learning how to reduce the residual errors from the prior predictions. The predictions from the new decision tree arc added to the previous predictions. The contribution of each new tree is scaled by a learning rate (or shrinkage), which controls the pace of learning and helps prevent the model from overadjusting to the training data. Throughout training, hyperparameters such as the number of trees, maximumGDM 3.4-008

[0050] depth, and learning rate (or shrinkage) may be tuned to improve the model’s performance in terms of accuracy, computational complexity, and / or to optimize some other performance metric(s) and / or criteria. Any suitable hyperparameter tuning methodology may be used to tune the XGBoost model, such as grid search, Bayesian optimization hyperband, and / or the like.

[0077] Once the decision trees have been trained, XGBoost makes predictions by combining the predictions of all the decision trees using a weighted average. The weights for each tree may be learned during training process using the same objective function. This may allow the XGBoost model to learn which decision trees should be given more weight in the final prediction. After the training process has completed, the trained XGBoost model may be evaluated using the testing dataset. The accuracy of the trained XGBoost model may be assessed based on how well the trained XGBoost model predicts the values in the testing dataset. Other performance metrics, such as speed, computational load and / or resource consumption, and / or the like, may also be assessed during the testing phase. Additional or alternative aspects of XGBoost model training are discussed in [XGBoost].

[0078] Now referring to the ML flow 500b, after the training and testing phases, and assuming that predictions of the trained XGBoost model are reasonably accurate, the trained XGBoost model (e.g., ML model 566) may be deployed to the inference engine 564 in the ML flow 500b in order to make delay and area predictions for AIGs, such as new AIGs 544, during an inference phase. During the inference phase, the ML flow 500b uses features 562 extracted from the new AIG 544 and a pre-trained ML model 566 to predict the post-mapping area and delay for the new AIG 544, and uses the prediction 568 to guide the optimization.

[0079] The ML flow 500b begins with the AfG transformer f42 transforming the current AfG f40b into a new AIG 544 in the same or similar manner as discussed previously. The AIG 140b may have the same or different structure than AIG 140a and / or AIG 140 of Fig. 1. The new AIG 544 is provided to the feature extractor 560, which extracts a set of features 562 from the new AIG 544. For example, the feature extractor 560 may traverse the new AIG 544 in the same or similar manner as the graph processor 146 to. for example, count the nodes and edges in the AIG 544. identity' or determine the depth of the AIG 544, and identify or determine the occurrence of different logic elements in the AIG 544. The feature extractor 560 may then calculate a critical path by backtracking from the output to the inputs along the path with the maximum delay, and may aggregate collected values (e.g., node count, depth, critical path, number of different types of nodes, etc.) as the set of features 562. The set of features 562 may be arranged into a feature vector or other suitable data structure. Such a feature vector may be referred to herein as “feature vector 562”.

[0080] In various embodiments, the features 562 can include AIG features and gate-level features to capture critical path, load variation, and mapping behavior. The AIG features may be extracted from the AIG 544 itself, while technology mapping 506 may need to be performed on the AIG 544 to extract the gate-level features. However, in some embodiments, an abbreviated version of technology mapping 506 may be performed on the AIG 544 to obtain the gate-level features while keeping resource consumptionGDM 3.4-008

[0050] and execution time relatively low. For example, a time efficient technology mapping technique can be used as a proxy of a more robust technology mapping technique to collect gate-level features.

[0081] Example AIG features that may be collected for the ML model 566 are shown by table 1 and table2 shows example gate-level features that may be collected for the ML model 566. Additional or alternative features 562 that may be collected are shown by Fig. 9.Table 1 : AIG FeaturesTable 2: Gate-level featuresGDM 3.4-008

[0050]

[0082] It should be noted that not all of the features shown by tables 1 and 2 need to be collected in order to make area and delay predictions. For example, in some implementations, only AIG features shown by table 1 are collected during the inference phase. In other implementations, only a subset of the AIG features of table 1 are collected during the inference phase. In other implementations, a first subset of the AIG features of table 1 and a second subset of gate-level features of table 2 are collected during the inference phase. Additional or alternative combinations of features 562 may be extracted in other implementations. However, it should also be noted that, at least in some cases, using a lower number of features 562 during model training and / or inference generation could result in less accurate predictions. Example feature extraction techniques are discussed below with respect to Fig. 5B.

[0083] After the features 562 are extracted, the features 562 are provided to an inference engine 564. The inference engine 564 operates the trained ML model 566 to generate predicted delay and predicted area 568 based on the features 562. The predicted delay and predicted area 568 are provided to the reward function 550. which generates a reward value 552 in the same or similar manner as discussed previously. This reward value 552 is then provided to the AIG selector 154, which decides to keep or reject the AIG 544 based on the reward 552 in the same or similar manner as discussed previously. The inference phase of the ML flow 500b may repeat for a predefined or configured number of iterations, or until reward value 552 convergence is observed.

[0084] In some cases, such as when the circuit is relatively small or has a relatively low complexity, the runtime and / or the resource consumption for the ground-truth flow 500a may be manageable. In such cases, the ML flow 500b can be skipped and rewards 552 generated during the ground-truth flow 500a may be compared and selected by the AIG selector 154 as discussed previously. In these ways, performance gains can be realized in comparison to conventional methodologies. While this approach is not commonly used, it can be particularly beneficial for smaller-scale circuits where the runtime, resource consumption, and / or energy expenditures is / are less of an issue.

[0085] Therefore, in some embodiments, the runtime of the optimization flow 104x can be optimized. In a first example, a cap or limit on the duration of each iteration of the ground-truth flow 500a can be set toGDM 3.4-008

[0050] a predefined amount of time (e g., 0.2 seconds, 0.1 seconds per iteration, 1 second per iteration, or the like). In this example, a condition can be defined for running the ML flow 500b, such as: if each of a specified number of iterations of the ground-truth flow 500a are completed within the time cap / limit, then the ML flow 500b can be skipped and the ground-truth dataset 558 are used for AIG selection 154. Here, the AIG selection 154 may be based on the reward values 552 stored in the database 556. If the condition is not met, the ML flow 500b may be employed using the ground-truth dataset 558 from the ground-truth flow 500a as discussed previously. A variation of the first example may include running the ground-truth flow 500a for an additional number of iterations if the condition is satisfied, and not running the ground-truth flow 500a for the additional number of iterations if the condition is not satisfied. For example, the specified number of iterations may be 100,000 iterations, and if each of these iterations arc completed within the specified cap / limit, then the ground-truth flow 500a may run for an additional 900,000 iterations. A second example may be the same as the first example, except that the time cap / limit may be defined for the entire runtime / duration of the ground-truth flow 500a for a specified number of iterations.

[0086] The performance-driven logic optimization flow 104x may be plugged into any logic synthesis optimization engine that queries a cost or reward computation submodule with relatively little setup and configuration. This makes the performance-driven optimization flow 104x applicable to various types of optimization engines that may be used by different chip designers and / or manufacturers.

[0087] Additionally, it should be noted that, although the example embodiments are described as using an XGBoost model, other types of ML models / algorithms may be used to predict area and delay metrics, such as predicted delay and predicted area 568. For example, other types of gradient tree boosting technique(s), such as classification and regression tree (CART) models, bootstrap aggregated decision trees such as random forests, rotation forests, and the like, may be used as, or with, model 566. Additionally or alternatively, graph-based ML models, such as graph neural networks (GNNs), convolutional neural networks (CNNs), and the like, may be used as, or with, model 566. Additionally or alternatively, reinforcement learning (RL) technique(s), such as a Markov decision process (MDP), temporal difference learning. Q-leaming, a deep Q-network (DQN), Q*, state-action-reward-state-action (SARSA) algorithms and the like, may be used as, instead of. or with, model 566.1.2. Feature Engineering

[0088] Fig. 5B shows different examples of feature extraction for an example AIG. Specifically, Fig. 5B demonstrates how features, such as features 562. may be extracted using an example AIG with paths between three primary’ inputs (Pls) and three primary outputs (POs). In this example, the Pls include primary input 0 (piO). primary input 1 (pil) , and primary input 2 (pi2). and the POs include primary output 0 (poO), primary output 1 (pol), and primary’ output 2 (po2). Each graph 590, 592, and 594 in Fig. 5B shows a different feature extraction technique for computing depth or complexity-related features post -mapping delay estimation. Different ty pes of depth calculations for POs are shown by graphs 590, 592, and 594, which take the nodes between POs and Pls, including the nodes for PI and excluding the PO nodes (which is a gate output). Graph 592 is an example of subgraph extraction for PO.GDM 3.4-008

[0050]

[0089] Examples of the features that may be extracted for each AIG may include any of features listed in table 1 and / or table 2. In one example implementation, the features may include number of node. aig level, aig_nth_long_path_depth, aig_nth_weighted_path_depth. aig_nth_binary_weighted_path_depth. fanout mean, max, std, sum, long path fanout mean, max, std, sum, and num_of_paths. In this example implementation, the features may be based on an analysis of the sources of timing miscorrelation between AIG depth and the maximum delay of a mapped netlist. Two primary sources of this miscorrelation may be considered for the example of FIG. 5B. The first source may include the path depth change in the mapped netlist compared to the AIG structure, which impacts the number of stages in the critical path, and thus, affects the overall path delay. The second source may include the fanout change after mapping, in which several nodes in AIG arc merged into a large cell, resulting in changes to the fanout of the node driving these cells, which affects the gate delay and contributes to the miscorrelation. In some aspects, the features extracted from AIGs can be classified into three categories: (i) features associated with the critical path, (ii) features related to the fanout distribution, and (iii) features related to the structural complexity of the subgraph corresponding to each PO reflecting how the topology may affect timing after mapping.

[0090] The features associated with the critical path may include three types of features related to AIG depth such as, for example, aig nth long path depth, aig nth weighted path depth, and aig nth binary weighted path depth. Aspects of these features are discussed in relation to graphs 590. 592, and 594.

[0091] Graph 590 shows an example long path depth feature extraction technique. This feature (aig_nth_long_path_depth) may measure the raw depth of AIG paths, which may roughly model the amount of delay in the AIG. The long path depth feature extraction technique involves obtaining the largest (maximum) depth for each PO by traversing the graph 590. The depth may refer to the number of nodes between the PO and PI. excluding the PO itself. The long path depth feature extraction technique annotates each PO by listing the maximum depth from a PI. For example, in graph 590. poO is annotated with a maximum depth of 6. pol is annotated with a maximum depth of 6, and po2 is annotated with a maximum depth of 5. In some implementations, the top n maximum depths among all POs may be selected as features. Tire parameter n may be an integer value.

[0092] Graph 592 shows an example weighted path depth (by fanout) feature extraction technique. This feature (aig_nth_weighted_path_depth) may measure depth adjusted by fanout and takes the impact of fanout into account on potential critical paths. This technique may model fanout-induced delay, which may indicate how fanout-related loading delays accumulate along different paths as nodes with higher fanout may drive more outputs, and hence, may introduce more delay due to, for example, higher capacitance. The weighted path depth (by fanout) feature extraction technique annotates each node with its fanout as the weight of the node. The fanout of a node may refer to the number of other nodes that take the output of a given node as their input. Then, the graph 592 is traversed to compute the largest depth for each PO with these weights, i.e., with the fanout considered. The weighted path depth may be the total fanout values of all nodes along a path from a PI to the PO. Thus, the weighted path depth may be computed by summingGDM 3.4-008

[0050] the fanout weights of the nodes along each path from a PI to the PO. For example, in graph 592, poO is annotated with a weighted fanout path depth of 7, po 1 is annotated with a weighted fanout path depth of 7. and po2 is annotated with a weighted fanout path depth of 6. In some implementations, the top n weighted depths may be used as features.

[0093] Graph 594 shows an example binary-weighted path depth feature extraction technique. This feature (aig_nth_binary_weighted_path_depth) may measure depth adjusted by merge likelihood. Binary -weighted path depth may model mapping behavior by approximating how many structurally sticky nodes remain on each path. Structurally sticky nodes may be nodes that may be difficult to merge during mapping, which may potentially lead to longer delays. The feature aig nth binary weighted path depth considers the probability of nodes being merged into relatively large cells during mapping, which can reduce the length of some paths, and thereby reduce delay. Nodes with high fanout have a lower probability' of being merged into a large cell. In diis technique, nodes with two or more fanouts are assigned a weight of 0, while nodes with fewer than two fanouts are given a weight of 1. Then, the largest depth for each PO is updated. For instance, tire weighted path depth may be calculated using the binary weights in the same manner as discussed previously with respect to the weighted path depth (by fanout) feature extraction technique. For example, poO is annotated with a binary -weighted path depth of 3, pol is annotated with a binary -weighted path depth of 3, and po2 is annotated with a binary -weighted path depth of 2. In other words, poO and pol may each include three nodes with a fanout greater than or equal to 2, and po2 may include two nodes with a fanout greater than or equal to 2. The binary weights help model the potential reduction in path depth after mapping. In some implementations, the parameter n in this path-depth-related feature may be empirically set to 3 or some other value.

[0094] The features related to the structural complexity of a subgraph may include, for example, number_of_paths. Such features is / are discussed in relation to graph 596.

[0095] Graph 596 shows an example number of paths feature extraction technique. This feature (number_of_paths) may measure topological complexity. Additionally, this feature (number of paths) approximates the probability of a PO having multiple critical and near -critical paths and avoids explicitly enumerating all near-critical paths which is a computationally expensive step for feature extraction. To capture the complexity7of the paths to each PO, this feature extraction technique considers the number of paths by traversing the subgraph of each PO. For instance, for each PO, the number of distinct paths from each PI to the PO is counted, and the PO is annotated accordingly. For example, poO is annotated with a “2” because there may be 2 unique paths from the Pls to poO, pol is annotated with an “8” because there may be 8 unique paths from the Pls to pol, and po2 is annotated w ith a “3” because there may be 3 unique paths from the Pls to po2. In this example, the subgraph of pol is highlighted using bold (thicker) lines to show7that subgraph pol has the largest number of paths.

[0096] For the features related to fanout distribution, high-fanout nodes arc likely to have high load capacitance, which results in large gate delay. Therefore, the features related to the fanout distribution over the graph, such as fanout mean, max, std, sum, may be included. These features quantify the overall fanoutGDM 3.4-008

[0050] distribution throughout the AIGby computing the mean, maximum, standard deviation, and sum of fanouts for all nodes. If fanout is uneven across the netlist, with certain regions having much higher fanout than others, the paths with higher fanout are more likely to dominate the overall delay. Similarly, insights into how fanout distributes at different stages over a long path may be identified using the feature(s) long path fanout mean, max, std, sum. If fanout is unevenly distributed along the path, the large delays at the high- fanout stages will result in large path delay due to their higher load capacitance.

[0097] In some forms, it is possible to use GNNs for feature extraction. GNNs are, in general, good at analyzing complex data. However, as the number of features for each node in an AIG is limited, GNNs are sometimes unable to outperform decision-tree-based models on predicting the maximum delay of an AIG. It has been found that, in some cases, GNN-bascd timing prediction is 2% worse than dccision-trcc-bascd models on average across the various designs. Additionally, the training costs, in terms of computational time and resource consumption, is also much higher than the lightweight decision-tree-based model. In the context of AIGs, the features available at each node, such as fanin, fanout, or logic type, are relatively simple, and do not fully leverage the strengths of GNNs, which may explain their inability to deliver better perfonnance than decision tree models. Moreover, the maximum delay of a graph are often dominated by several long path and is not greatly affected by the remaining paths, which can be difficult for a GNN to learn based on its paradigm of message passing. Thus, in some aspects, the technology may include decision-tree-based models to extract graph-level features and / or gate level features, which may be more efficient in learning than relying on node-to-node interactions in this case, for model training. However, in some forms. GNNs or other types of machine learning algorithms / models may be used to extract graphlevel features and / or gate level features, such as when relatively complex features are used for AIG optimization.1.3. Data Gathering and Model Training

[0098] In some examples, data may be collected from eight benchmarks from the International Workshop on Logic and Synthesis (IWLS) 2024 benchmark suite for both training and testing. For each design, 40,000 unique AIGs may be generated by randomly applying a series of logic transformations using the ABC logic synthesis framework to build an initial AIG representation of the design. The maximum delay labels are generated by performing technology mapping and STA under a 130nm technology, such as SkyWater 130nm process design kit (PDK) provided by SkyWater Technology®, using the ABC framework to map each AIG to a standard cell library.

[0099] In some examples, the ML models are implemented using XGBoost. The ML model(s) is / are trained using root mean squared error (RMSE) as the loss function, and the hyperparameter values may be chosen using a suitable technique such as grid search or the like. In one example implementation, a learning rate 0.01 may be used for the XGBoost regressor, the maximum tree depth may be 16, the number of estimators may be 5000, and the subsampling ratio may be 0.8.1.4. Example ExperimentationGDM 3.4-008

[0050]

[0100] Ail experiment was performed to demonstrate the effectiveness of the example embodiments by quantifying the performance gains from performance-driven logic optimization. This experiment involved optimizing an adder design (4-bit multiplier) using a baseline flow, such as baseline flow 104a. and a performance-driven logic optimization flow, such as performance -driven logic optimization flow 104x. The SKY 130nm PDK provided by SkyWater Technology® was used as the technology / process node for the experiment. Technology7mapping was performed using the ABC “map” function of the ABC logic synthesis system, and the ABC “stime” function of the ABC logic synthesis system was used as the STA function. A hyperparameter sweep for SA was performed by vary ing the annealing schedule. Three rewards were generated for the baseline flow based on A1G features, including: AIG node count (AIG NUM AND BLOCKS), AIG depth (AIG CRITICAL PATH LENGTH), and 0.5*AIG_NUM_AND_BLOCKS + 0.5*AIG_CRITICAL_PATH_LENGTH. Additionally, three rewards were generated for the ground-truth-based flow based on AIG features, including: post-technology mapping area (POST TECHMAP AREA), post-technology mapping delay (POST TECHMAP DELAY), and 0.5*POST_TECHMAP_AREA + 0.5*POST_TECHMAP_DELAY. Results of this experiment are discussed infra with respect to Figs. 6A-9.

[0101] Figs. 6A-6B depict graphs 600 and 610, respectively, which are Pareto-front comparisons based on operating the baseline flow and ground-truth-based flow during the experiment. Graph 600 shows a plot of AIG node count vs. AIG depth for AIGs generated using the baseline flow and AIGs generated using the ground-truth-based flow. Graph 610 shows a plot of post-technology mapped area vs. post-technology mapped delay for the AIGs generated using the baseline flow and the AIGs generated using the groundtruth-based flow. In graph 610, point 612 represents an AIG having an optimal area (i.e., an “area optimal” AIG). and point 614 represents an AIG having an optimal delay (i.e., a “delay optimal” AIG). Additionally, points 616A and 616B in graph 610 are shown to have the same area. However, graph 610 also shows that the AIG represented by point 616A has 22.7% less delay (-22.7% delay) than the AIG represented by point 603B. Graphs 600 and 610 show that the ground-truth-based flow can discover AIGs / circuit designs that are not findable by the baseline flow, as well as more optimal circuit designs when compared to those found using the baseline flow. Additionally, graphs 600 and 610 show that the ground-truth-based flow can find AIGs that are of the same area, but with up to 22.7% better delay characteristics; area optimal AIGs. and delay optimal AIGs. Such AIGs may not be discoverable when using the baseline flow.

[0102] Data collection for the experiment included generating 100,000 different AIGs for the adder design (4-bit multiplier) by applying random transformations to an initial AIG. Technology mapping and STA was performed on each AIG to collect delay and area labels for each AIG. After the data collection, an XGBoost model was trained with 80% of the collected data for the optimization task. The remaining data was used for model evaluation. Optimal hyperparameters for the XGBoost model were determined using grid search, which arc shown by tabic 3.Table 3: XGB Regression ParametersGDM 3.4-008

[0050]

[0103] Figs. 7A and 7B shows graphs showing the runtime for PPA reward calculations. The runtime for PPA reward calculation includes the runtime for technology mapping plus the runtime of ST A. Graphs 700 and 702 in Fig. 7A are based on a standard cell based design. Graph 700 shows a plot of node count vs. technology mapping runtime where the ABC “map” function was used for technology mapping. Graph 702 shows a plot of node count vs. STA rimtime where the OpenSTA static timing verifier was used for ST A. Graphs 704 and 706 in Fig. 7B are based on a transistor-level design. Graph 704 shows a plot of node count vs. technology mapping runtime where a Mockturtle function was used for technology mapping. Graph 706 shows a plot of node count vs. STA runtime where a proprietary static timing analyzer was used for STA. As shown by graphs 700, 702, 704, and 706. the rimtime for PPA reward calculation scales linearly with AIG node count. The runtime for PPA reward calculation for the standard cell based design (Fig. 7A) is O(s), and the runtime for PPA reward calculation is O(min) for the transistor-level design (Fig. 7B).

[0104] Figs. 8 A, 8B, and 8C show comparison of different features used for training and testing an ML model, such as model 566, to generate AIG timing predictions. Here, features were extracted from AIGs and gate-level graphs to capture top-K critical path (e.g., the K longest paths ranked by propagation delays), load variation, and mapping behavior. Model training involved training an XGBoost model for timing prediction and using grid search to determine hyperparameter values for the model.

[0105] To represent the baseline flow, the model was trained only using AIG level count (depth) as a single feature. Fig. 8A includes graphs 800 and 802, which show maximum delay prediction vs maximum delay ground-truth values during training (graph 800) and testing (graph 802) when only AIG level is used for predicting the maximum delay.

[0106] The XGBoost model was also trained using a set of AIG features (see table 1, supra). Fig. 8B includes graphs 804 and 806, which show maximum delay prediction vs maximum delay ground-truth values during model training (graph 804) and testing (graph 806) when the set of AIG features were used for predicting the maximum delay.

[0107] The XGBoost model was also (re)trained using both AIG features and gate-level features (see tables 1 and 2, supra). Fig. 8C includes graphs 804 and 806, which show maximum delay prediction vs maximum delay ground-truth values during model training (graph 808) and testing (graph 810) when the AIG features and gate-level features were used for predicting the maximum delay.

[0108] Based on the results shown by Figs. 8A, 8B, and 8C. the XGBoost model can capture timingrelevant structural features in AIGs.

[0109] Table 4 summarizes the mean and maximum percentage error for models trained using different features, including AIG level (baseline), All AIG features, and AIG plus gate-level features. The model trained with the AIG features shows improvement on mean and maximum percentage error from a modelGDM 3.4-008

[0050] trained with only AIG depth (i.e., baseline). The model trained with the AIG features achieves 2.02% training accuracy, outperforming the AIG Level (baseline) model.Table 4

[0110] Fig. 9 shows a bar graph 900 demonstrating the importance of different features used for the model training during the experiment. Specifically, graph 900 shows the predictive performance for each considered feature in terms of F score, where a larger F score indicates a larger effect on predictive performance.

[0111] Additional experiments were conducted on eight designs from the IWLS benchmark suite (see section 1.3 above), each from a different functional category and with more than three POs, minimizing similarity between designs and ensuring diversity of the data. In these experiments, designs with fewer than three POs tend to be simpler and can be handled efficiently without using ML inference, and are therefore not considered in such experiments. The first column in Table 5 summarizes the design names used in these experiments, and the second column summarizes the number of Pls and POs. The median number of AIG nodes across the 40,000 generated AIGs for each design range from 69 to 2290 nodes, and the precise range for the set of AIGs for each benchmark is shown in the third column of table 5. Four designs are used for model training, and four designs are used for testing to evaluate the ability of the mode to be generalized to unseen designs. The prediction accuracy of the model was evaluated across all designs and the ML -based SA logic optimization flow, such as ML flow 500b, was compared against both die baseline flow, such as baseline flow 104a, and the ground-truth-based flow, such as ground-truth flow 500a.

[0112] These experiments were conducted based on the SA paradigm, which has been applied for circuit optimization w ith ML in Hillier, et al., “Learning to Design Efficient Logic Circuits”, presented at IWLS (2023). In some implementations, the ML models can also be integrated into other conventional approaches besides SA. For these experiments, SA was chosen based on consideration of two factors. The first factor is. in comparison with deterministic algorithms, SA allows accepting temporary cost-increasing solutions with a certain probability during the search process, which allows “hill-climbing” that can enable the optimization to potentially find better solutions later. The second factor is that the SA implementation allows the designer to customize methods for estimating the PPA and for tuning the weights for each component in a cost function, making it more versatile in handling complex trade-offs. All runtimes for these experiments are reported on an AMD EPYC 7B13 CPU @ 2.3GHz.Table 5GDM 3.4-008

[0050] 1.4.1. Evaluation of Model Accuracy

[0113] Table 5 summarizes the metrics for the ML model and its prediction accuracy across all designs in these experiments. The metrics used for evaluation include the mean, maximum (max), and standard deviation (std) of the absolute percent error (%error) as metrics for evaluation, where the absolute %error is the absolute difference between the ground-truth and the predicted value with respect to the ground-truth value. The results show that the average prediction error across all designs is 4.03%, demonstrating good overall accuracy, and the average standard deviation is 3.27% across the designs, and thus, the prediction for most graphs are within a relatively small error.1.4.2. Evaluation ofML-Enhanced Logic Optimization

[0114] The three flows described in section 1.4.1 were applied to the eight IWLS benchmarks and evaluated in terms of both their quality of solution and runtime. Fig. 10 shows a graph 1000, which plots the optimal AIGs from these three flows. In graph 1000, the unfilled (white) dots represent the outcomes from the baseline optimization flow, the solid-black dots represent the outcomes from the ground-truthbased flow, and the stripe-filled dots represent the outcomes from the ML-based flow. Each point in the graph 1000 corresponds to an optimal AIG obtained from a specific run of SA logic optimization flow with a certain hyperparameter setting.

[0115] A hyperparameter sweep was performed to obtain an optimal AIG for different flow settings, which involves sweeping relative weights in cost function and sweep the annealing temperature decay rate. For each flow, a Pareto-optimal curve was generated and shown in Fig. 10. The curve 1002 for the ML-based flow is very closed to the curve 1004 for the ground -truth -based flow, demonstrating that the ML-enhanced approach achieves nearly the same level of quality in terms of delay and area. Both the curves 1002 and 1004 are significantly better than curve 1006 for tire baseline optimization flow using conventional proxy metrics. This shows that the ML-based and ground-truth-based flows outperform the original approach in exploring and identifying better designs.

[0116] Table 6 summarizes the runtime of single iteration of the three different flows. The runtime for the baseline flow includes the time elapsed for applying AIG transformation, graph processing to obtain the depth and the node count of the new AIG to evaluate the cost. The runtime for ground-truth based flow requires a large additional runtime overhead for performing technology mapping and ST A on the new AIG. In contrast, the ML-based flow includes a small amount additional runtime for feature extraction and ML inference on the new AIG, but avoids costly operations of mapping and STA. The ML-based flow achieves a significant runtime reduction of 80.83% compared to the ground-truth-based flow on average and maximum 88.79% reduction across all test cases, while delivering similar quality of solution. This demonstrates that the ML-enhanced logic optimization flow, not only maintains high-quality results, but also makes substantial improvements on efficiency by generating designs of better quality with smallerGDM 3.4-008

[0050] runtime overhead. Thus, the present technology provides an improvement to the technical field of logic synthesis optimization, and provides an improvement in the functioning of the computer systems performing logic synthesis and logic optimizations.Table 62. Example Method

[0117] Fig. 13 illustrates an A1G optimization process 1300 in accordance with aspects of the present technology. Process 1300 may be performed by a computing device, such as any of the computing devices 1102, 1104, 1106 of Figs. 11-12. Process 1300 begins at operation 1302 where the computing device generates a ground-truth dataset 558 based on technology mapping 506 and STA 508 of a set of gate-level netlists 516 generated from a set of AIGs 514. At operation 1304. the computing device trains an ML model 566 based on the ground-truth dataset 558. At operation 1306, the computing device operates the trained ML model 566 to generate predicted area and delay metrics 568 for each AIG 544 in another set of AIGs 544. The predicted area and delay metrics 568 of each AIG 544 may be based on extracted features 562 of each AIG 544. At operation 1308, the computing device calculates a reward value 552 for each AIG 544 in the other set of AIGs 544 based on the predicted area and delay metrics 568. At operation 1310, the computing device selects, as an optimal AIG, one AIG544 from the other set of AIGs 544 having a best reward value 552 in comparison to other reward values 552 of other AIGs 544 in the other set of AIGs 544. In one example, the best reward value 552 may be a smallest reward value. In another example, the best reward value 552 may be a largest reward value. At operation 1312, the optimal AIG is used as a basis for other logic synthesis stages, such as performing technology mapping 106 on the optimal AIG to produce a gate-level netlist 116. After operation 1312, the gate-level netlist 116, which is based on the optimal AIG, can be used for various physical processes 120 of a digital IC design flow.3. Example System

[0118] Figs. 11-12 depict an example of a system 1100 configured to implement the technology discussed herein. In particular, Fig. 11 is a block diagram and Fig. 12 is a functional diagram, of an example system 1100 that includes a plurality of computing devices 1102, 1104, 1106 and a storage system (e.g., one or more databases) 1108 coimected via a network 1110. System 1100 may also include a fabrication facilityGDM 3.4-008

[0050] 1112 (also referred to as “fab 1112”) that is configured to produce circuitry designed according to the processes described herein.

[0119] Computing device(s) 102 may represent one or more servers and / or other physical and / or virtual computing device(s) that provide access to a pool of physical and / or virtual resources, data, services, and / or programs to other computer device(s), such as computer device(s) 1104 and / or 1106. over a network, such as network 1110. The server(s) 1102 may be implemented as web servers, application servers, email servers, file and / or storage servers, and / or rim virtual machines (VMs), containers, applications, and / or other executable code. The various servers 1102 discussed herein can be embodied as rack servers, tower servers, blade servers, microservers, converged infrastructure, hyper-converged infrastructure (HCI), edge servers, and / or the like. The servers 1102 may represent a cluster of servers, a load balanced server farm, a cloud computing scn icc / architcclurc. an edge computing network / architecture, and / or other grouping or pool of servers, which may be located in one or more datacenters and / or other sites. Additionally, the servers 1102 may be interconnected with one another using any suitable networking and / or interconnection technologies, such as Ethernet, fiber channel, data center interconnect, virtual extensible LAN, InfiniBand, switch fabrics, and / or the like.

[0120] In some examples, computing devices 1102 may exchange information with different network nodes for the purpose of receiving, processing, and transmitting the data to and from other computing devices. Here, the server(s) 1102 may handle requests from clients such as computing devices 1104, 1106 and / or fab 1112 (or computing devices therein), processes the requests, and returns appropriate responses via the network 1110. In this regard, the server(s) 1102 may provide one or more services to one or more clients. Such services may communicate with each other and / or with one or more of computing devices 1104, 1106 and / or fab 1112 (or computing devices therein) via one or more software interfaces, such as application programming interfaces (APIs), application binary interfaces (ABIs), remote procedure calls (RPCs), and / or other interfaces.

[0121] In the example of Figs. 11-12. computing device 1104 is depicted as a workstation and computing device(s) 1106 is depicted as a laptop. However, the client devices 1104. 1106 could be other types of user devices, such as smartphones, tablet computers, desktop computers, wearable devices, video game consoles, networked appliances, drones, robots, single-board computers, plug computers or dongles, and / or any type of computing devices . Additionally or alternatively, the computing devices 1102, 1104, 1106 may be implemented as part of fab 1112 and / or any other system discussed herein.

[0122] Fab 1112 may be a foundry, factory, manufacturing plant, or other location where semiconductor device fabrication takes place to produce semiconductor structures, such as integrated circuits and the like. For example, fab 1112 may include various types of fabrication equipment, robots, computing systems, and / or other systems / devices configured to perform photolithographic and physico-chemical processes during which semiconductor devices arc created on a wafer using various semiconducting matcrial(s). Such semiconductor manufacturing processes may include (not in any particular order), for example, wafer preparation (e.g., ingot growth, wafer slicing, wafer cleaning, wafer polishing, etc.), oxidation,GDM 3.4-008

[0050] photolithography (e.g., photoresist application, mask alignment, UV light exposure, etc.), etching (e.g.. wet chemical etching, dry etching, mechanical grinding, chemical mechanical planarization (CMP), etc.), ion implantation or doping, annealing (e.g., spike annealing, drive-in annealing, etc ), deposition (e.g., atomic layer deposition, molecular layer deposition, chemical vapor deposition, physical vapor deposition, conformal film deposition, etc.), planarization (e.g.. CMP, etc.), metal layer deposition and patterning, passivation, die preparation. IC packaging, IC testing, and / or other processes. Additional or alternative PCB and / or semiconductor manufacturing techniques may be used, such as silk-screen printing, photoengraving, PCB milling, laser resist ablation, laser etching, plasma exposure, thermal treatments (e.g., rapid thennal processing (RTP), furnace annealing, laser annealing, thermal oxidation, etc.), plasma ashing, epitaxy , and / or the like.

[0123] As shown in Fig. 12, each of the computing devices 1102, 1104, and 1106 may include one or more processors, memory, data and instructions. Some or all of the computing devices 1102, 1104, and 1106 may also include communication interfaces, output device(s), and / or input device(s).

[0124] The one or more processors may include one or more general-purpose processors, which may be processor(s) designed to perfonn a wide variety of tasks and / or processor(s) capable of running a broad range of applications and programs efficiently. Additionally or alternatively, the one or more processors may include one or more special-purpose processors, which may be processor(s) designed to perform specific tasks or functions with relatively high efficiency and / or processor(s) optimized for particular applications or workloads. By way of example, the one or more processors may include any number and / or combination of: central processing units (CPUs), graphical processing units (GPUs), accelerated processing units (APUs), microcontrollers, neural processing units (NPUs), tensor processing units (TPUs), hardware accelerators, p-bit devices, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, data processing units (DPUs), quantum processing units (QPUs), crypto-processors, programmable logic devices (PLDs). and / or any other hardware-based processor. References to a processor or processor(s) should be understood to include references to a single processor or a collection of processors that may or may not operate in parallel.

[0125] The memory for each computing device stores information accessible by the one or more processors, including instructions and data that may be executed or otherwise used by the processor(s). The memory’ may be of aity type capable of storing information accessible by’ the processor, including a computing device or computer-readable medium, or other medium that stores data that may be read with the aid of an electronic device, such as random access memory (RAM), read-only memory (ROM), nonvolatile RAM (NVRAM), flash memory, solid-state storage, memory cards, magnetic disk storage mediums, optical storage mediums such as CDs and DVDs, as well as other write-capable and read-only memories. Systems and methods may include different combinations of the foregoing, whereby different portions of the instructions and data arc stored on different types of media.

[0126] Tire instructions may be any set of instructions to be executed directly (such as machine code) or indirectly (such as scripts) by the processor. For example, the instructions may be stored as computingGDM 3.4-008

[0050] device code on the computing device-readable medium. In that regard, the terms “instructions” and “programs” may be used interchangeably herein. The instructions may be stored in object code format for direct processing by the processor, or in any other computing device language including scripts or collections of independent source code modules that are interpreted on demand or compiled in advance. Tire instructions may be stored in additional or alternative formats. The optimization flows shown by Figs. 1 and 5, and the process shown by Fig. ml, illustrate examples of algorithms that may be implemented according to such instructions or programs.

[0127] Tire data may be retrieved, stored or modified by one or more processors in accordance with the instructions. The data may also be formatted in any computing device-readable format. For instance, although the claimed subject matter is not limited by any particular data structure, the data may be stored in computing device registers, in relational and / or non-relational databases having a plurality of different fields and records, electronic documents (e.g., HTML, XML, JSON, Protobufs, etc.) or flat files, HDL information, GDSIf information, and / or the like. The data may also be formatted and / or stored in any computing device-readable format.

[0128] The computing devices may also include a communication system having one or more wired or wireless connections to facilitate communication with other computing devices of system 1100 and / or the fabrication facility 1112. The communication interfaces may include interconnection or network interface controllers, components, or other suitable devices to communicate with one or more peripheral devices such as input and / or output device(s), one or more databases such as database(s) 1108, and / or network nodes via one or more networks such as network 1110. For example, the communication interfaces may include wired communication components (e.g., for coupling via USB, Ethernet, fiber optics, and / or the like), cellular communication components, wireless local area network (WLAN), short range communication components, NFC components, and other communication components. It should be noted that the computing devices 1102 may also be connected to network 1110 and / or to one another via an external communication interface, such as a switch fabric, gateway node, and / or the like.

[0129] The computing devices may include all of the components normally used in connection with a computing device such as the processor and memory described above as well as a user interface having one or more input devices (e g., one or more of a button, mouse, keyboard, touch screen, touch pad, gesture input, dial, switch, microphone, sensors such as sensors including cameras and the like, etc.), various output devices (e.g.. electronic display having a screen or projector, speakers, actuators or haptic feedback devices, etc.), and / or other devices / components to enable user interaction with the computing devices.

[0130] Tire various computing devices may communicate directly or indirectly via one or more networks, such as network 1110. The network 1110 and any intervening nodes may include various configurations and protocols including wired protocols (e.g., Ethernet, etc.), fiber optics networks, cellular communication protocols (e.g., 3GPP) LTE, 3GPP 5G / NR, WiMAX, GSM, etc.), WLAN communication protocols (e.g., WiFi®, Infrared Data Association (IrDA), P2P, etc.), short range communication protocols (e.g., Bluetooth™, WiFi-direct, Miracast, ANT+, Z-Wave, Zigbee® etc.), the Internet (e.g., including HTTP,GDM 3.4-008

[0050] TCP / IP, and / or other Open Systems Interconnection (OSI) layer protocols), intranets, enterprise networks, virtual private networks, wide area networks, local networks, private networks using communication protocols proprietary to one or more companies, and various combinations of tire foregoing. Such communication may be facilitated by any device capable of transmitting data to and from other computing devices, such as modems and wireless interfaces.

[0131] Tire computing devices may be configmed to implement the logic synthesis optimization techniques discussed herein. In some examples, client computing device 1104 may be an engineering workstation used by a developer to perform circuit design and / or other processes for integrated circuit design and fabrication. Client computing device 1106 may also be used by a developer, for instance to prepare system requirements for the integrated circuit or manage the manufacturing process with the fabrication facility 1112. Servers 1102 may also be used via the client devices 1104, 1106 to perform the logic synthesis, including the performance -driven optimization flow 104x discussed previously. For example, one or more servers 1102 (or individual virtual machines or containers running on the server(s) 1102) may operate the ground-truth flow 400a in parallel to collect ground-truth data 558. Additionally, one or more servers 1102 (or individual virtual machines or containers running on the server(s) 1102) may train the ML model 566 using the ground-truth data 558 and operate the ML flow 500b to predict delay and area metrics 568 for AIGs 544 as part of the optimization stage of logic synthesis. The logic synthesis may then be used as a basis for fabricating ICs at the fab 1112.

[0132] Storage system 1108 can be of any ty pe of computerized storage capable of storing information accessible by the server computing devices 1102. 11041104 and / or 1106, such as a hard-drive, memory card, ROM, RAM. DVD, CD-ROM, flash drive and / or tape drive. In addition, storage system 1108 may include a distributed storage system where data is stored on a plurality of different storage devices which may be physically located at the same or different geographic locations. Storage system 1108 may be connected to the computing devices via the network 1110 as shown in Figs. 11-12, and / or may be directly connected to or incorporated into any of the computing devices. Storage system 1108 may store various types of information. For instance, the storage system 1108 may store one or more optimization algorithms, ground-truth data, trained ML models, AIGs, netlists, and / or other integrated circuit requirements. Alternatively or additionally, storage system 1108 may store the any final circuitry designs that may be provided for circuit fabrication by facility 1112.4. Further Remarks

[0133] For the purposes of the present disclosure, the singular forms “a,” “an” and “the” are intended to include plural forms as well, unless the context clearly indicates otherwise. The terms “comprises” and / or “comprising.” when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups and / or combinations thereof. Additionally , the phrase “A and / or B” means (A), (B), or (A and B), and the phrase “A, B, and / or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C). The phrase “X(s)” means one or more X, a set of X, or aGDM 3.4-008

[0050] plurality of X. As used herein, the term “each” refers to each member of a set or each member of a subset of a set. The phrases “in an embodiment,” “In some embodiments.” “in one implementation,” “In some implementations.” “in some examples”, and other similar phrases used herein may refer to one or more of the same or different embodiments, implementations, and / or examples. Furthermore, the terms “comprising.” “including.” “having,” and the like, as used with respect to the present.

[0134] Reference to “one or more processors” herein includes situations where a set of processors may be configured to perform one or more operations. Any combination of such a set of processors may perform individual operations or a group of operations, in series and / or in parallel. This may include two or more CPUs, GPUs, TPUs, NPUs, QPUs, ASICs, FPGAs, DSPs, PLDs (or other hardware-based processing elements), or any combination thereof. It may also include situations where the processors have multiple processing cores. Therefore, reference to “one or more” such devices do not require that all processing elements (or cores) in the set must each perform all of the operations. Rather, unless expressly stated, any one of the one or more processing elements (or cores) may perform different operations when a set of operations is indicated, and different processing elements (or cores) may perform specific operations, either sequentially or in parallel.

[0135] References to “optimization” herein includes a situation, act, process, or methodology of making something (e.g.. a design, system, decision, etc.) as efficient, functional, or effective as possible. Additionally, references to “optimal” herein may include a desirable or satisfactory end. outcome, or output. Moreover, references to an “optimum” herein may refer to the amount or degree of something that is favorable to some end and / or an extrema (maximum or minimum) point of the objective function.

[0136] Unless otherwise specifically noted, articles depicted in the drawings are not necessarily drawn to scale. In the appended drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. Like numerals having different letter suffixes may represent different instances of similar components.

[0137] Although the technology herein has been described with reference to particular embodiments and configurations, it is to be understood that these are merely illustrative of the principles and applications of the present technology. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present technology as defined by the appended claims. By way of example only, components that are illustrated as being arranged in series may have a complementary configuration in parallel; similarly, components that are illustrated as being arranged in parallel may have a complementary configuration in series.

Claims

GDM 3.4-008 [50]CLAIMS1. A computer-implemented method of And-Inverter Graph (AIG) optimization for logic synthesis, the method comprising: generating, by at least one processor, a ground-truth dataset based on technology mapping and static timing analysis of a set of gate-level netlists generated from a set of AIGs; training, by the at least one processor, a machine learning model to predict area and delay metrics based on the ground-truth dataset; generating, by the at least one processor, predicted area and delay metrics for each AIG in another set of AIGs using the trained machine learning model; calculating, by the at least one processor, a reward value for each AIG in the other set of AIGs based on the predicted area and delay metrics; selecting, by the at least one processor, as an optimal AIG, one AIG from the other set of AIGs based on a comparison of the calculated reward values; and providing, by the at least one processor, the optimal AIG to one or more physical integrated circuit design processes.

2. The method of claim 1. wherein generating the ground-truth dataset comprises: obtaining, by the at least one processor, an initial AIG produced from a register-transfer level description; generating, by the at least one processor, the set of AIGs based on the initial AIG, wherein each AIG in the set of AIGs has a different structure than the initial AIG; generating, by the at least one processor, a set of gate-level netlists from each AIG, wherein each gate-level netlist in the set of gate-level netlists corresponds to a respective AIG in the set of set of AIGs; and deriving, by the at least one processor, delay and area metrics from each gate-level netlist.

3. The method of claim 2, wherein generating the ground-truth dataset further comprises: calculating, by the at least one processor, a reward value for each gate-level netlist based on the delay and area metrics; and storing, by the at least one processor, the calculated reward value in association with corresponding ones of the set of second AIGs.

4. The method of claim 3, wherein the reward value is a weighted sum of the delay metric and the area metric of the respective gate-level netlists.

5. The method of claim 2, wherein generating the ground-truth dataset further comprises: storing, by the at least one processor, the delay and area metrics of each gate-level netlist in association with corresponding ones of the set of AIGs.GDM 3.4-008 [50]6. The method of claim 2, wherein generating the set of AIGs based on the initial AIG comprises: applying, by the at least one processor, different random transformations to the initial AIG to produce different AIGs to be part of the set of AIGs.

7. The method of claim 2. wherein generating the set of AIGs based on the initial AIG comprises: generating, by the at least one processor, at least two AIGs from the initial AIG in parallel.

8. The method of claim 2, wherein generating the set of gate-level netlists from each AIG comprises: performing, by the at least one processor, technology mapping on each AIG to produce corresponding gate-level netlists in the set of gate-level netlists.

9. The method of claim 2. wherein deriving the delay metric and the area metric from each gate-level netlist comprises: performing, by the at least one processor, static timing analysis on each gate-level netlist.

10. The method of claim 1, further comprising: extracting, by the at least one processor, a set of features from each AIG in the other set of AIGs; and operating, by the at least one processor, the trained machine learning model to generate the predicted area and delay metrics for each AIG in the other set of AIGs based on the extracted set of features.

11. A computing system, comprising: at least one memory device configured to store instructions for performing And-Inverter Graph (AIG) optimization for logic synthesis; and at least one processor connected to the at least one memory device, wherein the at least one processor is configured to execute the instructions to: generate a ground-truth dataset based on technology mapping and static timing analysis of a set of gate-level netlists generated from a set of AIGs; train a machine learning model to predict area and delay metrics based on the ground-truth dataset; generate predicted area and delay metrics for each AIG in another set of AIGs using the trained machine learning model; calculate a reward value for each AIG in the other set of AIGs based on the predicted area and delay metrics; select, as an optimal AIG. one AIG from the other set of AIGs based on a comparison of the calculated reward values; and provide the optimal AIG to one or more physical integrated circuit design processes.GDM 3.4-008 [50]12. The system of claim 11, wherein, to generate the ground-truth dataset, the at least one processor is configured to execute the instructions to: obtain an initial AIG produced from a register-transfer level description; generate tire set of AIGs based on the initial AIG, wherein each AIG in the set of AIGs has a different structure than the initial AIG; generate a set of gate-level netlists from each AIG, wherein each gate-level netlist in the set of gatelevel netlists corresponds to a respective AIG in the set of set of AIGs; and derive delay and area metrics from each gate-level netlist.

13. The system of claim 12, wherein, to generate the ground-truth dataset, the at least one processor is configured to execute the instructions to: calculate a reward value for each gate-level netlist based on the delay and area metrics, wherein the reward value is a weighted sum of the delay metric and the area metric of the respective gate-level netlists; and store the calculated reward value in association with corresponding ones of the set of second AIGs.

14. The system of claim 12, wherein, to generate the ground-truth dataset, the at least one processor is configured to execute the instructions to: store the delay and area metrics of each gate-level netlist in association with corresponding ones of the set of AIGs.

15. The system of claim 12, wherein, to generate the set of AIGs based on the initial AIG, the at least one processor is configured to execute the instructions to: apply different random transformations to the initial AIG to produce different AIGs to be part of the set of AIGs.

16. The system of claim 12. wherein, to generate the set of AIGs based on the initial AIG, the at least one processor is configured to execute the instructions to: generate at least two AIGs from the initial AIG in parallel.

17. The system of claim 12, wherein, to generate the set of gate-level netlists from each AIG, the at least one processor is configured to execute the instructions to: perform technology mapping on each AIG to produce corresponding gate-level netlists in the set of gate-level netlists.

18. The system of claim 12, wherein, to derive the delay metric and the area metric from each gate-level netlist. the at least one processor is configmed to execute the instructions to: perform static timing analysis on each gate-level netlist.

19. The system of claim 11, wherein the at least one processor is configured to execute the instructions to:GDM 3.4-008 [50] extract a set of features from each AIG in the other set of AIGs; and operate the trained machine learning model to generate the predicted area and delay metrics for each AIG in the other set of AIGs based on the extracted set of features.

20. The system of claim 11, wherein the machine learning model is an extreme gradient boosting (XGBoost) model.

Images