A method to maintain high performance of ternary neural networks in the presence of memristor failures

Abstract

The present invention belongs to the field of neural network technology, and discloses a method for maintaining high performance of a ternary neural network when a memristor fails, comprising: pre-training the ternary neural network on software to obtain weight matrices of each layer; detecting whether a memristor device in a memristor array has a stuck fault and obtaining a fault map; adjusting the memristor device in the memristor array according to the weight matrix and the fault map, that is, initializing the memristor array; performing row and column flipping operations on the memristor array according to the weight matrix and the fault map; performing row and column permutation operations on the memristor array according to the weight matrix and the fault map; and optimizing the original memristor array by adding a redundant memristor array. The present invention does not require retraining, and requires low computing power; the Hungarian algorithm used in the present invention has lower complexity than the existing KM algorithm. The present invention can enable a ternary neural network based on a memristor array to exhibit good classification accuracy even when a certain proportion of memristor devices have stuck faults.

Description

Technical Field

[0001] The present invention belongs to the technical field of neural networks, and in particular to a method for maintaining the overall high performance of a ternary neural network when a memristor in a memristor array fails. Background Art

[0002] A ternary neural network is a neural network model that reduces computational and storage requirements by limiting the weights in the network to three values ​​(+1, 0, -1). This network structure is particularly suitable for solving problems with limited memory and computing resources, and is common in deep learning applications. In addition, ternary neural networks are also widely used in image processing, speech recognition and other fields, and can provide efficient model training and inference speed. In other words, as an efficient deep learning model, ternary neural networks have received increasing attention on resource-constrained hardware devices. Because they can significantly reduce storage requirements and computing costs while maintaining high inference accuracy.

[0003] Memristor, full name memory resistor. It is a circuit device that represents the relationship between magnetic flux and charge. Memristor has the dimension of resistance, but unlike resistor, the resistance of memristor is determined by the charge flowing through it. Therefore, by measuring the resistance of memristor, we can know the amount of charge flowing through it, so it has the function of memorizing charge. In 2008, researchers from HP made nano memristor devices for the first time, which set off a wave of memristor research. The emergence of nano memristor devices is expected to realize non-volatile random access memory. In addition, the integration, power consumption and read and write speed of random access memory based on memristor are superior to traditional random access memory. In addition, memristor is the best way to realize artificial neural network synapse in hardware. Due to the nonlinear nature of memristor, chaotic circuits can be generated, which has many applications in confidential communication. Due to its small size and low energy consumption, memristor can store and process information well. The workload of a memristor is equivalent to the utility produced by more than a dozen transistors in a CPU chip. In general, memristors have the advantages of small size, low power consumption, adjustable resistance, and low volatility, and are considered to be very suitable for storing the network weights of each layer in ternary neural networks. However, immature manufacturing processes lead to a variety of faults in memristors, the most prominent of which is the stuck fault, i.e., the fixed fault. In practical applications, the stuck fault seriously reduces the overall performance of the ternary neural network based on memristors.

[0004] Memristor failures can affect the classification accuracy of neural networks, which is a technical problem that needs to be solved in this field. In the prior art, for example, the invention patent application CN202410326666.X discloses a memristor neural network fault-tolerant calculation method and system for fixed faults, including: analyzing the fixed faults existing in the memristor cross array; performing corresponding processing on the original weights of the neural network according to the analysis results, obtaining the processed weights, and mapping the processed weights to the memristor cross array for storage; defining a loss function, using the loss function to regularize the original weights of the neural network and perform weight decay processing; using a search algorithm to determine the optimal hyperparameters, complete the weight update, obtain the updated weights, and complete the learning and training of the memristor neural network. This invention can reduce the fault-tolerant hardware overhead, reduce the accuracy loss caused by fixed faults, and improve the reliability and robustness of memristor-based neural networks. In addition, invention patent CN202010325588.3 provides a method and device for generating adversarial samples, the method comprising: obtaining a hardware fault distribution map of the memristor array where the target neural network is located; determining the actual weight of the target neural network deployed on the memristor array based on the hardware fault distribution map and the weight map of the target neural network on the memristor array; updating the original training sample of the target neural network based on the actual weight and the original weight of the target neural network to obtain an adversarial sample. Thus, it is possible to use adversarial samples to find the weaknesses of the target neural network caused by hardware defects of the memristor array, thereby improving these weaknesses to enhance the robustness of the target neural network deployed on the memristor array. However, both of the above inventions first obtain adversarial samples, and then use adversarial samples to retrain the target neural network, which can improve the weakness that memristor failures will reduce the classification accuracy of the neural network.

[0005] The invention patent application CN202010355449.5 discloses a method for constructing a large-scale NCS fault-tolerant framework based on a fixed-size memristor array, which not only improves the computational reliability of the neuromorphic computing system, accelerates the running time of the framework algorithm, and greatly increases the scale of neural networks that the system can handle, but also reduces the resource consumption of the memristor array. The use of a fixed-size memristor array is more convenient for subsequent general integrated design. The purpose of this invention is also to solve the problem that memristor failures will affect the classification accuracy of neural networks. In this invention, bipartite graph matching is used to optimize the problem, and the KM algorithm used has a time complexity of o(n 3 ), that is, the complexity of the algorithm in this scheme is high.

[0006] Because the above inventions still have various shortcomings, such as the need for retraining, which requires high computing power or the need to use a highly complex KM algorithm; and the above inventions are all used for traditional neural networks, not for ternary neural networks. Therefore, the art still needs a method for maintaining the overall high performance of the ternary neural network without affecting the classification accuracy of the ternary neural network when a memristor in a memristor array has a stuck fault, that is, the art needs a method for maintaining the high performance of the ternary neural network with lower computing power and lower complexity when a memristor fails. Summary of the invention

[0007] In view of the problem that the stuck fault of the memristor seriously affects the overall performance of the ternary neural network, the present invention provides a ternary neural network fault-tolerant method based on a memristor array, that is, a method for maintaining the high performance of the ternary neural network when the memristor fails, comprising: selecting several data sets (for example: MNIST, Fashion-MNIST) to train the corresponding ternary neural network models at the software level to make the network have a higher classification accuracy. Then extract the weight matrices of each layer of the convolution layer and the fully connected layer from the pre-trained ternary neural network. Detect whether the memristor device in the memristor array used to carry the weight matrix of each layer has a stuck fault, and obtain whether its stuck state is a high resistance state or a low resistance state, so as to obtain its corresponding fault map. According to the weight matrix of each layer and the fault map corresponding to the memristor array used to carry the weight matrix, adjust the resistance state of the memristor.

[0008] The present invention first provides a method for maintaining high performance of a ternary neural network when a memristor fails, and the method at least comprises the following steps: S1, pre-training the ternary neural network: pre-training the ternary neural network on software according to a corresponding data set and obtaining weight matrices of a convolutional layer and a fully connected layer; S2, obtaining a fault map: detecting whether a memristor device in a memristor array has a stuck fault, and obtaining whether its stuck state is a high resistance state or a low resistance state, thereby obtaining its corresponding fault map; steps S1 and S2 are performed in any order; S3, initializing the memristor array: initializing the weight matrix obtained in S1 and S2 and fault map, adjust the resistance state of the memristor device in the memristor array; S4, row and column flip optimization: according to the weight matrix and fault map obtained in S1 and S2, perform row and column flip operations on the memristor array; S5, row and column replacement optimization: according to the weight matrix and fault map obtained in S1 and S2, perform row and column replacement operations on the memristor array; S6, redundant memristor array addition: optimize the original memristor array by adding a redundant memristor array; wherein steps S4 to S6 include: calculating the number of errors in each row of the weight matrix mapped to each row of the memristor array and the redundant memristor array before and after the row flip, and obtaining T 1 、T 2 、T 3 and T 4;T 1( i, j ) is a matrix T 1 A value in T 1( i, j ) represents the first i The row mapping weight matrix j The number of errors in the row; T 2( i, j ) represents the first row of the memristor array after the row flip operation. i The row mapping weight matrix j The number of errors in the row; T 3( i, j ) represents the redundant memristor array i The row mapping weight matrix j The number of errors in the row; T 4( i, j ) represents the first row of the redundant memristor array after the row flip operation. i The row mapping weight matrix j The number of errors in the row; in the matrix M are the number of rows of the memristor array; comparison T 1 、T 2 、T 3 and T 4 The size of each value, take the smaller value of each mapping relationship among the four to obtain T 5. According to H 1 Perform row permutation operation on the memristor array, according to Row_Flipping Perform row flipping operation on the memristor array and Row_submit Perform row redundancy addition operation on the memristor array; calculate the number of errors in each column of the mapping weight matrix of each column of the memristor array before and after the column flip, and obtain T 6 and T 7; T 6( i, j ) represents the first i The column mapping weight matrix j The number of errors in the column; T 7( i, j ) represents the first column of the memristor array after the column flipping operation. i The column mapping weight matrix j The number of errors in the column; in the matrix N are the number of columns of the memristor array; comparison T 6 and T 7, take the smaller value of each mapping relationship between the two to get T 8 and column flip label matrix Column_Flipping ;according to T 8 and Column_Flipping , use the Hungarian algorithm to obtain the permutation matrix H 2 .

[0009] In a specific implementation, the data set in step S1 is MNIST or Fashion-MNIST.

[0010] In a specific implementation, step S4 includes the following steps: S4a, calculating the number of errors between the weight value mapped by the memristor before and after each row of the memristor array is flipped and the target weight value, according to Y=W·X=(-W)·(-X) ,in X For input, W is the weight matrix, Y As output, if the number of errors after the row flip is less than that before the flip, the input of each row is processed in reverse; S4b, calculate the number of errors between the weight value mapped by the memristor before and after each column of the memristor array flip and the target weight value, according to －Y =(-W)·(X) If the number of errors after the column flip is less than that before the flip, the output of each column is processed in reverse; step S4a and step S4b are performed in any order.

[0011] In a specific embodiment, the matrix T 1 、T 2 、T 3. T 4. T 5. Row_Flipping , Row_ Submit , T 6. T 7. T 8. Column_Flipping and H 2 They are as follows:

[0012] .

[0013] In the present invention, in the matrix Row_submit For example i =1 and Row_subsitute(i) =3, it means that the first row of the redundant memristor array replaces the third row of the original memristor array; in the matrix H 1, for example i =2 and H 1( i ) = 4, it means that the second row of the memristor array is replaced with the fourth row of the original memristor array; in the matrix H 2, for example i =5 and H 2( i)=6, it means that the 5th column of the memristor array is replaced with the 6th column of the original memristor array.

[0014] In a specific implementation, Pytorch is used to train the ternary neural network.

[0015] The present invention also provides a memristor array for executing the above method of maintaining high performance of a ternary neural network when a memristor fails.

[0016] The present invention also provides a terminal device, comprising the memristor array as described above.

[0017] Based on the above method, the present invention constructs a three-value neural network fault tolerance method framework based on a memristor array, and reduces the impact of fixed faults of memristor devices on network performance by performing row and column flipping, row and column replacement, and redundant addition operations on the memristor array.

[0018] The beneficial effects of the present invention include: the present invention addresses the technical problem that the fixed faults of memristors may affect the classification accuracy of a ternary neural network, and combines the three fault-tolerant methods of row-column flipping, row-column permutation, and redundant memristor array addition, so that even if a certain proportion of memristors in the ternary neural network have fixed faults, a higher classification accuracy can be achieved.

[0019] Compared with the prior art, the present invention does not need to perform retraining, but instead uses flipping, replacement and redundant addition methods on the memristor array to improve the weakness that the stuck fault of the memristor will reduce the classification accuracy of the neural network. Compared with retraining, the method of the present invention requires lower computing power; and the present invention can fundamentally solve the impact of the stuck fault problem of the memristor. Compared with the prior art, the bipartite graph matching of the present invention is also mainly used in the row and column permutation operation of the memristor array. Preferably, the matching algorithm of the present invention adopts the Hungarian algorithm, and its time complexity is o(nm), that is, its time complexity is equivalent to o(n 2 ), while the time complexity of the KM algorithm used in the prior art is o(n 3 ), the time complexity of the KM algorithm is high, and the algorithm complexity used in the row-column permutation optimization of the present invention is lower. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solution of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope of protection of the present invention.

[0021] Figure 1 A flow chart of a method for maintaining high performance of a ternary neural network when a memristor fails provided by the present invention is shown.

[0022] Figure 2 The results of the effects of various methods on the accuracy recovery of the memristor ternary neural network based on the MNIST dataset are shown.

[0023] Figure 3 The results of the effects of various methods on the accuracy recovery of the memristor ternary neural network based on the Fashion-MNIST dataset are shown. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solution and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with embodiments. The specific embodiments described here are only used to explain the present invention and are not used to limit the present invention.

[0025] The optimization effects of the operations of row-column flipping, row-column replacement, and redundancy addition on a memristor array with a certain proportion of fixed faults in the present invention will be given in the specific embodiments below, and a more obvious description can be obtained from the following.

[0026] In the present invention, the memristor is a component of the memristor array. The memristor array of the present invention is composed of 2M×N memristors, and several memristors in the memristor array are prone to stuck failure. The role played by the memristor in the present invention is that the corresponding memristor array is used to carry the weight matrix of the ternary neural network.

[0027] With the widespread application of neural networks in various fields such as image segmentation, image processing, and natural language processing, researchers have gradually realized the limitations of traditional computing architectures in managing complex tasks. These architectures usually rely on the von Neumann model, which leads to data transmission bottlenecks and reduced computing efficiency. In order to meet these challenges, memristors have emerged as a new type of non-volatile memory element. Their unique adjustable resistance characteristics make them an ideal candidate for building neural network circuits.

[0028] Memristors effectively simulate the functions of biological neuron synapses, enabling circuits to exhibit learning and memory capabilities at the hardware level. Previous studies have shown that circuits built using memristors have considerable potential in improving computing efficiency, reducing power consumption, and increasing processing speed. However, stuck-at faults that occur during the manufacturing process of memristors limit the practical application of this technology. Stuck-at faults indicate that the conductance state of the memristor may be fixed at a high level or a low level, which significantly reduces the overall performance of the network.

[0029] In this embodiment, the ternary neural network is mainly composed of a convolutional layer and a fully connected layer, and the data sets MNIST and Fashion-MNIST are used to train the network structure.

[0030] For the convenience of description, the present invention adopts the following simulation experiment setting to train the ternary neural network.

[0031] Among them, Pytorch is used to train the ternary neural network, and Python is used to perform fault injection and method optimization on the memristor array to obtain the corresponding hardware network accuracy.

[0032] For the memristor model parameters, two memristors are used to form a differential pair to represent the weight value. For example, when the resistance states of a group of upper and lower memristors are high resistance and low resistance respectively, the weight value of the mapping is -1; when the resistance states of a group of upper and lower memristors are low resistance and high resistance respectively, the weight value of the mapping is 1; when the resistance states of a group of upper and lower memristors are the same, the weight value of the mapping is 0.

[0033] For the fixed fault ratio problem of the memristor array, the memristors in the memristor array will be randomly set to a fixed fault state in this example. The optimization effect of the optimization method is analyzed when the probability of the faulty memristor resistance state being fixed to the high and low resistance states is the same.

[0034] For the fault tolerance method, for the convenience of description. Figure 2 and Figure 3 In the figure, “-” means that no fault optimization method is adopted; “F” means that the row-column flipping optimization method is adopted; “FP” means that the row-column flipping and row-column permutation optimization methods are adopted; “FPR” means that the row-column flipping, row-column permutation and redundant memristor array adding optimization methods are adopted.

[0035] like Figure 1 As shown, the method comprises the following steps. Figure 1 The method for maintaining high performance of a ternary neural network when a memristor fails requires obtaining a fault map. Before the method was developed, when studying a method for solving the corresponding problem, the proportion of fixed faults in memristors in a memristor array was directly set to fixed data.

[0036] S1. Ternary neural network pre-training: Use MNIST and Fashion-MNIST data sets to train the ternary neural network respectively, and obtain the weight matrix of the corresponding network layer.

[0037] S3: Initialize the memristor array; set the proportion of fixed faults in the memristors in the memristor array to 5%, 10%, 20%, 30%, 40% and 50% and set the faulty memristors to the corresponding resistance states and distribute them evenly. According to the weight matrix obtained in S1, adjust the resistance states of the normal memristor devices in the memristor array.

[0038] S4: Optimization of row and column flipping: According to the weight matrix obtained in S1, the memristor array is optimized by using the row and column flipping method, and the values ​​of the corresponding memristors in the memristor array are adjusted. The test sets in MNIST and Fashion-MNIST are input into the memristor ternary neural network before and after the row and column flipping to obtain the corresponding classification accuracy. Figure 2 As shown in the figure, when the data set is MNIST, compared with not using any optimization method, the row-column flipping optimization method significantly improves the recovery accuracy of the memristor ternary neural network. When the fixed failure rate of the memristor is 50%, it can increase the network accuracy from 67% to 85%. Figure 3 As shown in the figure, when the data set is Fashion-MNIST, compared with not using any optimization method, the row-column flipping optimization method can greatly improve the recovery accuracy of the memristor ternary neural network. When the fixed failure rate of the memristor is 30%, it can increase the network accuracy from 34% to 62%. When the fixed failure rate of the memristor is 50%, since the data set is more complex than MNIST, the change of weight value will have a greater impact on the accuracy, and the accuracy improvement at this time is relatively low.

[0039] S5: row-column permutation optimization; according to the weight matrix obtained in S1, the row-column permutation optimization method and the row-column flipping method are used to optimize the memristor array, and the values ​​of the corresponding memristors in the memristor array are adjusted. The test sets in MNIST and Fashion-MNIST are input into the memristor ternary neural network in S4 before and after adding the row-column permutation optimization to obtain the corresponding classification accuracy. Figure 2 As shown in the figure, when the data set is MNIST, compared with the row-column flipping optimization method, the row-column flipping and row-column permutation optimization methods can further improve the recovery accuracy of the memristor ternary neural network. When the fixed failure rate of the memristor is 50%, it can restore the network accuracy to about 98% of the original; and when the fixed failure rate is less than 30%, the corresponding network accuracy can be restored to 100% of the pre-trained network accuracy on the software. Figure 3 As shown in the figure, when the data set is Fashion-MNIST, compared with the row-column flipping optimization method, the row-column flipping and row-column permutation optimization methods significantly improve the recovery accuracy of the memristor ternary neural network. When the fixed fault rate is less than 10%, the network accuracy can be restored to 100% of the pre-trained network accuracy on the software. When the fixed fault rate of the memristor is greater than 10%, the recovery accuracy is also greatly improved. For example, when the fixed fault rate of the memristor is 30%, the recovery accuracy increases from 34% to 91%.

[0040] S6: Redundant memristor array addition; Based on the weight matrix obtained in S1, the memristor array is optimized by row-column flipping optimization, row-column permutation optimization and redundant memristor array addition methods, and the values ​​of the corresponding memristors in the memristor array are adjusted. The test sets in MNIST and Fashion-MNIST are input into the memristor ternary neural network in S5 before and after the redundant memristor array is added to obtain the corresponding classification accuracy. Figure 2 As shown, when the data set is MNIST, compared with the row-column flipping and row-column permutation optimization methods, the row-column flipping, row-column permutation optimization methods and redundant memristor array addition methods have less improvement in the recovery accuracy of the memristor ternary neural network; the reason is that the row-column flipping and row-column permutation optimization methods have improved the recovery accuracy to a level close to the network accuracy pre-trained on the software. When the proportion of fixed faults in the memristor array is less than 40%, its network classification accuracy can be restored to 100% of the network accuracy pre-trained on the software. When the fixed faults of the memristor are 50%, although it is difficult to restore the classification accuracy to the original 100%, the method of optimizing the memristor array using row-column flipping optimization, row-column permutation optimization and redundant memristor array addition described in the present invention can restore the network classification accuracy to 99% of the network accuracy pre-trained on the software. As Figure 3 As shown in the figure, when the data set is Fashion-MNIST, compared with the row-column flipping and row-column permutation optimization methods, the row-column flipping, row-column permutation optimization methods and redundant memristor array addition methods have a higher improvement in the recovery accuracy of the memristor ternary neural network. When the fixed fault rate is less than 20%, the row-column flipping, row-column permutation optimization methods and redundant memristor array addition methods can restore the network accuracy to 100% of the network accuracy pre-trained on the software. When the fixed fault rate of the memristor is greater than 20%, the row-column flipping, row-column permutation optimization methods and redundant memristor array addition methods also significantly improve the network recovery accuracy; for example, when the fixed fault rate of the memristor is 50%, the recovery accuracy increases from 64% using the row-column flipping and row-column permutation optimization methods to 74%.

[0041] In summary, the present invention provides a method and a memristor array for maintaining high performance of a ternary neural network when a memristor fails. In the MNIST data set, when the fixed fault ratio in the memristor array is less than 40%, the network classification accuracy can be restored to 100% of the pre-trained network accuracy on the software; and when the fixed fault ratio in the memristor array is less than 50%, the network classification accuracy can be restored to more than 98% of the pre-trained network accuracy on the software. In the Fashion-MNIST data set, when the fixed fault ratio in the memristor array is less than 20%, the network classification accuracy can be restored to 100% of the pre-trained network accuracy on the software; and when the fixed fault ratio in the memristor array is less than 50%, the network classification accuracy can be restored to more than 74% of the pre-trained network accuracy on the software.

[0042] In general, the present invention belongs to the field of neural network technology, and discloses a method for maintaining high performance of a ternary neural network when a memristor fails, including: pre-training the ternary neural network on software to obtain weight matrices of each layer; detecting whether a memristor device in a memristor array has a stuck fault and obtaining a fault map; adjusting the memristor device in the memristor array according to the weight matrix and the fault map, that is, initializing the memristor array; performing row and column flipping operations on the memristor array according to the weight matrix and the fault map; performing row and column permutation operations on the memristor array according to the weight matrix and the fault map; and optimizing the original memristor array by adding a redundant memristor array. The present invention does not require retraining, and the required computing power is low; the Hungarian algorithm used in the present invention has lower complexity than the existing KM algorithm. The present invention can enable a ternary neural network based on a memristor array to exhibit good classification accuracy even when a certain proportion of memristor devices have stuck faults.

[0043] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions and substitutions can be made without departing from the concept of the present invention, which should be regarded as belonging to the protection scope of the present invention.

Claims

1. A method for maintaining high performance of a ternary neural network when a memristor fails, characterized in that: The method comprises at least the following steps: S1. Ternary neural network pre-training: pre-train the ternary neural network on the software according to the corresponding data set and obtain the weight matrix of the convolution layer and the fully connected layer; S2, obtaining a fault map: detecting whether the memristor device in the memristor array has a stuck fault, and obtaining whether its stuck state is a high-resistance state or a low-resistance state, thereby obtaining its corresponding fault map; step S1 and step S2 may be performed in any order; S3, memristor array initialization: adjusting the resistance state of the memristor devices in the memristor array according to the weight matrix and fault map obtained in S1 and S2; S4, row-column flip optimization: perform row-column flip operations on the memristor array according to the weight matrix and fault map obtained in S1 and S2; S5, row-column permutation optimization: perform row-column permutation operations on the memristor array according to the weight matrix and fault map obtained in S1 and S2; S6, adding redundant memristor array: optimizing the original memristor array by adding redundant memristor array; Among them, steps S4 to S6 include: calculating the number of errors in each row of the mapping weight matrix of each row of the memristor array and the redundant memristor array before and after the row flip, and obtaining T 1 、T 2 、T 3 and T 4; T 1( i, j ) is a matrix T 1 A value in T 1( i, j ) represents the first i The row mapping weight matrix j The number of errors in the row; T 2( i, j ) represents the first row of the memristor array after the row flip operation. i The row mapping weight matrix j The number of errors in the row; T 3( i, j ) represents the redundant memristor array i The row mapping weight matrix j The number of errors in the row; T 4( i, j ) represents the first row of the redundant memristor array after the row flip operation. i The row mapping weight matrix j The number of errors in the row; in the matrix M are the number of rows of the memristor array; comparison T 1 、T 2 、T 3 and T 4 The size of each value, take the smaller value of each mapping relationship among the four to obtain T 5. According to H 1 Perform row permutation operation on the memristor array, according to Row_ Flipping Perform row flipping operation on the memristor array and Row_submit Perform row redundancy addition operation on the memristor array; calculate the number of errors in each column of the mapping weight matrix of each column of the memristor array before and after the column flip, and obtain T 6 and T 7; T 6( i, j ) represents the first i The column mapping weight matrix j The number of errors in the column; T 7( i, j ) represents the first column of the memristor array after the column flipping operation. i The column mapping weight matrix j The number of errors in the column; in the matrix N are the number of columns of the memristor array; comparison T 6 and T 7, take the smaller value of each mapping relationship between the two to get T 8 and column flip label matrix Column_ Flipping ;according to T 8 and Column_Flipping , use the Hungarian algorithm to obtain the permutation matrix H 2 .

2. The method for maintaining high performance of a ternary neural network when a memristor fails according to claim 1, characterized in that: The data set in step S1 is MNIST or Fashion-MNIST.

3. The method for maintaining high performance of a ternary neural network when a memristor fails according to claim 1, characterized in that: The matrix T 1 、T 2 、T 3. T 4. T 5. Row_Flipping , Row_submit , T 6. T 7. T 8. Column_Flipping and H 2 They are as follows: 。 4. The method for maintaining high performance of a ternary neural network when a memristor fails according to claim 1, characterized in that: Use Pytorch to train the ternary neural network.

5. A memristor array, characterized in that: A method for maintaining high performance of a ternary neural network when a memristor fails as described in any one of claims 1 to 4.

6. A terminal device, characterized in that: Comprising the memristor array as claimed in claim 5.

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