Signal processing device and neural signal acquisition system

Abstract

This invention discloses a signal processing device and a neural signal acquisition system. The signal processing device includes an FPGA processing unit and a microcontroller processing unit. The FPGA processing unit is adapted to connect to an analog front-end chip, wherein the analog front-end chip is an RHD2164 chip. The microcontroller processing unit is connected to the FPGA processing unit and a host computer. The FPGA processing unit is used to perform interface protocol conversion for signals transmitted between the microcontroller processing unit and the analog front-end chip, and to perform signal preprocessing for signals transmitted between the microcontroller processing unit and the analog front-end chip. The microcontroller processing unit is used to perform signal analysis and processing for signals transmitted between the FPGA processing unit and the host computer. The signal processing device of this invention has the characteristics of short development cycle, low power consumption, small circuit area, accurate resource assessment, good functional reusability, and suitability for rapid iteration. It is also more suitable for implantable devices, enabling lower power neural signal processing and convenient development.

Description

Technical Field

[0001] This invention relates to the field of neural signal acquisition technology, and in particular to a signal processing device and a neural signal acquisition system. Background Technology

[0002] In related technologies, traditional neural signal acquisition schemes achieve neural signal acquisition and data processing by using FPGA (Field Programmable Gate Array) chips alone. This approach has problems such as difficulty in evaluating logic resources, large circuit area, excessive power consumption, long development cycle, slow iteration, and poor functional reuse. Summary of the Invention

[0003] The present invention aims to at least solve one of the technical problems existing in the prior art. To this end, the first objective of the present invention is to provide a signal processing device with the characteristics of short development cycle, low overall system power consumption, small circuit area, accurate resource assessment, good functional reusability, and suitability for rapid iteration, and is more suitable for implantable devices, enabling lower power consumption neural signal processing and convenient development.

[0004] The second objective of this invention is to provide a neural signal acquisition system.

[0005] To achieve the above objectives, the signal processing apparatus proposed in the first aspect of the present invention includes: an FPGA processing unit adapted to connect to an analog front-end chip, wherein the analog front-end chip is an RHD2164 chip; and a microcontroller processing unit connected to the FPGA processing unit and a host computer; wherein the FPGA processing unit is used to perform interface protocol conversion for signals transmitted between the microcontroller processing unit and the analog front-end chip, and to perform signal preprocessing for signals transmitted between the microcontroller processing unit and the analog front-end chip; and the microcontroller processing unit is used to perform signal analysis and processing for signals transmitted between the FPGA processing unit and the host computer.

[0006] According to the signal processing device proposed in the embodiments of the present invention, the FPGA processing unit is connected to the analog front-end chip and the microcontroller processing unit. It is used to realize interface protocol conversion of the signals transmitted between the microcontroller processing unit and the analog front-end chip, and to realize signal preprocessing of the signals transmitted between the microcontroller processing unit and the analog front-end chip, thereby enabling the microcontroller processing unit to communicate with the analog front-end chip. Furthermore, the microcontroller processing unit is used to perform signal analysis processing on the signals transmitted between the FPGA processing unit and the host computer. Thus, this application, while retaining the original signal preprocessing function of the FPGA processing unit, utilizes the microcontroller processing unit to realize signal analysis processing function. This allows the FPGA processing unit and the microcontroller processing unit to cooperate in processing neural signals. Moreover, compared to using only the FPGA chip to realize neural signal acquisition and data processing functions, the microcontroller used in this application has a shorter development cycle, lower overall system power consumption, smaller circuit area, and is more suitable for implantable devices, effectively solving the problems of long development cycles and slow iterations caused by using only the FPGA processing unit for data processing.

[0007] In some embodiments of the present invention, the communication port of the microcontroller processing unit adopts an SPI interface, the communication port of the analog front-end chip adopts a DDR interface, and the FPGA processing unit is specifically used to convert the raw neural signals sent by the analog front-end chip from the DDR data protocol format to the SPI data protocol format.

[0008] In some embodiments of the present invention, the FPGA processing unit includes: a mode control module, the input of which is connected to the microcontroller processing unit, for receiving a first digital signal sent by the microcontroller processing unit, the first digital signal carrying mode processing information; a first receiving module, the input of which is adapted to be connected to the analog front-end chip, for receiving raw neural signals sent by the analog front-end chip, and for performing interface protocol conversion on the raw neural signals; and a data processing module, the input of which is connected to the mode control module and the first receiving module, the output of which is connected to the microcontroller processing unit, the data processing module being used to perform signal preprocessing on the converted raw neural signals according to the mode processing information, and to send the preprocessed raw neural signals to the microcontroller processing unit.

[0009] In some embodiments of the present invention, the microcontroller processing unit includes at least one microcontroller. When the microcontroller processing unit includes one microcontroller, the microcontroller is used to manage the signal analysis and processing of all analog front-end chips and the host computer. Alternatively, when the microcontroller processing unit includes multiple microcontrollers, each microcontroller is used to manage the signal analysis and processing of corresponding analog front-end chips and the host computer.

[0010] In some embodiments of the present invention, the microcontroller includes: an uplink communication port connected to the host computer via a serial bus, the uplink communication port being used to realize signal transmission between the microcontroller processing unit and the host computer; a downlink communication port connected to the FPGA processing module, the downlink communication port being used to realize signal transmission between the microcontroller processing unit and the FPGA processing unit; and a signal processing module connected to the uplink communication port and the downlink communication port, the signal processing module being used to perform signal analysis and processing of the signals transmitted between the FPGA processing unit and the host computer.

[0011] In some embodiments of the present invention, the FPGA processing unit includes a mode control port, an uplink transmit port, and an uplink receive port. The mode control port is connected to the input terminal of the mode control module. The microcontroller processing unit includes a microcontroller. The downlink communication port of the microcontroller includes a downlink control port, a downlink transmit port, and a downlink receive port. The downlink control port is connected to the mode control port. The downlink transmit port is connected to the uplink receive port of the FPGA processing unit so that the FPGA processing unit forwards the downlink signal of the microcontroller to the analog front-end chip. The downlink receive port is connected to the uplink transmit port of the FPGA processing unit.

[0012] In some embodiments of the present invention, the FPGA processing unit includes a mode control port and an uplink transmission port, the mode control port being connected to the input terminal of the mode control module; the microcontroller processing unit includes a microcontroller, the downlink communication port of the microcontroller including a downlink control port, a downlink transmission port, and a downlink receiving port, the downlink control port being connected to the mode control port, the downlink transmission port being connected to the receiving port of the analog front-end chip to transmit downlink signals to the analog front-end chip, and the downlink receiving port being connected to the uplink transmission port of the FPGA processing unit.

[0013] In some embodiments of the present invention, the FPGA processing unit includes a mode control port, an uplink transmit port, and an uplink receive port. The mode control port is connected to the input terminal of the mode control module. The microcontroller processing unit includes multiple microcontrollers, including: a master microcontroller, whose downlink communication port includes a downlink control port, a downlink transmit port, and a first downlink receive port. The downlink control port of the master microcontroller is connected to the mode control port. The downlink transmit port of the master microcontroller is connected to the uplink receive port of the FPGA processing unit so that the FPGA processing unit forwards the downlink signal of the microcontroller to the analog front-end chip. The first downlink receive port of the master microcontroller is connected to the uplink transmit port of the FPGA processing unit. At least one slave microcontroller, whose downlink communication port includes a second downlink receive port. The second downlink receive port of the slave microcontroller is connected to the uplink transmit port of the FPGA processing unit.

[0014] In some embodiments of the present invention, the FPGA processing unit includes a mode control port and an uplink transmission port. The mode control port is connected to the input terminal of the mode control module. The microcontroller processing unit includes multiple microcontrollers, including: a master microcontroller, whose downlink communication port includes a downlink control port, a downlink transmission port, and a first downlink receiving port. The downlink control port of the master microcontroller is connected to the mode control port. The downlink transmission port of the master microcontroller is connected to the receiving port of the analog front-end chip to transmit downlink signals to the analog front-end chip. The first downlink receiving port of the master microcontroller is connected to the uplink transmission port of the FPGA processing unit. At least one slave microcontroller, whose downlink communication port includes a second downlink receiving port. The second downlink receiving port of the slave microcontroller is connected to the uplink transmission port of the FPGA processing unit.

[0015] In some embodiments of the present invention, the FPGA processing unit further includes: an asynchronous FIFO module, the input of which is connected to the uplink receiving port of the FPGA processing unit, and the asynchronous FIFO module is connected to the analog front-end chip through the downlink transmitting port of the FPGA processing unit. The asynchronous FIFO module is used for asynchronous transmission and buffering of the downlink signal. The mode control module is also used to receive a second digital signal sent by the microcontroller processing unit, the second digital signal carrying at least one or more of data format information and data transmission ID information. The output of the mode control module is also connected to the downlink transmitting port of the FPGA processing unit to transmit the second digital signal through the downlink transmitting port, wherein the data format information is a 16-bit data format or an 8-bit data format.

[0016] To achieve the above objectives, a neural signal acquisition system according to a second aspect of the present invention includes: at least one analog front-end chip, wherein the analog front-end chip is an RHD2164 chip; and a signal processing device as described in any of the above embodiments, wherein the signal processing device is connected to the analog front-end chip.

[0017] The neural signal acquisition system proposed in this embodiment of the invention is based on the connection between a signal processing device and an analog front-end chip. The signal processing device can perform neural signal acquisition and signal analysis processing on the analog front-end chip. The signal processing device uses a processing unit to realize the interface protocol conversion and signal preprocessing of the signals transmitted between the microcontroller processing unit and the analog front-end chip. Then, the microcontroller processing unit performs signal analysis processing. Compared with using an FPGA chip alone to realize neural signal acquisition and data processing functions, it has the characteristics of short development cycle, low overall system power consumption, small circuit area, accurate resource assessment, good functional reusability, and suitability for rapid iteration. It is also more suitable for implantable devices, enabling lower power neural signal processing and convenient development.

[0018] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0019] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0020] Figure 1 This is a block diagram of a signal processing apparatus according to an embodiment of the present invention;

[0021] Figure 2 This is a timing diagram of a DDR interface according to an embodiment of the present invention;

[0022] Figure 3 This is a timing diagram of a standard SPI interface according to an embodiment of the present invention;

[0023] Figure 4 A block diagram of an FPGA processing unit according to an embodiment of the present invention;

[0024] Figure 5 This is a connection block diagram of a single microcontroller and an FPGA processing unit according to an embodiment of the present invention;

[0025] Figure 6 This is a connection block diagram of a single microcontroller and an FPGA processing unit according to another embodiment of the present invention;

[0026] Figure 7This is a block diagram showing the connection between multiple microcontrollers and FPGA processing units according to an embodiment of the present invention;

[0027] Figure 8 This is a block diagram showing the connection between multiple microcontrollers and FPGA processing units according to another embodiment of the present invention;

[0028] Figure 9 This is a block diagram of an FPGA processing unit according to another embodiment of the present invention;

[0029] Figure 10 This is a block diagram of a neural signal acquisition system according to an embodiment of the present invention.

[0030] Figure label:

[0031] Signal processing device 100;

[0032] Neural signal acquisition system 1000;

[0033] FPGA processing unit 10, microcontroller processing unit 20, analog front-end chip 30, host computer 40;

[0034] Mode control module 11, first receiving module 12, data processing module 13, asynchronous FIFO module 14, downlink transmission port of FPGA processing unit 15, mode control port 16, uplink receiving port 17, uplink transmission port 18;

[0035] Microcontroller 2, master microcontroller 21, slave microcontroller 22. Detailed Implementation

[0036] The embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. The embodiments of the present invention are described in detail below.

[0037] In related technologies, FPGA processing units are used alone to implement neural signal acquisition and data processing functions. Specifically, the FPGA chips that meet these requirements are from many years ago, with the common manufacturing process remaining at 130nm. These chips have poor low-power performance, and the logic units in low-power FPGA chips are insufficient to meet the logic scale required for high-throughput neural signal acquisition. Furthermore, the required logic resource size can only be determined after all functional designs of the FPGA system are completed. Usually, small-package chips have insufficient logic resources, requiring larger-area chips, which increases the system design area and power consumption. Secondly, FPGA-based system design requires precise digital logic, resulting in long development cycles, poor functional reuse, and even small changes in requirements can lead to extensive redesign, making it unsuitable for rapid iteration.

[0038] To address the aforementioned issues, the first aspect of this invention proposes a signal processing device that features a short development cycle, low overall system power consumption, small circuit area, accurate resource assessment, good functional reusability, and suitability for rapid iteration. Furthermore, it is more suitable for implantable devices, enabling lower power consumption neural signal processing and convenient development.

[0039] The following is for reference. Figure 1 The signal processing apparatus 100 according to an embodiment of the present invention includes an FPGA processing unit 10 and a microcontroller processing unit 20. The FPGA processing unit 10 is adapted to connect to an analog front-end chip 30, wherein the analog front-end chip 30 is an RHD2164 chip. The microcontroller processing unit 20 is connected to the FPGA processing unit 10 and a host computer 40. The FPGA processing unit 10 is used to perform interface protocol conversion of the signals transmitted between the microcontroller processing unit 20 and the analog front-end chip 30, and to perform signal preprocessing of the signals transmitted between the microcontroller processing unit 20 and the analog front-end chip 30. The microcontroller processing unit 20 is used to perform signal analysis and processing of the signals transmitted between the FPGA processing unit 10 and the host computer 40.

[0040] The analog front-end chip 30 is used to acquire neural signals, and the host computer 40 is used to display or record the neural signals after signal analysis and processing. The host computer 40 can be a PC, mobile phone, iPad, etc., without specific limitations. The analog front-end chip 30 can be an Intan RHD2164 chip, the microcontroller of the microcontroller processing unit 20 can be an STM32U5 series, and the FPGA processing unit 10 can use Lattice ice40LP series or Gowin GW1N series chips. Since the communication interface of the microcontroller processing unit 20 is an SPI interface, while the communication interface of the analog front-end chip 30 is a non-standard SPI interface, their interface protocols are different. Therefore, the microcontroller processing unit 20 and the analog front-end chip 30 cannot communicate directly. The FPGA processing unit 10 can be used to implement interface protocol conversion for signals transmitted between the microcontroller processing unit 20 and the analog front-end chip 30. Specifically, the FPGA processing unit 10 can be used to write an interface that conforms to the acquisition logic of the analog front-end chip 30 to acquire neural signals, thereby realizing signal transmission between the microcontroller processing unit 20 and the analog front-end chip 30, and further enabling the microcontroller processing unit 20 to perform signal analysis and processing on the signals transmitted between the FPGA processing unit 10 and the host computer 40. In some embodiments, the host computer 40 and the microcontroller processing unit 20 can choose to use common serial buses such as UART (Universal Asynchronous Receiver / Transmitter) or SPI (Serial Peripheral Interface) for data transmission.

[0041] Specifically, existing technologies rely solely on FPGA chips to implement all processing of neural signals, namely signal preprocessing and signal analysis. Therefore, FPGA-based system designs require precise digital logic, have long development cycles, poor functional reuse, and even minor changes in requirements can lead to extensive redesigns, making them unsuitable for rapid iteration. To address these issues, this application designs an FPGA processing unit 10 and a microcontroller processing unit 20 that work together to process neural signals. The FPGA processing unit 10 retains general signal processing functions, namely signal preprocessing. In other words, signal preprocessing can be understood as some general functions that must be processed for all neural signals, such as basic processing procedures like data filtering, data smoothing, and threshold comparison. Typically, all data must undergo signal preprocessing before subsequent signal analysis. Signal preprocessing is relatively simple and widespread, so the signal preprocessing function is implemented by the FPGA processing unit 10. This reduces the frequency of subsequent development and iteration of the FPGA processing unit 10 and also reduces the logic resources and design area of ​​the FPGA processing unit 10, making it suitable for low-power FPGA chips with small to medium logic resources. Meanwhile, leveraging the advantages of C language programming development cycle, low overall system power consumption, and smaller circuit area of ​​microcontrollers, the complex and specialized signal analysis and processing functions are implemented by the microcontroller processing unit 20. Signal analysis and processing can be understood as specific functions involving the analysis, processing, and application of signals. In other words, developers typically design and develop specific systems based on the end-use requirements or iterative upgrade needs of neural signals. Different end-use requirements or iterative upgrade needs will result in different signal analysis and processing processes. Therefore, considering that microcontroller resources are mainly on-chip RAM and Flash, this application assesses whether the selected chip meets the requirements before the project begins, ensuring a clear upper limit for system power consumption that does not exceed expectations. Thus, the microcontroller processing unit 20 is designed to undertake the signal analysis and processing functions. This leverages its advantages of fast programming development cycle, good functional reusability, and suitability for rapid iteration to solve the problem of slow FPGA chip iteration. Therefore, in the event of changes in requirements or functional upgrades, there is no need to redesign the FPGA processing unit 10; only the microcontroller processing unit 20 needs to be designed and developed to achieve rapid system iteration, greatly shortening the development cycle and improving functional reusability.

[0042] In some embodiments, the microcontroller processing unit 20 implements the main data processing functions. Compared to using the FPGA processing unit 10 alone to implement neural signal acquisition and data processing functions, modern low-power microcontrollers use a 40nm process, run at a maximum clock speed of 160MHz, have sufficient performance to process neural signals, and have excellent low-power performance.

[0043] According to the signal processing apparatus 100 proposed in this embodiment of the invention, the FPGA processing unit 10 is connected to the analog front-end chip 30 and the microcontroller processing unit 20. It is used to perform interface protocol conversion of signals transmitted between the microcontroller processing unit 20 and the analog front-end chip 30, and to perform signal preprocessing of signals transmitted between the microcontroller processing unit 20 and the analog front-end chip 30, thereby enabling the microcontroller processing unit 20 to communicate with the analog front-end chip 30. Furthermore, the microcontroller processing unit 20 is used to perform signal analysis and processing of signals transmitted between the FPGA processing unit 10 and the host computer 40. This application retains the original signal preprocessing function of the FPGA processing unit 10 and uses the microcontroller processing unit 20 to realize the signal analysis and processing function. This allows the FPGA processing unit 10 and the microcontroller processing unit 20 to cooperate to realize the processing of neural signals. Moreover, compared with using only the FPGA chip to realize the neural signal acquisition and data processing function, the microcontroller used in this application has a shorter development cycle, lower overall system power consumption, smaller circuit area, and is more suitable for implantable devices. It effectively solves the problems of long development cycle and slow iteration caused by using the FPGA processing unit 10 alone for data processing.

[0044] In some embodiments of the present invention, the communication port of the microcontroller processing unit 20 adopts the SPI interface, the communication port of the analog front-end chip 30 adopts the DDR (Double Data Rate Synchronous Dynamic Random Access Memory) interface, and the FPGA processing unit 10 is specifically used to convert the raw neural signals sent by the analog front-end chip 30 from the DDR data protocol format to the SPI data protocol format.

[0045] For details, please refer to Figure 2 As shown, the characteristic of DDR timing is that data is output in MISO on both rising and falling edges of the 16 SCLK clock cycles, with the data empty on the first rising edge and the last data latched on the rising edge of CS; while the reference... Figure 3 As shown, the standard SPI timing is characterized by transmitting 16 bits of data over 16 clock cycles. However, for the DDR interface, data groups A and B alternate bitwise during data transmission. Therefore, the data transmission timing of the DDR interface differs from that of the SPI interface. Consequently, the raw neural signals sent by the analog front-end chip 30 are not easily processed by the microcontroller processing unit 20. Therefore, in this application, the FPGA processing unit 10 converts the raw neural signals sent by the analog front-end chip 30 from the DDR data protocol format to the SPI data protocol format, for example, referring to... Figure 2 and Figure 3As shown, the original neural signal, in DDR data protocol format (A0 B0 A1 B1…A15 B15), is converted to SPI data protocol format (A0 A1 A2…A15, B0B1 B2…B15). The converted original neural signal is then sent to the microcontroller processing unit 20, enabling signal transmission between the microcontroller processing unit 20 and the analog front-end chip 30. During data transmission, the MSB (Maximum Significant bit) comes first, followed by the LSB (Less Significant bit).

[0046] In some embodiments of the present invention, such as Figure 4 As shown, the FPGA processing unit 10 includes a mode control module 11, a first receiving module 12, and a data processing module 13. The input terminal of the mode control module 11 is connected to the microcontroller processing unit 20 and is used to receive a first digital signal sent by the microcontroller processing unit 20. The first digital signal carries mode processing information. The input terminal of the first receiving module 12 is adapted to connect to the analog front-end chip 30 to receive the raw neural signal sent by the analog front-end chip 30 and to perform interface protocol conversion on the raw neural signal. The input terminal of the data processing module 13 is connected to the mode control module 11 and the first receiving module 12, and the output terminal of the data processing module 13 is connected to the microcontroller processing unit 20. The data processing module 13 is used to perform signal preprocessing on the converted raw neural signal according to the mode processing information and send the preprocessed raw neural signal to the microcontroller processing unit 20.

[0047] The pattern processing information refers to the control signals sent by the microcontroller processing unit 20. The data processing module 13 can perform signal preprocessing on the raw neural signals according to the pattern processing information, including selecting the data receiving format and selecting the data processing mode. The data processing modes include filtering, threshold comparison, and raw data mode. Preprocessing is the signal processing process performed according to the pattern processing information.

[0048] For example, the filtering mode can filter the original neural signal as needed; the threshold comparison mode is to compare the original neural signal with a threshold, that is, first set a threshold range, and then compare the original neural signal with the threshold; the raw data mode does not process the original neural signal and directly outputs the original neural signal.

[0049] Additionally, the first receiving module 12 receives the raw neural signals collected by the analog front-end chip 30 and performs interface protocol conversion on the raw neural signals. For example, it converts the non-standard SPI interface protocol (such as DDR interface) of the analog front-end chip 30 into an interface protocol that the microcontroller processing unit 20 can recognize, such as the standard SPI interface protocol, so as to realize the signal transmission between the analog front-end chip 30 and the microcontroller processing unit 20.

[0050] Specifically, the microcontroller and the FPGA processing unit 10 can use the SPI protocol for signal transmission. The SPI protocol is suitable for a master-slave scenario and includes four signal lines: SCLK, CS, MISO, and MOSI. SCLK is the clock signal, CS is the chip select signal, MISO is the master input and slave output signal, and MOSI is the master output and slave input signal. When the microcontroller sends signals to the FPGA processing unit 10, the microcontroller operates in master mode, and the FPGA processing unit 10 operates in slave mode. When the microcontroller is in master mode for SPI communication, the FPGA processing unit 10 and each analog front-end chip 30 share the SPI clock signal (SCLK) and the independent SPI chip select signal (CS) of each analog front-end chip 30. When the FPGA processing unit 10 sends signals to the microcontroller, the FPGA processing unit 10 operates in master mode, and the microcontroller operates in slave mode. The number of SPI interfaces required is the same as the number of microcontrollers; that is, each microcontroller needs an independent SPI interface.

[0051] In some embodiments of the present invention, the microcontroller processing unit 20 includes at least one microcontroller. When the microcontroller processing unit 20 includes one microcontroller, the microcontroller is used to manage the signal analysis and processing of all signals transmitted between the analog front-end chips 30 and the host computer 40. Alternatively, when the microcontroller processing unit 20 includes multiple microcontrollers, each microcontroller is used to manage the signal analysis and processing of the corresponding portion of the signals transmitted between the analog front-end chips 30 and the host computer 40.

[0052] Specifically, the FPGA processing unit 10 can be connected to one or more analog front-end chips 30, providing flexible expansion. If a single microcontroller can independently handle the signal analysis and processing functions of multiple analog front-end chips 30, then the microcontroller processing unit 20 can include one microcontroller that manages the signal analysis and processing of all signals transmitted between the analog front-end chips 30 and the host computer 40. Alternatively, if a single microcontroller cannot independently handle the signal analysis and processing functions of multiple analog front-end chips 30, then the microcontroller processing unit 20 can include multiple microcontrollers, including a master microcontroller and slave microcontrollers. Each microcontroller can correspond to one or some of the analog front-end chips 30. In other words, each microcontroller manages the signal analysis and processing of the signals transmitted between its corresponding portion of the analog front-end chips 30 and the host computer 40. This reduces the amount of signal analysis and processing required by each microcontroller and greatly improves the signal analysis and processing speed.

[0053] In some embodiments of the present invention, the microcontroller includes an uplink communication port, a downlink communication port, and a signal processing module. The uplink communication port is connected to the host computer 40 via a serial bus and is used to realize signal transmission between the microcontroller processing unit 20 and the host computer 40. The downlink communication port is connected to the FPGA processing module and is used to realize signal transmission between the microcontroller processing unit 20 and the FPGA processing unit 10. The signal processing module is connected to the uplink communication port and the downlink communication port and is used to realize signal analysis and processing of the signals transmitted between the FPGA processing unit 10 and the host computer 40.

[0054] Based on the above, the microcontroller can realize signal transmission between the microcontroller processing unit 20 and the host computer 40 through the uplink communication port, and realize signal transmission between the microcontroller processing unit 20 and the FPGA processing unit 10 through the downlink communication port. The signal processing module can realize signal analysis and processing of the signals transmitted between the FPGA processing unit 10 and the host computer 40, and can send the neural signals after signal analysis and processing to the host computer 40 for subsequent analysis and use.

[0055] In some embodiments of the present invention, the FPGA processing unit 10 includes a mode control port, an uplink transmit port, and an uplink receive port. The mode control port is connected to the input terminal of the mode control module 11. The microcontroller processing unit 20 includes a microcontroller. The downlink communication port of the microcontroller includes a downlink control port, a downlink transmit port, and a downlink receive port. The downlink control port is connected to the mode control port. The downlink transmit port is connected to the uplink receive port of the FPGA processing unit 10 so that the FPGA processing unit 10 forwards the downlink signal of the microcontroller to the analog front-end chip 30. The downlink receive port is connected to the uplink transmit port of the FPGA processing unit 10.

[0056] The mode control port can be a GPIO (General Purpose Input Output) port, or it can read and write registers through an additional SPI interface to control the internal mode of the FPGA processing unit 10.

[0057] In some embodiments, because the port type used by the microcontroller is different from the interface type used by the analog front-end chip 30, there will be a problem of different data transmission timing. For example, taking the analog front-end chip 30 using a DDR interface and the microcontroller using an SPI interface as an example, the DDR interface sends data simultaneously on both the rising and falling edges of the CLK clock, while the SPI interface usually sends data on either the rising or falling edge of the CLK clock. Therefore, the data transmission rate of the DDR interface is twice that of the ordinary SPI interface. Thus, the CLK rate of the converted SPI interface must be at least twice that of the original DDR interface to ensure real-time data transmission. Therefore, to accommodate situations where the microcontroller's SPI transmission timing does not meet the timing requirements of the analog front-end chip 30, this application sets the downlink communication port of the microcontroller to be directly connected to the port of the FPGA processing unit 10 in a one-to-one correspondence. That is, the FPGA processing unit 10 isolates the microcontroller from the analog front-end chip 30 in the middle. Specifically, the data acquisition of the analog front-end chip 30 includes two parts: a transmission part and a reception part. When the microcontroller's transmission timing does not meet the timing requirements of the analog front-end chip 30, for example, when the microcontroller interface is a standard SPI interface while the analog front-end chip 30 is a DDR interface, the microcontroller and the analog front-end chip 30 cannot be directly connected. An FPGA processing unit 10 is needed to isolate the microcontroller processing unit 20 and the analog front-end chip 30, enabling interface protocol conversion for signals transmitted between them. Furthermore, the FPGA processing unit 10 can receive signals from the microcontroller to be sent to the analog front-end chip 30 by setting an uplink receive port.

[0058] Understandably, when the number of analog front-end chips (30) is small or the amount of signal analysis and processing required is small, a single microcontroller can perform all signal analysis and processing functions. In this case, a single microcontroller can be used for signal analysis and processing, such as... Figure 5As shown, in the case where the microcontroller processing unit 20 includes a single microcontroller, the microcontroller 2 and the analog front-end chip 30 transmit signals through the FPGA processing unit 10. The mode control port of the FPGA processing unit 10 is connected to the downlink control port of the microcontroller 2, and is used to transmit the first digital signal sent by the microcontroller processing unit 20 to the mode control module 11. The uplink transmission port of the FPGA processing unit 10 is connected to the downlink reception port of the microcontroller 2, and is used to transmit the raw neural signal preprocessed by the data processing module 13 to the microcontroller 2 for subsequent signal processing and signal analysis. The uplink reception port of the FPGA processing unit 10 is connected to the downlink transmission port of the microcontroller 2, and is used to directly forward the data from the microcontroller 2 to the analog front-end chip 30.

[0059] In some embodiments of the present invention, the FPGA processing unit 10 includes a mode control port and an uplink transmission port, the mode control port being connected to the input terminal of the mode control module 11; the microcontroller processing unit 20 includes a microcontroller, the downlink communication port of the microcontroller including a downlink control port, a downlink transmission port and a downlink receiving port, the downlink control port being connected to the mode control port, the downlink transmission port being connected to the receiving port of the analog front-end chip 30 to send downlink signals to the analog front-end chip 30, and the downlink receiving port being connected to the uplink transmission port of the FPGA processing unit 10.

[0060] Specifically, if the microcontroller's data transmission timing meets the data reception timing requirements of the analog front-end chip 30, this application allows the microcontroller's downlink transmission port to be directly connected to the analog front-end chip 30. This allows the microcontroller to directly send signals to the analog front-end chip 30 without requiring the FPGA processing unit 10 to receive and forward the data sent by the microcontroller. See details for further information. Figure 6 As shown, the downlink transmitting port of the microcontroller 2 is connected to the receiving port of the analog front-end chip 30 to send downlink signals to the analog front-end chip 30.

[0061] In some embodiments of the present invention, the FPGA processing unit 10 includes a mode control port, an uplink transmit port, and an uplink receive port. The mode control port is connected to the input terminal of the mode control module 11. The microcontroller processing unit 20 includes multiple microcontrollers, including: a master microcontroller, whose downlink communication port includes a downlink control port, a downlink transmit port, and a first downlink receive port. The downlink control port of the master microcontroller is connected to the mode control port. The downlink transmit port of the master microcontroller is connected to the uplink receive port of the FPGA processing unit 10 so that the FPGA processing unit 10 forwards the downlink signal of the microcontroller to the analog front-end chip 30. The first downlink receive port of the master microcontroller is connected to the uplink transmit port of the FPGA processing unit 10. At least one slave microcontroller, whose downlink communication port includes a second downlink receive port. The second downlink receive port of the slave microcontroller is connected to the uplink transmit port of the FPGA processing unit 10.

[0062] If there are many analog front-end chips 30, more than one microcontroller may be needed for signal analysis and processing. One of these microcontrollers needs to be the master microcontroller, which needs to be configured with both a transmitting and receiving module. The remaining microcontrollers are slave microcontrollers, which only need to be configured with a receiving module.

[0063] In some embodiments, to address situations where the SPI transmission timing of the microcontroller does not meet the timing requirements of the analog front-end chip 30, this application configures each microcontroller's downlink communication port to be directly connected to a port of the FPGA processing unit 10 in a one-to-one correspondence. That is, the FPGA processing unit 10 isolates each microcontroller from the analog front-end chip 30 in the middle. Specifically, signal transmission between the microcontroller processing unit 20 and the analog front-end chip 30 is achieved through the FPGA processing unit 10. Figure 7 As shown, in the case where the microcontroller processing unit 20 includes multiple microcontrollers, the master microcontroller 21 is used to manage the signal analysis and processing of the signals transmitted between the analog front-end chip 30 and the host computer 40, as well as the transmission of control signals, while the slave microcontroller 22 is only used to manage the signal analysis and processing of the signals transmitted between the corresponding analog front-end chip 30 and the host computer 40.

[0064] Furthermore, the mode control port of the FPGA processing unit 10 is internally connected to the input terminal of the mode control module 11 and externally connected to the downlink control port of the main microcontroller 21, used by the FPGA processing unit 10 to receive the first digital signal sent by the main microcontroller 21 of the microcontroller processing unit 20; the uplink transmission port of the FPGA processing unit 10 is connected to the first downlink receiving port of the main microcontroller 21 and the second downlink receiving port of the slave microcontroller 22, used to forward the raw neural signals from the analog front-end chip 30 to the corresponding microcontroller, thereby realizing signal analysis and processing of the signals transmitted between the corresponding analog front-end chip 30 and the host computer 40 managed by each microcontroller; the uplink receiving port of the FPGA processing unit 10 is connected to the downlink transmission port of the main microcontroller 21, used to receive the downlink signals of the main microcontroller 21 and transmit them to the asynchronous FIFO module, thereby realizing the forwarding of the downlink signals of the main microcontroller 21 to the analog front-end chip 30.

[0065] In some embodiments of the present invention, such as Figure 4 As shown, the FPGA processing unit 10 includes a mode control port 16 and an uplink transmission port 18. The mode control port 16 is connected to the input terminal of the mode control module 11. The microcontroller processing unit 20 includes multiple microcontrollers, including: a master microcontroller 21, whose downlink communication port includes a downlink control port, a downlink transmission port, and a first downlink receiving port. The downlink control port of the master microcontroller 21 is connected to the mode control port 16. The downlink transmission port of the master microcontroller 21 is connected to the receiving port of the analog front-end chip 30 to send downlink signals to the analog front-end chip 30. The first downlink receiving port of the master microcontroller 21 is connected to the uplink transmission port 18 of the FPGA processing unit 10. At least one slave microcontroller 22, whose downlink communication port includes a second downlink receiving port. The second downlink receiving port of the slave microcontroller 22 is connected to the uplink transmission port 18 of the FPGA processing unit 10.

[0066] Specifically, if the data transmission timing of the microcontroller meets the data reception timing requirements of the analog front-end chip 30, this application configures the downlink transmission port of the main microcontroller 21 to directly transmit signals with the analog front-end chip 30. When the microcontroller processing unit 20 includes multiple microcontrollers, refer to... Figure 8As shown, the mode control port 16 is connected to the downlink control port of the main microcontroller 21 and is used to receive the first digital signal sent by the main microcontroller 21; the uplink transmission port 18 of the FPGA processing unit 10 is connected to the first downlink receiving port of the main microcontroller 21 and the second downlink receiving port of the slave microcontroller 22, and is used to forward the raw neural signals from the analog front-end chip 30 to the corresponding microcontroller, thereby realizing the signal analysis and processing of the signals transmitted between the corresponding analog front-end chip 30 and the host computer 40 managed by each microcontroller; the downlink transmission port of the main microcontroller 21 is directly connected to the analog front-end chip 30, which can realize the signal transmission from the main microcontroller 21 to the analog front-end chip 30.

[0067] In some embodiments of the present invention, the FPGA processing unit 10 further includes an asynchronous FIFO (First in First out) module, such as... Figure 9 As shown, the input terminal of the asynchronous FIFO module 14 is connected to the uplink receiving port 17 of the FPGA processing unit 10. The asynchronous FIFO module 14 is connected to the analog front-end chip 30 through the downlink transmitting port 15 of the FPGA processing unit. The asynchronous FIFO module 14 is used for asynchronous transmission and buffering of the downlink signal. The mode control module 11 is also used to receive the second digital signal sent by the microcontroller processing unit 20. The second digital signal carries at least one or more of the data format information and data transmission ID (Identity document) information. The output terminal of the mode control module 11 is also connected to the downlink transmitting port 15 of the FPGA processing unit to send the second digital signal through the downlink transmitting port 15. The data format information is either a 16-bit data format or an 8-bit data format.

[0068] The data format information refers to the data format input to the microcontroller processing unit 20, which can be 16-bit or 8-bit. The original neural signal data format of the analog front-end chip 30 is 16-bit, and the data format can be selected through the mode control port 16. Then, the data processing module 13 processes the original neural signal according to the data format information. For example, it can select the same 16-bit data format as the original neural signal, or it can convert the original neural signal data format to 8-bit through the data processing module 13. The data transmission ID information is the ID information of the analog front-end chip. Each analog front-end chip 30 has a unique ID information corresponding to it. The FPGA processing unit 10 can send data to all or a specified analog front-end chip 30 according to the data transmission ID information. The output of the mode control module 11 is also connected to the downlink transmission port 15 of the FPGA processing unit, which can be used to forward the second digital signal to the analog front-end chip 30 to realize data transmission to all or a specified analog front-end chip 30.

[0069] Specifically, when the FPGA processing unit 10 includes a mode control port 16, an uplink transmit port 18, and an uplink receive port 17, the asynchronous FIFO module 14 receives the data sent by the microcontroller processing unit 20 through the uplink receive port 17 of the FPGA processing unit 10, and performs asynchronous transmission and buffering of the downlink signal, i.e. the signal sent by the microcontroller processing unit 20, to achieve rate matching.

[0070] In addition, the FPGA processing unit has independent control transmit and receive ports for each analog front-end chip, including a shared clock signal (SCLK) for multiple chips, a shared data transmit signal (MOSI), an independent chip select signal (CS) for each chip, and an independent receive signal (MISO) for each chip.

[0071] A second aspect of the present invention provides a neural signal acquisition system, such as... Figure 10 As shown, the neural signal acquisition system 1000 includes at least one analog front-end chip 30 and the signal processing device 100 described in any of the above embodiments, wherein the analog front-end chip 30 is an RHD2164 chip, and the signal processing device 100 is connected to the analog front-end chip 30.

[0072] The neural signal acquisition system 1000 proposed in this embodiment of the invention is based on the connection between the signal processing device 100 and the analog front-end chip 30. The signal processing device 100 can perform neural signal acquisition and signal analysis processing on the analog front-end chip 30. The signal processing device 100 uses the FPGA processing unit 10 to realize the interface protocol conversion and signal preprocessing of the signals transmitted between the microcontroller processing unit 20 and the analog front-end chip 30. Then, the microcontroller processing unit 20 is used for signal analysis processing. Compared with using the FPGA chip alone to realize neural signal acquisition and data processing functions, it has the characteristics of short development cycle, low overall system power consumption, small circuit area, accurate resource assessment, good functional reusability, and suitability for rapid iteration. It is also more suitable for implantable devices and can realize lower power neural signal processing and convenient development.

[0073] In the description of this invention, "a plurality of" means two or more.

[0074] Other configurations and operations of the signal processing apparatus 100 and the neural signal acquisition system 1000 according to embodiments of the present invention are known to those skilled in the art and will not be described in detail here.

[0075] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.

[0076] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A signal processing apparatus, characterized in that, include: An FPGA processing unit, wherein the FPGA processing unit is adapted to connect to an analog front-end chip, wherein the analog front-end chip is an RHD2164 chip; A microcontroller processing unit, which is connected to the FPGA processing unit and the host computer; The FPGA processing unit is used to implement the interface protocol conversion of the signals transmitted between the microcontroller processing unit and the analog front-end chip, and to implement the signal preprocessing of the signals transmitted between the microcontroller processing unit and the analog front-end chip. The microcontroller processing unit is used to perform signal analysis and processing of the signals transmitted between the FPGA processing unit and the host computer. The microcontroller processing unit includes at least one microcontroller. When the microcontroller processing unit includes one microcontroller, the microcontroller is used to manage the signal analysis and processing of all analog front-end chips and the host computer. Alternatively, when the microcontroller processing unit includes multiple microcontrollers, each microcontroller is used to manage the signal analysis and processing of the signals transmitted between a corresponding part of the analog front-end chips and the host computer. The microcontroller includes: An uplink communication port is provided, which is connected to the host computer via a serial bus. The uplink communication port is used to realize signal transmission between the microcontroller processing unit and the host computer. A downlink communication port is provided, which is connected to the FPGA processing module. The downlink communication port is used to realize signal transmission between the microcontroller processing unit and the FPGA processing unit. A signal processing module is connected to the uplink communication port and the downlink communication port. The signal processing module is used to perform signal analysis and processing on the signals transmitted between the FPGA processing unit and the host computer. The FPGA processing unit includes a mode control port and an uplink transmission port. The mode control port is connected to the input terminal of the mode control module. The microcontroller processing unit includes multiple microcontrollers, which include: The main microcontroller has a downlink communication port including a downlink control port, a downlink transmit port, and a first downlink receive port. The downlink control port of the main microcontroller is connected to the mode control port. The downlink transmit port of the main microcontroller is connected to the receive port of the analog front-end chip to send downlink signals to the analog front-end chip. The first downlink receive port of the main microcontroller is connected to the uplink transmit port of the FPGA processing unit. At least one slave microcontroller, wherein the downlink communication port of the slave microcontroller includes a second downlink receiving port, and the second downlink receiving port of the slave microcontroller is connected to the uplink transmitting port of the FPGA processing unit.

2. The signal processing apparatus according to claim 1, characterized in that, The communication port of the microcontroller processing unit adopts the SPI interface, the communication port of the analog front-end chip adopts the DDR interface, and the FPGA processing unit is specifically used to convert the raw neural signals sent by the analog front-end chip from the DDR data protocol format to the SPI data protocol format.

3. The signal processing apparatus according to claim 1 or 2, characterized in that, The FPGA processing unit includes: A mode control module, the input terminal of which is connected to the microcontroller processing unit, is used to receive a first digital signal sent by the microcontroller processing unit, the first digital signal carrying mode processing information; A first receiving module, wherein the input terminal of the first receiving module is adapted to be connected to the analog front-end chip to receive the raw neural signals sent by the analog front-end chip and to perform interface protocol conversion on the raw neural signals; The data processing module has its input end connected to the mode control module and the first receiving module, and its output end connected to the microcontroller processing unit. The data processing module is used to perform signal preprocessing on the converted raw neural signal according to the mode processing information, and send the preprocessed raw neural signal to the microcontroller processing unit.

4. The signal processing apparatus according to claim 1, characterized in that, The FPGA processing unit includes a mode control port, an uplink transmit port, and an uplink receive port, wherein the mode control port is connected to the input terminal of the mode control module; The microcontroller processing unit includes a microcontroller. The downlink communication port of the microcontroller includes a downlink control port, a downlink transmit port, and a downlink receive port. The downlink control port is connected to the mode control port. The downlink transmit port is connected to the uplink receive port of the FPGA processing unit so that the FPGA processing unit forwards the downlink signal of the microcontroller to the analog front-end chip. The downlink receive port is connected to the uplink transmit port of the FPGA processing unit.

5. The signal processing apparatus according to claim 1, characterized in that, The FPGA processing unit includes a mode control port and an uplink transmission port, and the mode control port is connected to the input terminal of the mode control module. The microcontroller processing unit includes a microcontroller. The downlink communication port of the microcontroller includes a downlink control port, a downlink transmit port, and a downlink receive port. The downlink control port is connected to the mode control port. The downlink transmit port is connected to the receive port of the analog front-end chip to send downlink signals to the analog front-end chip. The downlink receive port is connected to the uplink transmit port of the FPGA processing unit.

6. The signal processing apparatus according to claim 1, characterized in that, The FPGA processing unit includes a mode control port, an uplink transmit port, and an uplink receive port. The mode control port is connected to the input terminal of the mode control module. The microcontroller processing unit includes multiple microcontrollers, which include: The main microcontroller has a downlink communication port including a downlink control port, a downlink transmit port, and a first downlink receive port. The downlink control port of the main microcontroller is connected to the mode control port. The downlink transmit port of the main microcontroller is connected to the uplink receive port of the FPGA processing unit so that the FPGA processing unit forwards the downlink signal of the microcontroller to the analog front-end chip. The first downlink receive port of the main microcontroller is connected to the uplink transmit port of the FPGA processing unit. At least one slave microcontroller, wherein the downlink communication port of the slave microcontroller includes a second downlink receiving port, and the second downlink receiving port of the slave microcontroller is connected to the uplink transmitting port of the FPGA processing unit.

7. The signal processing apparatus according to claim 4 or 6, characterized in that, The FPGA processing unit further includes: An asynchronous FIFO module is provided, wherein the input of the asynchronous FIFO module is connected to the uplink receiving port of the FPGA processing unit, and the asynchronous FIFO module is connected to the analog front-end chip through the downlink transmitting port of the FPGA processing unit. The asynchronous FIFO module is used to asynchronously transmit and buffer the downlink signal. The mode control module is further configured to receive a second digital signal sent by the microcontroller processing unit. The second digital signal carries at least one or more of data format information and data transmission ID information. The output of the mode control module is also connected to the downlink transmission port of the FPGA processing unit to transmit the second digital signal through the downlink transmission port. The data format information is either a 16-bit data format or an 8-bit data format.

8. A neural signal acquisition system, characterized in that, include: At least one analog front-end chip, wherein the analog front-end chip is an RHD2164 chip; The signal processing apparatus according to any one of claims 1-7, wherein the signal processing apparatus is connected to the analog front-end chip.

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