In-memory computing array and operation method thereof

Abstract

The present invention discloses an in-memory computing array and an operating method thereof, belonging to the field of semiconductor and CMOS hybrid integrated circuit technology. The present invention designs a 2T1R in-memory computing array based on subthreshold current. Each unit in the array consists of a memristor, a gate transistor T1, and a readout transistor T2. The write and erase operations are similar to those of a 1T1R array architecture, but the readout is performed through a transistor T2 operating in the subthreshold region. The readout current generated by the readout transistor is relatively small, which is conducive to increasing the parallelism of in-memory computing and can achieve ultra-high parallel computing of the order of 100 to 1000. At the same time, the readout current of the readout transistor T2 is exponentially related to the gate voltage, which can obtain a larger switching current ratio and amplify the readout window of the in-memory computing unit. Compared with the 1T1R array architecture, the present invention can realize more complex in-memory computing operations and can flexibly select operation strategies, thereby achieving more efficient multiplication and accumulation operations.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductors and CMOS hybrid integrated circuits, and in particular relates to an array architecture based on a novel memory (Emerging Memory) integrated with CMOS and an operation strategy thereof. Background Art

[0002] Modern computers typically employ a von Neumann architecture that separates computation and storage, requiring data to be transferred between the processor and memory. With the recent development of artificial intelligence and cloud computing, the total amount of data has rapidly expanded, significantly increasing the time and power consumption of frequent data exchanges between the processor and memory. Furthermore, while processor performance and density are increasing in line with Moore's Law, memories such as dynamic random access memory (DRAM) and flash memory (Flash) face numerous limitations, including physical limits, during miniaturization. Their performance and density have lagged behind Moore's Law, leading to a growing speed mismatch between the two. Against this backdrop, the convergence of storage and computing has become a future trend. Research on nonvolatile, two-terminal memristor devices, such as resistive random access memory (RRAM), phase-change memory (PCRAM), magnetic random access memory (MRAM), and ferroelectric tunnel junctions (FTJs), as well as compute-in-memory array architectures based on these devices, has become increasingly important.

[0003] For memristors represented by resistive random access memory (RRAM), traditional array architectures can generally be divided into three categories: 1R, 1S1R, and 1T1R.

[0004] 1R array, word lines and bit lines overlap to form a Crossbar structure. The area of ​​each memory cell is determined by its overlapping part, which can achieve a minimum area of ​​4F. 2 , but there are various problems such as leakage path and write crosstalk.

[0005] The 1S1R array is a series connection between a memristor and a nonlinear switch selector. The selector has a simple structure, does not add extra area, and can be stacked in three dimensions. The effective unit area of ​​each memory cell is only 4F. 2 / N (N is the number of stacked layers). However, the material system of the gate transistor is complex, the device performance fluctuates greatly, and the read voltage threshold of the memory is increased, the nonlinearity provided is limited, and leakage is still serious in larger-scale arrays.

[0006] 1T1R array, which is the most common structure at present. This structure uses transistors (transistors) as gating units to shut off the leakage path, but the area occupied by each memory cell is mainly determined by the three-terminal transistor as a switching device. Each memory cell occupies an area of ​​6F. 2 .

[0007] Therefore, existing memristors represented by resistive random access memory (RRAM) and phase change memory (PCRAM) generate microampere-level currents during read operations. The large read current limits the parallelism of in-memory calculations, resulting in increased computing power consumption and deterioration in the linearity of calculation results. Summary of the Invention

[0008] In order to improve the computational parallelism of in-memory computing array architectures represented by resistive random access memory (RRAM) and reduce power consumption and nonlinearity problems, the present invention proposes a 2T1R in-memory computing array architecture based on subthreshold current and four in-memory computing operation strategies supported by the architecture.

[0009] The technical solutions provided by the present invention are as follows:

[0010] An in-memory computing array, characterized by comprising a 2T1R array, wherein each 2T1R unit in the array consists of a memristor, a gating transistor T1, and a readout transistor T2, wherein the memristor is used to store weight information, T1 is used to control the current path, and T2 operates in a subthreshold region and is used to read the state of the memristor, wherein the anode of the memristor is connected to the drain of T1 and the gate of T2, and the cathode of the memristor is connected to a write source line WSL; the gate of T1 is controlled by a word line WL voltage, the source of T1 is connected to a write bit line WBL, the drain of T1 is connected to the anode of the memristor and the gate of T2; the gate of T2 is connected to the anode of the memristor, and the source and drain of T2 are respectively connected to a read bit line RBL and a write bit line RSL; the periphery of the 2T1R array is connected to a multifunctional digital write unit and a multimode analog IO unit for controlling the write and read operations of the 2T1R array.

[0011] Furthermore, the multifunctional digital write unit includes multiple multiplexers MUX, which are responsible for distributing the voltage signal generated by the external power supply to the corresponding connection lines of the array to achieve precise control of the 2T1R unit; wherein several WLs in the array are distributed to the output end of the same MUX, and the voltage applied to each WL includes the read voltage, the write weight voltage, the erase weight voltage and the ground. The MUX that controls the WL is a 4-to-1 MUX, and several WBLs in the array are simultaneously distributed to the output end of the same MUX, and the voltage applied to each WBL includes the voltage when writing the weight, the voltage when erasing the weight, and the voltage when verifying the weight. The MUX that controls the WBL is a 3-to-1 MUX, and several WSLs in the array are simultaneously distributed to the output end of the same MUX, and the voltage applied to each WSL is only 0 and the erase weight voltage. The MUX that controls the WSL is a 2-to-1 MUX.

[0012] Furthermore, the multi-mode analog IO unit is responsible for controlling the read bit line RBL and read source line RSL of the 2T1R array, supporting the input and output of analog signals. The multi-mode analog IO unit includes a bidirectional conversion module that integrates the functions of a DAC and an ADC. In input mode, the digital signal is converted into an analog voltage by the DAC to activate the 2T1R in-memory computing array; in output mode, the analog current generated by the 2T1R in-memory computing array is converted into an analog voltage by a transimpedance amplifier, and then converted into a digital signal for output by the SAR ADC.

[0013] Furthermore, the memristor is a resistive memory, a phase change memory, a magnetic memory or a ferroelectric tunnel junction.

[0014] Furthermore, a method for operating an in-memory computing array is provided, characterized in that it is used to accelerate vector matrix multiplication (VMM), wherein the activation vector is input from the outside in the form of voltage, the matrix elements (i.e., weights) are stored in the form of RRAM resistors in advance in the 2T1R in-memory computing array, and a multiply accumulate (MAC) operation is performed based on Ohm's law and Kirchhoff's current law, and the result is output in the form of the sum of currents, wherein the multi-bit privilege value written in the memristor satisfies The nonlinear dependency of n, where n represents the integer weight size of the neural network, n ranges from 1 to 2 N Continuous value (N is the number of weight bits), the resistance difference between two adjacent weight states in the low resistance range is small, and the resistance difference between two adjacent states in the high resistance range is large. The specific operating voltage conditions of the in-memory calculation array are as follows:

[0015] (1) The voltage applied to WL includes 0, V WL 、V SET_G、V RESET_G Four values, among which V WL It is the voltage applied to WL during the read operation, which makes the anode voltage difference between the maximum and minimum resistance of RRAM the largest word line voltage; V SET_G is the word line voltage when writing weight; V RESET_G is the word line voltage when the weight is erased;

[0016] (2) The voltage applied to WBL includes 0, V SET and V READ Three values, among which V WBL =V SET , when erasing weight V WBL =0, when verifying weight V WBL =V READ ;

[0017] (3) The voltage applied to WSL is only 0 and V RESET Two values, where V is written when weight is written WSL =0, when weight is erased, V WSL =V RESET , when verifying the weight V WSL =0;

[0018] (4) Apply analog voltage to RBL. In input mode, when the activation vector is input into the array from RBL, V RBL Equal to the analog value generated according to the multi-bit digital input signal, in other cases V RBL = VDD; In output mode, RBL is pulled down to ground through the operational amplifier working in deep negative feedback state, outputting current to the peripheral circuit;

[0019] (5) Apply analog voltage to RSL. In input mode, when the activation vector is input into the array from RSL, V RSL Equal to the analog value generated according to the multi-bit digital input signal, in other cases V RSL =VDD; In output mode, RSL is pulled down to ground through the operational amplifier working in a deep negative feedback state, outputting current to the peripheral circuit.

[0020] Furthermore, an operation strategy for an in-memory computing array is provided, the steps of which include:

[0021] 1) The WBL voltage of the selected 2T1R unit is selected by the multi-function digital write unit to V READ ,WSL voltage is gated to ground by the multi-function digital write unit, the multi-mode analog IO unit corresponding to RSL is in the input state, its voltage is connected to the analog voltage of VDD, and the multi-mode analog IO unit corresponding to RBL is in the output state;

[0022] 2) The WL voltage of the calculation array in the 2T1R memory is 0 and V WL The two values ​​represent inputs of 0 and 1, respectively, controlling the turn-off and turn-on of T1 in the row. When the WL voltage is equal to 0, the off-state current I flows through T2. off , the result of the operation is equal to 0×w; when the WL voltage is equal to V WL When , the current flowing through T2 reflects the size of the weight stored in the memristor, and the result of the operation is equal to 1×w;

[0023] 3) The operation results are accumulated on the RBL in the form of current and converted into digital signals for output through the multi-mode analog IO unit in output mode.

[0024] The second operation strategy of the in-memory computing array includes the following steps:

[0025] 1) The WL voltage of the selected 2T1R unit is selected by the multi-function digital write unit to V WL ,WSL voltage is strobed to ground by the multi-function digital write unit, the multi-mode analog IO unit corresponding to RBL is in the input state, its voltage is connected to the analog voltage of VDD, and the multi-mode analog IO unit corresponding to RSL is in the output state;

[0026] 2)WBL voltage has 0 and V READ The two values ​​represent input 0 and 1 respectively. When the WBL voltage is equal to 0, the off-state current I flows through T2. off , the result is equal to 0×w; when the WBL voltage is equal to V RAED When , the current flowing through T2 reflects the size of the weight stored in the memristor, and the result of the operation is equal to 1×w;

[0027] 3) The operation results are accumulated on RSL in the form of current; and converted into digital signals and output through the multi-mode analog IO unit in output mode.

[0028] The third in-memory computing array operation strategy includes the following steps:

[0029] 1) The WL voltage of the selected 2T1R unit is selected by the multi-function digital write unit to V WL , the WBL voltage is selected by the multi-function digital write unit to V READ ,The WSL voltage is gated to ground by the multi-function digital write unit, and the multi-mode analog IO unit corresponding to RBL is in the input state;

[0030] 2) RBL is connected to the analog voltage, which is V RBL The nonlinear dependence value of ~-lnm; where m=1,2…,2 M , get the operation result;

[0031] 3) The operation results are accumulated on RSL in the form of current and converted into digital signals for output through the multi-mode analog IO unit in output mode.

[0032] The fourth in-memory computing array operation strategy includes the following steps:

[0033] 1) The WL voltage of the selected 2T1R unit is selected by the multi-function digital write unit to V WL , the WBL voltage is selected by the multi-function digital write unit as V READ ,The WSL voltage is gated to ground by the multi-function digital write unit, and the multi-mode analog IO unit corresponding to RSL is in the input state;

[0034] 2)RSL is connected to the analog voltage, which is V RBL The nonlinear dependence value of ~-lnm; where m=1,2…,2 M , and get the result of the operation

[0035] 3) The operation results are accumulated on the RBL in the form of current and converted into digital signals for output through the multi-mode analog IO unit in output mode.

[0036] The technical effects of the present invention are as follows:

[0037] The present invention achieves read-write separation. The write and erase operations are similar to those of the 1T1R array architecture, but the data is read out through another transistor operating in the subthreshold region. The readout current of the subthreshold transistor is exponentially related to the gate voltage, which can achieve a larger switching current ratio and amplify the readout window of the 2T1R in-memory computing unit. Because the writing, erasing, and reading of the memristor require relatively large currents, the gate transistor T1 is designed with a large width-to-length ratio and a small threshold voltage. The multiplication and accumulation operation requires a relatively small read current, and the readout transistor T2 is designed with a small width-to-length ratio (and a smaller area) and a large threshold voltage, thereby improving linearity without incurring excessive area overhead for the memory cell. At the same time, additional multifunctional digital write units and multi-mode analog IO units are introduced. Compared to the 1T1R array architecture, the present invention can implement more complex in-memory computing operations. The readout transistor operating in the subthreshold region generates a smaller read current, which is conducive to increasing the parallelism of in-memory computing, and can achieve ultra-high parallel computing on the order of 100 to 1000. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a schematic diagram of a 2T1R unit in the in-memory computing array of the present invention;

[0039] Figure 2 This is a schematic diagram of the in-memory computing array architecture of the present invention, including a centrally located array and peripheral multi-function digital write units and multi-mode analog IO unit circuits;

[0040] Figure 3 This is a schematic diagram of the bidirectional conversion module of the present invention;

[0041] Figure 4 It is a schematic diagram of the WL input type operation strategy of the present invention;

[0042] Figure 5 It is a schematic diagram of the WBL input type operation strategy of the present invention;

[0043] Figure 6 It is a schematic diagram of the RBL input type operation strategy of the present invention;

[0044] Figure 7 Schematic diagram of the RSL input operation strategy of the present invention.

[0045] Specific implementation cases

[0046] The present invention is further described below with reference to specific embodiments and accompanying drawings.

[0047] The present invention takes the memristor in the 2T1R cell as an example of resistive random access memory (RRAM).

[0048] like Figure 1 As shown in the in-memory computing array architecture proposed by the present invention, each 2T1R cell contains an RRAM for storing node information. Its anode is at the top and its cathode is at the bottom. The anode is connected to the drain of the gate transistor T1 and the gate of the readout transistor T2, while the cathode is connected to the write source line (WSL). A gate transistor T1, located in the upper left corner of the cell, controls the current path through the RRAM. Its gate is controlled by the word line (WL) voltage. The source is on the left and connected to the write bit line (WBL). The drain is on the right and connected to the anode of the RRAM and the gate of the readout transistor T2. A readout transistor T2, located on the right side of the cell, reads the state stored in the memristor. Its gate voltage is controlled by the RRAM anode voltage. The source and drain are connected to the read bit line (RBL) and write bit line (RSL), respectively. The cell is expanded horizontally and vertically to form a 2T1R in-memory computing array. Since writing, erasing, and reading memristors require relatively large currents, the selection transistor T1 is designed with a larger width-to-length ratio and a smaller threshold voltage. The multiplication-accumulation operation requires a relatively small read current, and the readout transistor T2 operates in the subthreshold region. T2 is designed with a smaller width-to-length ratio (and a smaller area) and a larger threshold voltage, thereby improving the switching current ratio without incurring excessive area overhead for the storage unit.

[0049] Figure 2This is a schematic diagram of the in-memory computing array architecture of the present invention. It includes a 2T1R array, and a multifunctional digital write unit and a multi-mode analog IO unit connected to its outside. The multifunctional digital write unit includes several multiplexers (MUX), which are responsible for controlling the WL, WBL and WSL of the 2T1R array. It can write information to the RRAM through set and reset operations. Its operation method is similar to that of the conventional 1T1R array, and it can also generate input voltage signals for in-memory calculations. Since the voltages applied to these lines are digital, the array can be switched between different operating modes with the help of a multiplexer (MUX). Specifically, for the above three lines, there are three types of multiplexers (MUX):

[0050] (1) Multiplexer for controlling WL: This type of MUX is located on the left side of the array. Based on different design specifications, MUX can be assigned to WL according to different granularities, that is, one, two or more WLs can share one MUX. Since the voltage applied to each WL includes 0, V WL 、V SET_G 、V RESET_G Four values, among which V WL It is the voltage applied to WL during the read operation, and is also the word line voltage that maximizes the anode voltage difference when the RRAM resistance is maximum and minimum. V SET_G is the word line voltage when writing weight, V RESET_G The word line voltage when erasing weights is used. Therefore, the multiplexer should be a 4-to-1 MUX, with its input connected to the three voltage levels generated by the external power supply and GND, and its output connected to the corresponding WL. By controlling the selection signal of the MUX, the voltage on the corresponding WL can be determined.

[0051] (2) Multiplexer for controlling WBL: This type of MUX is located on the upper side of the array. Based on different design specifications, MUX can be allocated to WBL at different granularities, that is, one, two or more WBLs can share one MUX. SET and V READ Three values, among which V WBL =V SET , when erasing weight V WBL =0, when verifying weight V WBL =V READ Therefore, the multiplexer should be a 3-to-1 MUX, whose input terminals are connected to the two voltage levels and GND generated by the external power supply, and the output terminals are connected to the corresponding WBL. By controlling the selection signal of the MUX, the voltage on the corresponding WBL can be determined. It should be noted that the V READIt cannot be set too large, and the T2 tube always works in the subthreshold region, so that within a certain range, no matter what the input or weight value is, the gate voltage of T2 is always less than its threshold voltage.

[0052] (3) Multiplexer for controlling WSL: This type of MUX is located on the left side of the array. Depending on the design specifications, MUX can be assigned to WSL at different granularities, allowing one, two, or more WSLs to share a MUX. RESET Two values, where V is written when weight is written WSL =0, when weight is erased, V WSL =V RESET , when verifying the weight V WSL = 0. Therefore, the multiplexer should be a 2-to-1 MUX, with its input connected to the two voltage levels generated by the external power supply and GND, and its output connected to the corresponding WSL. By controlling the selection signal of the MUX, the voltage on the corresponding WSL can be determined.

[0053] The multi-mode analog IO unit is responsible for controlling the RBL and RSL of the 2T1R array. For any 2T1R cell in the array, since the source and drain of its readout transistor T2 are connected to the corresponding RBL and RSL, respectively, there is always an input voltage and an output current in the RBL and RSL. These two connections can be used to obtain the T2 subthreshold current, which reflects the array input value and the cell storage information. Specifically, for the two connections of RBL and RSL:

[0054] (1) Analog voltage is allowed to be applied to RBL. In input mode, when the activation vector is input into the array in the form of voltage from RBL, V RBL Equal to the analog voltage generated according to the size of the multi-bit digital input signal. In other cases, V RBL = VDD; the bidirectional conversion module is in DAC mode. In output mode, RBL is pulled down to ground through the operational amplifier operating in deep negative feedback, outputting current to the peripheral circuit; the bidirectional conversion module is in ADC mode.

[0055] (2) Analog voltage is allowed to be applied to RSL. In input mode, when the activation vector is input into the array from RSL, V RSL Equal to the analog value generated according to the multi-bit digital input signal, in other cases V RSL = VDD; the bidirectional conversion module is in DAC mode. In output mode, RSL is pulled down to ground through the operational amplifier operating in deep negative feedback, outputting current to the peripheral circuit; the bidirectional conversion module is in ADC mode.

[0056] Figure 3This is the schematic diagram of the bidirectional conversion module. Since the digital-to-analog converter (DAC) and the analog-to-digital converter (ADC) are not enabled at the same time, the bidirectional conversion module reduces the peripheral circuit area overhead by multiplexing the DAC and ADC circuits. In input mode, Figure 3 The lower path in the bidirectional conversion module is enabled, and digital signals are input from the IO interface. These signals are converted to analog voltages by a digital-to-analog converter (DAC) and fed directly into the 2T1R array for subsequent calculations. In output mode, both the upper and lower paths are enabled, and the analog current calculated in the 2T1R array is first converted to an analog voltage by a transimpedance amplifier (TIA). This voltage is then converted to a digital signal using a successive approximation register analog-to-digital converter (SAR ADC) (consisting of a sample-and-hold circuit, a comparator, a successive approximation register, and a DAC), and then output from the IO interface. It should be noted that the DAC is active in both input and output modes. The difference lies in that in input mode, its output is connected to the 2T1R array, while in output mode, it is connected to the sample-and-hold circuit. To achieve this, a 2-to-1 demultiplexer (Demux) is used in the bidirectional conversion module. By controlling its select signal, the connection between the DAC output and either the 2T1R array or the sample-and-hold circuit can be switched.

[0057] The proposed in-memory computation array, when applied to in-memory computations, is primarily used to accelerate vector matrix multiplication (VMM). The activation vector is input externally as a voltage, and the matrix elements (i.e., weights) are pre-stored in the 2T1R in-memory computation array as RRAM resistors. Multiply-accumulate (MAC) operations are performed based on Ohm's law and Kirchhoff's current law, with the result output as the sum of currents. In the VMM implemented by the present invention, the matrix elements (weights) have multi-bit precision, with the upper limit determined by the RRAM window size. The input vector can have either single-bit or multi-bit precision, depending on the VMM's operational strategy.

[0058] The present invention proposes that the multi-bit privilege value written to RRAM should meet The nonlinear dependency of n, where n represents the integer weight size of the neural network, n ranges from 1 to 2 N Continuous value (N is the number of weight bits), the resistance difference between two adjacent weight states in the low resistance range is small, and the resistance difference between two adjacent states in the high resistance range is large. The derivation is as follows: It is known that the subthreshold current of MOSFET can be expressed as Where V GS is the voltage difference between the gate and source, V DS is the voltage difference between the drain and source, V Tis the threshold voltage. In the in-memory computing array of the present invention, Where V WBL is the voltage applied to WBL, R ch is the equivalent channel resistance when T1 is turned on, and R is the RRAM resistance. The correctness of the MAC operation depends on the readout tube T2 current {I d,n}(n=1,2…,2 N ) is equally spaced, so we need To ensure this.

[0059] This invention will take a simple neural network inference scenario as an example. The weight of each neuron in the neural network will be stored in the RRAM of 2T1R unit, and the input vector will be input into the array in the form of voltage. In this embodiment, each RRAM can be modulated into 2 M There are different conductance states, that is, N bits of information can be stored. In the initialization phase of the in-memory calculation, the weight matrix W is written into the 2T1R array. The method of writing the weight is: the WL voltage is set to V RESET_G , WBL voltage is set to 0, WSL voltage is set to V RESET , apply several pulses to erase the original information in the array; the WL voltage is set to V SET_G , WBL voltage is set to V SET , WSL voltage is set to 0, multiple pulses are applied to write N bit precision weight; WL voltage is set to V WL , WBL voltage is set to V READ , set the WSL voltage to 0, read the current, and verify whether the weight is written correctly.

[0060] During the in-memory computation phase, the present invention proposes four different in-memory computation operation strategies based on the position of the activation vector input array and the position of the computation result output from the array. It should be noted that since the read current involved in the calculation in the present invention is a subthreshold current, its value is much smaller than the conventional read current of RRAM, and the total current after summation is also small, the present invention can support a higher degree of computational parallelism under the same computational error constraint. The following four operation strategies can all achieve ultra-high parallel computations of the order of 100 to 1000:

[0061] (1) WL input, RBL output type

[0062] Figure 4 This is a schematic diagram of the WL input and RBL output operation strategy. The WL voltage has 0 and V WLThe two values ​​represent inputs of 0 and 1, respectively, controlling the T1 of the row to turn off and on. The application of different WL voltages is completed by the MUX that controls the WL in the multifunctional write unit. For the selected 2T1R unit in the schematic, their WBL voltage is selected by the MUX to V READ , the WSL voltage is selected by the MUX to ground, the bidirectional conversion module corresponding to RSL is in the input state, and its voltage is connected to the analog voltage of VDD. The bidirectional conversion module corresponding to RBL is in the output state, and its voltage is pulled down to ground by the transimpedance amplifier in a deep negative feedback state. The multiplication result follows Kirchhoff's law and is accumulated on RBL in the form of current, and is converted into a digital signal output by the bidirectional conversion module in output mode (transimpedance amplifier + ADC). When the WL voltage is equal to 0, the RRAM anode voltage is also 0, regardless of the size of the RRAM storage weight. The off-state current I flows through T2. off , the result of the operation is approximately equal to 0×w; when the WL voltage is equal to V WL When , the current flowing through T2 can reflect the size of the weight stored in the RRAM, that is, 1×w. This strategy is simple to operate, and since single-bit input does not require a DAC, power consumption and delay are small, but the disadvantage is that the input vector has only 1-bit accuracy. Specifically, each bit of the input vector is encoded as a voltage on WL, 0 or V WL For example, assuming the input is a 512-dimensional vector [1,0,1,0,…,1,0], the corresponding WL voltage sequence is [V WL ,0,V WL ,0,…,V WL ,0]. By controlling MUX, these voltages can be applied to the corresponding WL. At the same time, the voltages of WBL and WSL are set to V READ The calculation results will be accumulated on RBL in the form of current and converted into digital signal output by ADC.

[0063] (2) WBL input, RSL output type

[0064] Figure 5 This is a schematic diagram of the principle of the WBL input and RSL output operation strategy. The WBL voltage has 0 and V READ The two values ​​represent input 0 and 1 respectively. The application of different WL voltages is completed by the MUX that controls the WBL in the multifunctional write unit. For the selected 2T1R unit in the schematic diagram, their WL voltage is selected by the MUX to V WL, the WSL voltage is selected by the MUX to ground, the bidirectional conversion module corresponding to RBL is in the input state, and its voltage is connected to the analog voltage of VDD. The bidirectional conversion module corresponding to RSL is in the output state, and its voltage is pulled down to ground by the transimpedance amplifier in a deep negative feedback state. The multiplication result follows Kirchhoff's law and is accumulated and output on RSL in the form of current. When the WBL voltage is equal to 0, the RRAM anode voltage in the cell is also 0, regardless of the size of the RRAM storage weight. The off-state current I flows through T2. off , the result of the operation is approximately equal to 0×w; when the WBL voltage is equal to V RAED When , the current flowing through T2 can reflect the size of the weight stored in RRAM, that is, 1×w. The advantages and disadvantages of this strategy are similar to the first strategy. The advantage is that it is simple to operate and does not require a DAC. The disadvantage is that the input vector has only 1-bit accuracy. Specifically, each bit of the input vector is encoded as a voltage on WBL, 0 or V READ For example, assuming the input is also a 512-dimensional vector [1,0,1,0,…,1,0], the corresponding WBL voltage sequence is [V READ ,0,V READ ,0,…,V READ ,0]. The voltage settings of WL and WSL are similar to the first strategy, that is, the voltages of WL and WSL are set to V respectively through MUX. WL The calculation result will be accumulated on RSL in the form of current and converted into a digital signal output by ADC.

[0065] (3) RBL input, RSL output type

[0066] Figure 6 This is a schematic diagram of the principle of the RBL input and RSL output operation strategy. The RBL voltage is based on V RBL ~-lnm(where m=1,2…,2 M ) indicates that the input has M bit precision. For the selected 2T1R cells in the diagram, their WL voltage is selected by MUX to V WL , the WBL voltage is selected by MUX to V READ , the WSL voltage is selected by MUX to ground, and the bidirectional conversion module corresponding to RBL is in the input state, so that the RBL voltage is connected to the above V RBL The analog voltage of -1nm is 0.01V. The bidirectional conversion module corresponding to RSL is in the output state, and its voltage is pulled down to ground by the transimpedance amplifier in the deep negative feedback state. The multiplication result follows Kirchhoff's law and is accumulated and output on RSL in the form of current. In this operation mode, due to V READ and V WLare all fixed values, and the T2 gate voltage is also determined accordingly. RBL Depend on becomes hour, The change in d is d, and the corresponding I can be detected d Therefore, this strategy can achieve MAC with M-bit precision input and N-bit precision weight, effectively improving the computing power of the in-memory computing array. Specifically, each bit of the input vector will be encoded as an analog voltage and applied to the RBL after conversion by DAC. For example, assuming the input is a 512-dimensional vector [1,0,2,0,…,n,0], the analog voltage of each bit can be set to [V1,0,V2,0,…,V n ,0], where V1, V2, … V n It is an analog voltage generated according to the size of the input signal. The voltage of WL and WBL is set to V WL and V READ , the WSL is grounded, placing the RRAM in a read state. The computation results are accumulated as current on the RSL and converted to digital signals for output via the ADC. This strategy enables MAC with M-bit precision input and N-bit precision weights, effectively increasing the computing power of the in-memory computation array.

[0067] (4) RSL input, RBL output type

[0068] Figure 7 This is a schematic diagram of the principle of the RSL input operation strategy, which is essentially the transposition of (3). Among them, the RSL voltage is based on V RSL ~-lnm(where m=1,2…,2 M ) indicates that the input has M bit precision. For the selected 2T1R cells in the diagram, their WL voltage is selected by MUX to V WL , the WBL voltage is selected by MUX as V READ , the WSL voltage is selected by MUX to ground, and the bidirectional conversion module corresponding to RSL is in the input state, so that the RSL voltage is connected to the above V RSLThe analog voltage of ~-lnm, the bidirectional conversion module corresponding to RBL is in the output state, and its voltage is pulled down to the ground by the transimpedance amplifier in the deep negative feedback state. The multiplication result follows Kirchhoff's law and is accumulated and output on RBL in the form of current. This strategy can also realize MAC with M-bit precision input and N-bit precision weight, effectively improving the computing power of the in-memory computing array. Specifically, each bit of the input vector will be encoded as an analog voltage and applied to RSL after conversion by DAC. The calculation result will be accumulated on RBL in the form of current and converted into a digital signal output by ADC. For example, assuming that the input is a 512-dimensional vector [1,0,2,0,…,n,0], we can set the analog voltage of each bit to [V1,0,V2,0,…,V n ,0], where V1, V2, … V n It is an analog voltage generated according to the size of the input signal. The voltage of WL and WBL is set to V WL and V READ , WSL is grounded to put the RRAM in the read state. This strategy can also implement MAC with M-bit precision input and N-bit precision weight.

[0069] Through the four aforementioned operation strategies, the present invention can flexibly implement vector-matrix multiplication. Specifically, based on the accuracy, input dimension, and output dimension of the neural network weight matrix, parameters such as the number of rows and columns of the 2T1R array, and requirements for inference speed and power consumption, the four operation strategies are flexibly selected based on their inherent characteristics, thereby more efficiently accelerating the forward propagation process of the neural network.

[0070] The above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit the same. Those skilled in the art may modify or make equivalent substitutions for the technical solutions of the present invention without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be based on the claims.

Claims

1. An in-memory computing array, characterized in that: The invention comprises a 2T1R array, wherein each 2T1R unit in the array consists of a memristor, a gate transistor T1, and a readout transistor T2. The memristor is used to store weight information, T1 is used to control the current path, T2 operates in the subthreshold region and is used to read the state of the memristor, and the readout current of T2 is exponentially related to the gate voltage. The anode of the memristor is connected to the drain of T1 and the gate of T2, and the cathode of the memristor is connected to the write source line WSL; the gate of T1 is controlled by the word line WL voltage, the source of T1 is connected to the write bit line WBL, the drain of T1 is connected to the anode of the memristor and the gate of T2; the gate of T2 is connected to the anode of the memristor, and the source and drain of T2 are connected to the read bit line RBL and the write bit line RSL, respectively. The periphery of the 2T1R array is connected to a multifunctional digital write unit and a multimode analog IO unit for controlling the write and read operations of the 2T1R array.

2. The in-memory computing array according to claim 1, wherein: The multifunctional digital write unit includes multiple multiplexers MUX, which are responsible for distributing the voltage signal generated by an external power supply to the corresponding connection line of the 2T1R array to achieve precise control of the 2T1R unit; wherein several WLs in the 2T1R array are distributed to the output end of the same MUX, and the voltage applied to each WL includes a read voltage, a write weight voltage, an erase weight voltage and a ground. The MUX that controls the WL is a 4-to-1 MUX. Several WBLs in the 2T1R array are simultaneously distributed to the output end of the same MUX, and the voltage applied to each WBL includes the voltage when writing the weight, the voltage when erasing the weight, and the voltage when verifying the weight. The MUX that controls the WBL is a 3-to-1 MUX. Several WSLs in the 2T1R array are simultaneously distributed to the output end of the same MUX, and the voltage applied to each WSL is only 0 and the erase weight voltage. The MUX that controls the WSL is a 2-to-1 MUX.

3. The in-memory computing array according to claim 1, wherein: The multi-mode analog IO unit is responsible for controlling the read bit line RBL and read source line RSL of the 2T1R array, supporting the input and output of analog signals. The multi-mode analog IO unit includes a bidirectional conversion module that integrates the functions of a DAC and an ADC. In input mode, the digital signal is converted into an analog voltage by the DAC to activate the 2T1R in-memory computing array. In output mode, the analog current generated by the 2T1R in-memory computing array is converted into an analog voltage by a transimpedance amplifier, and then converted into a digital signal by the SAR ADC for output.

4. The in-memory computing array according to claim 1, wherein: The memristor is a resistive memory, a phase change memory, a magnetic memory or a ferroelectric tunnel junction.

5. The method for operating an in-memory computing array according to claim 1, wherein: It is used to accelerate vector-matrix multiplication, where the activation vector is input from the outside in the form of voltage, and the matrix elements are stored in the form of memristor resistance in the 2T1R memory calculation array. The multiplication and accumulation operations are performed based on Ohm's law and Kirchhoff's current law, and the result is output in the form of the sum of currents. The multi-bit privilege value written in the memristor satisfies The nonlinear dependency of n, where n represents the integer weight size of the neural network, n ranges from 1 to 2 M Continuous value, N is the number of weight bits, the specific operating voltage conditions of the in-memory calculation array are as follows: 1) The voltage applied to WL includes 0, V WL 、V SET_G 、V RESET_G Four values, among which V WL V is the voltage applied to WL during the read operation, which makes the anode voltage difference between the maximum and minimum resistance of the memristor the largest; SET_G is the word line voltage when writing weight; V RESET_G is the word line voltage when the weight is erased; 2) The voltage applied to WBL includes 0, V SET and V READ Three values, among which V WBL =V SET , when erasing weight V WBL =0, when verifying weight V WBL =V READ ; 3) The voltage applied to WSL is only 0 and V RESET Two values, where V is written when weight is written WSL =0, when weight is erased, V WSL =V RESET , when verifying the weight V WSL =0; 4) Apply analog voltage to RBL. In input mode, when the activation vector is input into the array from RBL, V RBL Equal to the analog value generated according to the multi-bit digital input signal, in other cases V RBL = VDD; In output mode, RBL is pulled down to ground through the operational amplifier working in deep negative feedback state, outputting current to the peripheral circuit; 5) Apply analog voltage to RSL. In input mode, when the activation vector is input into the array from RSL, V RSL Equal to the analog value generated according to the multi-bit digital input signal, in other cases V RSL =VDD; In output mode, RSL is pulled down to ground through the operational amplifier working in a deep negative feedback state, outputting current to the peripheral circuit.

6. The method for operating an in-memory computing array according to claim 5, comprising the steps of: 1) The WBL voltage of the selected 2T1R unit is selected by the multi-function digital write unit to V READ ,WSL voltage is gated to ground by the multi-function digital write unit, the multi-mode analog IO unit corresponding to RSL is in the input state, its voltage is connected to the analog voltage of VDD, and the multi-mode analog IO unit corresponding to RBL is in the output state; 2) The WL voltage of the calculation array in the 2T1R memory is 0 and V WL The two values ​​represent inputs of 0 and 1, respectively, to control T1 in the row to be turned off and on; When the WL voltage is equal to 0, the off-state current I flows through T2. off , the result of the operation is equal to 0×w; when the WL voltage is equal to V WL When , the current flowing through T2 reflects the size of the weight stored in the memristor, and the result of the operation is equal to 1×w; 3) The operation results are accumulated on the RBL in the form of current and converted into digital signals for output through the multi-mode analog IO unit in output mode.

7. The method for operating an in-memory computing array according to claim 5, comprising the steps of: 1) The WL voltage of the selected 2T1R unit is selected by the multi-function digital write unit to V WL ,WSL voltage is strobed to ground by the multi-function digital write unit, the multi-mode analog IO unit corresponding to RBL is in the input state, its voltage is connected to the analog voltage of VDD, and the multi-mode analog IO unit corresponding to RSL is in the output state; 2)WBL voltage has 0 and V READ The two values ​​represent input 0 and 1 respectively. When the WBL voltage is equal to 0, the off-state current I flows through T2. off , the result is equal to 0×w; when the WBL voltage is equal to V RAED When , the current flowing through T2 reflects the size of the weight stored in the memristor, and the result of the operation is equal to 1×w; 3) The operation results are accumulated on RSL in the form of current; and converted into digital signals and output through the multi-mode analog IO unit in output mode.

8. The method for operating an in-memory computing array according to claim 5, comprising the steps of: 1) The WL voltage of the selected 2T1R unit is selected by the multi-function digital write unit to V WL , the WBL voltage is selected by the multi-function digital write unit to V READ , the WSL voltage is gated to ground by the multifunctional digital write unit, and the multimode analog I0 unit corresponding to RBL is in the input state; 2) RBL is connected to the analog voltage, which is V RBL The nonlinear dependence of -lnm is taken as the value; where m=1, 2…, 2 M , get the operation result; 3) The operation results are accumulated on RSL in the form of current and converted into digital signals for output through the multi-mode analog IO unit in output mode.

9. The method for operating an in-memory computing array according to claim 5, comprising the steps of: 1) The WL voltage of the selected 2T1R unit is selected by the multi-function digital write unit to V WL , the WBL voltage is selected by the multi-function digital write unit as V READ ,The WSL voltage is gated to ground by the multi-function digital write unit, and the multi-mode analog IO unit corresponding to RSL is in the input state; 2)RSL is connected to the analog voltage, which is V RBL ~-ln m nonlinear dependence value; where m=1, 2…, 2 M , and get the result of the operation 3) The operation results are accumulated on RBL in the form of current and converted into digital signal output by the multi-mode analog I0 unit in output mode.

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