Array substrate, display panel and display device

Abstract

An array substrate, a display panel and a display device.The array substrate comprises a plurality of sub-pixels arranged in an array, a plurality of scanning control lines, data signal lines and initial signal lines, each sub-pixel comprises a pixel circuit and a light emitting device electrically connected with the pixel circuit, each scanning control line is electrically connected with at least one row of pixel circuits, and the data signal lines are electrically connected with the initial signal lines. The scanning control line comprises a first scanning signal line and a first reset control line, the array substrate further comprises a first GOA circuit and a second GOA circuit, the first GOA circuit comprises a plurality of first GOA units in cascade connection, and each first GOA unit provides a first scanning signal for a coupling sub-circuit in one row of pixel circuits; the second GOA circuit comprises a plurality of second GOA units which are in cascade connection, the second GOA units are arranged on one side of the display area and carry out single-side driving on the first reset control line, or each second GOA unit provides first reset control signals for coupling sub-circuits in two or more rows of pixel circuits.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Art

[0002] For active-matrix organic light-emitting diode (AMOLED) display devices, multiple driving signals are required in each pixel. In order to generate these driving signals that are turned on / off in sequence, array substrate row driving (Gate Driver on Array, GOA) circuits are required on both sides of the effective display (Active Area, AA) area to realize the row-by-row scanning driving function of the display panel. Generally, the pixel circuit cannot be placed at the same time in the area where the GOA circuit is placed, thus forming a border area around the display device that cannot emit light. In order to ensure the image quality of the AA area, the number of different driving signals required in the pixel structure is increasing, and the number of GOA circuits required to exist at the same time is also increasing, which is inconsistent with the design concept of narrowing the border. However, if some important driving signals are forced to be driven unilaterally in order to narrow the border, the screen quality will also be affected. Summary of the invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] An embodiment of the present disclosure provides an array substrate, comprising a plurality of sub-pixels arranged in an array and a plurality of scan control lines, data signal lines and initial signal lines, wherein the sub-pixels include a pixel circuit and a light-emitting device electrically connected to the pixel circuit, each scan control line is electrically connected to at least one row of pixel circuits, the scan control lines include a first scan signal line and a first reset control line, the array substrate further includes a GOA circuit group for driving the pixel circuits in rows, the GOA circuit group includes: a first GOA circuit and a second GOA circuit, wherein: The pixel circuit comprises a first node, a second node, a third node, a driving subcircuit and a coupling subcircuit, wherein the driving subcircuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide a driving signal to the third node under the control of signals of the first node and the second node; the coupling subcircuit is connected to a first scanning signal line, a first reset control line, a data signal line, a first initial signal line and the third node respectively, and is configured to couple the signal of the first initial signal line to the third node under the control of a first reset control signal provided by the first reset control line, and to couple the signal of the data signal line to the third node under the control of a first scanning signal provided by the first scanning signal line; The first GOA circuit includes a plurality of first GOA units connected in cascade, each of the first GOA units is connected to a first scanning signal line, and is configured to provide a first scanning signal to a coupling sub-circuit in a row of pixel circuits; The second GOA circuit includes a plurality of second GOA units connected in cascade, and the second GOA unit is arranged on one side of the display area to perform unilateral driving on the first reset control line, or each of the second GOA units is connected to two or more of the first reset control lines and is configured to provide the first reset control signal to the coupling sub-circuits in two or more rows of pixel circuits.

[0005] An embodiment of the present disclosure further provides a display panel, comprising the array substrate as described in any embodiment of the present disclosure.

[0006] An embodiment of the present disclosure further provides a display device, comprising a display panel as described in any embodiment of the present disclosure.

[0007] The array substrate, display panel and display device of the disclosed embodiments can achieve a narrow frame effect without affecting the screen quality by driving part of the GOA circuit in a unilateral manner or a one-drive-multiple manner.

[0008] Other features and advantages of the present disclosure will be described in the following description, and partly become apparent from the description, or be understood by implementing the present disclosure. Other advantages of the present disclosure can be realized and obtained by the schemes described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure.

[0010] Figure 1 is a structural schematic diagram of a display device; Figure 2 It is a structural schematic diagram of a display substrate; Figure 3 It is a schematic diagram of the planar structure of a display area in a display substrate; Figure 4 A schematic diagram of the cross-sectional structure of a display area in a display substrate; Figure 5 A schematic diagram of the structure of a pixel circuit provided by an embodiment of the present disclosure; Figure 6 is an equivalent circuit diagram of a pixel circuit according to an embodiment of the present disclosure; Figure 7 for Figure 6A driving timing diagram of a pixel circuit is provided; Fig. 8A for Figure 6 A schematic diagram showing the effect of the first reset control signal provided by the first reset control line on the driving current at different delay times; Figure 8B for Figure 6 A schematic diagram showing the effect of the second reset control signal provided by the second reset control line on the driving current at different delay times; Figure 8C for Figure 6 A schematic diagram showing the effect of a third reset control signal provided by a third reset control line on a drive current at different delay times; Fig.8D for Figure 6 A schematic diagram showing the effect of the first light-emitting control signal provided by the first light-emitting control line on the driving current at different delay times; Fig. 8E for Figure 6 Schematic diagram of the effect of the second light emitting control signal provided by the second light emitting control line on the driving current at different delay times; Fig.8F for Figure 6 A schematic diagram showing the influence of the first scanning signal provided by the first scanning signal line on the driving current at different delay times; Fig. 9 for Figure 6 The pixel circuit shown is a simulation waveform result diagram when six groups of GOA circuits corresponding to each scanning control line are driven by a one-drive-two scheme; Figures 10 to 23 Schematic diagram of driving modes of several GOA circuits according to exemplary embodiments of the present disclosure; Fig.24 for Figure 6 The pixel circuit provided adopts Figures 18 to 22 A timing diagram corresponding to the signals of each scanning control line when driving in any of the driving modes shown. DETAILED DESCRIPTION

[0011] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail in conjunction with the accompanying drawings below. Note that the embodiments can be implemented in multiple different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0012] The proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited to this. For example: the width-to-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in this disclosure are only structural schematic diagrams, and one method of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0013] In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0014] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0015] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0016] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region through which current mainly flows.

[0017] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged, and the "source terminal" and the "drain terminal" may be interchanged.

[0018] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0019] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0020] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced by "conductive film". Similarly, "insulating film" may be replaced by "insulating layer".

[0021] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0022] The term "about" in the present disclosure refers to a numerical value that is not strictly limited to allow for process and measurement errors.

[0023] Figure 1 FIG. 1 is a schematic diagram of the structure of a display device. Figure 1As shown, the display device may include a timing controller, a data signal driver, a scan signal driver, a light emitting signal driver and a pixel array, the timing controller is respectively connected to the data signal driver, the scan signal driver and the light emitting signal driver, the data signal driver is respectively connected to a plurality of data signal lines (D1 to Dn), the scan signal driver is respectively connected to a plurality of scan signal lines (S1 to Sm), and the light emitting signal driver is respectively connected to a plurality of light emitting control lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light emitting unit, the circuit unit may include at least a pixel circuit, the pixel circuit is respectively connected to the scan signal line, the light emitting control line and the data signal line, the light emitting unit may include a light emitting device, and the light emitting device is connected to the pixel circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide a grayscale value and a control signal suitable for the specification of the data signal driver to the data signal driver, may provide a clock signal, a scan start signal, etc. suitable for the specification of the scan signal driver to the scan signal driver, and may provide a clock signal, an emission stop signal, etc. suitable for the specification of the light emitting signal driver to the light emitting signal driver. The data signal driver can generate a data voltage to be provided to the data signal lines D1, D2, D3, ... and Dn using the grayscale value and the control signal received from the timing controller. For example, the data signal driver can sample the grayscale value using the clock signal, and apply the data voltage corresponding to the grayscale value to the data signal lines D1 to Dn in units of pixel rows, and n can be a natural number. The scan signal driver can generate a scan signal to be provided to the scan signal lines S1, S2, S3, ... and Sm by receiving a clock signal, a scan start signal, etc. from the timing controller. For example, the scan signal driver can sequentially provide a scan signal with a conduction level pulse to the scan signal lines S1 to Sm. For example, the scan signal driver can be constructed in the form of a shift register, and can sequentially transmit the scan start signal provided in the form of a conduction level pulse to the next level circuit under the control of the clock signal to generate a scan signal, and m can be a natural number. The light-emitting signal driver can generate an emission signal to be provided to the light-emitting control lines E1, E2, E3, ... and Eo by receiving a clock signal, an emission stop signal, etc. from the timing controller. For example, the light emitting signal driver may sequentially provide an emission signal having a cut-off level pulse to the light emitting control lines E1 to Eo. For example, the light emitting signal driver may be configured in the form of a shift register, and may generate an emission signal in a manner of sequentially transmitting an emission stop signal provided in the form of a cut-off level pulse to a next stage circuit under the control of a clock signal, and o may be a natural number. In an exemplary embodiment, a pixel array may be provided on a display substrate.

[0024] Figure 2FIG. 1 is a schematic diagram of the structure of a display substrate. Figure 2 As shown, the display substrate may include a display area 100, a binding area 200 located on one side of the display area 100, and a frame area 300 located on the other side of the display area 100. In an exemplary embodiment, the display area 100 may be a flat area including a plurality of sub-pixels Pxij constituting a pixel array, the plurality of sub-pixels being configured to display a dynamic picture or a still image, and the display area 100 may be referred to as an effective display (AA) area. In an exemplary embodiment, the display substrate may be a flexible substrate, and thus the display substrate may be deformable, such as curling, bending, folding, or rolling up.

[0025] In an exemplary embodiment, the binding area 200 may include a fan-out area, a bending area, a driver chip area, and a binding pin area arranged in sequence in a direction away from the display area 100. The fan-out area is connected to the display area 100 and may include at least a plurality of data lead-out lines. The bending area is connected to the fan-out area and may include a composite insulating layer provided with a groove, and the groove is configured to bend the binding area to the back of the display area. The driver chip area may include at least an integrated circuit (IC), which is configured to be connected to a plurality of data lead-out lines. The binding pin area may include at least a plurality of binding pads (Bonding Pad), which are configured to be bound and connected to an external flexible printed circuit (FPC).

[0026] In an exemplary embodiment, the frame region 300 may include at least a circuit region connected to the display region 100 , and may include at least a gate driving circuit electrically connected to a pixel circuit in the display region 100 .

[0027] In an exemplary embodiment, at least one isolation dam may be provided in the binding area 200 and the border area 300. The isolation dam may extend in a direction parallel to the edge of the display area to form an annular structure surrounding the display area 100. The edge of the display area is the edge of the display area close to the binding area or the border area.

[0028] Figure 3 FIG. 1 is a schematic diagram of a planar structure of a display area in a display substrate. Figure 3As shown, the display area may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each sub-pixel may include a circuit unit and a light-emitting unit, and the circuit unit may include at least a pixel circuit, and the pixel circuit is respectively connected to a scan signal line, a light-emitting control line, a data signal line, and a high-potential power line, and the pixel circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting control line, and output a corresponding current to the light-emitting unit. The light-emitting unit in each sub-pixel is respectively connected to the pixel circuit of the sub-pixel, and the light-emitting unit is configured to emit light of corresponding brightness in response to the current output by the pixel circuit of the sub-pixel.

[0029] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) emitting red light, the second sub-pixel P2 may be a green sub-pixel (G) emitting green light, and the third sub-pixel P3 may be a blue sub-pixel (B) emitting blue light. In an exemplary embodiment, the shape of the sub-pixels may be rectangular, rhombus, pentagonal, or hexagonal. In some exemplary embodiments, the three sub-pixels may be arranged in parallel horizontally, vertically, or in any other manner, which is not limited in the present disclosure.

[0030] In an exemplary embodiment, a pixel unit may include four sub-pixels, and the four sub-pixels may be arranged in a diamond shape to form an RGBG pixel arrangement, or may be arranged horizontally, vertically, or in any other manner, which is not limited in the present disclosure.

[0031] Figure 4 FIG. 1 is a schematic diagram of a cross-sectional structure of a display region in a display substrate, illustrating the structure of three sub-pixels in the display region. Figure 4 As shown, on a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 102 disposed on a substrate 101, a light emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 101, and a packaging structure layer 104 disposed on a side of the light emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which is not limited in the present disclosure.

[0032] In an exemplary embodiment, the substrate 101 may be a flexible substrate, or may be a rigid substrate. The driving circuit layer 102 may include a plurality of circuit units, each of which may include at least a pixel circuit composed of a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 may include a plurality of light-emitting units, each of which may include a light-emitting device, and the light-emitting device may include at least an anode, an organic light-emitting layer and a cathode, the anode is connected to the pixel circuit, the organic light-emitting layer is connected to the anode and the cathode respectively, and the organic light-emitting layer emits light of corresponding colors under the drive of the anode and the cathode. The encapsulation structure layer 104 may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0033] Figure 5 Schematic diagram of a pixel circuit provided by an embodiment of the present disclosure. Figure 5 As shown, the pixel circuit provided by the embodiment of the present disclosure may include: a driving subcircuit 1021 and a coupling subcircuit 1022 .

[0034] The driving sub-circuit 1021 is electrically connected to the first node N1, the second node N2 and the third node N3, respectively, and is configured to provide a driving signal to the third node N3 under the control of the signals of the first node N1 and the second node N2.

[0035] The coupling sub-circuit 1022 is electrically connected to the scan signal line Gate1, the first reset control line Reset1, the data signal line DL, the first initial signal line INIT1 and the third node N3, respectively, and is configured to couple the signal of the first initial signal line INIT1 to the third node N3 under the control of the first reset control signal provided by the first reset control line Reset1, and to couple the signal of the data signal line DL to the third node N3 under the control of the first scan signal provided by the first scan signal line Gate1.

[0036] In an exemplary embodiment, the coupling subcircuit 1022 may include a data write subcircuit, a first reset subcircuit and a first coupling subcircuit (not shown in the figure), wherein the data write subcircuit is configured to write the signal of the data signal line DL to a fifth node (not shown in the figure) under the control of a first scan signal provided by the first scan signal line Gate1; the first reset subcircuit is configured to write the signal of the first initial signal line INIT1 to the fifth node under the control of a first reset control signal provided by the first reset control line Reset1; and the first coupling subcircuit is configured to couple the signal of the fifth node to the third node N3.

[0037] In an exemplary embodiment, Figure 5 As shown, the pixel circuit may further include: a second reset sub-circuit 1023, wherein the second reset sub-circuit 1023 is electrically connected to the second reset control line Reset2, the second initial signal line INIT2 and the first node N1, respectively, and is configured to provide a signal of the second initial signal line INIT2 to the first node N1 under the control of a second reset control signal provided by the second reset control line Reset2, i.e., the first node N1 is reset using the signal of the second initial signal line INIT2.

[0038] In an exemplary embodiment, Figure 5 As shown, the pixel circuit may further include: a third reset sub-circuit 1024, wherein the third reset sub-circuit 1024 is electrically connected to the third reset control line Reset3, the third initial signal line INIT3 and the fourth node N4 (i.e., the anode of the light-emitting device), respectively, and is configured to provide a signal of the third initial signal line INIT3 to the fourth node N4 under the control of a third reset control signal provided by the third reset control line Reset3, i.e., the fourth node N4 is reset using the signal of the third initial signal line INIT3.

[0039] In an exemplary embodiment, Figure 5 As shown, the pixel circuit may further include: a holding subcircuit 1025, wherein the holding subcircuit 1025 is electrically connected to the first node N1 and the third node N3, respectively, and is configured to store a voltage difference of a signal between the first node N1 and the third node N3.

[0040] In an exemplary embodiment, Figure 5 As shown, the pixel circuit may further include: a first light-emitting control subcircuit 1026, wherein the first light-emitting control subcircuit 1026 is electrically connected to the second node N2, the first light-emitting control line EM1 and the first power line VDD, respectively, and is configured to provide a signal of the first power line VDD to the second node N2 under the control of the signal of the first light-emitting control line EM1.

[0041] In an exemplary embodiment, Figure 5 As shown, the pixel circuit may further include: a second light-emitting control subcircuit 1027, wherein the second light-emitting control subcircuit 1027 is electrically connected to the third node N3, the fourth node N4 and the second light-emitting control line EM2, respectively, and is configured to turn on the third node N3 and the fourth node N4, that is, turn on the third node N3 and the anode of the light-emitting device under the control of the signal of the second light-emitting control line EM2.

[0042] In an exemplary embodiment, the first power line VDD may continuously provide a high level signal, and the signal of the first power line VDD is a DC signal.

[0043] In the embodiment of the present disclosure, the second reset sub-circuit 1023 connected to the first node is electrically connected only to the second initial signal line INIT2 and the second reset control line Reset2, which means that the number of transistors connected to the first node N1 is relatively small, and the setting of the coupling sub-circuit 1022 can couple the data signal of the data signal line to the third node N3 connected to the driving sub-circuit 1021, thereby reducing the number of transistors directly coupled to the first node N1 connected to the driving sub-circuit 1021, and achieving normal data writing and threshold compensation. Therefore, the pixel circuit provided in the embodiment of the present disclosure can reduce the parasitic capacitance coupled to the first node N1 while ensuring normal display, so that the voltage of the driving signal maintained between the gate electrode and the source electrode of the driving sub-circuit 1021 is not easy to deviate, thereby ensuring the consistency of the display brightness of the display product and improving the display effect of the display substrate.

[0044] In an exemplary embodiment, the pixel circuit is configured to drive the light emitting device L to emit light.

[0045] In an exemplary embodiment, the light emitting device may include a stacked first electrode (anode), an organic light emitting layer and a second electrode (cathode). Exemplarily, the anode of the light emitting device is electrically connected to the pixel circuit, and the cathode of the light emitting device is electrically connected to the second power supply terminal VSS.

[0046] In an exemplary embodiment, the second power supply terminal VSS may continuously provide a low level signal, and the signal of the second power supply terminal VSS is a DC signal.

[0047] In an exemplary embodiment, the light emitting device may include a current driven device, and a current light emitting diode may be used, such as a micro light emitting diode (Micro Light Emitting Diode, Micro LED for short) or a mini light emitting diode (Mini Light Emitting Diode, Mini LED for short) or an organic light emitting diode (Organic Light Emitting Diode, OLED for short) or a quantum dot light emitting diode (Quantum Light Emitting Diode, QLED for short). The typical size (e.g., length) of a Micro LED may be less than 100 μm, such as 10 μm to 50 μm. The typical size (e.g., length) of a Mini LED may be about 100 μm to 300 μm, such as 120 μm to 260 μm.

[0048] In an exemplary embodiment, the organic light emitting layer may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), an emitting layer (EML), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the electron transport layers of all sub-pixels may be a common layer connected together, the hole blocking layers of all sub-pixels may be a common layer connected together, the light emitting layers of adjacent sub-pixels may have a small overlap, or may be isolated, and the electron blocking layers of adjacent sub-pixels may have a small overlap, or may be isolated.

[0049] Figure 6 is an equivalent circuit diagram of a pixel circuit according to an embodiment of the present disclosure. In an exemplary embodiment, Figure 6 As shown, the driving subcircuit 1021 includes: a driving transistor T3. In some exemplary embodiments, the driving transistor T3 may be a single-gate transistor. The control electrode of the driving transistor T3 is electrically connected to the first node N1, the first electrode of the driving transistor T3 is electrically connected to the second node N2, and the second electrode of the driving transistor T3 is electrically connected to the third node N3.

[0050] In some other exemplary embodiments, the driving transistor T3 may be a dual-gate transistor, and the driving transistor T3 includes: a first control electrode and a second control electrode. The first control electrode of the driving transistor T3 may be electrically connected to the first node N1, and the second control electrode of the driving transistor T3 may be electrically connected to the third node N3 (not shown in the figure). The connection method of the driving transistor in the present disclosure may improve the output saturation characteristics of the driving transistor T3.

[0051] In an exemplary embodiment, if Figure 6As shown, the coupling subcircuit 1022 may include: a first reset transistor T7, a data writing transistor T4 and a second capacitor C2. The control electrode of the first reset transistor T7 is electrically connected to the first reset control line Reset1, the first electrode of the first reset transistor T7 is electrically connected to the first initial signal line INIT1, and the second electrode of the first reset transistor T7 is electrically connected to the fifth node N5; the control electrode of the data writing transistor T4 is electrically connected to the first scanning signal line Gate1, the first electrode of the data writing transistor T4 is electrically connected to the data signal line DL, and the second electrode of the data writing transistor T4 is electrically connected to the fifth node N5; the first end of the second capacitor C2 is electrically connected to the fifth node N5, and the second end of the second capacitor C2 is electrically connected to the third node N3.

[0052] In an exemplary embodiment, the first initial signal line INIT1 may receive a first initial signal. The first reset transistor T7 writes the first initial signal into the fifth node N5 under the control of the first reset control signal of the first reset control line Reset1.

[0053] In an exemplary embodiment, the data signal line DL may receive a data signal. The data write transistor T4 writes the data signal into the fifth node N5 under the control of the first scan signal of the first scan signal line Gate1.

[0054] In an exemplary embodiment, if Figure 6 As shown, the second reset subcircuit 1023 may include: a second reset transistor T1. The control electrode of the second reset transistor T1 is electrically connected to the second reset control line Reset2, the first electrode of the second reset transistor T1 is electrically connected to the second initial signal line INIT2, and the second electrode of the second reset transistor T1 is electrically connected to the first node N1.

[0055] In an exemplary embodiment, the second initial signal line INIT2 may receive a second initial signal. The second reset transistor T1 writes the second initial signal into the first node N1 under the control of the second reset control signal of the second reset control line Reset2, that is, resets the first node N1.

[0056] In an exemplary embodiment, if Figure 6 As shown, the third reset subcircuit 1024 may include: a third reset transistor T2. The control electrode of the third reset transistor T2 is electrically connected to the third reset control line Reset3, the first electrode of the third reset transistor T2 is electrically connected to the third initial signal line INIT3, and the second electrode of the third reset transistor T2 is electrically connected to the fourth node N4.

[0057] In an exemplary embodiment, the third initial signal line INIT3 may receive a third initial signal. The third reset transistor T2 writes the third initial signal to the fourth node N4 under the control of the third reset control signal of the third reset control line Reset3, that is, resets the fourth node N4. In other exemplary embodiments, the third reset transistor T2 may also write the third initial signal to the third node N3 under the control of the third reset control signal of the third reset control line Reset3, that is, resets the third node N3. That is, the third reset transistor T2 writes the third initial signal to the third node N3 or the fourth node N4 under the control of the signal of the third reset control line Reset3, and initializes the third node N3 or the fourth node N4. Exemplarily, the third reset transistor T2 may be turned on once in a display frame, or may be turned on multiple times, and the present disclosure does not limit this. When the second electrode of the third reset transistor T2 is electrically connected to the third node N3, the third reset transistor T2 may be turned on to initialize the second electrode of the driving transistor T3, or bias the driving transistor T3. When the second electrode of the third reset transistor T2 is electrically connected to the fourth node N4, the third reset transistor T2 is turned on to initialize the anode of the light emitting device.

[0058] In an exemplary embodiment, if Figure 6 As shown, the holding subcircuit 1025 includes: a first capacitor C1. A first end of the first capacitor C1 is electrically connected to the first node N1, and a second end of the first capacitor C1 is electrically connected to the third node N3.

[0059] In an exemplary embodiment, the first capacitor C1 can ensure the stability of the signal of the first node N1 and can improve the reliability of the pixel circuit.

[0060] In an exemplary embodiment, if Figure 6 As shown, the first light emission control subcircuit 1026 may include: a first light emission control transistor T5. The control electrode of the first light emission control transistor T5 is electrically connected to the first light emission control line EM1, the first electrode of the first light emission control transistor T5 is electrically connected to the first power supply line VDD, and the second electrode of the first light emission control transistor T5 is electrically connected to the second node N2.

[0061] In an exemplary embodiment, if Figure 6 As shown, the second light emitting control subcircuit 1027 may include: a second light emitting control transistor T6. The control electrode of the second light emitting control transistor T6 is electrically connected to the second light emitting control line EM2, the first electrode of the second light emitting control transistor T6 is electrically connected to the third node N3, and the second electrode of the second light emitting control transistor T6 is electrically connected to the fourth node N4.

[0062] In an exemplary embodiment, the signals received by the second initial signal line INIT2 and the first power line VDD connected to the same pixel circuit may be the same signal.

[0063] In an exemplary embodiment, the second initial signal received by the second initial signal line INIT2 is a positive voltage signal to ensure that the driving transistor T3 can be normally turned on, thereby improving the reliability of the pixel circuit.

[0064] In an exemplary embodiment, the signals received by the first initial signal line INIT1 and the second initial signal line INIT2 connected to the same pixel circuit may be the same signal.

[0065] In an exemplary embodiment, the voltage value of the third initial signal received by the third initial signal line INIT3 is less than the sum of the voltage value of the signal of the second power line VSS and the voltage value between the two electrodes of the light-emitting device, so as to ensure that the light-emitting device does not emit light when the anode of the light-emitting device L is initialized.

[0066] In an exemplary embodiment, a voltage value of the second initial signal received by the second initial signal line INIT2 may be equal to a voltage value of the first initial signal received by the first initial signal line INIT1, and a voltage value of the second initial signal received by the second initial signal line INIT2 may be greater than a voltage value of the third initial signal received by the third initial signal line INIT3.

[0067] In an exemplary embodiment, the signal received by the first reset control line Reset1 connected to the same pixel circuit and the signal received by the first light-emitting control line EM1 can be the same signal, or the signal received by the first reset control line Reset1 connected to the i-th row of pixel circuits and the second reset control line Reset2 connected to the i-1-th row of pixel circuits can be the same signal.

[0068] In an exemplary embodiment, the signals received by at least two signal terminals connected to the pixel circuit are the same signal, which can reduce the number of signal lines connected to the pixel circuit and achieve a high PPI of the display device.

[0069] In an exemplary embodiment, transistors can be divided into N-type transistors and P-type transistors according to the characteristics of the transistors. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltages), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltages). When the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltages), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltages).

[0070] In an exemplary embodiment, the N-type transistor may be an oxide thin film transistor. The active pattern of the oxide thin film transistor is an oxide semiconductor. The oxide thin film transistor has the advantages of low leakage current, which can reduce power consumption and improve display quality.

[0071] In an exemplary embodiment, any one of the first capacitor C1 and the second capacitor C2 can be a capacitor device made by a process. For example, the capacitor device can be realized by making a special capacitor electrode, and the multiple capacitor electrodes of the capacitor can be realized by a metal layer, a semiconductor layer (such as doped polysilicon), etc. Alternatively, any one of the first capacitor C1 and the second capacitor C2 can be a parasitic capacitor between multiple devices, which can be realized by the transistor itself and other devices and circuits. The connection method of any one of the first capacitor C1 and the second capacitor C2 includes but is not limited to the method described above, and can be other applicable connection methods, and the level of the corresponding node can be stored. Here, the exemplary embodiment of the present disclosure does not limit this.

[0072] In an exemplary embodiment, Figure 6 At least one of the second reset transistor T1, the third reset transistor T2, the driving transistor T3, the data writing transistor T4, the first light emission control transistor T5, the second light emission control transistor T6 and the first reset transistor T7 is an N-type transistor. Exemplarily, the second reset transistor T1, the third reset transistor T2, the driving transistor T3, the data writing transistor T4, the first light emission control transistor T5, the second light emission control transistor T6 and the first reset transistor T7 may all be N-type transistors, or the second reset transistor T1, the third reset transistor T2, the driving transistor T3, the data writing transistor T4, the second light emission control transistor T6 and the first reset transistor T7 may be N-type transistors, and the first light emission control transistor T5 may be a P-type transistor, which is not limited in the present disclosure.

[0073] Figure 7 for Figure 6 A driving timing diagram of a pixel circuit is provided. Figure 7 So Figure 6 The description is made by taking the example that the first light emitting control transistor T5 is a P-type transistor and all other transistors are N-type transistors. Figure 7 The following description is made by taking the case that the signals received by the first reset control line Reset1 connected to the pixel circuits in the i-th row and the second reset control line Reset2 connected to the pixel circuits in the i-1th row are the same signal. Figure 7 As shown, Figure 6 The working process of the provided pixel circuit may include: In the first stage H1, the initialization stage, the signals of the first light-emitting control line EM1, the first reset control line Reset1, the second reset control line Reset2 and the third reset control line Reset3 are high-level signals, and the signals of the second light-emitting control line EM2 and the first scanning signal line Gate1 are low-level signals. The first reset transistor T7, the second reset transistor T1 and the third reset transistor T2 are turned on, and the data writing transistor T4, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned off.

[0074] The first reset transistor T7 is turned on, and the signal of the first initial signal line INIT1 is written into the fifth node N5, and the voltage value VN5 of the signal of the fifth node N5 is Vinit1, where Vinit1 is the voltage value of the signal of the first initial signal line INIT1. The second reset transistor T1 is turned on, and the signal of the second initial signal line INIT2 is written into the first node N1, and the voltage value VN1 of the signal of the first node N1 is Vinit2, where Vinit2 is the voltage value of the signal of the second initial signal line INIT2. The third reset transistor T2 is turned on, and the signal of the third initial signal line INIT3 is written into the fourth node N4, and the voltage value VN4 of the signal of the fourth node N4 is Vinit3, where Vinit3 is the voltage value of the signal of the third initial signal line INIT3.

[0075] In the second stage H2, the threshold compensation stage, the signals of the first reset control line Reset1, the second reset control line Reset2 and the third reset control line Reset3 are high level signals, and the first light emission control line EM1, the second light emission control line EM2 and the first scanning signal line Gate1 are low level signals. The first reset transistor T7, the second reset transistor T1, the third reset transistor T2 and the first light emission control transistor T5 are turned on, and the data writing transistor T4 and the second light emission control transistor T6 are turned off.

[0076] The first reset transistor T7 is turned on, and the signal of the first initial signal line INIT1 is written into the fifth node N5, and the voltage value VN5 of the signal of the fifth node N5 is Vinit1. The second reset transistor T1 is turned on, and the signal of the second initial signal line INIT2 is written into the first node N1, and the voltage value VN1 of the signal of the first node N1 is Vinit2. The third reset transistor T2 is turned on, and the signal of the third initial signal line INIT3 is written into the fourth node N4, and the voltage value VN4 of the signal of the fourth node N4 is Vinit3. The first light-emitting control transistor T5 is turned on, and the first power line VDD charges the third node N3 through the turned-on first light-emitting control transistor T5, the second node N2 and the turned-on driving transistor T3, until the voltage value VN3 of the signal of the third node N3 is Vinit2-Vth, where Vth is the threshold voltage of the driving transistor T3. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is Vinit1-Vinit2+Vth.

[0077] In the third stage H3, the data writing stage, the signals of the first light emitting control line EM1, the second reset control line Reset2, the third reset control line Reset3 and the first scanning signal line Gate1 are high level signals, and the signals of the second light emitting control line EM2 and the first reset control line Reset1 are low level signals. The second reset transistor T1, the third reset transistor T2 and the data writing transistor T4 are turned on, and the first light emitting control transistor T5, the second light emitting control transistor T6 and the first reset transistor T7 are turned off.

[0078] The second reset transistor T1 is turned on, and the signal of the second initial signal line INIT2 is written into the first node N1, and the voltage value VN1 of the signal of the first node N1 is Vinit2. The third reset transistor T2 is turned on, and the signal of the third initial signal line INIT3 is written into the fourth node N4, and the voltage value VN4 of the signal of the fourth node N4 is Vinit3. The data writing transistor T4 is turned on, and the signal of the data signal line DL is written into the fifth node N5, and the voltage value VN5 of the signal of the fifth node N5 is Vdata. The voltage value of the signal of the fifth node N5 jumps from Vinit1 in the previous stage to Vdata. Under the coupling effect of the second capacitor C2, the voltage value VN3 of the signal of the third node N3 also jumps, VN3= Vinit2-Vth+(Vdata-Vinit1)(C2 / C1+C2), C1 is the capacitance value of the first capacitor C1, and C2 is the capacitance value of the second capacitor C2.

[0079] In the fourth stage H4, the light-emitting stage, the signal of the second light-emitting control line EM2 is a high-level signal, and the signals of the first light-emitting control line EM1, the first reset control line Reset1, the second reset control line Reset2, the third reset control line Reset3 and the first scanning signal line Gate1 are all low-level signals. The first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on, and the first reset transistor T7, the second reset transistor T1, the third reset transistor T2 and the data writing transistor T4 are turned off.

[0080] The first light emitting control transistor T5 and the second light emitting control transistor T6 are turned on so that the first power supply voltage output by the first power supply line VDD provides a driving current to the first electrode of the light emitting device EL through the turned-on first light emitting control transistor T5, the turned-on driving transistor T3 and the turned-on second light emitting control transistor T6, so as to drive the light emitting device EL to emit light.

[0081] During the pixel circuit driving process, the driving current flowing through the driving transistor T3 of each pixel circuit is determined by the voltage difference between its gate electrode and the second electrode. The voltage value VN3 of the signal at the third node N3 = Vss + VOLED, and the signal at the first node N1 jumps under the coupling effect of the first capacitor C1. The voltage value VN1 of the signal at the first node N1 = Vinit2 + Vss + VOLED OLED -[Vinit2-Vth+(Vdata-Vinit1)(C2 / C1+C2)]=Vss+V OLED +Vth-(Vdata-Vinit1)(C2 / C1+C2).

[0082] At this time, the driving current I flowing through the driving transistor T3 (also the driving current driving the light emitting device EL) satisfies: I=K*(Vgs-Vth) 2 =K*(V1-V3-Vth) 2 =K*[(Vinit1-Vdata)(C2 / C1+C2)] 2 Wherein, K is a constant related to process and design, and Vgs is a voltage difference between the gate electrode and the second electrode of the driving transistor T3.

[0083] In the above formula, the driving current I is independent of the first power supply voltage Vdd and the threshold voltage Vth, thereby eliminating the influence of the voltage drop of the first power supply line VDD and the threshold voltage Vth drift of the driving transistor T3 on the driving signal, thereby ensuring uniform display brightness and improving display effect.

[0084] In the disclosed embodiment, the signal of the third initial voltage line INIT3 is provided to the fourth node N4 through the turned-on third reset transistor T2, so that the fourth node N4 is reset to the third initial voltage Vinit3. On the one hand, the leakage current of the second light-emitting control transistor T6 is released from the third reset transistor T2, thereby preventing the leakage current of the second light-emitting control transistor T6 from turning on the light-emitting device prematurely; on the other hand, the signal noise generated by the jump of the second light-emitting control signal EM2 can be filtered through the third reset transistor T2, thereby preventing the signal noise from damaging the light-emitting device.

[0085] The present disclosure provides an array substrate, including a plurality of sub-pixels arranged in an array and a plurality of scan control lines, data signal lines and initial signal lines, wherein the sub-pixels include a pixel circuit and a light-emitting device electrically connected to the pixel circuit, each scan control line is electrically connected to at least one row of pixel circuits, the scan control line includes a first scan signal line Gate1 and a first reset control line Reset1, the array substrate further includes a GOA circuit group for driving the pixel circuits in rows, the GOA circuit group includes: a first GOA circuit and a second GOA circuit, wherein: The first GOA circuit includes a plurality of first GOA units connected in cascade, each of which is connected to a first scanning signal line Gate1 and is configured to provide a first scanning signal to a coupling subcircuit 1022 in a row of pixel circuits; The second GOA circuit includes a plurality of second GOA units connected in cascade, each second GOA unit is connected to at least one first reset control line Reset1, and is configured to provide a first reset control signal to a coupling subcircuit 1022 in at least one row of pixel circuits, and the second GOA unit is arranged on one side of the display area to perform unilateral driving on the first reset control line Reset1, or each second GOA unit is connected to two or more first reset control lines Reset1, and is configured to provide a first reset control signal to the coupling subcircuit 1022 in two or more rows of pixel circuits.

[0086] The array substrate of the disclosed embodiment can achieve both the desired pixel display effect and a narrow frame by driving the GOA circuits connected to some scanning control lines in a single-side manner or a one-drive-multiple manner.

[0087] Exemplarily, each second GOA unit is connected to two or three first reset control lines Reset1 and is configured to provide a first reset control signal to the coupling sub-circuit 1022 in two or three rows of pixel circuits.

[0088] In some exemplary embodiments, the GOA circuit group further includes: a third GOA circuit, the third GOA circuit including a plurality of third GOA units connected in cascade, each third GOA unit being connected to at least one second reset control line Reset2, and being configured to provide a second reset control signal to the second reset subcircuit 1023 in at least one row of pixel circuits; The third GOA unit is disposed on the left and right sides of the display area to perform bilateral driving on the second reset control line Reset2.

[0089] Exemplarily, each third GOA unit is connected to two or three second reset control lines Reset2 and is configured to provide a second reset control signal to the second reset sub-circuit 1023 in two or three rows of pixel circuits.

[0090] In some exemplary embodiments, the GOA circuit group further includes: a fourth GOA circuit, the fourth GOA circuit including a plurality of fourth GOA units connected in cascade, each fourth GOA unit being connected to at least one third reset control line Reset3, and being configured to provide a third reset control signal to a third reset subcircuit 1024 in at least one row of pixel circuits; The fourth GOA unit is arranged on one side of the display area to unilaterally drive the third reset control line Reset3, or each fourth GOA unit is connected to two or more third reset control lines Reset3, and is configured to provide a third reset control signal to the third reset sub-circuit 1024 in two or more rows of pixel circuits.

[0091] Exemplarily, each fourth GOA unit is connected to two or three third reset control lines Reset3 and is configured to provide a third reset control signal to the third reset sub-circuit 1024 in two or three rows of pixel circuits.

[0092] In some exemplary embodiments, the GOA circuit group further includes: a fifth GOA circuit, the fifth GOA circuit including a plurality of fifth GOA units connected in cascade, each fifth GOA unit being connected to at least one first light emission control line EM1, and being configured to provide a first light emission control signal to a first light emission control subcircuit 1026 in at least one row of pixel circuits; The fifth GOA unit is arranged on one side of the display area to unilaterally drive the first light-emitting control line EM1, or each fifth GOA unit is connected to two or more first light-emitting control lines EM1, and is configured to provide a first light-emitting control signal to the first light-emitting control sub-circuit 1026 in two or more rows of pixel circuits.

[0093] Exemplarily, each fifth GOA unit is connected to two or three first light emission control lines EM1 and is configured to provide the first light emission control signal to the first light emission control sub-circuit 1026 in two or three rows of pixel circuits.

[0094] In some exemplary embodiments, the GOA circuit group further includes: a sixth GOA circuit, the sixth GOA circuit including a plurality of sixth GOA units connected in cascade, each sixth GOA unit being connected to at least one second light emission control line EM2, and being configured to provide a second light emission control signal to a second light emission control sub-circuit in at least one row of pixel circuits; The sixth GOA unit is arranged on one side of the display area to unilaterally drive the second light-emitting control line EM2, or each sixth GOA unit is connected to two or more second light-emitting control lines EM2, and is configured to provide a second light-emitting control signal to the second light-emitting control sub-circuit 1027 in two or more rows of pixel circuits.

[0095] Exemplarily, each sixth GOA unit is connected to two or three second light emitting control lines EM2 and is configured to provide the second light emitting control signal to the second light emitting control sub-circuit 1027 in two or three rows of pixel circuits.

[0096] FIG. 8A to FIG. 8F They are Figure 6 Schematic diagram of the effect of the signals provided by the first reset control line Reset1, the second reset control line Reset2, the third reset control line Reset3, the first light-emitting control line EM1, the second light-emitting control line EM2, and the first scanning signal line Gate1 on the driving current under different delay times, wherein Tr represents the rising edge delay, and Tf represents the falling edge delay. When the GOA circuit connected to a certain scanning control line adopts a unilateral driving scheme, the difference between the rising edge delay and the falling edge delay corresponding to the input end and the far end of the scanning control line is greater; when the GOA circuit connected to a certain scanning control line adopts a bilateral driving scheme, the left and right sides of the scanning control line are both input ends, and the far end is the center of the screen. Therefore, at this time, the difference between the rising edge delay and the falling edge delay on the left and right sides of the scanning control line is smaller. FIG. 8A to FIG. 8F As shown, after simulation, it is found that when the GOA circuit corresponding to the second reset control line Reset2 and the first scanning signal line Gate1 adopts a unilateral driving scheme, the difference in pixel driving current between the input position and the opposite side of the input position of this group of GOA circuits is large, while when the other four groups of GOA circuits (the first light-emitting control line EM1, the second light-emitting control line EM2, the first reset control line Reset1, and the third reset control line Reset3) adopt a unilateral driving scheme, the difference in pixel driving current between their input position and the opposite side of the input position is small, so these four groups of GOA can adopt a unilateral driving scheme.

[0097] Fig. 9 for Figure 6 When the pixel circuit shown in the figure is driven by a one-drive-two scheme, the first node N1 to the fifth node N5 and the gate-source voltage Vgs are simulated waveform results, as shown in FIG. Fig. 9 As shown in FIG. 1 , if the GOA circuits of the other scan control lines except the first scan signal line Gate1 are driven by a one-drive-two scheme, within the time range a, due to the unequal voltage between the second node N2 and the third node N3 (at this time, the driving transistor T3 is turned on, and the second node N2 slowly charges the third node N3), it will cause the brightness difference of the odd and even rows, but this problem can be improved by extending the time range a. Table 1 shows Figure 6 The pixel circuit shown is a simulation result of the odd-even row current difference when the six groups of GOA circuits corresponding to the first reset control line Reset1, the second reset control line Reset2, the third reset control line Reset3, the first light-emitting control line EM1, the second light-emitting control line EM2, and the first scanning signal line Gate1 are driven by a one-drive-two scheme, where 2H represents the scanning time of two pixel rows, 3H represents the scanning time of three pixel rows, and 4H represents the scanning time of four pixel rows.

[0098]

[0099] Table 1 As shown in Table 1, according to the simulation results, when the time range of period a is extended to the scanning time of three or more pixel rows, the pixel circuit of the embodiment of the present disclosure can be driven by one-drive-two and one-drive-many schemes.

[0100] In some exemplary embodiments, for each row of pixel circuits, a start writing time of the first scanning signal and an end writing time of the first reset control signal differ by at least three pixel row scanning times (3H).

[0101] Exemplarily, for each row of pixel circuits, the difference between the start writing time of the first scanning signal and the end writing time of the first reset control signal is the scanning time of four pixel rows (4H).

[0102] Figures 10 to 23 Schematic diagram of driving modes of several GOA circuits according to exemplary embodiments of the present disclosure. Figures 10 to 23In the figure, each GOA circuit is identified by the scan control line connected to it. For example, Gate1 in the figure represents the first GOA circuit (or the first GOA unit) connected to the first scan signal line Gate1, Reset1 in the figure represents the second GOA circuit (or the second GOA unit) connected to the first reset control line Reset1, Reset2 in the figure represents the third GOA circuit (or the third GOA unit) connected to the second reset control line Reset2, Reset3 in the figure represents the fourth GOA circuit (or the fourth GOA unit) connected to the third reset control line Reset3, EM1 in the figure represents the fifth GOA circuit (or the fifth GOA unit) connected to the first light-emitting control line EM1, and EM2 in the figure represents the sixth GOA circuit (or the sixth GOA unit) connected to the second light-emitting control line EM2.

[0103] like Fig.10 As shown, the pixel circuit of the embodiment of the present disclosure can be driven by six groups of GOA circuits, and the six groups of GOA circuits include the first GOA circuit to the sixth GOA circuit, wherein the first GOA circuit includes a plurality of first GOA units connected in cascade, each of which is connected to the first scan signal line Gate1, and is configured to provide a first scan signal to the coupling subcircuit 1022 in a row of pixel circuits. The second GOA circuit includes a plurality of second GOA units connected in cascade, each of which is connected to a first reset control line Reset1, and is configured to provide a first reset control signal to the coupling subcircuit 1022 in a row of pixel circuits. The third GOA circuit includes a plurality of third GOA units connected in cascade, each of which is connected to a second reset control line Reset2, and is configured to provide a second reset control signal to the second reset subcircuit 1023 in a row of pixel circuits. The fourth GOA circuit includes a plurality of fourth GOA units connected in cascade, each of which is connected to a third reset control line Reset3, and is configured to provide a third reset control signal to the third reset subcircuit 1024 in a row of pixel circuits. The fifth GOA circuit includes a plurality of fifth GOA units connected in cascade, each of which is connected to a first light-emitting control line EM1, and is configured to provide a first light-emitting control signal to a first light-emitting control subcircuit 1026 in a row of pixel circuits. The sixth GOA circuit includes a plurality of sixth GOA units connected in cascade, each of which is connected to a second light-emitting control line EM2, and is configured to provide a second light-emitting control signal to a second light-emitting control subcircuit 1027 in a row of pixel circuits. In this embodiment, the first GOA circuit to the sixth GOA circuit are arranged on the left and right sides of the display area, and perform bilateral driving on the scanning control lines connected to them.

[0104] like Fig.11As shown, the pixel circuit of the embodiment of the present disclosure can be driven by five groups of GOA circuits, and the five groups of GOA circuits include the first GOA circuit, the third GOA circuit to the sixth GOA circuit, wherein the first GOA circuit includes a plurality of first GOA units connected in cascade, each of which is connected to the first scan signal line Gate1, and is configured to provide a first scan signal to the coupling subcircuit 1022 in a row of pixel circuits. The third GOA circuit includes a plurality of third GOA units connected in cascade, each of which is connected to a second reset control line Reset2, and is configured to provide a second reset control signal to the second reset subcircuit 1023 in a row of pixel circuits. The fourth GOA circuit includes a plurality of fourth GOA units connected in cascade, each of which is connected to a third reset control line Reset3, and is configured to provide a third reset control signal to the third reset subcircuit 1024 in a row of pixel circuits. The fifth GOA circuit includes a plurality of fifth GOA units connected in cascade, each of which is connected to a first light-emitting control line EM1, and is configured to provide a first light-emitting control signal to a first light-emitting control subcircuit 1026 in a row of pixel circuits. The sixth GOA circuit includes a plurality of sixth GOA units connected in cascade, each of which is connected to a second light-emitting control line EM2, and is configured to provide a second light-emitting control signal to a second light-emitting control subcircuit 1027 in a row of pixel circuits. In this embodiment, the first reset control line Reset1 and the second reset control line Reset2 share the third GOA unit, and the first reset control line Reset1 is driven by the advance stage of the second reset control line Reset2, thereby saving a set of GOA circuits. In this embodiment, the first GOA circuit to the fifth GOA circuit are arranged on the left and right sides of the display area, and the scanning control lines connected to each other are driven on both sides.

[0105] like Fig.12 As shown, the pixel circuit of the embodiment of the present disclosure is driven by six groups of GOA circuits. The correspondence between the six groups of GOA circuits and the scan control lines connected to them can refer to the above description, which will not be repeated here. In this embodiment, the second GOA circuit is only arranged on one side of the display area (such as the left side), and the first reset control line Reset1 is driven unilaterally. The third GOA circuit is also only arranged on one side of the display area (such as the right side), and the second reset control line Reset2 is driven unilaterally. The first GOA circuit, the fourth GOA circuit to the sixth GOA circuit are arranged on the left and right sides of the display area, and the scan control lines connected to them are driven bilaterally. Since the second GOA circuit and the third GOA circuit are only arranged on one side of the display area, the GOA circuit driving method of the embodiment of the present disclosure can achieve the effect of a narrow frame.

[0106] like Fig.13As shown, the pixel circuit of the embodiment of the present disclosure is driven by six groups of GOA circuits. The correspondence between the six groups of GOA circuits and the scan control lines connected to them can refer to the above description, which will not be repeated here. In this embodiment, the second GOA circuit is only arranged on one side of the display area (such as the right side), and the first reset control line Reset1 is driven unilaterally. The fourth GOA circuit is also only arranged on one side of the display area (such as the left side), and the third reset control line Reset3 is driven unilaterally. The first GOA circuit, the third GOA circuit, the fifth GOA circuit to the sixth GOA circuit are arranged on the left and right sides of the display area, and the scan control lines connected to them are driven bilaterally. Since the second GOA circuit and the fourth GOA circuit are only arranged on one side of the display area, the GOA circuit driving method of the embodiment of the present disclosure can achieve the effect of a narrow frame.

[0107] In the embodiment of the present disclosure, any one of the first GOA circuit, the fifth GOA circuit and the sixth GOA circuit may also be considered to be arranged only on one side of the display area to perform unilateral driving on the scanning control lines connected to each other, and the present disclosure does not impose any restrictions on this.

[0108] For example, the second GOA circuit can be set only on one side of the display area (such as the right side) to perform unilateral driving on the first reset control line Reset1, the fifth GOA circuit can also be set only on one side of the display area (such as the left side) to perform unilateral driving on the first light-emitting control line EM1, and the first GOA circuit, the third GOA circuit, the fourth GOA circuit and the sixth GOA circuit can be set on the left and right sides of the display area to perform bilateral driving on the scanning control lines connected to them respectively.

[0109] Alternatively, the second GOA circuit can be set only on one side of the display area (such as the right side) to perform unilateral driving on the first reset control line Reset1, the sixth GOA circuit can also be set only on one side of the display area (such as the left side) to perform unilateral driving on the second light-emitting control line EM2, and the first GOA circuit, the third GOA circuit, the fourth GOA circuit and the fifth GOA circuit can be set on the left and right sides of the display area to perform bilateral driving on the scanning control lines connected to them respectively.

[0110] Alternatively, the second GOA circuit can be set only on one side of the display area (such as the right side) to perform unilateral driving on the first reset control line Reset1, the first GOA circuit can also be set only on one side of the display area (such as the left side) to perform unilateral driving on the first scanning signal line Gate1, and the third to sixth GOA circuits can be set on the left and right sides of the display area to perform bilateral driving on the scanning control lines connected to them respectively.

[0111] Alternatively, the sixth GOA circuit can be set only on one side of the display area (such as the right side) to perform unilateral driving on the second light-emitting control line EM2, the third GOA circuit can also be set only on one side of the display area (such as the left side) to perform unilateral driving on the second reset control line Reset2, and the first GOA circuit to the second GOA circuit and the fourth GOA circuit to the fifth GOA circuit are set on the left and right sides of the display area to perform bilateral driving on the scanning control lines connected to them respectively.

[0112] Alternatively, the sixth GOA circuit can be set only on one side of the display area (such as the right side) to perform unilateral driving on the second light-emitting control line EM2, the fourth GOA circuit can also be set only on one side of the display area (such as the left side) to perform unilateral driving on the third reset control line Reset3, and the first GOA circuit to the third GOA circuit and the fifth GOA circuit are set on the left and right sides of the display area to perform bilateral driving on the scanning control lines connected to them respectively.

[0113] Alternatively, the sixth GOA circuit can be arranged only on one side of the display area (such as the right side) to perform unilateral driving on the second light-emitting control line EM2, the fifth GOA circuit can also be arranged only on one side of the display area (such as the left side) to perform unilateral driving on the first light-emitting control line EM1, and the first to fourth GOA circuits can be arranged on the left and right sides of the display area to perform bilateral driving on the scanning control lines connected to them respectively.

[0114] Alternatively, the sixth GOA circuit can be set only on one side of the display area (such as the right side) to perform unilateral driving on the second light-emitting control line EM2, the first GOA circuit can also be set only on one side of the display area (such as the left side) to perform unilateral driving on the first scanning signal line Gate1, and the second GOA circuit to the fifth GOA circuit can be set on the left and right sides of the display area to perform bilateral driving on the scanning control lines connected to them respectively.

[0115] like Fig.14 As shown, the pixel circuit of the embodiment of the present disclosure is driven by five groups of GOA circuits. The correspondence between the five groups of GOA circuits and the scan control lines connected to them can refer to the above description, which will not be repeated here. In this embodiment, the sixth GOA circuit is only arranged on one side of the display area (such as the right side), and the second light-emitting control line EM2 is driven unilaterally. The fourth GOA circuit is also only arranged on one side of the display area (such as the left side), and the third reset control line Reset3 is driven unilaterally. The first GOA circuit, the third GOA circuit, and the fifth GOA circuit are arranged on the left and right sides of the display area, and the scan control lines connected to them are driven bilaterally. Since the first reset control line Reset1 and the second reset control line Reset2 share the third GOA circuit, and the fourth GOA circuit and the sixth GOA circuit are only arranged on one side of the display area, the GOA circuit driving method of the embodiment of the present disclosure can achieve the effect of a narrow frame.

[0116] In the disclosed embodiment, any group of GOA circuits among the second GOA circuit and the fourth GOA circuit to the sixth GOA circuit can be driven on one side, so that a narrow frame effect can be achieved.

[0117] like Fig.15 As shown, the pixel circuit of the embodiment of the present disclosure is driven by six groups of GOA circuits. The corresponding relationship between the six groups of GOA circuits and the scan control lines connected to them can be referred to the above description, which will not be repeated here. In this embodiment, the six groups of GOA circuits are each only arranged on one side of the display area, and the scan control lines connected to them are driven unilaterally, so as to achieve the effect of a narrow frame.

[0118] like Fig.16 As shown, the pixel circuit of the disclosed embodiment is driven by six groups of GOA circuits. The correspondence between the six groups of GOA circuits and the scan control lines connected to them can be referred to as described above and will not be repeated here. In this embodiment, the six groups of GOA circuits are respectively arranged on the left and right sides of the display area to perform bilateral driving on the scan control lines connected to them, wherein each first GOA unit is connected to a first scan signal line Gate1, and is configured to provide a first scan signal to a coupling sub-circuit 1022 in a row of pixel circuits, each second GOA unit is connected to two first reset control lines Reset1, and is configured to provide a first reset control signal to the coupling sub-circuit 1022 in two rows of pixel circuits, and each third GOA unit is connected to two second reset control lines Reset2, and is configured to provide a first reset control signal to the coupling sub-circuit 1022 in two rows of pixel circuits. The second reset subcircuit 1023 provides a second reset control signal, each fourth GOA unit is connected to two third reset control lines Reset3, and is configured to provide a third reset control signal to the third reset subcircuit 1024 in the two rows of pixel circuits, each fifth GOA unit is connected to two first light-emitting control lines EM1, and is configured to provide a first light-emitting control signal to the first light-emitting control subcircuit 1026 in the two rows of pixel circuits, and each sixth GOA unit is connected to two second light-emitting control lines EM2, and is configured to provide a second light-emitting control signal to the second light-emitting control subcircuit 1027 in the two rows of pixel circuits. Since the second to sixth GOA circuits are all driven in a one-drive-two manner, the arrangement space of the GOA circuit in the column direction becomes larger, and the row direction space can be compressed, thereby achieving a narrow frame effect.

[0119] In this embodiment, the nth second GOA unit is disposed on the left and right sides of the 2n-1th row of sub-pixels and the 2nth row of sub-pixels, and is configured to provide a first reset control signal to the coupling sub-circuit 1022 in the 2n-1th row of sub-pixels and the 2nth row of pixel circuits; The nth third GOA unit is disposed on the left and right sides of the 2n-1th row of sub-pixels and the 2nth row of sub-pixels, and is configured to provide a second reset control signal to the second reset sub-circuit 1023 in the 2n-1th row of sub-pixels and the 2nth row of pixel circuits; The nth fourth GOA unit is disposed on the left and right sides of the 2n-1th row of sub-pixels and the 2nth row of sub-pixels, and is configured to provide a third reset control signal to the third reset sub-circuit 1024 in the 2n-1th row of sub-pixels and the 2nth row of pixel circuits; The nth fifth GOA unit is disposed on the left and right sides of the 2n-1th row of sub-pixels and the 2nth row of sub-pixels, and is configured to provide a first light emission control signal to the first light emission control sub-circuit 1026 in the pixel circuit of the 2n-1th row of sub-pixels and the 2nth row; The nth sixth GOA unit is arranged on the left and right sides of the 2n-1th row of sub-pixels and the 2nth row of sub-pixels, and is configured to provide a second light-emitting control signal to the second light-emitting control sub-circuit 1027 in the pixel circuit of the 2n-1th row of sub-pixels and the 2nth row.

[0120] In the disclosed embodiment, among the second to sixth GOA circuits, some of the GOA circuits may be driven in a one-drive-one manner, and some of the GOA circuits may be driven in a one-drive-two manner. For example, any four groups of GOA circuits among the second to sixth GOA circuits may be driven in a one-drive-two manner, and the other group of GOA circuits may be driven in a one-drive-one manner. Alternatively, any three groups of GOA circuits among the second to sixth GOA circuits may be driven in a one-drive-two manner, and the other two groups of GOA circuits may be driven in a one-drive-one manner. Alternatively, any two groups of GOA circuits among the second to sixth GOA circuits may be driven in a one-drive-two manner, and the other three groups of GOA circuits may be driven in a one-drive-one manner. Alternatively, any group of GOA circuits among the second to sixth GOA circuits may be driven in a one-drive-two manner, and the other four groups of GOA circuits may be driven in a one-drive-one manner.

[0121] In the disclosed embodiment, among the second to sixth GOA circuits, some GOA circuits can be driven in a one-drive-one manner, and some GOA circuits can be driven in a one-drive-two manner. At the same time, some GOA circuits can be driven in a unilateral manner, and some GOA circuits can be driven in a bilateral manner, that is, a mixture of one-drive-two and unilateral driving can be adopted to achieve the effect of a narrow bezel.

[0122] For example, Fig.17As shown, the pixel circuit of the embodiment of the present disclosure is driven by six groups of GOA circuits. The corresponding relationship between the six groups of GOA circuits and the scan control lines connected to them can be referred to the above description, which will not be repeated here. In this embodiment, among the six groups of GOA circuits, the first GOA circuit, the fourth GOA circuit to the sixth GOA circuit are respectively arranged on the left and right sides of the display area, and the scan control lines connected to them are driven on both sides, and the second GOA circuit to the third GOA circuit are respectively arranged on only one side of the display area, and the scan control lines connected to them are driven on one side. Among them, each first GOA unit is connected to a first scanning signal line Gate1, and is configured to provide a first scanning signal to a coupling subcircuit 1022 in a row of pixel circuits, each second GOA unit is connected to two first reset control lines Reset1, and is configured to provide a first reset control signal to the coupling subcircuit 1022 in the two rows of pixel circuits, each third GOA unit is connected to two second reset control lines Reset2, and is configured to provide a second reset control signal to the second reset subcircuit 1023 in the two rows of pixel circuits, each fourth GOA unit is connected to two third reset control lines Reset3, and is configured to provide a third reset control signal to the third reset subcircuit 1024 in the two rows of pixel circuits, each fifth GOA unit is connected to a first light-emitting control line EM1, and is configured to provide a first light-emitting control signal to the first light-emitting control subcircuit 1026 in a row of pixel circuits, and each sixth GOA unit is connected to two second light-emitting control lines EM2, and is configured to provide a second light-emitting control signal to the second light-emitting control subcircuit 1027 in the two rows of pixel circuits. Since the second GOA circuit to the third GOA circuit adopts unilateral driving, and the second GOA circuit to the fourth GOA circuit and the sixth GOA circuit are all driven in a one-drive-two manner, a narrow frame effect can be achieved.

[0123] In the disclosed embodiment, in the second to sixth GOA circuits, some or all of the GOA circuits may be driven in a one-drive-three manner to achieve a narrow frame effect.

[0124] For example, Fig.18As shown, the pixel circuit of the embodiment of the present disclosure is driven by six groups of GOA circuits. The corresponding relationship between the six groups of GOA circuits and the scan control lines connected to them can be referred to the above description, which will not be repeated here. In this embodiment, among the six groups of GOA circuits, the first GOA circuit to the sixth GOA circuit are respectively arranged on the left and right sides of the display area, and the scan control lines connected to them are driven on both sides. Among them, each first GOA unit is connected to a first scanning signal line Gate1, and is configured to provide a first scanning signal to a coupling subcircuit 1022 in a row of pixel circuits, each second GOA unit is connected to three first reset control lines Reset1, and is configured to provide a first reset control signal to the coupling subcircuit 1022 in three rows of pixel circuits, each third GOA unit is connected to three second reset control lines Reset2, and is configured to provide a second reset control signal to the second reset subcircuit 1023 in the three rows of pixel circuits, each fourth GOA unit is connected to three third reset control lines Reset3, and is configured to provide a third reset control signal to the third reset subcircuit 1024 in the three rows of pixel circuits, each fifth GOA unit is connected to three first light-emitting control lines EM1, and is configured to provide a first light-emitting control signal to the first light-emitting control subcircuit 1026 in the three rows of pixel circuits, and each sixth GOA unit is connected to three second light-emitting control lines EM2, and is configured to provide a second light-emitting control signal to the second light-emitting control subcircuit 1027 in the three rows of pixel circuits. Since the second to sixth GOA circuits are all driven in a one-drive-three mode, the arrangement space of the GOA circuits in the column direction becomes larger and the space in the row direction can be compressed, thereby achieving a narrow frame effect.

[0125] In this embodiment, the nth second GOA unit is arranged on the left and right sides of the 3n-2nd row of sub-pixels, the 3n-1st row of sub-pixels and the 3nth row of sub-pixels, and is configured to provide a first reset control signal to the coupling sub-circuit 1022 in the pixel circuit of the 3n-2nd row of sub-pixels, the 3n-1st row of sub-pixels and the 3nth row of sub-pixels; The nth third GOA unit is disposed on the left and right sides of the 3n-2nd row of sub-pixels, the 3n-1st row of sub-pixels, and the 3nth row of sub-pixels, and is configured to provide a second reset control signal to the second reset sub-circuit 1023 in the pixel circuit of the 3n-2nd row of sub-pixels, the 3n-1st row of sub-pixels, and the 3nth row of sub-pixels; The nth fourth GOA unit is disposed on the left and right sides of the 3n-2nd row of sub-pixels, the 3n-1st row of sub-pixels, and the 3nth row of sub-pixels, and is configured to provide a third reset control signal to the third reset sub-circuit 1024 in the pixel circuit of the 3n-2nd row of sub-pixels, the 3n-1st row of sub-pixels, and the 3nth row of sub-pixels; The nth fifth GOA unit is disposed on the left and right sides of the 3n-2nd row of sub-pixels, the 3n-1st row of sub-pixels, and the 3nth row of sub-pixels, and is configured to provide a first light emission control signal to the first light emission control sub-circuit 1026 in the pixel circuit of the 3n-2nd row of sub-pixels, the 3n-1st row of sub-pixels, and the 3nth row of sub-pixels; The nth sixth GOA unit is arranged on the left and right sides of the 3n-2th row of sub-pixels, the 3n-1th row of sub-pixels and the 3nth row of sub-pixels, and is configured to provide a second light-emitting control signal to the second light-emitting control sub-circuit 1027 in the pixel circuit of the 3n-2th row of sub-pixels, the 3n-1th row of sub-pixels and the 3nth row of sub-pixels.

[0126] In the disclosed embodiment, in the second to sixth GOA circuits, two or more GOA circuits may be placed in columns to achieve a narrow frame effect.

[0127] For example, Fig.19 As shown, the pixel circuit of the embodiment of the present disclosure is driven by six groups of GOA circuits. The corresponding relationship between the six groups of GOA circuits and the scan control lines connected to them can be referred to the above description, which will not be repeated here. In this embodiment, among the six groups of GOA circuits, the first GOA circuit to the sixth GOA circuit are respectively arranged on the left and right sides of the display area, and the scan control lines connected to them are driven unilaterally or bilaterally. Among them, each first GOA unit is connected to a first scanning signal line Gate1, and is configured to provide a first scanning signal to a coupling subcircuit 1022 in a row of pixel circuits, each second GOA unit is connected to three first reset control lines Reset1, and is configured to provide a first reset control signal to the coupling subcircuit 1022 in three rows of pixel circuits, each third GOA unit is connected to three second reset control lines Reset2, and is configured to provide a second reset control signal to the second reset subcircuit 1023 in the three rows of pixel circuits, each fourth GOA unit is connected to three third reset control lines Reset3, and is configured to provide a third reset control signal to the third reset subcircuit 1024 in the three rows of pixel circuits, each fifth GOA unit is connected to three first light-emitting control lines EM1, and is configured to provide a first light-emitting control signal to the first light-emitting control subcircuit 1026 in the three rows of pixel circuits, and each sixth GOA unit is connected to three second light-emitting control lines EM2, and is configured to provide a second light-emitting control signal to the second light-emitting control subcircuit 1027 in the three rows of pixel circuits. In this embodiment, the second GOA circuit to the fourth GOA circuit on the left and / or right side can be placed in columns. Since the second GOA circuit to the sixth GOA circuit are all driven in a one-drive-three mode, and the second GOA circuit to the fourth GOA circuit are arranged in a column, the arrangement space of the GOA circuit in the column direction and the row direction is increased, and the effect of a narrow border can be achieved.

[0128] In this embodiment, the 2n-1th second GOA unit is arranged on the left side of the 6n-5th row sub-pixel and the 6n-4th row sub-pixel, and is configured to provide the first reset control signal to the coupling sub-circuit 1022 in the pixel circuits of the 6n-5th row, the 6n-3th row and the 6n-1th row, and the 2nth second GOA unit is arranged on the right side of the 6n-5th row sub-pixel and the 6n-4th row sub-pixel, and is configured to provide the first reset control signal to the coupling sub-circuit 1022 in the pixel circuits of the 6n-4th row, the 6n-2th row and the 6nth row; The 2n-1th third GOA unit is arranged on the left side of the 6n-3th row sub-pixel and the 6n-2th row sub-pixel, and is configured to provide a second reset control signal to the second reset sub-circuit 1023 in the pixel circuits of the 6n-5th row, the 6n-3th row, and the 6n-1th row; the 2nth third GOA unit is arranged on the right side of the 6n-3th row sub-pixel and the 6n-2th row sub-pixel, and is configured to provide a second reset control signal to the second reset sub-circuit 1023 in the pixel circuits of the 6n-4th row, the 6n-2th row, and the 6nth row; The 2n-1th fourth GOA unit is arranged on the left side of the 6n-1th row of sub-pixels and the 6nth row of sub-pixels, and is configured to provide a third reset control signal to the third reset sub-circuit 1024 in the pixel circuits of the 6n-5th row, the 6n-3th row, and the 6n-1th row; the 2nth fourth GOA unit is arranged on the right side of the 6n-1th row of sub-pixels and the 6nth row of sub-pixels, and is configured to provide a third reset control signal to the third reset sub-circuit 1024 in the pixel circuits of the 6n-4th row, the 6n-2nd row, and the 6nth row; The nth fifth GOA unit is disposed on the left and right sides of the 3n-2nd row of sub-pixels, the 3n-1st row of sub-pixels, and the 3nth row of sub-pixels, and is configured to provide a first light emission control signal to the first light emission control sub-circuit 1026 in the pixel circuit of the 3n-2nd row of sub-pixels, the 3n-1st row of sub-pixels, and the 3nth row of sub-pixels; The nth sixth GOA unit is arranged on the left and right sides of the 3n-2th row of sub-pixels, the 3n-1th row of sub-pixels and the 3nth row of sub-pixels, and is configured to provide a second light-emitting control signal to the second light-emitting control sub-circuit 1027 in the pixel circuit of the 3n-2th row of sub-pixels, the 3n-1th row of sub-pixels and the 3nth row of sub-pixels, where n is a natural number greater than or equal to 1.

[0129] For example, Fig. 20As shown, the pixel circuit of the disclosed embodiment is driven by six groups of GOA circuits. The correspondence between the six groups of GOA circuits and the scan control lines connected to them can refer to the above description, which will not be repeated here. In this embodiment, the second GOA circuit to the fourth GOA circuit on the left and right sides are placed in a column and the second GOA circuit to the fourth GOA circuit adopt a bilateral driving scheme. Since the second GOA circuit to the sixth GOA circuit are driven by a one-drive-three mode and a bilateral driving mode, and the second GOA circuit to the fourth GOA circuit are placed in a column respectively, the arrangement space of the GOA circuit in the column direction and the row direction is enlarged, and the effect of a narrow frame can be achieved while ensuring the pixel display effect.

[0130] In this embodiment, the nth third GOA unit is arranged on the left and right sides of the 3n-2th row of sub-pixels, and is configured to provide a second reset control signal to the second reset sub-circuit 1023 in the pixel circuits of the 3n-2th row of sub-pixels, the 3n-1th row of sub-pixels, and the 3nth row of sub-pixels; The nth fourth GOA unit is disposed on the left and right sides of the 3n-1th row of sub-pixels, and is configured to provide a third reset control signal to the third reset sub-circuit 1023 in the pixel circuits of the 3n-2th row of sub-pixels, the 3n-1th row of sub-pixels, and the 3nth row of sub-pixels; The nth second GOA unit is disposed on the left and right sides of the 3nth row of sub-pixels, and is configured to provide a first reset control signal to the coupling sub-circuit 1022 in the pixel circuits of the 3n-2th row of sub-pixels, the 3n-1th row of sub-pixels, and the 3nth row of sub-pixels; The nth fifth GOA unit is disposed on the left and right sides of the 3n-2nd row of sub-pixels, the 3n-1st row of sub-pixels, and the 3nth row of sub-pixels, and is configured to provide a first light emission control signal to the first light emission control sub-circuit 1026 in the pixel circuit of the 3n-2nd row of sub-pixels, the 3n-1st row of sub-pixels, and the 3nth row of sub-pixels; The nth sixth GOA unit is arranged on the left and right sides of the 3n-2th row of sub-pixels, the 3n-1th row of sub-pixels and the 3nth row of sub-pixels, and is configured to provide a second light-emitting control signal to the second light-emitting control sub-circuit 1027 in the pixel circuit of the 3n-2th row of sub-pixels, the 3n-1th row of sub-pixels and the 3nth row of sub-pixels, where n is a natural number greater than or equal to 1.

[0131] In the disclosed embodiment, Fig.19 and Fig. 20 The arrangement order of the second GOA unit, the third GOA unit and the fourth GOA unit in the column direction can be set as needed, and the present disclosure does not limit this. By arranging the second GOA unit, the third GOA unit and the fourth GOA unit in one column, the arrangement space in the row direction can be saved, thereby achieving the effect of a narrow border.

[0132] For example, Fig.21 As shown, the pixel circuit of the disclosed embodiment is driven by six groups of GOA circuits. The correspondence between the six groups of GOA circuits and the scan control lines connected to them can refer to the above description and will not be repeated here. In this embodiment, the second GOA circuit to the fourth GOA circuit on the left and / or right side are placed in a column, and the fifth GOA circuit to the sixth GOA circuit on the left and / or right side are placed in a column. Since the second GOA circuit to the sixth GOA circuit are driven by a one-drive-three mode, and the second GOA circuit to the fourth GOA circuit and the fifth GOA circuit to the sixth GOA circuit are respectively placed in a column, the arrangement space of the GOA circuit in the column direction and the row direction is enlarged, and the effect of a narrow frame can be achieved.

[0133] In this embodiment, the connection method from the second GOA unit to the fourth GOA unit is as described above. Fig.19 The description is not repeated here.

[0134] In this embodiment, the 2n-1th fifth GOA unit is arranged on the left side of the 6n-5th row sub-pixel, the 6n-4th row and the 6n-3th row sub-pixel, and is configured to provide the first light control signal to the first light control sub-circuit 1026 in the pixel circuit of the 6n-5th row, the 6n-3th row and the 6n-1th row, and the 2nth second GOA unit is arranged on the right side of the 6n-5th row sub-pixel, the 6n-4th row and the 6n-3th row sub-pixel, and is configured to provide the first light control signal to the first light control sub-circuit 1026 in the pixel circuit of the 6n-4th row, the 6n-2th row and the 6nth row; The 2n-1th sixth GOA unit is set on the left side of the 6n-2th row sub-pixel, the 6n-1th row sub-pixel and the 6nth row sub-pixel, and is configured to provide a second light-emitting control signal to the second light-emitting control sub-circuit 1027 in the pixel circuit of the 6n-5th row, the 6n-3th row and the 6n-1th row, and the 2nth sixth GOA unit is set on the right side of the 6n-2th row sub-pixel, the 6n-1th row sub-pixel and the 6nth row sub-pixel, and is configured to provide a second light-emitting control signal to the second light-emitting control sub-circuit 1027 in the pixel circuit of the 6n-4th row, the 6n-2th row and the 6nth row.

[0135] In the embodiment of the present disclosure, the arrangement order of the fifth GOA unit and the sixth GOA unit in the column direction can be set as needed, and the present disclosure does not impose any restrictions on this. By arranging the second GOA unit, the third GOA unit and the fourth GOA unit in the same column, and the fifth GOA unit and the sixth GOA unit in the same column, the arrangement space in the row direction can be saved, thereby achieving the effect of a narrow border.

[0136] For example, Fig. 22As shown, the pixel circuit of the disclosed embodiment is driven by six groups of GOA circuits. The correspondence between the six groups of GOA circuits and the scan control lines connected to them can be referred to the above description, which will not be repeated here. In this embodiment, the second GOA circuit to the fourth GOA circuit on the left and right sides are placed in a column, and the fifth GOA circuit to the sixth GOA circuit on the left and right sides are placed in a column. Since the second GOA circuit to the sixth GOA circuit are driven by a one-drive-three mode and a bilateral mode, and the second GOA circuit to the fourth GOA circuit and the fifth GOA circuit to the sixth GOA circuit are respectively placed in a column, the arrangement space of the GOA circuit in the column direction and the row direction is enlarged, and the effect of a narrow frame can be achieved.

[0137] In this embodiment, the connection method from the second GOA unit to the fourth GOA unit is as described above. Fig. 20 The description is not repeated here.

[0138] In this embodiment, the nth fifth GOA unit and the nth sixth GOA unit are arranged on the left and right sides of the 3n-2th row of sub-pixels, the 3n-1th row of sub-pixels and the 3nth row of sub-pixels, and the nth fifth GOA unit and the nth sixth GOA unit on the left and right sides are arranged in a row respectively, and the nth fifth GOA unit is configured to provide a first light-emitting control signal to the first light-emitting control sub-circuit in the pixel circuit of the 3n-2th row of sub-pixels, the 3n-1th row of sub-pixels and the 3nth row of sub-pixels, and the nth sixth GOA unit is configured to provide a second light-emitting control signal to the second light-emitting control sub-circuit in the pixel circuit of the 3n-2th row of sub-pixels, the 3n-1th row of sub-pixels and the 3nth row of sub-pixels.

[0139] In the embodiment of the present disclosure, the arrangement order of the fifth GOA unit and the sixth GOA unit in the column direction can be set as needed, and the present disclosure does not impose any restrictions on this. By arranging the second GOA unit, the third GOA unit and the fourth GOA unit in the same column, and the fifth GOA unit and the sixth GOA unit in the same column, the arrangement space in the row direction can be saved, thereby achieving the effect of a narrow border.

[0140] In the disclosed embodiment, among the first to sixth GOA circuits, some GOA circuits can be driven in a one-drive-one mode, some GOA circuits can be driven in a one-drive-two mode, and some GOA circuits can be driven in a one-drive-three mode, thereby achieving a narrow bezel effect.

[0141] For example, Fig.23As shown, the pixel circuit of the disclosed embodiment is driven by six groups of GOA circuits. The correspondence between the six groups of GOA circuits and the scan control lines connected to them can refer to the above description, which will not be repeated here. In this embodiment, among the six groups of GOA circuits, the first GOA circuit to the sixth GOA circuit are respectively arranged on the left and right sides of the display area, and the scan control lines connected to them are driven on both sides, wherein the first GOA circuit is driven by a one-drive-one mode, the second GOA circuit to the fourth GOA circuit are driven by a one-drive-two mode, and the fifth GOA circuit to the sixth GOA circuit are driven by a one-drive-three mode, which can also achieve the effect of a narrow frame.

[0142] In this embodiment, in addition to the first GOA circuit, other groups of partial GOA circuits may be designed to be driven in a one-drive-one manner, thereby simultaneously ensuring the pixel display effect and achieving the effect of a narrow frame.

[0143] Fig.24 The pixel circuit of the embodiment of the present disclosure adopts Figures 18 to 22 The timing diagram corresponding to the signals of each scanning control line when driven by any of the driving modes shown. Fig.24 As shown, for each row of pixel circuits, the start writing time of the first scanning signal and the end writing time of the first reset control signal differ by three or more pixel row scanning times (for example, a=3H or a=4H).

[0144] An embodiment of the present disclosure further provides a display panel, comprising the array substrate as described in any embodiment of the present disclosure.

[0145] An embodiment of the present disclosure further provides a display device, comprising a display panel as described in any embodiment of the present disclosure.

[0146] In an exemplary embodiment, the display device may be any product or component having a display function, such as a wearable device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or the like.

[0147] The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures may refer to the general design.

[0148] For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness and size of the layer or microstructure are exaggerated. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element, or there may be intermediate elements.

[0149] Although the embodiments disclosed in the present disclosure are as above, the contents described are only embodiments adopted to facilitate understanding of the present disclosure and are not intended to limit the present disclosure. Any technician in the field to which the present disclosure belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present disclosure, but the scope of patent protection of the present disclosure shall still be subject to the scope defined in the attached claims.

Claims

1. An array substrate, characterized in that: The array substrate includes a plurality of sub-pixels arranged in an array and a plurality of scan control lines, data signal lines and initial signal lines, wherein the sub-pixels include a pixel circuit and a light-emitting device electrically connected to the pixel circuit, each scan control line is electrically connected to at least one row of pixel circuits, the scan control line includes a first scan signal line and a first reset control line, the array substrate also includes a GOA circuit group for driving the pixel circuits in rows, the GOA circuit group includes: a first GOA circuit and a second GOA circuit, wherein: The pixel circuit comprises a first node, a second node, a third node, a driving subcircuit and a coupling subcircuit, wherein the driving subcircuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide a driving signal to the third node under the control of signals of the first node and the second node; the coupling subcircuit is connected to a first scanning signal line, a first reset control line, a data signal line, a first initial signal line and the third node respectively, and is configured to couple the signal of the first initial signal line to the third node under the control of a first reset control signal provided by the first reset control line, and to couple the signal of the data signal line to the third node under the control of a first scanning signal provided by the first scanning signal line; The first GOA circuit includes a plurality of first GOA units connected in cascade, each of the first GOA units is connected to a first scanning signal line, and is configured to provide a first scanning signal to a coupling sub-circuit in a row of pixel circuits; The second GOA circuit includes a plurality of second GOA units connected in cascade, and the second GOA unit is arranged on one side of the display area to perform unilateral driving on the first reset control line, or each of the second GOA units is connected to two or more of the first reset control lines and is configured to provide the first reset control signal to the coupling sub-circuits in two or more rows of pixel circuits.

2. The array substrate according to claim 1, characterized in that: For each row of pixel circuits, a difference between a start writing time of the first scanning signal and an end writing time of the first reset control signal is at least a scanning time of three pixel rows.

3. The array substrate according to claim 2, characterized in that: For each row of pixel circuits, a difference between a start writing time of the first scanning signal and an end writing time of the first reset control signal is a scanning time of four pixel rows.

4. The array substrate according to claim 1, characterized in that: The scanning control line further includes a second reset control line, and the pixel circuit further includes a second reset subcircuit, the second reset subcircuit is electrically connected to the second reset control line, the second initial signal line and the first node respectively, and is configured to provide a signal of the second initial signal line to the first node under the control of a second reset control signal provided by the second reset control line; The first reset control line connected to the pixel circuits in the i-th row is the second reset control line connected to the pixel circuits in the (i-1)th row, where i is a natural number greater than 1.

5. The array substrate according to claim 1, characterized in that: The scanning control line further includes a second reset control line, and the pixel circuit further includes a second reset subcircuit, the second reset subcircuit is electrically connected to the second reset control line, the second initial signal line and the first node respectively, and is configured to provide a signal of the second initial signal line to the first node under the control of a second reset control signal provided by the second reset control line; The GOA circuit group further includes: a third GOA circuit, the third GOA circuit including a plurality of third GOA units connected in cascade, each of the third GOA units being connected to at least one second reset control line and configured to provide a second reset control signal to a second reset subcircuit in at least one row of pixel circuits; The third GOA unit is disposed on the left and right sides of the display area to perform bilateral driving on the second reset control line.

6. The array substrate according to claim 5, characterized in that: The scanning control line further includes a third reset control line, and the pixel circuit further includes a third reset subcircuit, the third reset subcircuit is electrically connected to the third reset control line, the third initial signal line and the anode of the light-emitting device, respectively, and is configured to reset the anode of the light-emitting device using a signal of the third initial signal line under the control of a third reset control signal provided by the third reset control line; The GOA circuit group further includes: a fourth GOA circuit, the fourth GOA circuit including a plurality of fourth GOA units connected in cascade, each of the fourth GOA units being connected to at least one third reset control line and configured to provide a third reset control signal to a third reset subcircuit in at least one row of pixel circuits; The fourth GOA unit is arranged on one side of the display area to unilaterally drive the third reset control line, or each of the fourth GOA units is connected to two or more of the third reset control lines and is configured to provide the third reset control signal to the third reset sub-circuit in two or more rows of pixel circuits.

7. The array substrate according to claim 6, characterized in that: Each of the second GOA units is connected to three of the first reset control lines and is configured to provide the first reset control signal to the coupling sub-circuits in the three rows of pixel circuits; Each of the third GOA units is connected to three of the second reset control lines and is configured to provide the second reset control signal to the second reset sub-circuits in the three rows of pixel circuits; Each of the fourth GOA units is connected to three of the third reset control lines and is configured to provide the third reset control signal to the third reset sub-circuits in the three rows of pixel circuits.

8. The array substrate according to claim 7, characterized in that: The 2n-1th second GOA unit, the 2n-1th third GOA unit and the 2n-1th fourth GOA unit are arranged in a row on the left side of the 6n-5th row of sub-pixels to the 6nth row of sub-pixels, the 2n-1th second GOA unit is configured to provide a first reset control signal to the coupling sub-circuit in the pixel circuits of the 6n-5th row, the 6n-3rd row and the 6n-1th row, the 2n-1th third GOA unit is configured to provide a second reset control signal to the second reset sub-circuit in the pixel circuits of the 6n-5th row, the 6n-3rd row and the 6n-1th row, and the 2n-1th fourth GOA unit is configured to provide a third reset control signal to the third reset sub-circuit in the pixel circuits of the 6n-5th row, the 6n-3rd row and the 6n-1th row; The 2nth second GOA unit, the 2nth third GOA unit and the 2nth fourth GOA unit are arranged in a row on the right side of the 6n-5th row of sub-pixels to the 6nth row of sub-pixels, the 2nth second GOA unit is configured to provide a first reset control signal to the coupling sub-circuit in the pixel circuits of the 6n-4th row, the 6n-2nd row and the 6nth row, the 2nth third GOA unit is configured to provide a second reset control signal to the second reset sub-circuit in the pixel circuits of the 6n-4th row, the 6n-2nd row and the 6nth row, and the 2nth fourth GOA unit is configured to provide a third reset control signal to the third reset sub-circuit in the pixel circuits of the 6n-4th row, the 6n-2nd row and the 6nth row, wherein n is a natural number greater than or equal to 1.

9. The array substrate according to claim 7, characterized in that: The nth second GOA unit, the nth third GOA unit and the nth fourth GOA unit are arranged on the left and right sides of the 3n-2nd row of sub-pixels to the 3nth row of sub-pixels, and the nth second GOA unit, the nth third GOA unit and the nth fourth GOA unit on the left and right sides are arranged in a row respectively, and the nth second GOA unit is configured to provide a first reset control signal to the coupling subcircuit in the pixel circuit of the 3n-2nd row of sub-pixels, the 3n-1st row of sub-pixels and the 3nth row of sub-pixels, the nth third GOA unit is configured to provide a second reset control signal to the second reset subcircuit in the pixel circuit of the 3n-2nd row of sub-pixels, the 3n-1st row of sub-pixels and the 3nth row of sub-pixels, and the nth fourth GOA unit is configured to provide a third reset control signal to the third reset subcircuit in the pixel circuit of the 3n-2nd row of sub-pixels, the 3n-1st row of sub-pixels and the 3nth row of sub-pixels.

10. The array substrate according to claim 6, characterized in that: Each of the second GOA units is connected to two of the first reset control lines and is configured to provide the first reset control signal to the coupling sub-circuits in the two rows of pixel circuits; Each of the third GOA units is connected to two of the second reset control lines and is configured to provide the second reset control signal to the second reset sub-circuits in the two rows of pixel circuits; Each of the fourth GOA units is connected to two of the third reset control lines and is configured to provide the third reset control signal to the third reset sub-circuits in two rows of pixel circuits.

11. The array substrate according to claim 1, characterized in that: The scanning control line further includes a first light-emitting control line and a second light-emitting control line, and the pixel circuit further includes a first light-emitting control subcircuit and a second light-emitting control subcircuit, the first light-emitting control subcircuit is electrically connected to the first light-emitting control line, the first power line and the second node respectively, and is configured to provide a signal of the first power line to the second node under the control of a first light-emitting control signal provided by the first light-emitting control line; the second light-emitting control subcircuit is electrically connected to the second light-emitting control line, the third node and the anode of the light-emitting device respectively, and is configured to conduct the third node and the anode of the light-emitting device under the control of a second light-emitting control signal provided by the second light-emitting control line; The GOA circuit group further includes: a fifth GOA circuit and a sixth GOA circuit, wherein the fifth GOA circuit includes a plurality of fifth GOA units connected in cascade, each of the fifth GOA units is connected to at least one first light emission control line, and is configured to provide a first light emission control signal to a first light emission control subcircuit in at least one row of pixel circuits; The sixth GOA circuit comprises a plurality of sixth GOA units connected in cascade, each of the sixth GOA units being connected to at least one second light emission control line and configured to provide a second light emission control signal to a second light emission control subcircuit in at least one row of pixel circuits; The fifth GOA unit is arranged at one side of the display area to unilaterally drive the first light-emitting control line, or each of the fifth GOA units is connected to two or more of the first light-emitting control lines and is configured to provide a first light-emitting control signal to the first light-emitting control sub-circuit in two or more rows of pixel circuits; The sixth GOA unit is arranged on one side of the display area to unilaterally drive the second light-emitting control line, or each of the sixth GOA units is connected to two or more of the second light-emitting control lines and is configured to provide a second light-emitting control signal to the second light-emitting control sub-circuit in two or more rows of pixel circuits.

12. The array substrate according to claim 11, characterized in that: The 2n-1th fifth GOA unit and the 2n-1th sixth GOA unit are arranged in a row on the left side of the 6n-5th row of sub-pixels to the 6nth row of sub-pixels, the 2n-1th fifth GOA unit is configured to provide a first light-emitting control signal to a first light-emitting control sub-circuit in a pixel circuit of the 6n-5th row of sub-pixels, the 6n-3th row of sub-pixels and the 6n-1th row of sub-pixels, and the 2n-1th sixth GOA unit is configured to provide a second light-emitting control signal to a second light-emitting control sub-circuit in a pixel circuit of the 6n-5th row of sub-pixels, the 6n-3th row of sub-pixels and the 6n-1th row of sub-pixels; The 2nth fifth GOA unit and the 2nth sixth GOA unit are arranged in a row on the left side of the 6n-5th row of sub-pixels to the 6nth row of sub-pixels, the 2nth fifth GOA unit is configured to provide a first light-emitting control signal to the first light-emitting control sub-circuit in the pixel circuit of the 6n-4th row of sub-pixels, the 6n-2th row of sub-pixels and the 6nth row of sub-pixels, and the 2nth sixth GOA unit is configured to provide a second light-emitting control signal to the second light-emitting control sub-circuit in the pixel circuit of the 6n-4th row of sub-pixels, the 6n-2th row of sub-pixels and the 6nth row of sub-pixels, wherein n is a natural number greater than or equal to 1.

13. The array substrate according to claim 11, characterized in that: The nth fifth GOA unit and the nth sixth GOA unit are arranged on the left and right sides of the 3n-2th row of sub-pixels, the 3n-1th row of sub-pixels and the 3nth row of sub-pixels, and the nth fifth GOA unit and the nth sixth GOA unit on the left and right sides are arranged in a row respectively, and the nth fifth GOA unit is configured to provide a first light-emitting control signal to the first light-emitting control sub-circuit in the pixel circuit of the 3n-2th row of sub-pixels, the 3n-1th row of sub-pixels and the 3nth row of sub-pixels, and the nth sixth GOA unit is configured to provide a second light-emitting control signal to the second light-emitting control sub-circuit in the pixel circuit of the 3n-2th row of sub-pixels, the 3n-1th row of sub-pixels and the 3nth row of sub-pixels, wherein n is a natural number greater than or equal to 1.

14. A display panel, characterized in that: It comprises the array substrate as claimed in any one of claims 1 to 13.

15. A display device, characterized in that: include: The display panel as claimed in claim 13.

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