A display panel and display device

Abstract

The application discloses a display panel and a display device, comprising a multi-stage shift register; the shift register comprises an input module, a first potential control module, a second potential control module, a first output module and a second output module; the first output module is used for outputting a second clock signal as a first gate driving signal in response to the potential of a first node, or outputting a second potential signal as the first gate driving signal in response to the potential of a second node; the second output module is used for outputting a frequency control signal as a second gate driving signal in response to the potential of the first node, or outputting a first potential signal as the second gate driving signal in response to the potential of a third node; wherein the frequency control signal controls the frequency of the appearance of a conduction level in the second gate driving signal by controlling the potential of the output end of the second output module.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] With the development of display technology, the application scenarios of display devices are more and more, and the display requirements of users for display devices are more and more diversified. Based on the release of folding mobile phones and folding laptops and other products, the application scenarios of display devices are further expanded. For the user's demand for multiple applications to be displayed simultaneously on a terminal product, part of the interface (such as a game interface) in the display screen needs to be displayed at a high frequency to ensure the smoothness of the picture, and part of the interface can meet the display requirement by using low frequency. This part is expected to use low frequency display to reduce product power consumption. However, the scanning driving circuit in the prior art only supports the full-screen switching frequency of the display panel, and cannot meet the user's demand for displaying multiple scenarios in one screen on a terminal product, cannot realize the partition frequency display of the display device, and cannot adjust the partition position. SUMMARY

[0003] The present application provides a display panel and a display device, so that the display device has the function of partition multi-frequency display, and the partition position is adjustable.

[0004] In a first aspect, an embodiment of the present application provides a display panel, comprising: a gate driving circuit, the gate driving circuit comprising a plurality of stages of shift registers; the shift register comprising: an input module, a first potential control module, a second potential control module, a first output module and a second output module; the output end of the input module is connected to a first node, and is configured to transmit an input signal to the first node in response to a first clock signal; the first potential control module is connected between the first node and a second node, and is configured to transmit a first potential signal or a second potential signal to the second node in response to the potential of the first node; the second potential control module is connected between the second node and a third node, and is configured to transmit the potential of the second node to the third node according to the first potential signal and the first clock signal; the first output module is connected with the first node and the second node respectively, and is configured to output a second clock signal as a first gate driving signal in response to the potential of the first node, or output the second potential signal as the first gate driving signal in response to the potential of the second node; the second output module is connected between the first node and the third node, and is configured to output a frequency control signal as a second gate driving signal in response to the potential of the first node, or output the first potential signal as the second gate driving signal in response to the potential of the third node; wherein the frequency control signal controls the frequency of the on level appearing in the second gate driving signal by controlling the potential of the output end of the second output module.

[0005] In a second aspect, an embodiment of the present application provides a display device comprising the display panel provided by any of the embodiments of the present application.

[0006] The display panel provided by the embodiment of the present application comprises a gate drive circuit, the gate drive circuit comprises a plurality of shift registers, each shift register comprises an input module, a first potential control module, a second potential control module, a first output module and a second output module. The on-off state of the transistor in the second output module can be controlled through the potential of the first node and the potential of the third node, so that the output end of the second output module outputs a second gate drive signal, the high-low level state of the second gate drive signal can be controlled by controlling the high-low level state of the frequency control signal, and the working mode of the shift register is controlled. By controlling the potential jump process of the frequency control signal, the working mode combination of each shift register can be controlled to be different, so that the frequency of the on level in the second gate drive signals output by at least two shift registers is different, and the partition frequency display of the display panel is realized. At the same time, the shift register can simultaneously generate two kinds of gate drive signals, compared with the conventional shift register which can only generate a single gate drive signal, the number of shift registers used in the display panel can be reduced. The reduction of the number of shift registers helps to reduce the frame size of the display panel, improve the screen ratio of the display panel, bring better visual experience to the user, and thus improve the user experience.

[0007] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0008] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0009] Figure 1 is a schematic diagram of a display frame under different refresh frequencies in the prior art;

[0010] Figure 2 is a structural schematic diagram of a display panel provided by the embodiment of the present application;

[0011] Figure 3 is a structural schematic diagram of a gate drive circuit provided by the embodiment of the present application;

[0012] Figure 4 is a driving timing diagram of a shift register provided by the embodiment of the present application;

[0013] Figure 5is a driving timing diagram of a shift register provided by an embodiment of the present application;

[0014] Figure 6 is a three-part screen schematic diagram of a display panel provided by an embodiment of the present application;

[0015] Figure 7 is a structure schematic diagram of a display panel provided by an embodiment of the present application;

[0016] Figure 8 is a schematic diagram of frequency control signal jump in a first display frame and a second display frame provided by an embodiment of the present application;

[0017] Figure 9 is a structure schematic diagram of a shift register provided by an embodiment of the present application;

[0018] Figure 10 is a structure schematic diagram of a shift register provided by an embodiment of the present application;

[0019] Figure 11 is a structure schematic diagram of a shift register provided by an embodiment of the present application;

[0020] Figure 12 is a structure schematic diagram of a shift register provided by an embodiment of the present application;

[0021] Figure 13 is a structure schematic diagram of a shift register provided by an embodiment of the present application;

[0022] Figure 14 is a structure schematic diagram of a shift register provided by an embodiment of the present application;

[0023] Figure 15 is a structure schematic diagram of a shift register provided by an embodiment of the present application;

[0024] Figure 16 is a structure schematic diagram of a shift register provided by an embodiment of the present application;

[0025] Figure 17 is a structure schematic diagram of a shift register provided by an embodiment of the present application;

[0026] Figure 18 is a structure schematic diagram of a shift register provided by an embodiment of the present application;

[0027] Figure 19 is a structure schematic diagram of a shift register provided by an embodiment of the present application;

[0028] Figure 20 is a structure schematic diagram of a shift register provided by an embodiment of the present application;

[0029] Figure 21 1 is a structural diagram of another shift register provided by an embodiment of the present invention;

[0030] Figure 22 1 is a structural diagram of another shift register provided by an embodiment of the present invention;

[0031] Figure 23 1 is a structural diagram of another shift register provided by an embodiment of the present invention;

[0032] Figure 24 1 is a structural diagram of another shift register provided by an embodiment of the present invention;

[0033] Figures 25 to 28 Schematic diagrams of the working process of the shift register provided by the embodiment of the present invention at each stage;

[0034] Figure 29 This is a simulation waveform diagram of each key node of a shift register provided by an embodiment of the present invention working in a high-frequency working mode;

[0035] Figure 30 This is a simulation waveform diagram of each key node of a shift register provided by an embodiment of the present invention working in a low-frequency working mode;

[0036] Figure 31 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0037] Figure 32 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0038] Figure 33 This is a driving timing diagram of a pixel circuit provided by an embodiment of the present invention;

[0039] Figure 34 This is a structural diagram of another display panel provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0040] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0041] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily have to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion.

[0042] The display panel generally includes a gate driving circuit and pixel circuits arranged in an array in a display area of the display panel. The gate driving circuit includes a plurality of shift registers arranged in cascade, and each pixel circuit cooperates with a light emitting device to form a sub-pixel. Each shift register is connected to at least one gate driving signal line and provides a gate driving signal to the corresponding row of sub-pixels through the gate driving signal line. Each column of sub-pixels is connected to one data line.

[0043] In the process of displaying a picture, data is written to each pixel circuit by line-by-line scanning, i.e., the shift register provides a gate driving signal to the pixel circuit through the gate driving signal line. During the duration of the on-potential of the gate driving signal, the data voltage on the data line is transmitted to the corresponding pixel circuit to achieve data writing. Each pixel circuit outputs a driving current according to the data voltage to drive the light emitting device to emit light for display. When the gate driving signal line provides an off-potential, the data voltage on the data line cannot be transmitted to the corresponding pixel circuit, and data writing is not performed.

[0044] In the prior art, for a display panel capable of switching display frequency, the display frame of a sub-pixel can be divided into a refresh frame and a hold frame. In the refresh frame, the shift register provides an on-potential to the pixel circuit, and the data voltage is written to the pixel circuit; in the hold frame, the shift register provides an off-potential to the pixel circuit, and the pixel circuit no longer performs data writing.

[0045] The refresh frequency can be understood as the number of refresh frames contained in a unit of time. For example, in high-frequency display, only refresh frames can be included. Specifically, referring to Figure 1A refresh frame is represented by a square filled with shadow, and a keep frame is represented by a square filled with blank. Under the refresh frequency f, the display frame of the display panel only includes refresh frames. Exemplarily, when f=60Hz, the display panel refreshes 60 display frames in 1 second. The low-frequency refresh implementation is as follows: when the refresh frequency is reduced, a keep frame is inserted between adjacent refresh frames, the total number of display frames contained in a unit time does not change, and the display duration of each display frame does not change. When the refresh frequency is f / 2, 1 keep frame is inserted between every two adjacent refresh frames. When the refresh frequency is f / 3, 2 keep frames are inserted between every two adjacent refresh frames. By analogy, when the refresh frequency is f / (N+1), N keep frames are inserted between every two adjacent refresh frames.

[0046] In the driving process of the existing display device, whether the conductive potential of the gate drive signal is output by the shift register of each stage is usually controlled by adjusting the input signal provided to the first-stage shift register in the scan driving circuit, so as to realize the frequency switching of the whole screen. However, in the prior art, only one refresh frequency can exist in the full screen of the display panel in one frame display, so that only the frequency switching of the whole screen can be realized, and the multi-part different frequency display of the display device in one screen cannot be supported.

[0047] To solve the above technical problems, an embodiment of the present application provides a display panel. Figure 2 is a structural schematic diagram of a display panel provided by an embodiment of the present application. Referring to Figure 2 The display panel comprises: pixel circuits PX arranged in an array, at least one gate drive circuit 210, a plurality of gate drive signal lines LS, and a plurality of clock signal lines, the gate drive circuit 210 is electrically connected with the pixel circuits PX of the corresponding row through the plurality of gate drive signal lines LS; and the plurality of clock signal lines are electrically connected with the at least one gate drive circuit 210.

[0048] Exemplarily, referring to Figure 2 The display panel comprises a display area AA and a non-display area NAA. The pixel circuits PX arranged in an array are arranged in the display area AA, and the gate drive circuit 210 is arranged in the non-display area NAA.

[0049] The display panel further comprises a driving chip, the driving chip is connected with the gate drive circuit through the clock signal line to output the clock pulse signal to the gate drive circuit. The driving chip can input the clock pulse signal to at least two clock signal lines, and the clock signal line can transmit the clock pulse signal to the gate drive circuit 210.

[0050] The pixel circuit PX can have any structure of a conventional pixel driving circuit. The gate driving circuit 210 can include a plurality of cascaded shift registers, each of which can be connected to functional modules in one or more rows of the pixel circuits PX through a corresponding gate driving signal line LS, such as functional modules for initializing the gate of a driving transistor in the pixel circuit PX. For example, one row of the pixel circuits PX can be connected to two cascaded shift registers, one of which can be connected to functional modules in the pixel circuits PX in odd columns through a corresponding gate driving signal line LS, and the other of which can be connected to functional modules in the pixel circuits PX in even columns through a corresponding gate driving signal line LS.

[0051] The gate driving circuit 210 can be a scanning circuit, a light-emitting control driving circuit, or the like. The gate driving circuit 210 is configured to output a gate driving signal according to at least an input signal and a clock signal, and the gate driving signal is transmitted to the pixel units in the display area AA of the display panel through the gate driving signal line LS, and is configured to drive the pixel units to display. The pixel units include the pixel circuit PX and the light-emitting element. The gate driving signal can include a gate driving signal, a light-emitting control signal, or the like. When the display panel includes a plurality of rows of the pixel circuits PX, the plurality of shift registers in each gate driving circuit are cascaded. The plurality of cascaded shift registers are configured to provide the gate driving signal for at least one row of the pixel circuits PX. The input signal of the first shift register can include the input signal provided by the driving chip to the start signal line STV, and the input signal of the other shift registers can be the gate driving signal output by the previous shift register.

[0052] For example, Figure 2 For example, the plurality of clock signal lines can include a first clock signal line CK1 and a second clock signal line CK2, which are not limited herein. The first clock signal line CK1 can be configured to provide the first clock signal to the odd shift registers and the second clock signal to the even shift registers. The second clock signal line CK2 can be configured to provide the second clock signal to the odd shift registers and the first clock signal to the even shift registers.

[0053] Figure 3 is a structural schematic diagram of a gate driving circuit provided by an embodiment of the present application. As shown in Figure 3 The gate driving circuit includes a plurality of shift registers 10, such as a plurality of cascaded shift registers 10. Each of the shift registers 10 can have the same or similar structure. Figure 3The first two stages of the shift register 10 are exemplarily shown. The shift register 10 (each of the at least one shift register 10) can comprise an input module 11, a first potential control module 12, a second potential control module 13, a first output module 14 and a second output module 15.

[0054] The output of the input module 11 is connected to a first node N1, for transmitting an input signal SIN to the first node N1 in response to a first clock signal SCK1. The first potential control module 12 is connected between the first node N1 and a second node N2, for transmitting a first potential signal VGL or a second potential signal VGH to the second node N2 in response to the potential of the first node N1. The second potential control module 13 is connected between the second node N2 and a third node N3, for transmitting the potential of the second node N2 to the third node N3 according to the first potential signal VGL and the first clock signal SCK1. The first output module 14 is connected to the first node N1 and the second node N2 respectively, for outputting a second clock signal SCK2 as a first gate driving signal S1 in response to the potential of the first node N1, or outputting the second potential signal VGH as the first gate driving signal S1 in response to the potential of the second node N2; the second output module 15 is connected between the first node N1 and the third node N3, for outputting a frequency control signal VFE as a second gate driving signal S2 in response to the potential of the first node N1, or outputting the first potential signal VGL as the second gate driving signal S2 in response to the potential of the third node N3; wherein the frequency control signal VFE controls the frequency of the on level appearing in the second gate driving signal S2 by controlling the potential of the output of the second output module 15.

[0055] Optionally, when the display panel comprises a plurality of rows of pixel units, the plurality of shift registers 10 are cascaded to provide the gate driving signals for at least one row of pixel units respectively. The input signal SIN of the first stage of the shift register can be an input signal provided by a driving chip to the input end of the input module 11 of the first stage of the shift register, and the input signal SIN of the other stages of the shift register is the first gate driving signal S1 output by the previous stage of the shift register. That is, the output end out1 of the first output module 14 of the previous stage of the shift register is connected to the input end of the input module 11 of the next stage of the shift register, to provide the input signal SIN for the next stage of the shift register.

[0056] Exemplarily, the first potential signal VGL is a cutoff level of a functional module in the pixel circuit which accesses the gate drive signal, and the second potential signal VGH is a turn-on level of the functional module in the pixel circuit which accesses the gate drive signal, for example, a functional module which controls a data voltage writing process of a gate of a driving transistor in the pixel circuit. The first potential signal VGL and the second potential signal VGH can both be direct current voltage signals, for example, the first potential signal VGL is a low level and the second potential signal VGH is a high level. The first clock signal SCK1 and the second clock signal SCK2 can include low levels and high levels.

[0057] Exemplarily, the first control end of the first output module 14 is connected to the first node N1, the second control end of the first output module 14 is connected to the second node N2, the first input end of the first output module 14 accesses the second potential signal VGH, the second input end of the first output module 14 accesses the second clock signal SCK2, and the output end of the first output module 14 outputs the first gate drive signal S1. Then, the first output module 14 can control whether the second input end and the output end are connected according to the potential of the first control end (the first node N1), so as to control whether the second clock signal SCK2 is output as the first gate drive signal S1; and control whether the first input end and the output end are connected according to the potential of the second control end (i.e., the second node N2), so as to control whether the second potential signal VGH is output as the first gate drive signal S1.

[0058] The third node N3 is connected to the third node N3, the second control end of the second output module 15 is connected to the first node N1, the first input end of the second output module 15 accesses the first potential signal VGL, the second input end of the second output module 15 accesses the frequency control signal VFE, and the output end of the second output module 15 outputs the second gate drive signal S2. Then, the second output module 15 can control whether the first input end and the output end are connected according to the potential of the first control end (i.e., the third node N3), so as to control whether the first potential signal VGL is output as the second gate drive signal S2; and control whether the second input end and the output end are connected according to the potential of the second control end (i.e., the first node N1), so as to control whether the frequency control signal VFE is output as the second gate drive signal S2.

[0059] When the second output module 15 controls the communication between the second input end and the output end according to the potential of the second control end, if the frequency control signal VFE is a conductive level signal (such as a high level signal), at this time, the second gate drive signal S2 is also a conductive level signal, which is equivalent to that the second gate drive signal S2 includes a conductive level in the display frame; if the frequency control signal VFE is a non-conductive level signal (such as a low level signal), the second gate drive signal S2 is a non-conductive level signal, which is equivalent to that the gate drive signal does not include a conductive level in the display frame. Therefore, the frequency control signal VFE can control the working mode of the shift register 10 by controlling the state of the second gate drive signal S2 output by the second output module 15. The frequency of the gate drive signal can be considered as the pulse frequency of the conductive level in the gate drive signal. The conductive level is a level for turning on the functional module in the pixel circuit, and the non-conductive level is a level for turning off the functional module in the pixel circuit. The conductive level can be a high level, and the non-conductive level can be a low level; or the conductive level can be a low level, and the non-conductive level can be a high level.

[0060] For ease of explanation, the working mode in which the shift register 10 can realize the shift output of the conductive level in the input signal SIN is called a high-frequency working mode, and the working mode in which the shift register 10 cannot realize the shift output of the conductive level in the input signal is called a low-frequency working mode. Then, the frequency control signal VFE can control the working mode of the shift register 10 by controlling the state of the second gate drive signal S2 output by the second output module 15. When a certain stage of the shift register 10 always works in the high-frequency working mode, the shift output of the conductive level in the input signal SIN can be realized, so that the frequency of the second gate drive signal S2 is the same as the frequency of the input signal SIN; when a certain stage of the shift register 10 is in the low-frequency working mode at least in part of the time period, the frequency of the second gate drive signal S2 output by the shift register 10 is lower than the frequency of the input signal SIN connected thereto.

[0061] Figure 4 is a driving timing diagram of a shift register provided by an embodiment of the present application, which can be used to drive Figure 3 the shift register shown in Figure 3 and Figure 4The driving timing of the shift register includes five stages, namely, a first stage P1, a second stage P2, a third stage P3, and a fourth stage P4. Taking a low-level signal input by the first potential signal VGL and a high-level signal as the second potential signal VGH as an example. In a high-frequency working mode, the frequency control signal VFE is a conductive-level signal, and the frequency control signal VFE can control the second gate drive signal S2 output by the second output module 15 to include a high-level state, which is equivalent to including a high-level pulse signal. The effective potential of the pulse signal is high level, and the non-effective potential of the pulse signal is low level. The specific process is as follows:

[0062] In the first stage P1, the input signal SIN and the first clock signal SCK1 are low level, and the second clock signal SCK2 is high level. The input module 11 is turned on in response to the low-level first clock signal, and transmits the input signal SIN to the first node N1. The first potential control module 12 responds to the low level of the first node N1, and transmits the second potential signal VGH (i.e. high level) to the second node N2, so that the potential of the second node N2 is high level. The first output module 14 responds to the potential of the first node N1, and outputs the high level of the second clock signal SCK2 as the first gate drive signal S1. The second output module 15 responds to the potential of the first node N1, and outputs the conductive-level signal (such as high-level signal) of the frequency control signal VFE as the second gate drive signal S2. That is, in the first stage P1, the first gate drive signal S1 output by the first output module 14 is consistent with the second gate drive signal S2 output by the second output module 15, both of which are high-level signals. That is, the second gate drive signal S2 output by the second gate drive signal output end of the shift register at this time is high level. Thus, the shift output of the input signal SIN can be realized, that is, in the current frame, the pixel unit connected corresponding to the shift register normally displays according to the second gate drive signal, so that the display refresh rate of the display panel is the same as the frequency of the input signal SIN.

[0063] In the second phase P2, the input signal SIN and the first clock signal SCK1 jump to high level, and the second clock signal SCK2 jumps to low level. The first node N1 keeps low level, the first potential control module 12 responds to the low level of the first node N1, and transmits the second potential signal VGH (i.e. high level) to the second node N2, so that the potential of the second node N2 is high level. The first output module 14 responds to the potential of the first node N1, and outputs the low level of the second clock signal SCK2 as the first gate driving signal S1. The second output module 15 responds to the potential of the first node N1, and outputs the on level signal (e.g. high level signal) of the frequency control signal VFE as the second gate driving signal S2. That is, in the second phase P2, the first gate driving signal S1 output by the first output module 14 is low level signal, and the second gate driving signal S2 output by the second output module 15 is high level signal.

[0064] In the third phase P3, the input signal SIN keeps high level, the first clock signal SCK1 jumps to low level, and the second clock signal SCK2 jumps to high level. The first node N1 jumps to high level, the first potential control module 12 responds to the high level of the first node N1, and transmits the first potential signal VGL (i.e. low level) to the second node N2, so that the potential of the second node N2 is low level. The second potential control module 13 transmits the low level of the second node N2 to the third node N3 according to the first potential signal VGL and the on of the first clock signal SCK1, so that the potential of the third node N3 is low level. The first output module 14 responds to the potential of the second node N2, and outputs the second potential signal VGH as the first gate driving signal S1. The second output module 15 responds to the potential of the third node N3, and outputs the first potential signal VGL as the second gate driving signal S2. That is, in the third phase P3, the first gate driving signal S1 output by the first output module 14 is high level signal, and the second gate driving signal S2 output by the second output module 15 is low level signal.

[0065] In the fourth stage P4, the input signal SIN keeps high level, the first clock signal SCK1 jumps to high level, and the second clock signal SCK2 jumps to low level. The first node N1 keeps high level, and the first potential control module 12 responds to the high level of the first node N1 and transmits the first potential signal VGL (i.e. low level) to the second node N2, so that the potential of the second node N2 is low level. The second potential control module 13 transmits the low level of the second node N2 to the third node N3 according to the first potential signal VGL and the conduction of the first clock signal SCK1, so that the potential of the third node N3 is low level. The first output module 14 responds to the potential of the second node N2 and outputs the second potential signal VGH as the first gate driving signal. The second output module 15 responds to the potential of the third node N3 and outputs the first potential signal VGL as the second gate driving signal. That is, in the fourth stage P4, the first gate driving signal S1 output by the first output module 14 is a high level signal, and the second gate driving signal S2 output by the second output module 15 is a low level signal.

[0066] Figure 5 is another driving timing diagram of a shift register provided by the embodiment of the present application, which can be used to drive Figure 3 the shift register shown in FIG. 6, with reference to Figure 3 and Figure 5 The driving timing of the shift register includes five stages, which are the first stage P1, the second stage P2, the third stage P3 and the fourth stage P4. Taking the signal input by the first potential signal VGL as a low level signal and the second potential signal VGH as a high level signal as an example. In the low frequency working mode, the frequency control signal VFE is an off level signal, and the frequency control signal VFE controls the second gate driving signal S2 output by the second output module 15 to only include a low level state (output maintained at the non-active potential of the pulse signal). The specific process is as follows:

[0067] In the first stage P1, the input signal SIN and the first clock signal SCK1 are low, and the second clock signal SCK2 is high. The input module 11 is turned on in response to the low first clock signal, and the input signal SIN is transmitted to the first node N1. The first potential control module 12 responds to the low first node N1, and transmits the second potential signal VGH (i.e. high level) to the second node N2, so that the potential of the second node N2 is high. The first output module 14 responds to the potential of the first node N1, and outputs the high level of the second clock signal SCK2 as the first gate drive signal S1. The second output module 15 responds to the potential of the first node N1, and outputs the off level signal (e.g. low level signal) of the frequency control signal VFE as the second gate drive signal S2. That is, in the first stage P1, the first gate drive signal S1 output by the first output module 14 is a high level signal, and the second gate drive signal S2 output by the second output module 15 is a low level signal. That is, at this time, the second gate drive signal S2 output by the second gate drive signal output end of the shift register is low, and the shift output of the input signal SIN cannot be realized, that is, in the current frame, the pixel unit connected corresponding to the shift register cannot be normally displayed according to the second gate drive signal S2, so that the display refresh rate of the display panel is less than the frequency of the input signal SIN, and the control of the display refresh rate of the pixel unit connected corresponding to the current shift register is realized.

[0068] In the second stage P2, the input signal SIN and the first clock signal SCK1 jump to high, and the second clock signal SCK2 jumps to low. The first node N1 remains low, and the first potential control module 12 responds to the low first node N1, and transmits the second potential signal VGH (i.e. high level) to the second node N2, so that the potential of the second node N2 is high. The first output module 14 responds to the potential of the first node N1, and outputs the low level of the second clock signal SCK2 as the first gate drive signal S1. The second output module 15 responds to the potential of the first node N1, and outputs the on level signal (e.g. high level signal) of the frequency control signal VFE as the second gate drive signal S2. That is, in the second stage P2, the first gate drive signal S1 output by the first output module 14 is consistent with the second gate drive signal S2 output by the second output module 15, and both are low level signals.

[0069] In the third phase P3, the input signal SIN keeps high level, the first clock signal SCK1 jumps to low level, and the second clock signal SCK2 jumps to high level. The first node N1 jumps to high level, the first potential control module 12 responds to the high level of the first node N1, and transmits the first potential signal VGL (i.e. low level) to the second node N2, so that the potential of the second node N2 is low level. The second potential control module 13 conducts according to the first potential signal VGL and the first clock signal SCK1, transmits the low level of the second node N2 to the third node N3, so that the potential of the third node N3 is low level. The first output module 14 responds to the potential of the second node N2, and outputs the second potential signal VGH as the first gate driving signal S1. The second output module 15 responds to the potential of the third node N3, and outputs the first potential signal VGL as the second gate driving signal S2. That is, in the third phase P3, the first gate driving signal S1 output by the first output module 14 is high level signal, and the second gate driving signal S2 output by the second output module 15 is low level signal.

[0070] In the fourth phase P4, the input signal SIN keeps high level, the first clock signal SCK1 jumps to high level, and the second clock signal SCK2 jumps to low level. The first node N1 keeps high level, the first potential control module 12 responds to the high level of the first node N1, and transmits the first potential signal VGL (i.e. low level) to the second node N2, so that the potential of the second node N2 is low level. The second potential control module 13 conducts according to the first potential signal VGL and the first clock signal SCK1, transmits the low level of the second node N2 to the third node N3, so that the potential of the third node N3 is low level. The first output module 14 responds to the potential of the second node N2, and outputs the second potential signal VGH as the first gate driving signal. The second output module 15 responds to the potential of the third node N3, and outputs the first potential signal VGL as the second gate driving signal. That is, in the fourth phase P4, the first gate driving signal S1 output by the first output module 14 is high level signal, and the second gate driving signal S2 output by the second output module 15 is low level signal.

[0071] The second gate drive signal S2 output by each shift register 10 is transmitted to the functional module in each row of pixel circuit related to the data voltage writing process through each row of gate drive signal line. When a certain stage of shift register 10 works in the high frequency working mode, since the second gate drive signal S2 contains the conduction level, the data refresh of the corresponding row of pixel circuit can be controlled, so that the current frame of the row of pixel circuit is the refresh frame. When a certain stage of shift register 10 works in the low frequency working mode, since the second gate drive signal S2 does not contain the conduction level, the data refresh of the corresponding row of pixel circuit cannot be controlled, so that the current frame of the row of pixel circuit is the holding frame. Therefore, the frequency of the gate drive signal determines the data refresh frequency of the pixel circuit. Based on this, by controlling the potential jump of the frequency control signal VFE, the working mode of each shift register 10 in each frame of display can be controlled, so that the display device realizes the display of different frequencies in the column direction.

[0072] With Figure 6For example, assuming that the display panel is divided into first display partition A1, second display partition A2 and third display partition A3 from top to bottom, and the refresh frequencies of the three display partitions are first refresh frequency f1, second refresh frequency f2 and first refresh frequency f1 in sequence, f1>f2. Then, from the first display partition A1 to the second display partition A2 is equivalent to realizing frequency division display of display frequency from high to low, and from the second display partition A2 to the third display partition A3 is equivalent to realizing frequency division display of display frequency from low to high. The size of each display partition is determined by the number of shift registers 10 providing the second gate drive signal S2 of the corresponding frequency. For example, the frequency of the second gate drive signal S2 output by the shift register 10 corresponding to the first display partition A1 and the third display partition A3 is the first refresh frequency f1, for example, the 1st, 2nd, 5th and 6th shift registers 10 are set to work in high-frequency working mode in each display frame. The frequency of the second gate drive signal S2 output by the shift register 10 corresponding to the second display partition A2 is the second refresh frequency f2, for example, the 3rd and 4th shift registers 10 are set to work in high-frequency working mode in part of the display frame, and in low-frequency working mode in part of the display frame. That is, by controlling the frequency control signal VFE to keep the second gate drive signal S2 output by the second output module 15 including an off level in part of the display frame, the shift register 10 can work in low-frequency working mode in part of the display frame, by controlling the frequency control signal VFE to jump in potential in part of the display frame, the second gate drive signal S2 output by the second output module 15 in part of the display frame includes an on level, so that the shift register 10 works in high-frequency working mode in part of the display frame, so that the frequencies of the second gate drive signals S2 output by at least two shift registers 10 are different, so as to realize the frequency division display of the display panel. In addition, by adjusting the potential jump time of the frequency control signal VFE in a frame of display, the boundary position of the working mode switching of the shift register 10 can be adjusted, so as to realize the adjustment of the display partition position of the display panel. One level shift register 10 is connected to at least one row of pixel circuits, and the number of shift registers 10 working in high-frequency working mode in a frame determines the number of rows of pixel circuits refreshed in the frame.

[0073] The gate drive circuit provided by the embodiment of the present application comprises a plurality of shift registers, each of which comprises an input module, a first potential control module, a second potential control module, a first output module and a second output module. The on-off state of the transistor in the second output module can be controlled by the potential of the first node and the potential of the third node, so that the output end of the second output module outputs a second gate drive signal. The high-low level state of the second gate drive signal can be controlled by controlling the high-low level state of the frequency control signal, so as to control the working mode of the shift register. By controlling the potential jump process of the frequency control signal, the working mode combination of each shift register can be controlled to be different, so that the frequency of the on level in the second gate drive signals output by at least two shift registers is different, thereby realizing the partition frequency display of the display panel. At the same time, the shift register can simultaneously generate two kinds of gate drive signals. Compared with the traditional shift register which can only generate a single gate drive signal, the number of shift registers used in the display panel can be reduced. The reduction of the number of shift registers helps to reduce the frame size of the display panel, improve the screen ratio of the display panel, bring better visual experience to the user, and thus improve the user experience.

[0074] Optionally, with reference to Figure 2 , the display panel further comprises at least one frequency control signal line ENL for providing the frequency control signal VFE to the shift register 10.

[0075] Figure 7 is another structure diagram of a display panel provided by the embodiment of the present application. With reference to Figure 7 Optionally, the display panel comprises k frequency control signal lines, the gate drive circuit comprises a plurality of cascaded shift register groups 20, the shift register group 20 comprises k cascaded shift register units 21, k is an integer greater than or equal to 2, the shift register unit 21 comprises m shift registers 10, m is an integer greater than or equal to 1, different shift register units 21 in the same shift register group 20 are electrically connected with different frequency control signal lines, and different shift register groups 20 are connected with the same k frequency control signal lines.

[0076] The display partition comprises a plurality of pixel circuit groups 30; the pixel circuit group 30 comprises k sub-pixel circuit groups 31, the sub-pixel circuit group 31 comprises a plurality of rows of pixel circuits PX; the sub-pixel circuit group 31 is electrically connected with the shift register unit 21 in a one-to-one manner; the output end of the first shift register 10 is electrically connected with r rows of pixel circuits PX, and r is an integer greater than or equal to 1. Optionally, m is greater than or equal to 8, and k is greater than or equal to 4. Optionally, the number of rows of pixel circuits PX in each pixel circuit group 30 is the same.

[0077] wherein, Figure 7The case of k = 4 is shown schematically. Exemplarily, m can be 16 and r can be 1. Each shift register group 20 can control the display of k*m*r rows of pixel circuits. Figure 7 The shift register group 20 of the gate driving circuit in the display panel shown can be considered to include four cascaded shift register units 21, and include four frequency control signal lines, namely ENL1, EN2, ENL3 and ENL4. One frequency control signal line is connected with m shift registers 10 in one shift register unit 21. Each frequency control signal line can drive m*r rows of pixel circuits driven by one shift register unit 21, and the number of rows driven by the four frequency control signal lines is one period.

[0078] Optionally, continuing to refer to Figure 2 , the display area AA of the display panel includes at least two display sub-areas, and the at least two display sub-areas include a first display sub-area A1 and a second display sub-area A2; the refresh frequency of the first display sub-area A1 is a first refresh frequency, and the refresh frequency of the second display sub-area A2 is a second refresh frequency, and the first refresh frequency is less than the second refresh frequency.

[0079] Figure 8 is a schematic diagram of frequency control signal jump in a first display frame and a second display frame provided by an embodiment of the present application, referring to Figure 8 , in the first display frame, the pulse jump of the frequency control signal VFE of the k frequency control signal lines is delayed in turn at the time of the turn-on level NVGH; in the second display frame, the frequency control signal on the k frequency control signal lines is the turn-on level NVGH. Wherein, the first display frame is the holding frame of at least part of the row pixel circuits in the first display sub-area, and is the refresh frame of the second display sub-area; the second display frame is the refresh frame of the first display sub-area and the second display sub-area; in the second display frame, the first display sub-area refreshes before the second display sub-area;

[0080] Specifically, in combination with Figure 7 and Figure 8 , in the first display frame F1, it is the refresh frame of the at least one display sub-area, and is the holding frame of the at least one display sub-area, so as to Figure 8In the case shown, the pixel circuit connected to the shift register corresponding to the off level NVGL works in the holding frame, and the pixel circuit connected to the shift register corresponding to the on level NVGH works in the refresh frame. In this case, the time of pulse jump of the signal on the k frequency control signal lines is sequentially delayed to facilitate the divisional multi-frequency control. The second display frame F2 is the refresh frame of each display division, and the signal on the k frequency control signal lines is set to the on level in the second display frame F2, so that each display division can be refreshed in the second display frame, and the signal on the frequency control signal line does not need to be jumped. The first frequency control signal line ENL1 transmits the first frequency control signal VFE1 to the corresponding shift register. The second frequency control signal line ENL2 transmits the second frequency control signal VFE2 to the corresponding shift register. The third frequency control signal line ENL3 transmits the third frequency control signal VFE3 to the corresponding shift register. The fourth frequency control signal line ENL4 transmits the fourth frequency control signal VFE4 to the corresponding shift register.

[0081] Optionally, k-1 shift register units 21 are connected between the two adjacent shift register units 21 connected to the same frequency control signal line.

[0082] Specifically, the sub-pixel rows connected to the k partition enable signal lines are periodically arranged. For example, the first partition enable signal line ENL1 is connected to 1-16 rows, 65-80 rows, … of sub-pixel rows. The second partition enable signal line ENL2 is connected to 17-32 rows, 81-96 rows, … of sub-pixel rows. The third partition enable signal line ENL3 is connected to 33-48 rows, 97-112 rows, … of sub-pixel rows. The fourth partition enable signal line ENL4 is connected to 49-64 rows, 98-128 rows, … of sub-pixel rows.

[0083] Based on the above embodiment, with reference to Figure 4 and Figure 5 Optionally, the waveform of the second clock signal SCK2 is the same as that of the first clock signal SCK1. That is, the duty cycles of the first clock signal SCK1 and the second clock signal SCK2 are the same, that is, the low level time of the first clock signal SCK1 and the second clock signal SCK2 is the same, and the high level time of the first clock signal SCK1 and the second clock signal SCK2 is the same.

[0084] Based on the above embodiment, with reference to Figure 4 and Figure 5Optionally, the period of the second clock signal SCK2 is the same as the period of the first clock signal SCK1. For example, the period of the first clock signal SCK1 and the second clock signal SCK2 is two row times, which is related to the refresh frequency and resolution of the display panel, i.e. the row time can be calculated according to the refresh frequency and resolution.

[0085] On the basis of the above-mentioned embodiments, with reference to Figure 4 and Figure 5 Optionally, the waveform of the second clock signal SCK2 is delayed relative to the waveform of the first clock signal SCK1. In this way, when the first clock signal SCK1 is at an active level (e.g. low level), the second clock signal SCK2 is at an inactive level (e.g. high level), and when the second clock signal SCK2 is at an active level, the first clock signal SCK1 is at an inactive level. This ensures that the first clock signal SCK1 and the second clock signal SCK2 are not at an active level at the same time, so that each module can be accurately controlled and control disorder can be avoided.

[0086] On the basis of the above-mentioned embodiments, with reference to Figure 4 and Figure 5 Optionally, the waveform of the second clock signal SCK2 is delayed by half a period relative to the waveform of the first clock signal SCK1. In this way, when the first clock signal SCK1 just controls the input module 11 to turn on, the second clock signal SCK2 is at an inactive level and cannot couple the potential of the first node N1 to a more active level, so that the input signal SIN at an active level cannot control the first output module 14 to turn on completely, and the first output module 14 can be shifted relative to the input signal SIN, so that the shift register can output the input signal SIN after being shifted.

[0087] On the basis of the above-mentioned embodiments, with reference to Figure 4 and Figure 5 Optionally, the duration of the low level in the first clock signal SCK1 is less than or equal to half a period, and the duration of the high level in the first clock signal SCK1 is greater than half a period. Optionally, the duration of the low level in the second clock signal SCK2 is less than or equal to half a period, and the duration of the high level in the second clock signal SCK2 is greater than half a period. In this way, the on time of the first clock signal SCK1 can be ensured not to be too long, and the on time of the second clock signal SCK2 can be ensured not to be too long, so that there can be a blank area between the low level of the first clock signal SCK1 and the second clock signal SCK2, which can avoid the modules responding to the low levels of the first clock signal SCK1 and the second clock signal SCK2 at the same time, and can help to ensure the accuracy of the control.

[0088] Figure 9 is a structural schematic diagram of a shift register provided by an embodiment of the present application. As shown in Figure 9As shown, the first potential control module 12 includes a first inverter, which includes a first transistor T1 and a second transistor T2.

[0089] The gate of the first transistor T1 is connected with the first node N1, the first pole of the first transistor T1 is connected with the first potential signal VGL, and the second pole of the first transistor T1 is connected with the second node N2. The gate of the second transistor T2 is connected with the first node N1, the first pole of the second transistor T2 is connected with the second potential signal VGH, and the second pole of the second transistor T2 is connected with the second node N2.

[0090] Specifically, the first transistor T1 is turned on or turned off according to the potential of the first node N1 connected with the gate of the first transistor T1, and transmits the first potential signal VGL to the second node N2 when turned on. The second transistor T2 is turned on or turned off according to the potential of the first node N1 connected with the gate of the second transistor T2, and transmits the second potential signal VGH to the first node N1 when turned on. Wherein, the channel type of the first transistor T1 is different from the channel type of the second transistor T2. For example, when the first transistor is an N-channel type transistor and the second transistor is a P-channel type transistor, the first transistor T1 is turned on when the potential of the first node N1 is high, and the second transistor T2 is turned on when the potential of the first node N1 is low. The potential of the second node N2 can be controlled through the first transistor T1 and the second transistor T2, thereby controlling the on or off state of the first output module 14 and the second output module 15, and realizing the output control of the first gate drive signal S1 and the second gate drive signal S2. Moreover, the structure of the transistor is simple, and the manufacturing process is simple. When the shift register is applied to a display panel, the transistor in the shift register and the transistor on the display panel can be manufactured in the same process flow, thereby saving the process flow and reducing the cost.

[0091] Figure 10 is another structure diagram of a shift register provided by an embodiment of the present application. As shown in Figure 10 As shown, the second potential control module 13 includes a third transistor T3 and a fourth transistor T4.

[0092] The gate of the third transistor T3 is connected with the first clock signal SCK1, the first pole of the third transistor T3 is connected with the second node N2, and the second pole of the third transistor T3 is connected with the first pole of the fourth transistor T4. The gate of the fourth transistor T4 is connected with the first potential signal VGL, and the second pole of the fourth transistor T4 is connected with the third node N3.

[0093] Specifically, the third transistor T3 is turned on or turned off according to the first clock signal SCK1 connected to the gate of the third transistor T3, and transmits the potential of the second node N2 to the first electrode of the fourth transistor T4 when turned on. The fourth transistor T4 is turned on or turned off according to the first potential signal VGL connected to the gate of the fourth transistor T4, and transmits the potential of the first electrode of the fourth transistor T4 to the third node N3 when turned on. The third transistor T3 and the fourth transistor T4 can be P-type transistors or N-type transistors. For example, when the third transistor T3 and the fourth transistor T4 are both P-type transistors, and the first clock signal SCK1 is a low potential signal, the third transistor T3 is always in a turned-on state when the low potential signal is input to the gate, and the fourth transistor T4 is turned on when the first potential signal VGL is a low potential signal, so as to transmit the potential of the second node N2 to the third node N3. The second potential control module 13 including the third transistor T3 and the fourth transistor T4 can effectively control the potential of the third node N3. Moreover, the structure of the transistors is simple, and the manufacturing process is simple. When the shift register is applied to a display panel, the transistors in the shift register and the transistors on the display panel can be manufactured in the same process flow, so as to save the process flow and reduce the cost.

[0094] Figure 11 is a structural diagram of another shift register provided by an embodiment of the present application. As shown in Figure 11 Optionally, the first output module 14 includes a first output unit 141 and a second output unit 142. The first output unit 141 is connected to the second node N2, and is configured to output the second potential signal VGH as the first gate driving signal S1 according to the potential of the second node N2. The second output unit 142 is connected to the first node N1, and is configured to output the second clock signal SCK2 as the first gate driving signal S1 according to the potential of the first node N1.

[0095] As a preferred embodiment provided by an embodiment of the present application, Figure 12 is a structural diagram of another shift register provided by an embodiment of the present application. As shown in Figure 12 Optionally, the first output unit 141 includes a fifth transistor T5, the gate of the fifth transistor T5 is connected to the second node N2, the first electrode of the fifth transistor T5 is connected to the second potential signal VGH, and the second electrode of the fifth transistor T5 is an output terminal of the first output unit 141.

[0096] The second output unit 142 comprises a sixth transistor T6 and a first capacitor C1. The gate of the sixth transistor T6 is connected with the first node N1 and the first terminal of the first capacitor C1 respectively. The first terminal of the sixth transistor T6 is connected with the second terminal of the first capacitor C1, and the second terminal of the sixth transistor T6 is connected with the second clock signal SCK2 as the output terminal of the second output unit 142.

[0097] The fifth transistor T5 and the sixth transistor T6 can be P-type transistors or N-type transistors. The fifth transistor T5 is turned on or turned off in response to the potential of the second node N2, and transmits the second potential signal VGH to the first gate driving signal output terminal out 1 of the shift register when turned on. The sixth transistor T6 is turned on or turned off in response to the potential of the first node N1, and transmits the second clock signal SCK2 to the first gate driving signal output terminal out 1 of the shift register when turned on. The first capacitor C1 has a storage function to realize charge holding. When the input signal SIN is transmitted to the first node N1, the first capacitor C1 will be charged and discharged to maintain the potential of the first node N1 to be the same as the potential of the previous stage when there is no input signal SIN transmitted to the first node N1.

[0098] Figure 13 is another structure diagram of a shift register provided by an embodiment of the present application. As shown in Figure 13 Optionally, the second output module 15 comprises a second inverter, and the second inverter comprises a third output unit 151 and a fourth output unit 152.

[0099] The third output unit 151 is connected with the first node N1, and is configured to output the frequency control signal VFE as the second gate driving signal S2 according to the potential of the first node N1. The fourth output unit 152 is connected with the third node N3, and is configured to output the first potential signal VGL as the second gate driving signal S2 according to the potential of the third node N3.

[0100] As a preferred embodiment provided by an embodiment of the present application, Figure 14 is another structure diagram of a shift register provided by an embodiment of the present application. As shown in Figure 14 Optionally, the third output unit 151 comprises a seventh transistor T7. The gate of the seventh transistor T7 is connected with the first node N1. The first terminal of the seventh transistor T7 is connected with the frequency control signal VFE. The second terminal of the seventh transistor T7 is connected with the output terminal of the third output unit 151.

[0101] The fourth output unit 152 comprises an eighth transistor T8. The gate of the eighth transistor T8 is connected with the third node N3. The second terminal of the eighth transistor T8 is connected with the first potential signal VGL as the output terminal of the fourth output unit 152.

[0102] The seventh transistor T7 and the eighth transistor T8 can be P-type transistors or N-type transistors. The seventh transistor T7 is turned on or turned off in response to the potential of the first node N1, and when turned on, transmits the frequency control signal VFE to the second gate driving signal output end out2 of the shift register. The eighth transistor T8 is turned on or turned off in response to the potential of the third node N3, and when turned on, transmits the first potential signal VGL to the second gate driving signal output end out2 of the shift register.

[0103] Figure 15 is a structural schematic diagram of still another shift register provided by an embodiment of the present application. As shown in Figure 15 Optionally, the shift register further includes a pull-down module 16. The pull-down module 16 is connected between the first node N1 and the third node N3, and is configured to control the potential of the third node N3 according to at least the potential of the first node N1, the second potential signal VGH and the second clock signal SCK2.

[0104] The pull-down module 16 controls the potential of the third node N3 according to the potential of the first node N1, the second potential signal VGH and the second clock signal SCK2. That is, the pull-down module 16 can control the potential of the third node N3 according to the potential of the first node N1, the first potential signal VGL and the second clock signal SCK2 when the potential of the second clock signal SCK2 jumps, for example, the pull-down module 16 can pull down the potential of the third node N3 to a potential lower than the potential corresponding to the second potential signal VGH. Since the second output module 15 can transmit the first potential signal VGL to the second gate drive signal output end out2 of the shift register in response to the potential (e.g. a low-level signal) of the third node N3, if the potential of the third node N3 is not low enough (i.e. the absolute value of the difference between the potential of the third node N3 and the second potential signal VGH is greater than a set threshold), the first potential signal VGL transmitted by the second output module 15 to the second gate drive signal output end out2 of the shift register will have a level loss. In the embodiment of the present application, when the second output module 15 transmits the first potential signal VGL to the second gate drive signal output end out2 of the shift register in response to the low-level signal of the third node N3, the pull-down module 16 is used to pull down the potential of the third node N3 to a potential lower than the second potential signal VGH, so that the potential of the third node N3 can reach a low enough potential (the low enough potential satisfies that the absolute value of the difference between the potential of the third node N3 and the second potential signal VGH is less than the set threshold), thereby reducing the level loss of the low-level signal output by the second gate drive signal output end out2 of the shift register. When the second output module 15 includes a transistor with the third node N3 connected to the gate, the first electrode connected to the first potential signal VGL, and the second electrode connected to the second gate drive signal output end out2 of the shift register, the set threshold can be equal to the threshold voltage of the transistor.

[0105] Figure 16 is another structure diagram of a shift register provided by an embodiment of the present application. As shown in Figure 16 Optionally, the pull-down module 16 includes a first control unit 161 and a second control unit 162.

[0106] The first control unit 161 is connected between the first node N1 and the fourth node N4, and is configured to control the potential of the fourth node N4 according to the potential of the first node N1, the second potential signal VGH and the second clock signal SCK2. The second control unit 162 is connected between the third node N3 and the fourth node N4, and is configured to control the potential of the third node N3 according to the potential of the fourth node N4.

[0107] Figure 17 is another structure diagram of a shift register provided by an embodiment of the present application. As shown in Figure 17As shown, the pull-down module further includes a third control unit 163 connected between the second node N2 and the fourth node N4, for transmitting the potential of the second node N2 to the fourth node N4 according to the first clock signal SCK1 and the first potential signal VGL.

[0108] As a preferred embodiment provided by the embodiment of the present application, Figure 18 is another structure diagram of the shift register provided by the embodiment of the present application. As shown in Figure 18 As shown, the first control unit 161 includes a ninth transistor T9, a tenth transistor T10 and a second capacitor C2.

[0109] The gate of the ninth transistor T9 is connected to the fourth node N4, the first pole of the ninth transistor T9 is connected to the second clock signal SCK2, and the second pole of the ninth transistor T9 and the first pole of the tenth transistor T10 are connected to the fifth node N5. The gate of the tenth transistor T10 is connected to the first node N1, and the second pole of the tenth transistor T10 is connected to the second potential signal VGH. The first end of the second capacitor C2 is connected to the fourth node N4, and the second end of the second capacitor C2 is connected to the fifth node N5.

[0110] The second control unit 162 includes an eleventh transistor T11; the gate of the eleventh transistor T11 is connected to the first pole of the eleventh transistor T11 and the gate of the ninth transistor T9, and serves as the first end of the second control unit 162, and the second pole of the eleventh transistor T11 is connected to the third node N3.

[0111] Specifically, when the potential of the first node N1, the second potential signal VGH and the second clock signal SCK2 change, the tenth transistor T10 will be turned on or turned off according to the potential of the first node N1. If the tenth transistor T10 is turned on, the second potential signal VGH will affect the potential of the first pole of the tenth transistor T10. At the same time, the ninth transistor T9 controls its conduction or non-conduction according to the potential of the fourth node N4 and the state of the second clock signal SCK2, thereby affecting the potential of the fourth node N4. The second capacitor C2 plays a role in storing charges and stabilizing the potential in this process, for example, when the potential changes, it can maintain a certain potential state through charging and discharging, so that the potential change of the fourth node N4 is more stable and controllable.

[0112] The potential change of the fourth node N4 directly affects the conduction state of the eleventh transistor T11. When the potential of the fourth node N4 is at an ultra-low potential, the diode formed by the eleventh transistor T11 is forward biased, the potential of the fourth node N4 pulls down the potential of the third node N3, compensates the charge to the third node N3, and keeps the third node N3 at an ultra-low potential, thereby ensuring that the second output module 15 can accurately output the second gate drive signal S2 according to the potential of the third node N3, and avoiding that the second gate drive signal S2 is outputted incorrectly due to the abnormal potential of the third node N3.

[0113] Optionally, with reference to Figure 18 , the third control unit 163 comprises a twelfth transistor T12 and a thirteenth transistor T13. The gate of the twelfth transistor T12 is connected to the first clock signal SCK1, the first electrode of the twelfth transistor T12 is connected to the second node N2, and the second electrode of the twelfth transistor T12 is connected to the first electrode of the thirteenth transistor T13. The gate of the thirteenth transistor T13 is connected to the first potential signal VGL, and the second electrode of the thirteenth transistor T13 is connected to the fourth node N4.

[0114] The twelfth transistor T12 and the thirteenth transistor T13 are used to provide an initial starting low potential before the fourth node N4 is pulled down. The thirteenth transistor T13 is a protection transistor, which prevents the twelfth transistor T12 from being affected by the ultra-low potential of the fourth node N4 for a long time and causing reliability problems.

[0115] Figure 19 is another structure diagram of a shift register provided by an embodiment of the present application. As shown in Figure 19 Optionally, the shift register further comprises a third potential control module 17 connected between the first node N1 and the second node N2, and used to control the potential of the first node N1 according to the potential of the second node N2.

[0116] Specifically, the third potential control module 17 is used to conduct when the second node N2 is at a low level, and stably transmit the high level of the second potential signal VGH to the first node N1, so as to ensure that the first node N1 and the second node N2 are not at a low level at the same time, and ensure the stability of the output state of the first output module 14.

[0117] Figure 20 is another structure diagram of a shift register provided by an embodiment of the present application. As shown in Figure 20As shown, optionally, the third potential control module 17 comprises a fourteenth transistor T14; a gate of the fourteenth transistor T14 is connected with the second node N2, a first pole of the fourteenth transistor T14 is connected with the second potential signal VGH, and a second pole of the fourteenth transistor T14 is connected with the first node N1. In this embodiment, the third potential control module 17 is configured by one transistor, so that the third potential control module 17 is simple in structure and easy to implement.

[0118] Figure 21 is a structural schematic diagram of another shift register provided by an embodiment of the present application. As shown in Figure 21 As shown, optionally, the third potential control module 17 further comprises a fifteenth transistor T15; a gate of the fifteenth transistor T15 is connected with the second clock signal SCK2, a first pole of the fifteenth transistor T15 is connected with the second pole of the fourteenth transistor T14, and a second pole of the fifteenth transistor T15 is connected with the first node N1.

[0119] In this embodiment, the third potential control module 17 and the input module 11 are configured by two transmission paths, so that the signal competition caused by the two transmission paths can be avoided. Specifically, when the second node N2 is at low level and the first node N1 is at low level, if the input signal SIN jumps to low level, when the first clock signal SCK1 is at low level, the low level of the input signal SIN is transmitted to the first node N1. The first potential control module 12 responds to the low level of the first node N1 and transmits the high level of the second potential signal VGH to the second node N2, so that the second node N2 jumps to high level. Before the second node N2 jumps to high level, the fourteenth transistor T14 is still kept on. If the fifteenth transistor T15 is not configured, at this time, the fourteenth transistor T14 tries to transmit the high level to the first node N1, while the third transistor M3 transmits the low level to the first node N1, which causes the signal competition and even leads to that the potential of the first node N1 cannot be normally pulled down. After the fifteenth transistor T15 is configured, before the first clock signal SCK1 jumps to low level, the second clock signal SCK2 has jumped to high level, which controls the fifteenth transistor T15 to be turned off and cuts off the transmission path of the third potential control module 17, so that the signal competition can be effectively avoided.

[0120] Figure 22 is a structural schematic diagram of another shift register provided by an embodiment of the present application. As shown in Figure 22 As shown, optionally, the shift register further comprises a potential isolation module 18; a control end of the potential isolation module 18 is connected with the first potential signal VGL, a first end of the potential isolation module 18 is connected with the first node N1, and a second end of the potential isolation module 18 is connected with the first control end of the first output module 14. The potential isolation module 18 is used for being turned on or turned off according to the potential difference between the first potential signal VGL and the first node N1.

[0121] The embodiment is configured in this way, so that the transmission of the extremely low potential of the first control point of the first output module 14 to the first node N1 due to the coupling of the capacitor is blocked, and the impact of the extremely low potential on the transistors connected with the first node N1 is avoided. Specifically, when the first node N1 is at a low potential, since the first potential signal VGL is also at a low potential, the potential difference between the control end and the first end of the potential isolation module 18 is substantially 0, so that the potential isolation module 18 is in a critical off state. Then, when the capacitor in the first output module 14 pulls the first control end of the first output module 14 to an extremely low potential, since the potential isolation module 18 is in a critical off state, the extremely low potential cannot be transmitted to the first node N1, and the transistors in the input module 11 and the first potential control module 12 and the like are not impacted. When the first node N1 is at a high potential, the potential difference between the control end and the first end of the potential isolation module 18 is greater than 0, so that the potential isolation module 18 is turned on, and the high potential of the first node N1 can be effectively transmitted to the first control end of the first output module 14. Therefore, the potential isolation module 18 only blocks the transmission path of the extremely low voltage to the first node N1, and does not affect the normal transmission of the high potential.

[0122] Optionally, the potential isolation module 18 comprises a sixteenth transistor T16; the gate of the sixteenth transistor T16 is configured as the control end of the potential isolation module 18, the first pole of the sixteenth transistor T16 is configured as the first end of the potential isolation module 18, and the second pole of the sixteenth transistor T16 is configured as the second end of the potential isolation module 18. The embodiment is configured that the potential isolation module 18 is composed of one transistor, so that the potential isolation module 18 is simple in structure and easy to implement.

[0123] Figure 23 is another structure diagram of a shift register provided by an embodiment of the application. As shown in Figure 23 Optionally, the input module 11 comprises a seventeenth transistor T17; the gate of the seventeenth transistor T17 is connected with the first clock signal SCK1, the first pole of the seventeenth transistor T17 is connected with the input signal SIN, and the second pole of the seventeenth transistor T17 is connected with the first node N1. The embodiment is configured that the input module 11 is composed of one transistor, so that the input module 11 is simple in structure and easy to implement.

[0124] Figure 24 is another structure diagram of a shift register provided by an embodiment of the application. As shown in Figure 24 Optionally, the shift register comprises an input module 11, a first potential control module 12, a second potential control module 13, a first output module 14 and a second output module 15.

[0125] Optionally, the first potential control module 12 includes a first transistor T1 and a second transistor T2. The second potential control module 13 includes a third transistor T3 and a fourth transistor T4.

[0126] Optionally, the first output module 14 includes a first output unit 141 and a second output unit 142. The first output unit 141 includes a fifth transistor T5, and the second output unit 142 includes a sixth transistor T6 and a first capacitor C1. Optionally, the second output module 15 includes a third output unit 151 and a fourth output unit 152. Optionally, the third output unit 151 includes a seventh transistor T7, and the fourth output unit 152 includes an eighth transistor T8.

[0127] Optionally, the shift register further includes a pull-down module 16. The pull-down module 16 includes a first control unit 161, a second control unit 162, and a third control unit 163. The first control unit 161 includes a ninth transistor T9, a tenth transistor T10, and a second capacitor C2. The second control unit 162 includes an eleventh transistor T11. The third control unit 163 includes a twelfth transistor T12 and a thirteenth transistor T13.

[0128] Optionally, the shift register further includes a third potential control module 17 , and the third potential control module 17 includes a fourteenth transistor T14 and a fifteenth transistor T15 .

[0129] Optionally, the shift register further includes a potential isolation module 18, and the potential isolation module 18 includes a sixteenth transistor T16. Optionally, the input module 11 includes a seventeenth transistor T17.

[0130] The second electrode of the sixteenth transistor T16 , the gate of the sixth transistor T6 , and the first end of the first capacitor C1 are connected to a sixth node N6 .

[0131] Figure 4 and Figure 5 The driving timing of the shift register shown is also applicable to Figure 24 The shift register shown. The second transistor T2 to the seventeenth transistor T17 in the shift register can be P-type transistors, and the first transistor T1 can be an N-type transistor. The first potential signal VGL is a low-level signal and the second potential signal VGH is a high-level signal. Figure 2 and Figure 15 The driving timing of the shift register includes a first stage P1, a second stage P2, a third stage P3 and a fourth stage P4.

[0132] Figures 25 to 28The working process of the shift register provided by the embodiment of the present application in each stage is shown in the figure, the arrow in the figure represents the direction of current flow, the circle represents the transistor being turned on, and the cross represents the transistor being turned off. Referring to Figure 4 and Figure 25 In the first stage P1, the input signal SIN and the first clock signal SCK1 are low, the second clock signal SCK2 is high, and the frequency control signal VFE is a high-level signal. The seventeenth transistor T17 is turned on in response to the low-level first clock signal SCK1, and the input signal SIN is transmitted to the first node N1. The sixth transistor T6 is turned on, that is, the sixth transistor T6 outputs the high level of the second clock signal SCK2 as the first gate drive signal S1 in response to the potential of the first node N1. The second transistor T2 responds to the low level of the first node N1 and transmits the second potential signal VGH (that is, the high level) to the second node N2, so that the potential of the second node N2 is high, and the fifth transistor T5 is turned off. The fourteenth transistor T14 is turned off to prevent the second potential signal VGH from being written to the first node N1. The high level of the second node N2 is written to the third node N3, and the eighth transistor T8 is turned off. The seventh transistor T7 outputs the frequency control signal VFE as a high-level signal as the second gate drive signal S2 in response to the potential of the first node N1. That is, in the first stage P1, the first gate drive signal S1 output by the first output module 14 and the second gate drive signal S2 output by the second output module 15 are consistent, and both are high-level signals.

[0133] Referring to Figure 4 and Figure 26In the second phase P2, the input signal SIN and the first clock signal SCK1 jump from low level to high level, the second clock signal SCK2 jumps from high level to low level, and the frequency control signal VFE is a high level signal. The first node N1 keeps the low level of the first phase P1, the sixth transistor T6 is turned on, the potential of the sixth node N6 is pulled to an ultra-low potential by the self-boosting effect of the first capacitor C1, the output capability of the sixth transistor T6 is improved, and the first gate drive signal output end out 1 of the shift register outputs the low level of the second clock signal SCK2 as the first gate drive signal S1. Since the second clock signal SCK2 is self-boosted by the first capacitor C1, the sixth node N6 is an ultra-low potential, the eleventh transistor T11 is a protection transistor, the first node N1 is a low potential, the seventh transistor T7 is kept open, and the second gate drive signal output end out2 of the shift register continues to output the high level signal of the frequency control signal VFE as the second gate drive signal S2. Since the first node N1 is a low potential, the second transistor T2 keeps open, the second potential signal VGH is continuously written into the second node N2, and the fifth transistor T5 keeps closed. The first clock signal SCK1 is high, the third transistor T3 is closed, the second capacitor C2 maintains the potential of the third node N3 as a high level, and the eighth transistor T8 is kept closed. That is, in the second phase P2, the first gate drive signal S1 output by the first output module 14 is a low level signal, and the second gate drive signal S2 output by the second output module 15 is a high level signal.

[0134] Reference Figure 4 and Figure 27In the third phase P3, the first clock signal SCK1 is low, the seventeenth transistor T17 is turned on, the high level of the input signal SIN is written to the first node N1 and the sixth node N6, the sixth transistor T6 is turned off, and the seventh transistor T7 is turned off; since the first node N1 is at a high level, the second transistor T2 is turned off, the first transistor T1 is turned on, the first potential signal VGL is written to the second node, the fifth transistor T5 is turned on, and the first gate drive signal output end out1 of the shift register continues to output the second potential signal VGH (i.e., a high level signal) as the first gate drive signal S1; the first clock signal SCK1 is low, the third transistor T3 is turned on, the potential of the second node N2 is written to the third node N3 through the third transistor T3, the eighth transistor T8 is gradually turned on, and the second gate drive signal output end out2 of the shift register begins to output a low potential; at the same time, the second gate drive signal output end out2 of the shift register pulls down the potential of the third node N3 through the bootstrapping effect of the gate-source parasitic capacitance of the eighth transistor T8 (an additional capacitor can also be added to improve the bootstrapping capability), and the output capability of the eighth transistor T8 is increased, so that the second gate drive signal output end out2 of the shift register can output the first potential signal VGL; the first clock signal SCK1 is low, the twelfth transistor T12 is turned on, and the first potential signal VGL of the second node N2 is written to the fourth node N4, preparing for the next phase in which the second clock signal SCK2 is coupled to pull down the fourth node N4 through the ninth transistor T9 and the second capacitor C2. Since the first node N1 is at a high potential, the tenth transistor T10 is turned off, the fourth node N4 and the fifth node N5 maintain the high potential of the second phase P2, and the eleventh transistor T11 is short-circuited at the gate and the source, which is equivalent to a diode; during the process in which the potential of the third node N3 is continuously reduced by the second gate drive signal output end out2 of the shift register, since the diode formed by the eleventh transistor T11 is in a reverse blocking state, the third node N3 can be guaranteed not to be affected by the fourth node N4. That is, in the third phase P3, the first gate drive signal S1 output by the first output module 14 is a high level signal, and the second gate drive signal S2 output by the second output module 15 is a low level signal.

[0135] Reference Figure 4 and Figure 28In the fourth stage P4, the first clock signal SCK1 is high, the seventeenth transistor T17 is closed, the first node N1 and the sixth node N6 maintain the high level in the third stage P3, the seventh transistor T7, the tenth transistor T10 and the sixth transistor T6 maintain closed; since the potential of the first node N1 is high, the first transistor T1 continues to maintain open, the first potential signal VGL is continuously written into the second node N2, and the second node N2 maintains low potential; since the second node N2 maintains low potential, the fourteenth transistor T14 is open, the second clock signal SCK2 is low to make the fifteenth transistor T15 open, and the second potential signal VGH is continuously written into the first node N1, keeping the first node N1 high; the first clock signal SCK1 is high, the third transistor T3 and the twelfth transistor T12 are closed, the fourth node N4 maintains the low level in the last stage, the second clock signal SCK2 is switched from high level to low level, and in this process, the bootstrap effect of the second capacitor C2 is used to pull down the potential of the fourth node N4 to an ultra-low potential, at this time, the diode formed by the eleventh transistor T11 is forward biased, the fourth node N4 pulls down the third node N3, compensates the charge of the third node N3, and keeps the third node N3 at an ultra-low potential. That is, in the fourth stage P4, the first output module 14 outputs the first gate drive signal S1 as a high level signal, and the second output module 15 outputs the second gate drive signal S2 as a low level signal. Then the third stage P3 and the fourth stage P4 are repeatedly performed.

[0136] Figure 29 is a simulation waveform diagram of each key node of the shift register working in a high-frequency working mode provided by the embodiment of the application. Figure 30 is a simulation waveform diagram of each key node of the shift register working in a low-frequency working mode provided by the embodiment of the application. Reference Figure 29 and Figure 30 It can be seen that the output waveforms of the first gate drive signal S1 output by the first gate drive signal output end out1 of the shift register and the second gate drive signal S2 output by the second gate drive signal output end out2 of the shift register meet the expectation.

[0137] Figure 31 is a structural schematic diagram of a pixel circuit provided by the embodiment of the application. As Figure 31 indicated, optionally, the pixel circuit includes a driving module 110, a threshold compensation module 120 and a data writing module 130; the data writing module 130 is connected between the data line Data and the first end of the driving module 110.

[0138] The control end of the data writing module 130 in the nth row of pixel circuits is electrically connected with the first gate drive signal output end out1 of the nth shift register in the gate drive circuit 210;

[0139] The threshold compensation module 120 is connected between the control end and the second end of the driving module 110, and the control end of the threshold compensation module 120 in the nth row of pixel circuits is electrically connected to the second gate driving signal output end out2 of the nth shift register in the gate driving circuit 210. n is an integer greater than or equal to 1.

[0140] Specifically, during the data writing and threshold compensation stage, the data writing module 130 is turned on in response to the first gate driving signal S1 output by the first gate driving signal output end out1 of the shift register 10. The threshold compensation module 120 is turned on in response to the second gate driving signal S2 output by the second gate driving signal output end out2 of the shift register 10. The data writing module 130 transmits the data signal on the data line Data to the first end of the driving module 110, and writes the data signal to the control end of the driving module 110 through the threshold compensation module 120.

[0141] Optionally, the pixel circuit further comprises a first initialization module 140, which is connected between the first end of the driving module 110 and the first initialization line Vref1. The first initialization module 140 in the nth+1 row and the nth+2 row of pixel circuits is electrically connected to the second gate driving signal output end out2 of the nth shift register in the gate driving circuit 210. The first initialization module 140 is used to write a first initialization voltage to the control end of the driving module 110 according to the third gate driving signal S3.

[0142] Optionally, the pixel circuit further comprises a second initialization module 150, which is connected between the first end of the light emitting module 160 and the second initialization line Vref2. The second initialization module 150 is used to write a second initialization voltage to the light emitting module 160 according to the fourth gate driving signal S4.

[0143] Optionally, the pixel circuit further comprises a third initialization module 170, which is connected between the first end of the driving module 110 and the third initialization line Vref3. The third initialization module 170 is used to write a third initialization voltage to the first end of the driving module 110 according to the fourth gate driving signal S4.

[0144] Optionally, the pixel circuit further comprises a first light emitting control module 180 and a second light emitting control module 190. The first light emitting control module 180 is connected between the first end of the driving module 110 and the first power supply line VDD. The second light emitting control module 190 is connected between the second end of the driving module 110 and the first end of the light emitting module 160. The second end of the light emitting module 160 is electrically connected to the second power supply line VSS.

[0145] Optionally, the pixel circuit further comprises a storage module 200. The storage module 200 is connected between the first power supply line VDD and the control terminal of the driving module 110, and the storage module 200 is configured to store the voltage of the control terminal of the driving module 110.

[0146] Figure 32 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present application. Referring to Figure 32 The light emitting module 160 comprises a light emitting element D1, the anode of the light emitting element D1 serving as the first terminal of the light emitting module 160, and the cathode of the light emitting element D1 serving as the second terminal of the light emitting module 160.

[0147] The driving module 110 can comprise a driving transistor DTFT, which is, for example, an NMOS transistor or a PMOS transistor. The gate, the first electrode and the second electrode of the driving transistor DTFT can serve as the control terminal, the first terminal and the second terminal of the driving module 110, respectively. The driving module 110 can generate a driving current according to the voltage between the control terminal and the first terminal thereof, and the light emitting element D1 emits light in response to the driving current.

[0148] The threshold compensation module 120 comprises a threshold compensation transistor M1, which is an NMOS transistor. The gate of the threshold compensation transistor M1 is connected to the second gate driving signal S2. The first electrode of the threshold compensation transistor M1 is connected to the second terminal of the driving module 110, and the second electrode of the threshold compensation transistor T6 is connected to the control terminal of the driving module 110.

[0149] The data writing module 130 comprises a data writing transistor M2, which is, for example, an NMOS transistor or a PMOS transistor. The first electrode of the data writing transistor M2 is connected to the first terminal of the driving module 110. The second electrode of the data writing transistor M2 is connected to the data line Data, and the gate of the data writing transistor M1 is connected to the first gate driving signal S1.

[0150] Optionally, the first initialization module 140 comprises a first initialization transistor M3, which is an NMOS transistor. The first electrode of the first initialization transistor M3 is connected to the control terminal of the driving module 110. The second electrode of the first initialization transistor M3 is connected to the first initialization signal line Vref1, and the gate of the first initialization transistor M3 is connected to the third gate driving signal S3.

[0151] Optionally, the second initialization module 150 comprises a second initialization transistor M4. The gate of the second initialization transistor M4 is connected to the fourth gate driving signal S4. The first electrode of the second initialization transistor M4 is connected to the second initialization signal line Vref2, and the second electrode of the second initialization transistor T5 is connected to the anode of the light emitting element D1. The second initialization transistor M4 can be an NMOS transistor or a PMOS transistor.

[0152] Optionally, the third initialization module 170 comprises a third initialization transistor M5, a gate of the third initialization transistor M5 is connected to the fourth gate driving signal S4, a first electrode of the third initialization transistor M5 is connected to the third initialization signal line Vref3, and a second electrode of the third initialization transistor M5 is connected to the first end of the driving module 110. The third initialization transistor M5 can be an NMOS transistor or a PMOS transistor.

[0153] Optionally, the first light emitting control module 180 comprises a first light emitting control transistor M6, the first light emitting control transistor M6 is a PMOS transistor or an NMOS transistor, a first electrode of the first light emitting control transistor M6 is connected to the first end of the driving module 110, a second electrode of the first light emitting control transistor M6 is connected to the first power supply line VDD, and a gate of the first light emitting control transistor M6 is connected to the light emitting control signal EM. The first light emitting control transistor M6 can be an NMOS transistor or a PMOS transistor.

[0154] Optionally, the second light emitting control module 190 comprises a second light emitting control transistor M7, the second light emitting control transistor M7 is a PMOS transistor or an NMOS transistor, a first electrode of the second light emitting control transistor M7 is connected to the second end of the driving module 110, a second electrode of the second light emitting control transistor M7 is connected to the anode of the light emitting element D1, and a gate of the second light emitting control transistor M7 is connected to the light emitting control signal EM. The second light emitting control transistor M7 can be an NMOS transistor or a PMOS transistor.

[0155] The storage module 200 comprises a storage capacitor Cst, a first electrode of the storage capacitor Cst is connected to the first power supply line VDD, so that the first electrode of the storage capacitor Cst is connected to the first power supply voltage, and a second electrode of the storage capacitor Cst is connected to the control end of the driving module 110.

[0156] Figure 33 is a driving timing diagram of the pixel circuit provided by the embodiment of the present application. Figure 33 The driving timing diagram shown can be applied to driving Figure 32 the pixel circuit shown. The working principle of the pixel circuit provided by the embodiment of the present application will be described below. Figure 32 and Figure 33 , and the working process of the pixel circuit in a display frame at least comprises a first initialization stage t1, a data writing and threshold compensation stage t2, a second initialization stage t3, and a light emitting stage t4. After the end of the i-1th display frame, the i th display frame is entered. i is an integer greater than or equal to 2.

[0157] In the first initialization stage t1 of the i-th display frame, the first initialization module 140 is turned on, and the threshold compensation module 120, the data writing module 130, the second initialization module 150, the third initialization module 170, the first light-emitting control module 180 and the second light-emitting control module 190 are turned off. That is, the first initialization transistor M3 is turned on, and the threshold compensation transistor M1, the second initialization transistor M4, the third initialization transistor M5, the first light-emitting control transistor M6 and the second light-emitting control transistor M7 are turned off. The first initialization voltage transmitted by the first initialization signal line Vref1 is written into the gate of the driving transistor DTFT through the first initialization transistor M3, so as to reset the gate voltage of the driving transistor DTFT to the first initialization voltage and control the driving transistor DTFT to be turned on.

[0158] In the data writing and threshold compensation stage t2 of the i-th display frame, the data writing module 130 and the threshold compensation module 120 are turned on, and the first initialization module 140, the second initialization module 150, the third initialization module 170, the first light-emitting control module 180 and the second light-emitting control module 190 are turned off. That is, the threshold compensation transistor M1 and the data writing transistor M2 are turned on, and the first initialization transistor M3, the second initialization transistor M4, the third initialization transistor M5, the first light-emitting control transistor M6 and the second light-emitting control transistor M7 are turned off. The data voltage transmitted by the data line Data is sequentially written into the gate of the driving transistor DTFT through the data writing transistor M2, the driving transistor DTFT and the threshold compensation transistor M1, so that the gate voltage of the driving transistor DTFT is related to both the data voltage and the threshold voltage of the driving transistor DTFT, and the gate voltage of the driving transistor DTFT is stored through the storage capacitor Cst.

[0159] In the light-emitting stage t3 of the i-th display frame, the second initialization module 150 and the third initialization module 170 are turned on, and the threshold compensation module 120, the data writing module 130, the first initialization module 140, the first light-emitting control module 180 and the second light-emitting control module 190 are turned off. That is, the second initialization transistor M4 and the third initialization transistor M5 are turned on, and the threshold compensation transistor M1, the data writing transistor M2, the first initialization transistor M3, the first light-emitting control transistor M6 and the second light-emitting control transistor M7 are turned off. The second initialization voltage transmitted by the second initialization signal line Vref2 is written into the anode of the light-emitting element D1 through the second initialization transistor M4. The second initialization voltage transmitted by the third initialization signal line Vref3 is written into the first pole of the driving transistor DTFT through the third initialization transistor M5.

[0160] In the light emitting stage t4 of the i-th display frame, the driving module 110, the first light emitting control module 180 and the second light emitting control module 190 are turned on, and the threshold compensation module 120, the data writing module 130, the first initialization module 140, the second initialization module 150 and the third initialization module 170 are turned off. That is, the first light emitting control transistor M6, the second light emitting control transistor M7 and the driving transistor DTFT are turned on, and the threshold compensation transistor M1, the data writing transistor M2, the first initialization transistor M3, the second initialization transistor M4 and the third initialization transistor M5 are turned off. The driving transistor DTFT generates a driving current according to the gate voltage of itself, so as to drive the light emitting element D1 to emit light with a corresponding brightness. In the light emitting stage t4, since the gate voltage of the driving transistor DTFT is related to both the data voltage and the threshold voltage of the driving transistor DTFT, it is helpful to compensate the influence of the threshold voltage of the driving transistor DTFT on the driving current, so as to improve the display uniformity of the light emitting stage.

[0161] Figure 34 is a structural schematic diagram of still another display panel provided by an embodiment of the present application. Referring to Figure 34 Optionally, the display panel further comprises a scanning circuit 220 and a plurality of gate driving signal lines LS, the scanning circuit is electrically connected to the control end of the second initialization module 150 and the control end of the third initialization module 170 through the gate driving signal lines LS, and is configured to provide a fourth gate driving signal S4 to the control end of the second initialization module 150 and the control end of the third initialization module 170.

[0162] Optionally, the display panel further comprises a light emitting control driving circuit 230, and the light emitting control driving circuit 230 is electrically connected to the control end of the first light emitting control module 180 and the control end of the second light emitting control module 190 through the gate driving signal lines LS.

[0163] Optionally, the scanning circuit 220 and the light emitting control driving circuit 230 each comprise a plurality of cascaded shift registers, Figure 32 It is schematically shown that the gate driving circuit 210 is double-ended driving, one level shift register drives one row of pixel circuits PX, the scanning circuit 220 is single-ended driving, one level shift register drives two rows of pixel circuits PX, and the light emitting control driving circuit 230 is single-ended driving, one level shift register drives two rows of pixel circuits PX.

[0164] Based on the same inventive concept, the present application also provides a display device comprising the display panel provided by any of the embodiments of the present application. It can be understood that the display device provided by the embodiments of the present application can be a mobile phone, a wearable product, a computer, a television, a vehicle-mounted display device, or any display device having a display function, and the present application does not make specific limitations thereon. The display device provided by the embodiments of the present application has the beneficial effects of the display panel provided by the embodiments of the present application, and specific descriptions of the display can be referred to the specific descriptions of the display in the above embodiments, which will not be described herein again.

[0165] The above detailed description does not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent replacement and improvement within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A display panel, characterized by, The display panel comprises: a gate drive circuit comprising a multi-stage shift register; the shift register comprises an input module, a first potential control module, a second potential control module, a first output module and a second output module; an output end of the input module is connected to a first node, and is configured to transmit an input signal to the first node in response to a first clock signal; the first potential control module is connected between the first node and a second node, and is configured to transmit a first potential signal or a second potential signal to the second node in response to a potential of the first node; the second potential control module is connected between the second node and a third node, and is configured to transmit a potential of the second node to the third node according to the first potential signal and the first clock signal; the first output module is connected to the first node and the second node respectively, and is configured to output a second clock signal as a first gate drive signal in response to the potential of the first node, or output the second potential signal as the first gate drive signal in response to the potential of the second node; the second output module is connected between the first node and the third node, and is configured to output a frequency control signal as a second gate drive signal in response to the potential of the first node, or output the first potential signal as the second gate drive signal in response to the potential of the third node; wherein the frequency control signal controls the frequency of the appearance of a conduction level in the second gate drive signal by controlling the potential of an output end of the second output module.

2. The display panel of claim 1, wherein, The display panel further comprises at least one frequency control signal line for providing the frequency control signal to the shift register.

3. The display panel of claim 2, wherein, The display panel comprises k frequency control signal lines, the gate drive circuit comprises a plurality of cascaded shift register groups, the shift register group comprises k cascaded shift register units, k is an integer greater than or equal to 2, the shift register unit comprises m shift registers, m is an integer greater than or equal to 1, different shift register units in the same shift register group are electrically connected to different frequency control signal lines, and different shift register groups are connected to the same k frequency control signal lines. The display panel comprises a plurality of pixel circuit groups; the pixel circuit group comprises k sub-pixel circuit groups, the sub-pixel circuit group comprises a plurality of rows of pixel circuits; the sub-pixel circuit group is electrically connected to the shift register unit in a one-to-one correspondence; an output end of a first shift register is electrically connected to r rows of pixel circuits, and r is an integer greater than or equal to 1.

4. The display panel of claim 3, wherein, The display area of the display panel comprises at least two display sub-areas, and the at least two display sub-areas comprise a first display sub-area and a second display sub-area; a refresh frequency of the first display sub-area is a first refresh frequency, a refresh frequency of the second display sub-area is a second refresh frequency, and the first refresh frequency is less than the second refresh frequency. In a first display frame, the time of pulse jump of the frequency control signal of the k frequency control signal lines to the on level is sequentially delayed; in a second display frame, the frequency control signal on the k frequency control signal lines is at the on level; The first display frame is a holding frame of at least part of the row pixel circuits in the first display area, and is a refresh frame of the second display area; the second display frame is a refresh frame of the first display area and the second display area. In the second display frame, the first display area is refreshed before the second display area.

5. The display panel of claim 4, wherein, K-1 shift register units are connected between two adjacent shift register units connected with the same frequency control signal line.

6. The display panel of claim 3, wherein, M is greater than or equal to 8, and k is greater than or equal to 4.

7. The display panel of claim 3, wherein, The number of rows of pixel circuits in each pixel circuit group is the same.

8. The display panel of claim 1, wherein, The first potential control module comprises a first inverter, and the first inverter comprises a first transistor and a second transistor. The gate of the first transistor is connected with the first node, the first pole of the first transistor is connected with the first potential signal, and the second pole of the first transistor is connected with the second node. The gate of the second transistor is connected with the first node, the first pole of the second transistor is connected with the second potential signal, and the second pole of the second transistor is connected with the second node.

9. The display panel of claim 8, wherein, The channel type of the first transistor is different from that of the second transistor.

10. The display panel of claim 9, wherein, The first transistor is an N-channel transistor, and the second transistor is a P-channel transistor.

11. The display panel of claim 1, wherein, The second potential control module comprises a third transistor and a fourth transistor. The gate of the third transistor is connected with the first clock signal, the first pole of the third transistor is connected with the second node, and the second pole of the third transistor is connected with the first pole of the fourth transistor. The gate of the fourth transistor is connected with the first potential signal, and the second pole of the fourth transistor is connected with the third node.

12. The display panel of claim 11, wherein, The third transistor and the fourth transistor are both P-channel transistors.

13. The display panel of claim 1, wherein, The first output module comprises a first output unit and a second output unit. The first output unit is connected with the second node, and is configured to output the second potential signal as the first gate driving signal according to the potential of the second node. The second output unit is connected with the first node, and is configured to output the second clock signal as the first gate driving signal according to the potential of the first node.

14. The display panel of claim 13, wherein, The first output unit comprises a fifth transistor, the gate of the fifth transistor is connected with the second node, the first pole of the fifth transistor is connected with the second potential signal, and the second pole of the fifth transistor is an output end of the first output unit. The second output unit comprises a sixth transistor and a first capacitor, a gate of the sixth transistor is connected with the first node and a first end of the first capacitor respectively, a first pole of the sixth transistor is connected with a second end of the first capacitor, and a second pole of the sixth transistor is connected with the second clock signal as an output terminal of the second output unit.

15. The display panel of claim 1, wherein, The second output module comprises a second inverter, and the second inverter comprises a third output unit and a fourth output unit. The third output unit is connected with the first node, and is configured to output the frequency control signal as the second gate driving signal according to a potential of the first node. The fourth output unit is connected with the third node, and is configured to output the first potential signal as the second gate driving signal according to a potential of the third node.

16. The display panel of claim 15, wherein, The third output unit comprises a seventh transistor, a gate of the seventh transistor is connected with the first node, a first pole of the seventh transistor is connected with the frequency control signal, and a second pole of the seventh transistor is connected with the third output unit as an output terminal of the third output unit. The fourth output unit comprises an eighth transistor, a gate of the eighth transistor is connected with the third node, the eighth transistor is connected with the fourth output unit as an output terminal of the fourth output unit, and a second pole of the eighth transistor is connected with the first potential signal.

17. The display panel of claim 1, wherein, The shift register further comprises a pull-down module. The pull-down module is connected between the first node and the third node, and is configured to control a potential of the third node according to at least the potential of the first node, the second potential signal and the second clock signal.

18. The display panel of claim 1, wherein, The waveform of the second clock signal is the same as the waveform of the first clock signal.

19. The display panel of claim 18, wherein, The period of the second clock signal is the same as the period of the first clock signal.

20. The display panel of claim 19, wherein, The waveform of the second clock signal is delayed relative to the waveform of the first clock signal.

21. The display panel of claim 20, wherein, The waveform of the second clock signal is later than the waveform of the first clock signal by half of the period.

22. The display panel of claim 19, wherein, The length of a low level in the first clock signal is less than or equal to half of the period, and the length of a high level in the first clock signal is greater than half of the period.

23. The display panel of claim 19, wherein, The length of a low level in the second clock signal is less than or equal to half of the period, and the length of a high level in the second clock signal is greater than half of the period.

24. The display panel of claim 23, wherein, The low level is the same as the first potential signal, and the high level is the same as the second potential signal.

25. The display panel of claim 17, wherein, The pull-down module comprises a first control unit and a second control unit. The first control unit is connected between the first node and a fourth node, and is configured to control a potential of the fourth node according to the potential of the first node, the second potential signal and the second clock signal. The second control unit is connected between the third node and the fourth node, and is configured to control the potential of the third node according to the potential of the fourth node.

26. The display panel of claim 25, wherein, The pull-down module further comprises a third control unit, the third control unit is connected between the second node and the fourth node, and is configured to transmit the potential of the second node to the fourth node according to the first clock signal and the first potential signal.

27. The display panel of claim 25, wherein, The first control unit comprises a ninth transistor, a tenth transistor and a second capacitor; The gate of the ninth transistor is connected to the fourth node, the first electrode of the ninth transistor is connected to the second clock signal, and the second electrode of the ninth transistor and the first electrode of the tenth transistor are connected to a fifth node; The gate of the tenth transistor is connected to the first node, and the second electrode of the tenth transistor is connected to the second potential signal; The first end of the second capacitor is connected to the fourth node, and the second end of the second capacitor is connected to the fifth node; The second control unit comprises an eleventh transistor; the gate of the eleventh transistor is connected to the gate of the ninth transistor and the first electrode of the eleventh transistor, and serves as the first end of the second control unit; and the second electrode of the eleventh transistor is connected to the third node.

28. The display panel of claim 26, wherein, The third control unit comprises a twelfth transistor and a thirteenth transistor; the gate of the twelfth transistor is connected to the first clock signal, the first electrode of the twelfth transistor is connected to the second node, and the second electrode of the twelfth transistor is connected to the first electrode of the thirteenth transistor; The gate of the thirteenth transistor is connected to the first potential signal, and the second electrode of the thirteenth transistor is connected to the fourth node.

29. The display panel of claim 1, wherein, The shift register further comprises a third potential control module connected between the first node and the second node, for controlling the potential of the first node according to the potential of the second node.

30. The display panel of claim 29, wherein, The third potential control module comprises a fourteenth transistor; the gate of the fourteenth transistor is connected to the second node, the first electrode of the fourteenth transistor is connected to the second potential signal, and the second electrode of the fourteenth transistor is connected to the first node.

31. The display panel of claim 30, wherein, The third potential control module further comprises a fifteenth transistor; the gate of the fifteenth transistor is connected to the second clock signal, the first electrode of the fifteenth transistor is connected to the second electrode of the fourteenth transistor, and the second electrode of the fifteenth transistor is connected to the first node.

32. The display panel of claim 1, wherein, The shift register further comprises a potential isolation module; the control end of the potential isolation module is connected to the first potential signal, the first end of the potential isolation module is connected to the first node, and the second end of the potential isolation module is connected to the first control end of the first output module; and the potential isolation module is used for being turned on or turned off according to the potential difference between the first potential signal and the first node.

33. The display panel of claim 32, wherein, The potential isolation module comprises a sixteenth transistor; the gate of the sixteenth transistor serves as the control end of the potential isolation module, the first electrode of the sixteenth transistor serves as the first end of the potential isolation module, and the second electrode of the sixteenth transistor serves as the second end of the potential isolation module.

34. The display panel of claim 1, wherein, The input module comprises a seventeenth transistor; the gate of the seventeenth transistor is connected to the first clock signal, the first electrode of the seventeenth transistor is connected to the input signal, and the second electrode of the seventeenth transistor is connected to the first node.

35. The display panel of claim 1, wherein, Further comprising pixel circuits arranged in an array; The pixel circuit comprises a driving module, a threshold compensation module and a data writing module; the data writing module is connected between a data line and a first end of the driving module; a control end of the data writing module in the pixel circuit of the nth row is electrically connected with a first gate driving signal output end of the nth shift register in the gate driving circuit; the threshold compensation module is connected between a control end and a second end of the driving module, and a control end of the threshold compensation module in the pixel circuit of the nth row is electrically connected with a second gate driving signal output end of the nth shift register in the gate driving circuit; n is an integer greater than or equal to 1.

36. The display panel of claim 35, wherein, The pixel circuit further comprises a first initialization module, the first initialization module is connected between the first end of the driving module and a first initialization line, and the first initialization modules in the pixel circuits of the nth+1 row and the nth+2 row are electrically connected with the second gate driving signal output end of the nth shift register in the gate driving circuit.

37. The display panel of claim 36, wherein, The pixel circuit further comprises a second initialization module, the second initialization module is connected between a first end of a light emitting module and a second initialization line.

38. The display panel of claim 37, wherein, The pixel circuit further comprises a third initialization module, the third initialization module is connected between the first end of the driving module and a third initialization line.

39. The display panel of claim 38, wherein, The display panel further comprises a scanning circuit and a plurality of gate driving signal lines, the scanning circuit is electrically connected with a control end of the second initialization module and a control end of the third initialization module through the gate driving signal lines.

40. The display panel of claim 39, wherein, The pixel circuit further comprises a first light emitting control module and a second light emitting control module, the first light emitting control module is connected between the first end of the driving module and a first power supply line, the second light emitting control module is connected between the second end of the driving module and a first end of a light emitting module, and a second end of the light emitting module is electrically connected with a second power supply line.

41. The display panel of claim 40, wherein, The display panel further comprises a light emitting control driving circuit; the light emitting control driving circuit is electrically connected with a control end of the first light emitting control module and a control end of the second light emitting control module through the gate driving signal lines.

42. A display device comprising: The display panel comprises the pixel circuit according to any one of claims 1-41.

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