Multi-value RRAM reading circuit and reading method thereof
By designing a multi-value RRAM reading circuit including RRAM, transistor, comparator, encoder and D flip-flop, using RC delay and clock signals of D flip-flops, the problem of high layout area and power consumption in the prior art is solved, and efficient multi-value RRAM information reading is achieved.
Patent Information
- Application Number
- CN202411821743.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-11
- Publication Date
- 2025-04-04
AI Technical Summary
Existing multi-value RRAM reading circuits require reference units and analog-to-digital converters (ADCs), resulting in increased layout area and increased power consumption.
A multi-value RRAM reading circuit is designed, including an RRAM, transistor, comparator, encoder and at least one D flip-flop. By applying a pulse voltage, an RC delay is provided to both ends of the RRAM, and a D flip-flop and a clock signal are used to output a signal representing the RRAM resistance value according to the pulse width, without the need for a reference unit and an ADC.
This solution reduces the layout area of the reading circuit and reduces its power consumption, achieving efficient multi-value RRAM information reading.
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Figure CN119763633A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor memory technology, and in particular to a multi-value RRAM reading circuit and a reading method thereof. Background Art
[0002] Resistive random access memory (RRAM), also known as memristor, is a new type of non-volatile random access memory. By applying a write voltage to it, the resistance state of RRAM can be changed to a high resistance state or a low resistance state to store information. When the information stored in RRAM needs to be read, the resistance state of RRAM is converted into a current signal or a voltage signal that can be recognized by the external circuit. In the current technical solution, the multi-value RRAM reading circuit usually requires a reference unit and an analog-to-digital converter (ADC), which not only increases the layout area, but also increases the power consumption. Summary of the invention
[0003] The embodiments of the present application provide a multi-value RRAM read circuit and a read method thereof, thereby reducing the layout area of the read circuit and lowering its power consumption at least to a certain extent.
[0004] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by the practice of the present application.
[0005] According to one aspect of an embodiment of the present application, a multi-value RRAM reading circuit is provided, including an RRAM, a transistor, a comparator, an encoder and at least one D flip-flop; the source of the transistor is connected to a bit line, the gate of the transistor is connected to a word line, and the drain of the transistor is connected to one end of the RRAM; the other end of the RRAM is connected to the negative input of the comparator, and the positive input of the comparator is connected to the bit line; the output of the comparator is connected to the input of the D flip-flop, and the output of the D flip-flop is connected to the input of the encoder, and the encoder is used to convert the data output by at least one of the D flip-flops into a corresponding binary digital signal and output it.
[0006] In some embodiments of the present application, a capacitor is further included, one end of the capacitor is connected to the negative input terminal of the comparator, and the other end is grounded.
[0007] In some embodiments of the present application, the number of the D flip-flops is the number of resistance states of the RRAM minus 1. When the number of the D flip-flops is multiple, the input end of each of the D flip-flops is connected to the output end of the comparator, the output end of each of the D flip-flops is connected to the input end of the encoder, and the pulse width of the clock signal of different D flip-flops is different.
[0008] In some embodiments of the present application, the clock signal of the D flip-flop is a single pulse signal, and the pulse width of each of the clock signals is between the pulse widths corresponding to two adjacent resistance states of the RRAM.
[0009] In some embodiments of the present application, the comparator is externally connected to a bias voltage or has an automatic offset compensation circuit integrated therein.
[0010] According to one aspect of an embodiment of the present application, a method for reading a multi-valued RRAM reading circuit is provided, comprising:
[0011] A pulse voltage signal is applied to the bit line, and a word line voltage is applied to turn on the transistor. The voltage at both ends of the RRAM outputs a pulse voltage signal through a comparator, and the pulse width of the pulse voltage signal is equal to the RC delay;
[0012] The D flip-flop makes a determination according to the pulse voltage signal to output an indication signal for representing the resistance value of the RRAM, and the encoder converts the indication signal into a corresponding binary digital signal.
[0013] In some embodiments of the present application, when there are multiple D flip-flops, a clock signal of each D flip-flop is obtained based on a time division multiplexing technology.
[0014] In the technical solutions provided in some embodiments of the present application, the RRAM reading circuit includes an RRAM, a transistor, a comparator, an encoder, and at least one D flip-flop. When reading, a voltage is applied to cause an RC delay at both ends of the RRAM, and the two ends of the RRAM after the pulse voltage is applied are connected to the comparator to obtain a voltage signal of a corresponding pulse width, and then a signal representing the resistance value of the RRAM to be measured is obtained according to the pulse width through the D flip-flop and a set clock signal, and then the signal is output through the encoder. In this way, the information stored in the multi-value RRAM can be read without a reference unit and an ADC, which reduces the layout area of the reading circuit and also reduces its power consumption.
[0015] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:
[0017] Figure 1A schematic structural diagram of a multi-valued RRAM reading circuit according to an embodiment of the present application is shown;
[0018] Figure 2 A schematic structural diagram of a dual-resistance RRAM reading circuit according to an embodiment of the present application is shown;
[0019] Figure 3 for Figure 2 Corresponding signal timing diagram;
[0020] Figure 4 A schematic structural diagram of a four-resistance-state RRAM reading circuit according to an embodiment of the present application is shown;
[0021] Figure 5 for Figure 4 Corresponding signal timing diagram. DETAILED DESCRIPTION
[0022] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more comprehensive and complete and fully convey the concept of the example embodiments to those skilled in the art.
[0023] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present application. However, those skilled in the art will appreciate that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, known methods, devices, realizations or operations are not shown or described in detail to avoid blurring the various aspects of the application.
[0024] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.
[0025] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.
[0026] Figure 1 A schematic structural diagram of a multi-valued RRAM reading circuit according to an embodiment of the present application is shown.
[0027] like Figure 1 As shown, the multi-value RRAM reading circuit includes an RRAM, a transistor M1, a comparator A1, an encoder, and at least one D flip-flop.
[0028] Specifically, transistor M1 is used to control the read operation of RRAM, the source of transistor M1 is connected to the bit line (BitLine, BL), the gate is connected to the word line, and the drain is connected to one end of RRAM. RRAM is used as a storage unit, and its other end is connected to the negative input end of comparator A1, and the positive input end of comparator A1 is connected to the bit line BL. The output end of transistor A1 is connected to the input end of the D flip-flop, and the output end of the D flip-flop is connected to the input end of the encoder. The encoder can convert the output signal of the D flip-flop into a corresponding binary digital signal and output it.
[0029] In this embodiment, when reading, a voltage is applied to cause an RC delay at both ends of the RRAM, and the two ends of the RRAM after the pulse voltage is applied are connected to the comparator A1 to obtain a voltage signal of a corresponding pulse width, and then a signal representing the resistance value of the RRAM to be measured is obtained according to the pulse width through a D flip-flop and a set clock signal, and then the signal is output through an encoder. In this way, the information stored in the multi-value RRAM can be read without a reference unit and an ADC, which reduces the layout area of the reading circuit and its power consumption.
[0030] In some embodiments of the present application, the multi-value RRAM reading circuit further includes a capacitor C1, one end of which is connected to the negative input end of the comparator A1, and the other end of which is grounded. Thus, when the transistor M1 is turned on, the RRAM and the capacitor C1 generate a corresponding RC delay, so that the information stored in the RRAM can be determined later according to the RC delay.
[0031] In some embodiments of the present application, the number of D flip-flops is the number of resistance states of the RRAM minus 1. For example, when the RRAM is in a dual resistance state, such as Figure 2 As shown, in the multi-value RRAM reading circuit, the number of D flip-flops is 1. When the RRAM is in a four-resistance state, as shown in FIG. Figure 4 As shown, in the multi-value RRAM reading circuit, the number of D flip-flops is 3.
[0032] And, if Figure 4 As shown, when the number of D flip-flops is multiple (i.e., two or any number above two), the input end of each D flip-flop is connected to the output end of transistor A1, the output end of each D flip-flop is connected to the input end of the encoder, and the pulse width of the clock signal of different D flip-flops is different.
[0033] In one example, the clock signal of the D flip-flop may be a single pulse signal, and the pulse width of each clock signal is between the pulse widths corresponding to two adjacent resistance states of the RRAM. Figure 2 As shown, when the RRAM is in a dual-resistance state, the pulse width corresponding to the clock signal t1 of the D flip-flop is between the pulse widths corresponding to the low-resistance state r1 and the high-resistance state r2 of the RRAM; Figure 4 As shown, when the RRAM is in a four-resistance state, assuming that the clock signals of the three D flip-flops are t1, t2 and t3 respectively, the pulse width corresponding to the clock signal t1 is between the pulse widths corresponding to the resistance states r1 and r2 of the RRAM, the pulse width corresponding to the clock signal t2 is between the pulse widths corresponding to the resistance states r2 and r3 of the RRAM, and the pulse width corresponding to the clock signal t3 is between the pulse widths corresponding to the resistance states r3 and r4 of the RRAM.
[0034] In one embodiment, the comparator A1 may be externally connected to a bias voltage or may be a comparator with an internally integrated offset adjustment or automatic offset compensation circuit, so that the voltage loss of the read voltage passing through the RC circuit can be eliminated.
[0035] Based on the foregoing embodiments, the present application further provides a method for reading a multi-valued RRAM reading circuit, the method comprising:
[0036] A pulse voltage signal is applied to the bit line, and a word line voltage is applied to turn on the transistor. The voltage at both ends of the RRAM outputs a pulse voltage signal through a comparator, and the pulse width of the pulse voltage signal is equal to the RC delay;
[0037] The D flip-flop makes a determination according to the pulse voltage signal to output an indication signal for representing the resistance value of the RRAM, and the encoder converts the indication signal into a corresponding binary digital signal.
[0038] In this embodiment, take RRAM in dual resistance state as an example. Figure 2 and Figure 3 As shown, when reading the resistance value of RRAM, a pulsed small voltage signal is applied to the BL line to generate an RC delay; when RRAM is in a low resistance state r1, the rising edge of Vb passing through RRAM is small; when RRAM is in a high resistance state r2, the rising edge of Vb passing through RRAM is large; the voltages Va and Vb at both ends of RRAM pass through the comparator A1, and according to the rising edge of Vb, the corresponding Vout is output, and Vout is connected to a D flip-flop, wherein the D flip-flop clock signal t1, the pulse width of t1 is between the pulse widths corresponding to r1 and r2, and when the D flip-flop outputs 0 / 1, it represents that the resistance state is low resistance state r1 / high resistance state r2 at this time, and finally the data Q output by the flip-flop is integrated and converted into a binary digital signal output through the encoder.
[0039] Take RRAM as an example with four resistance states, such as Figure 4 and Figure 5 As shown, when reading the resistance value of RRAM, a pulsed small voltage signal is applied to the BL line to generate an RC delay; when the resistance value of RRAM is larger, the slope of the rising edge of Vb passing through RRAM increases, and vice versa, when the resistance value of RRAM is smaller, the slope of the rising edge of Vb passing through RRAM decreases; the voltages Va and Vb at both ends of RRAM pass through the comparator A1, and the corresponding Vout is output according to the rising edge of Vb, and Vout is simultaneously connected to three D flip-flops, wherein the clock signals of the three D flip-flops are t1, t2 and t3, wherein the pulse width of t1 is between the pulse widths corresponding to r1 and r2, the pulse width of t2 is between the pulse widths corresponding to r2 and r3, and the pulse width of t3 is between the pulse widths corresponding to r3 and r4, and the resistance state of RRAM at this time is determined by the 0 / 1 signal finally output by the three D flip-flops, and finally the data Q output by the flip-flops is integrated and converted into a binary digital signal output through the encoder.
[0040] In one embodiment, when there are multiple D flip-flops, different pulse width signals can be allocated to different signal channels within a clock cycle based on time division multiplexing technology, so as to obtain clock signals of each D flip-flop.
[0041] Compared with the prior art, the multi-value RRAM reading circuit and the reading method thereof provided in the embodiment of the present application include RRAM, transistor M1, transistor A1, encoder and at least one D flip-flop. When reading, a voltage is applied to make an RC delay exist at both ends of the RRAM, and the two ends of the RRAM after the pulse voltage is applied are connected to the transistor A1 to obtain a voltage signal of a corresponding pulse width, and then a signal representing the resistance value of the RRAM to be measured is obtained according to the pulse width through the D flip-flop and the set clock signal, and then the signal is output through the encoder. In this way, the information stored in the multi-value RRAM can be read without a reference unit and an ADC, and while reducing the layout area of the reading circuit, its power consumption is also reduced.
[0042] Those skilled in the art will appreciate that all or part of the processes of the above-mentioned embodiments can be implemented by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, wherein the computer-readable storage medium is a disk, an optical disk, a read-only storage memory, or a random access memory, etc.
[0043] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.
Claims
1. A multi-value RRAM reading circuit, characterized in that: The invention comprises an RRAM, a transistor, a comparator, an encoder and at least one D flip-flop; the source of the transistor is connected to a bit line, the gate of the transistor is connected to a word line, and the drain of the transistor is connected to one end of the RRAM; the other end of the RRAM is connected to a negative input end of the comparator, and the positive input end of the comparator is connected to the bit line; the output end of the comparator is connected to an input end of the D flip-flop, and the output end of the D flip-flop is connected to an input end of the encoder, and the encoder is used to convert a signal output by at least one D flip-flop into a corresponding binary digital signal and output it.
2. The reading circuit according to claim 1, characterized in that: It also includes a capacitor, one end of which is connected to the negative input end of the comparator, and the other end of which is grounded.
3. The reading circuit according to claim 1 or 2, characterized in that: The number of the D flip-flops is the number of resistance states of the RRAM minus 1. When the number of the D flip-flops is multiple, the input end of each of the D flip-flops is connected to the output end of the comparator, the output end of each of the D flip-flops is connected to the input end of the encoder, and the pulse width of the clock signal of different D flip-flops is different.
4. The reading circuit according to claim 3, characterized in that: The clock signal of the D flip-flop is a single pulse signal, and the pulse width of each clock signal is between the pulse widths corresponding to two adjacent resistance states of the RRAM.
5. The reading circuit according to claim 1, characterized in that: The comparator is externally connected to a bias voltage or internally integrated with an automatic offset compensation circuit.
6. The reading method of the multi-valued RRAM reading circuit according to any one of claims 1 to 5, characterized in that: include: A pulse voltage signal is applied to the bit line, and a word line voltage is applied to turn on the transistor. The voltage at both ends of the RRAM outputs a pulse voltage signal through a comparator, and the pulse width of the pulse voltage signal is equal to the RC delay; The D flip-flop makes a determination according to the pulse voltage signal to output an indication signal for representing the resistance value of the RRAM, and the encoder converts the indication signal into a corresponding binary digital signal.
7. The reading method according to claim 6, characterized in that: When there are multiple D flip-flops, the clock signal of each D flip-flop is obtained based on time division multiplexing technology.