SRAM self-test system and test method based on 32-bit MCU

Abstract

The invention discloses an SRAM self-test system and a test method based on a 32-bit MCU, and belongs to the technical field of self-built test circuits in SRAM. The SRAM self-test system based on a 32-bit MCU comprises an external excitation module, a protocol analysis module, a function control module and an MBIST module. The invention solves the problem that the test process of the prior art is relatively complicated and the test cost is high. Under the premise of ensuring the fault coverage of the SRAM test, the invention controls the work of MBIST through a series of protocols, and can flexibly select different SRAMs according to the actual needs of the project. The test process is relatively simple, and the same type of projects can be directly used without too much modification, which saves the test cost. The compatibility of the invention is very high. When dealing with multiple SRAMs of different sizes, multiple SRAM tests can be configured through protocols to ensure the accuracy and reliability of the test results.

Description

Technical Field

[0001] The invention relates to the technical field of a self-built test circuit in an SRAM, in particular to a 32-bit MCU-based SRAM self-test system and a test method. Background Art

[0002] In semiconductor technology, SRAM plays a vital role in MCU chips. Since the geometry of SRAM is very small, it is susceptible to subtle defects. The testing of SRAM is very important, and the output of SRAM is very low during the manufacturing process. But for SRAM, since there are no main inputs and outputs, testing becomes very cumbersome.

[0003] A Chinese patent with publication number CN114639439A discloses a chip internal SRAM test method, device, storage medium and SSD device. The method includes: remapping the physical address area where the chip firmware runs to a physical address area outside the static random access memory SRAM inside the chip; clearing the data in the SRAM when receiving a start test instruction sent by a test machine; writing the data to be tested to the target test address in the SRAM, and performing reliability verification on the SRAM after the data is written. It can realize full-area reliability testing of the chip internal SRAM area when the chip is in normal working state, make up for the test blind spots that may exist in the chip internal SRAM from factory to product production. The test results are accurate, the test intensity is high, and no additional test equipment environment is required, which greatly reduces the test cost while achieving strict control of chip quality.

[0004] In actual use, the reliability test of the entire SRAM area inside the chip is carried out when the chip is in normal working condition. The test process is relatively complicated and the test cost is high. Summary of the invention

[0005] The purpose of the present invention is to provide an SRAM self-test system and a test method based on a 32-bit MCU. Under the premise of ensuring the SRAM test fault coverage, a series of protocols are used to control the work of MBIST, different SRAMs can be flexibly selected according to actual project requirements, the reusability is very high, the same type of projects can be directly used without too much modification, and the compatibility is very high. When dealing with multiple SRAMs of different sizes, multiple SRAM tests can be configured through protocols, thereby solving the problems raised in the background technology.

[0006] To achieve the purpose, the present invention provides the following technical solution: an SRAM self-test system based on a 32-bit MCU, comprising: The external stimulus module is used to generate a protocol sequence for entering the memory self-test mode, and transmit the sequence to the MBIST module and the protocol analysis module through the input port, and return the result fed back by the protocol analysis module to the external stimulus module through the output port; The protocol parsing module is connected to the external excitation module and the function control module, and is used to receive data transmitted from the external excitation module and parse the data according to the protocol; The function control module is used for receiving the results parsed by the mode enable and protocol parsing modules, and starting the corresponding function module according to the parsing results, transmitting the signal to the MBIST module and activating MBIST, and transmitting the MBIST_enable and SRAM_sel signals to the MBIST module to activate MBIST; MBIST module is used to write specific data to a specific address in SRAM, generate the required address of SRAM on demand, and compare the SRAM output at a given address with the expected pattern provided by the pattern generator.

[0007] Preferably, the external excitation module comprises 5 input ports MBIST_CLK, MBIST_RSTn, CLK, RSTn, DATA_in, and an output port DATA_out, wherein MBIST_CLK and MBIST_RSTn are delivered to the MBIST module, CLK, RSTn and DATA_in are delivered to the protocol analysis module, and DATA_out returns the result of the protocol analysis module feedback to the external excitation module.

[0008] Preferably, the protocol parsing module specifically includes: Receive CLK, RSTn and DATA_in from the external excitation module and parse them according to the protocol. Each segment of this protocol includes 20 bits of data. After parsing is completed, it is sent on the rising edge of the clock, where bit[19:18] and bit[1:0] are the start and end flags of the protocol respectively. The start flag is that bit19 is pulled high on the rising edge of the protocol clock, and bit18 is pulled low on the second protocol clock rising edge, and then the protocol is sent. During the entire protocol sending stage, the system must be kept in reset state; During the protocol sequence transmission process, the protocol parsing module feeds back a sequence of the received protocol content to the external excitation module. The external excitation module confirms whether the sequence is successfully received by the protocol parsing module. The end mark is that bit1 is pulled low at the rising edge of the protocol clock, and bit0 is pulled high at the second clock rising edge. After the protocol sequence is sent, the protocol parsing module parses the sequence protocol, and the parsing success or failure is fed back to the status indication module. The parsing status includes 4-bit data display; If the protocol is parsed successfully, the protocol parsing module will send the corresponding protocol instructions to the function control module, activate the corresponding function and give feedback. At the same time, the protocol parsing module will pull up the parsing success flag Enter_success and transmit it to the status display module.

[0009] Preferably, the MBIST module comprises: FSM, used to generate test vectors, control read and write operations, and analyze response data Test pattern generator, used to write specific data to specific addresses in SRAM and provide data comparison reference for output comparison module; An address generator is used to generate the addresses required by the SRAM as required; A read / write controller that determines when to write a new test pattern or read it back; Output compare module, which compares the SRAM output at a given address with the expected pattern provided by the pattern generator, and detects a fault if there is a mismatch; The status indication module is used to receive the output results of the protocol parsing module, the function control module, and the output comparison module. The status indication module is implemented by multiplexing the MCU-related PADs. In different modes, the multiplexing function of different PADs is enabled to ensure that more functions are achieved using limited PADs.

[0010] Preferably, described MBIST module also comprises 5 input ports and 7 output ports, wherein 5 output ports are respectively MBIST_CLK, MBIST_RTSn, MBIST_enable, SRAM_SEL, SRAM_out, and 7 output ports are respectively MBIST_pattern, MBIST_ADDR, MBIST_CLK_O, MBIST_Wen, MBIST_Cen, BIST_DONE and BIST_OK.

[0011] Preferably, the test pattern generator generates 6 patterns in total, and the 6 patterns are as follows: Pattern1: The written data is 0x00000000; Pattern2: The written data is 0xffffffff; Pattern3: The written data is 0xcccccccc; Pattern4: The written data is 0x0f0f0f0f; Pattern5: The written data is 0x00ff00ff; Pattern6: The written data is 0x55555555.

[0012] The SRAM test method based on 32-bit MCU includes the following steps: S1: After sending the sequence to enter the test mode to enable MBIST, the test is started; S2: Parse the received data according to the protocol; S3: If the protocol analysis result is correct, turn on the MBIST enable signal; S4: Receive the enable signal and activate MBIST, so that the FSM in MBIST starts working; S5: Generate addresses according to address generation and ascending and descending order requests; S6: Generate a set of test write data and transmit it to the SRAM and output comparison module; S7: FSM performs read and write operations; S8: After the FSM reads and writes, it compares the read and written data and outputs the final result to the status display module according to the current pattern mode; S9: After the test is completed, turn off the power and exit the test mode.

[0013] Preferably, when the FSM is kept in the reset state, the operation of the address generator, the read-write controller, and the test pattern generator is controlled by switching the state. The FSM consists of 8 states in total, namely: IDLE, UP_W0, UP_R0W1, UP_R1W0, DOWN_R0W1, DOWN_R1W0, DOWN_R0, and COMPLETE.

[0014] Preferably, the corresponding operations of the 8 states of the FSM are transmitted to the address generator and the test pattern generator to generate stimulus, and the operations corresponding to the 8 states are as follows: IDLE: Idle state, MBIST is in reset state, and FSM has no action; UP_W0: The address transmitted to SRAM is in ascending order through the shift register, and a write-0 operation is performed; UP_R0W1: The addresses sent to the SRAM are in ascending order through the shift register. For each address, a read operation is performed and the read data is compared with the data written in the previous step. After the read operation, the pattern is written, and then the pattern is inverted and the current read and write operation is performed again; UP_R1W0: The addresses sent to the SRAM are in ascending order through the shift register. For each address, a read operation is performed and the read data is compared with the data written in the previous step. After the read operation, the pattern is written, and then the pattern is inverted and the current read and write operation is performed again; DOWN_R0W1: The addresses sent to the SRAM are in descending order through the shift register. For each address, a read operation is performed and the read data is compared with the data written in the previous step. After the read operation, the pattern is written, and then the pattern is inverted and the current read and write operation is performed again; DOWN_R1W0: The addresses sent to the SRAM are in descending order through the shift register. For each address, a read operation is performed and the read data is compared with the data written in the previous step. After the read operation, the pattern is written, and then the pattern is inverted and the current read and write operation is performed again; DOWN_R0: The addresses sent to the SRAM are in descending order through the shift register. For each address, a read operation is performed and the read data is compared with the data written in the previous step. Then the pattern is inverted and the current read and write operation is performed again. COMPLETE: The FSM process is completed.

[0015] Preferably, after the FSM reads and writes in step S8, the read and written data are compared, and according to the pattern mode at this time, the final result is output to the status display module, which specifically includes: After the FSM reads and writes, the pattern is updated until the pattern traversal is completed; After all patterns are traversed, the BIST_DONE signal is output to the status indication module; At the same time, the output comparison module will output the mismatch information collected during the MBIST process to the status display module; If all comparisons are successful, the output comparison module will pull up and output bist_ok. If the comparison fails, bist_ok will not be set.

[0016] Compared with the prior art, the present invention has the following beneficial effects: The invention controls the work of MBIST through a series of protocols under the premise of ensuring the SRAM test fault coverage, and can flexibly select different SRAMs according to actual project requirements. Different types of SRAMs have different access speeds, power consumption and capacity characteristics. The appropriate SRAM is selected according to the project requirements, and the system performance requirements can be met to the maximum extent. While meeting the performance requirements, the overall cost of the project is reduced, and the energy efficiency ratio of the SRAM self-test circuit is improved. The requirements of the project in different stages or different application scenarios can be met, and the flexibility and scalability of the test are enhanced. The reusability is very high, and the test process is relatively simple. The same type of projects can be directly used without too much modification, which saves the test cost. At the same time, the compatibility of the invention is very high. When dealing with multiple SRAMs of different sizes, the multi-SRAM test is configured through the protocol, and the SRAM test of different sizes and types can be automatically processed, and the tediousness and error-proneness of manual configuration are avoided, thereby significantly improving the test efficiency. The test process is accurately controlled by the protocol, and the error caused by human intervention can be reduced, and the accuracy and reliability of the test result can be ensured. During the test process, the protocol can record detailed test information and fault data, which is convenient for subsequent fault analysis and positioning, and further shortens the test time. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 The figure is a schematic diagram of the SRAM self-test system based on 32-bit MCU of the present invention. DETAILED DESCRIPTION

[0018] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0019] In order to solve the problem that the existing testing process is relatively complex and the testing cost is high, please refer to Figure 1 , this embodiment provides the following technical solution: an SRAM self-test system based on a 32-bit MCU, comprising: The external stimulus module is used to generate a protocol sequence for entering the memory self-test mode, and transmit the sequence to the MBIST module and the protocol analysis module through the input port, and return the result fed back by the protocol analysis module to the external stimulus module through the output port; The protocol parsing module is connected to the external excitation module and the function control module, and is used to receive data transmitted from the external excitation module and parse the data according to the protocol; The function control module is used for receiving the results parsed by the mode enable and protocol parsing modules, and starting the corresponding function module according to the parsing results, transmitting the signal to the MBIST module and activating MBIST, and transmitting the MBIST_enable and SRAM_sel signals to the MBIST module to activate MBIST; MBIST module is used to write specific data to a specific address in SRAM, generate the required address of SRAM on demand, and compare the SRAM output at a given address with the expected pattern provided by the pattern generator.

[0020] The external excitation module contains five input ports, MBIST_CLK, MBIST_RSTn, CLK, RSTn, and DATA_in, and one output port, DATA_out. MBIST_CLK and MBIST_RSTn are sent to the MBIST module, CLK, RSTn, and DATA_in are sent to the protocol parsing module, and DATA_out returns the feedback result of the protocol parsing module to the external excitation module.

[0021] Protocol parsing module, including: Receive CLK, RSTn and DATA_in from the external excitation module and parse them according to the protocol. Each segment of this protocol includes 20 bits of data. After parsing is completed, it is sent on the rising edge of the clock, where bit[19:18] and bit[1:0] are the start and end flags of the protocol respectively. The start flag is that bit19 is pulled high on the rising edge of the protocol clock, and bit18 is pulled low on the second protocol clock rising edge, and then the protocol is sent. During the entire protocol sending stage, the system must be kept in reset state; During the protocol sequence transmission process, the protocol parsing module feeds back a sequence of the received protocol content to the external excitation module. The external excitation module confirms whether the sequence is successfully received by the protocol parsing module. The end mark is that bit1 is pulled low at the rising edge of the protocol clock, and bit0 is pulled high at the second clock rising edge. After the protocol sequence is sent, the protocol parsing module parses the sequence protocol, and the parsing success or failure is fed back to the status indication module. The parsing status includes 4-bit data display; If the protocol is parsed successfully, the protocol parsing module will send the corresponding protocol instructions to the function control module, activate the corresponding function and give feedback. At the same time, the protocol parsing module will pull up the parsing success flag Enter_success and transmit it to the status display module.

[0022] MBIST module, including: FSM, used to generate test vectors, control read and write operations, and analyze response data Test pattern generator, used to write specific data to specific addresses in SRAM and provide data comparison reference for output comparison module; An address generator is used to generate the addresses required by the SRAM as required; A read / write controller that determines when to write a new test pattern or read it back; Output compare module, which compares the SRAM output at a given address with the expected pattern provided by the pattern generator, and detects a fault if there is a mismatch; The status indication module is used to receive the output results of the protocol parsing module, the function control module, and the output comparison module. The status indication module is implemented by multiplexing the MCU-related PADs. In different modes, the multiplexing function of different PADs is enabled to ensure that more functions are achieved using limited PADs.

[0023] The MBIST module also includes 5 input ports and 7 output ports, wherein the 5 output ports are MBIST_CLK, MBIST_RTSn, MBIST_enable, SRAM_SEL, SRAM_out, and the 7 output ports are MBIST_pattern, MBIST_ADDR, MBIST_CLK_O, MBIST_Wen, MBIST_Cen, BIST_DONE, and BIST_OK.

[0024] The test pattern generator generates 6 patterns in total, which are as follows: Pattern1: The written data is 0x00000000; Pattern2: The written data is 0xffffffff; Pattern3: The written data is 0xcccccccc; Pattern4: The written data is 0x0f0f0f0f; Pattern5: The written data is 0x00ff00ff; Pattern6: The written data is 0x55555555.

[0025] The SRAM test method based on 32-bit MCU includes the following steps: S1: Transmit MBIST_CLK and MBIST_RSTn in the external excitation module to the MBIST module, transmit CLK, RSTn and DATA_in in the external excitation module to the protocol analysis module, and use DATA_out in the external excitation module to return the feedback result of the protocol analysis module to the external excitation module. During the entire protocol sending phase, keep the FSM in the reset state; S2: The protocol parsing module parses the received data according to the protocol, and sends the parsing results and configuration data to the function control module; S3: The function control module receives the data sent by the protocol analysis module. If the protocol analysis result is correct, the function control module turns on the MBIST enable signal and selects the SRAM of MBIST; S4: The MBIST module receives the enable signal from the function control module and activates MBIST, so that the FSM in MBIST starts working; S5: FSM controls address generation and sends ascending and descending requests to the address generator. After receiving the request, the address generator generates an address through the shift register and transmits it to the SRAM address input port; S6: The test pattern generator generates a set of test write data and transmits it to the SRAM and output comparison module; S7: MBIST performs read and write operations according to FSM, and outputs the read results to the output comparison module after the FSM read and write are completed; S8: The output comparison module compares the read and write data, and outputs the final result to the status display module according to the current pattern mode, and the status display module displays the MBIST test result; S9: After the test is completed, turn off the power and exit the test mode.

[0026] When the FSM is kept in the reset state, the operation of the address generator, read / write controller, and test pattern generator is controlled by switching the state. The FSM consists of 8 states: IDLE, UP_W0, UP_R0W1, UP_R1W0, DOWN_R0W1, DOWN_R1W0, DOWN_R0, and COMPLETE.

[0027] The corresponding operations of the 8 states of the FSM are transmitted to the address generator and the test pattern generator to generate stimulus. The operations corresponding to the 8 states are as follows: IDLE: Idle state, MBIST is in reset state, and FSM has no action; UP_W0: The address transmitted to SRAM is in ascending order through the shift register, and a write-0 operation is performed; UP_R0W1: The addresses sent to the SRAM are in ascending order through the shift register. For each address, a read operation is performed and the read data is compared with the data written in the previous step. After the read operation, the pattern is written, and then the pattern is inverted and the current read and write operation is performed again; UP_R1W0: The addresses sent to the SRAM are in ascending order through the shift register. For each address, a read operation is performed and the read data is compared with the data written in the previous step. After the read operation, the pattern is written, and then the pattern is inverted and the current read and write operation is performed again; DOWN_R0W1: The addresses sent to the SRAM are in descending order through the shift register. For each address, a read operation is performed and the read data is compared with the data written in the previous step. After the read operation, the pattern is written, and then the pattern is inverted and the current read and write operation is performed again; DOWN_R1W0: The addresses sent to the SRAM are in descending order through the shift register. For each address, a read operation is performed and the read data is compared with the data written in the previous step. After the read operation, the pattern is written, and then the pattern is inverted and the current read and write operation is performed again; DOWN_R0: The addresses sent to the SRAM are in descending order through the shift register. For each address, a read operation is performed and the read data is compared with the data written in the previous step. Then the pattern is inverted and the current read and write operation is performed again. COMPLETE: The FSM process is completed.

[0028] After the FSM reads and writes, the read result is output to the output comparison module in step S7, which specifically includes: After the FSM reads and writes, the pattern is updated until the pattern traversal is completed; After all patterns are traversed, the BIST_DONE signal is output to the status indication module; At the same time, the output comparison module will output the mismatch information collected during the MBIST process to the status display module; If all comparisons are successful, the output comparison module will pull up and output bist_ok. If the comparison fails, bist_ok will not be set.

[0029] Figure 1In the figure, MBIST_CLK represents the clock signal sent to MBIST by external excitation, MBIST_RSTn represents the reset signal sent to MBIST by external excitation, CLK represents the clock signal sent to the protocol analysis module by external excitation, DATA_in represents the data signal sent to the protocol analysis module by external excitation, DATA_out represents the feedback signal sent to the external excitation by the protocol analysis module, RSTn represents the reset signal sent to the protocol analysis module by external excitation, ENTER_DONE represents the signal sent to the status display module by the protocol analysis module indicating successful protocol analysis, STATE0 represents the feedback signal sent to the status display module by the protocol analysis module, STATE1 represents the feedback signal sent by the protocol analysis module to the status display module, STATE2 represents the feedback signal sent by the protocol analysis module to the status display module, STATE3 represents the feedback signal sent by the protocol analysis module to the status display module, MBIST_pattern represents the write data sent by MBIST to SRAM, MBIST_ADDR represents the address sent by MBIST to SRAM, MBIST_CLKO represents the clock sent by MBIST to SRAM, MBIST_Wen represents the read and write signals sent by MBIST to SRAM, and MBIST_Cen represents the chip select signal sent by MBIST to SRAM.

[0030] In summary, the SRAM self-test system and test method based on 32-bit MCU of the present invention, under the premise of ensuring the SRAM test fault coverage, controls the work of MBIST through a series of protocols, and can flexibly select different SRAMs according to the actual needs of the project. Different types of SRAMs have different access speeds, power consumption and capacity characteristics. Selecting a suitable SRAM according to the project needs can maximize the satisfaction of the system's performance requirements, such as high-speed data processing, low-latency response, etc. There are differences in the manufacturing costs and prices of different types of SRAMs. Through flexible selection, a more cost-effective SRAM can be selected, thereby reducing the overall cost of the project while meeting the performance requirements. Selecting a low-power or high-performance SRAM according to the actual application scenario can more effectively utilize energy and improve the energy efficiency ratio of the SRAM self-test circuit, which is particularly important for mobile devices or systems that need to run for a long time. Flexible selection of different SRAMs can meet the needs of the project at different stages or in different application scenarios. The test process is relatively simple, and the same type of projects can be used directly without too many changes, which saves the test cost. At the same time, the compatibility of the present invention is very high. When dealing with multiple SRAMs of different sizes, multiple SRAM tests are configured through protocols, and SRAM tests of different sizes and types can be automatically processed, avoiding the tediousness and error-proneness of manual configuration, thereby significantly improving the test efficiency. The protocol can flexibly adapt to the parameters and characteristics of different SRAMs, such as depth, address bit width, data bit width, etc., making the test scheme more universal and scalable. The test process is accurately controlled by the protocol, which can reduce the errors caused by human intervention and ensure the accuracy and reliability of the test results. During the test, the protocol can record detailed test information and fault data, which is convenient for subsequent fault analysis and location. For the test of multiple SRAMs, the protocol can support parallel test mode, further shorten the test time, and improve the test throughput.

[0031] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0032] While the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that many changes, modifications, substitutions and variations can be made to the embodiments without departing from the principles and spirit of the invention.

Claims

1. The SRAM self-test system based on 32-bit MCU is characterized by: include: The external stimulus module is used to generate a protocol sequence for entering the memory self-test mode, and transmit the sequence to the MBIST module and the protocol analysis module through the input port, and return the result fed back by the protocol analysis module to the external stimulus module through the output port; The protocol parsing module is connected to the external excitation module and the function control module, and is used to receive data transmitted from the external excitation module and parse the data according to the protocol; The function control module is used for receiving the results parsed by the mode enable and protocol parsing modules, and starting the corresponding function module according to the parsing results, transmitting the signal to the MBIST module and activating MBIST, and transmitting the MBIST_enable and SRAM_sel signals to the MBIST module to activate MBIST; MBIST module is used to write specific data to a specific address in SRAM, generate the required address of SRAM on demand, and compare the SRAM output at a given address with the expected pattern provided by the pattern generator.

2. The SRAM self-test system based on a 32-bit MCU according to claim 1, characterized in that: The external excitation module comprises five input ports, MBIST_CLK, MBIST_RSTn, CLK, RSTn and DATA_in, and one output port, DATA_out, wherein MBIST_CLK and MBIST_RSTn are delivered to the MBIST module, CLK, RSTn and DATA_in are delivered to the protocol analysis module, and DATA_out returns the result fed back by the protocol analysis module to the external excitation module.

3. The SRAM self-test system based on a 32-bit MCU according to claim 2, characterized in that: The protocol parsing module specifically includes: Receive CLK, RSTn and DATA_in from the external excitation module and parse them according to the protocol. Each segment of this protocol includes 20 bits of data. After parsing is completed, it is sent on the rising edge of the clock, where bit[19:18] and bit[1:0] are the start and end flags of the protocol respectively. The start flag is bit19 pulled high on the rising edge of the protocol clock, bit18 pulled low on the second protocol clock rising edge, and then the protocol is sent; During the protocol sequence transmission process, the protocol parsing module feeds back a sequence of the received protocol content to the external excitation module. The external excitation module confirms whether the sequence is successfully received by the protocol parsing module. The end mark is that bit1 is pulled low at the rising edge of the protocol clock, and bit0 is pulled high at the second clock rising edge. After the protocol sequence is sent, the protocol parsing module parses the sequence protocol, and the parsing success or failure is fed back to the status indication module. The parsing status includes 4-bit data display; If the protocol is parsed successfully, the protocol parsing module will send the corresponding protocol instructions to the function control module, activate the corresponding function and give feedback. At the same time, the protocol parsing module will pull up the parsing success flag Enter_success and transmit it to the status display module.

4. The SRAM self-test system based on a 32-bit MCU according to claim 1, characterized in that: The MBIST module comprises: FSM, used to generate test vectors, control read and write operations, and analyze response data; Test pattern generator, used to write specific data to specific addresses in SRAM and provide data comparison reference for output comparison module; An address generator is used to generate the addresses required by the SRAM as required; A read / write controller that determines when to write a new test pattern or read it back; Output compare module, which compares the SRAM output at a given address with the expected pattern provided by the pattern generator, and detects a fault if there is a mismatch; The status indication module is used to receive the output results of the protocol parsing module, the function control module, and the output comparison module. The status indication module is implemented by multiplexing the MCU-related PADs. In different modes, the multiplexing function of different PADs is enabled to ensure that more functions are achieved using limited PADs.

5. The SRAM self-test system based on 32-bit MCU according to claim 4, characterized in that: The MBIST module also includes 5 input ports and 7 output ports, wherein the 5 output ports are respectively MBIST_CLK, MBIST_RTSn, MBIST_enable, SRAM_SEL, SRAM_out, and the 7 output ports are respectively MBIST_pattern, MBIST_ADDR, MBIST_CLK_O, MBIST_Wen, MBIST_Cen, BIST_DONE and BIST_OK.

6. The SRAM self-test system based on 32-bit MCU according to claim 5, characterized in that: The test pattern generator generates 6 patterns in total, which are as follows: Pattern1: The written data is 0x00000000; Pattern2: The written data is 0xffffffff; Pattern3: The written data is 0xcccccccc; Pattern4: The written data is 0x0f0f0f0f; Pattern5: The written data is 0x00ff00ff; Pattern6: The written data is 0x55555555.

7. The SRAM test method based on 32-bit MCU is applied in the SRAM self-test system based on 32-bit MCU as claimed in claim 6, characterized in that: The following steps are involved: S1: After sending the sequence to enter the test mode to enable MBIST, the test is started; S2: Parse the received data according to the protocol; S3: If the protocol analysis result is correct, turn on the MBIST enable signal; S4: Receive the enable signal and activate MBIST, so that the FSM in MBIST starts working; S5: Generate addresses according to address generation and ascending and descending order requests; S6: Generate a set of test write data and transmit it to the SRAM and output comparison module; S7: FSM performs read and write operations; S8: After the FSM reads and writes, it compares the read and written data and outputs the final result to the status display module according to the current pattern mode; S9: After the test is completed, turn off the power and exit the test mode.

8. The SRAM testing method based on 32-bit MCU according to claim 7, characterized in that: When the FSM is kept in the reset state, the operation of the address generator, the read / write controller, and the test pattern generator is controlled by switching the state. The FSM consists of 8 states, namely: IDLE, UP_W0, UP_R0W1, UP_R1W0, DOWN_R0W1, DOWN_R1W0, DOWN_R0, and COMPLETE.

9. The SRAM testing method based on 32-bit MCU according to claim 8, characterized in that: The corresponding operations of the 8 states of the FSM are transmitted to the address generator and the test pattern generator to generate stimulus. The operations corresponding to the 8 states are as follows: IDLE: Idle state, MBIST is in reset state, and FSM has no action; UP_W0: The address transmitted to SRAM is in ascending order through the shift register, and a write-0 operation is performed; UP_R0W1: The addresses sent to the SRAM are in ascending order through the shift register. For each address, a read operation is performed and the read data is compared with the data written in the previous step. After the read operation, the pattern is written, and then the pattern is inverted and the current read and write operation is performed again; UP_R1W0: The addresses sent to the SRAM are in ascending order through the shift register. For each address, a read operation is performed and the read data is compared with the data written in the previous step. After the read operation, the pattern is written, and then the pattern is inverted and the current read and write operation is performed again; DOWN_R0W1: The addresses sent to the SRAM are in descending order through the shift register. For each address, a read operation is performed and the read data is compared with the data written in the previous step. After the read operation, the pattern is written, and then the pattern is inverted and the current read and write operation is performed again; DOWN_R1W0: The addresses sent to the SRAM are in descending order through the shift register. For each address, a read operation is performed and the read data is compared with the data written in the previous step. After the read operation, the pattern is written, and then the pattern is inverted and the current read and write operation is performed again; DOWN_R0: The addresses sent to the SRAM are in descending order through the shift register. For each address, a read operation is performed and the read data is compared with the data written in the previous step. Then the pattern is inverted and the current read and write operation is performed again. COMPLETE: The FSM process is completed.

10. The SRAM testing method based on 32-bit MCU according to claim 7, characterized in that: After the FSM reads and writes in step S8, the read and written data are compared, and the final result is output to the status display module according to the pattern mode at this time, which specifically includes: After the FSM reads and writes, the pattern is updated until the pattern traversal is completed; After all patterns are traversed, the BIST_DONE signal is output to the status indication module; At the same time, the output comparison module will output the mismatch information collected during the MBIST process to the status display module; If all comparisons are successful, the output comparison module will pull up and output bist_ok. If the comparison fails, bist_ok will not be set.

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