Method and system for evaluating space charging and discharging effects of volatile interlocking storage circuit

Abstract

The invention discloses an evaluation method and system for the space charge and discharge effect of a volatile interlocking storage circuit, and belongs to the technical field of the space charge and discharge effect, and the method comprises the steps: sequentially obtaining a positive SESD pulse kernel threshold value, a first SESD kernel threshold value and a second SESD kernel threshold value according to the volatile interlocking storage circuit; the positive SESD pulse kernel threshold value, the first SESD kernel threshold value and the second SESD kernel threshold value are substituted into the minimum SESD threshold value expression, and the minimum SESD threshold value is obtained through calculation; and substituting the lowest SESD threshold value into the SESD pulse flip threshold value expression, and calculating to obtain an SESD pulse flip threshold value so as to evaluate the space charge and discharge induced flip effect of the volatile interlocking storage circuit. The invention provides a brand-new and effective method for quickly evaluating the space charge-discharge effect resistance of the volatile interlocking storage circuit, and the method has important value.

Description

Technical Field

[0001] The present invention belongs to the technical field of spatial charge-discharge effect, and in particular relates to a method and system for evaluating the spatial charge-discharge effect of a volatile interlocking storage circuit. Background Art

[0002] Space charge-discharge effect and single particle effect are the main factors that induce data flipping in satellite storage circuits. At present, the test of the flipping effect induced by space charge-discharge in storage circuits is an important process for the development of devices resistant to space charge-discharge effect and their safe and reliable application in space missions.

[0003] However, there are many problems when using high-energy electron accelerators and proton accelerators to evaluate the resistance of aerospace components to space charging and discharging effects. Due to the complexity of the operation and operation of large-scale test equipment, the test cycle and cost are often greatly increased. In some cases, these problems may even hinder the normal development of components and the smooth delivery of space missions, seriously affecting the progress and efficiency of aerospace engineering. Summary of the invention

[0004] To solve the above technical problems, the present invention proposes a method and system for evaluating the space charging and discharging effect of a volatile interlock storage circuit, which uses space electrostatic discharge (SESD) pulses to solve the problems existing in the above-mentioned prior art.

[0005] To achieve the above objectives, in a first aspect, the present invention provides a method for evaluating spatial charge and discharge effects of a volatile interlocking storage circuit, comprising:

[0006] According to the volatile interlock storage circuit, the SESD pulse flip threshold expression corresponding to the lowest voltage that induces the data flip of the core storage circuit is obtained;

[0007] Acquire the paths of SESD-induced circuit data flipping, and obtain the lowest SESD threshold expression for inducing data flipping through each path; wherein each path includes a first path injected from the gate of the MOS transistor and a second path injected from the source of the MOS transistor;

[0008] Obtaining a positive SESD pulse core threshold injected into a storage circuit by a MOS transistor gate causing a storage node to change from a low level to a high level;

[0009] Calculating a first SESD core threshold value for output flipping induced by SESD pulse injected into a transistor of the storage circuit according to the core power supply voltage and noise margin of the storage circuit;

[0010] Calculating a second SESD core threshold for causing a storage data error induced by a SESD pulse injected by a storage circuit transistor according to an offset voltage of a latch structure of the storage circuit;

[0011] Substituting the positive SESD pulse kernel threshold, the first SESD kernel threshold and the second SESD kernel threshold into the minimum SESD threshold expression to calculate the minimum SESD threshold;

[0012] The lowest SESD threshold is substituted into the SESD pulse inversion threshold expression to calculate the SESD pulse inversion threshold so as to evaluate the spatial charge-discharge induced inversion effect of the volatile interlock storage circuit.

[0013] Preferably, the SESD pulse flip threshold expression corresponding to the lowest voltage that induces data flipping in the core storage circuit is obtained, which includes:

[0014] According to the volatile interlock storage circuit, a relationship expression between the SESD pulse voltage acting on the power input terminal of the storage circuit and the voltage related to the core of the storage circuit is determined;

[0015] Through the relational expression, the SESD pulse flip threshold expression corresponding to the lowest voltage that induces data flipping in the core storage circuit is obtained.

[0016] Preferably, the expression for determining the relationship between the SESD pulse voltage acting on the power input terminal of the storage circuit and the voltage related to the core of the storage circuit includes:

[0017] According to the volatile interlock storage circuit, the power supply rejection ratio expression of the low dropout regulator is obtained;

[0018] According to the power supply rejection ratio expression, an expression for the relationship between the SESD pulse voltage acting on the power input terminal of the storage circuit and the core-related voltage of the storage circuit is obtained.

[0019] Preferably, the volatile interlocking storage circuit is a complementary metal oxide semiconductor (CMOS) circuit and a digital logic circuit.

[0020] Preferably, the SESD pulse flip threshold expression is:

[0021] ;

[0022] Where PSRR is the power supply rejection ratio, is the core supply voltage, is the offset voltage, V IH is the upper limit of noise tolerance, V IL is the lower limit of noise tolerance.

[0023] Preferably, a dielectric discharge pulse is coupled to each pin of the volatile interlock storage circuit.

[0024] In a second aspect, the present invention further provides an evaluation system for spatial charge and discharge effects of a volatile interlock storage circuit, comprising:

[0025] The first derivation module is used to obtain a SESD pulse flip threshold expression corresponding to the lowest voltage that induces data flipping in the core storage circuit according to the volatile interlock storage circuit;

[0026] A second derivation module is used to obtain a path of SESD-induced circuit data flipping, and obtain a minimum SESD threshold expression for inducing data flipping through each path; wherein each path includes a first path injected from the gate of the MOS transistor and a second path injected from the source of the MOS transistor;

[0027] The first calculation module is used to obtain a positive SESD pulse core threshold value injected into the storage circuit by the MOS transistor gate causing the storage node to change from a low level to a high level;

[0028] A second calculation module is used to calculate a first SESD core threshold value for inducing output flipping by injecting SESD pulses into the storage circuit transistor according to the core power supply voltage and noise margin of the storage circuit;

[0029] A third calculation module is used to calculate a second SESD core threshold value for causing a storage data error induced by a SESD pulse injected by a storage circuit transistor according to an offset voltage of a latch structure of the storage circuit;

[0030] A first substitution module is used to substitute the positive SESD pulse kernel threshold, the first SESD kernel threshold and the second SESD kernel threshold into the minimum SESD threshold expression to calculate the minimum SESD threshold;

[0031] The second substitution module is used to substitute the minimum SESD threshold into the SESD pulse flip threshold expression to calculate the SESD pulse flip threshold so as to evaluate the spatial charge-discharge induced flip effect of the volatile interlock storage circuit.

[0032] In a third aspect, the present invention further discloses a computer-readable storage medium having a computer program stored thereon, which implements the steps of the method described in the first aspect when executed by a processor.

[0033] In a fourth aspect, the present invention further discloses a computer program product, comprising a computer program, which implements the steps of the method described in the first aspect when executed by a processor.

[0034] Compared with the prior art, the present invention has the following advantages and technical effects:

[0035] The present invention provides an evaluation method for spatial charge-discharge effect of a volatile interlocking storage circuit, comprising: firstly, according to the volatile interlocking storage circuit, obtaining a SESD pulse flip threshold expression corresponding to the lowest voltage that induces data flipping of a core storage circuit; secondly, obtaining a path for SESD to induce circuit data flipping, and obtaining a lowest SESD threshold expression for inducing data flipping through each path; wherein each path includes a first path injected from a MOS transistor gate and a second path injected from a MOS transistor source; then, obtaining a positive SESD pulse core threshold value that is injected from the MOS transistor gate into the storage circuit and causes a storage node to change from a low level to a high level; further, according to the core power supply voltage of the storage circuit, obtaining a positive SESD pulse core threshold value that is injected from the MOS transistor gate into the storage circuit and causing a storage node to change from a low level to a high level; The first SESD core threshold induced by the SESD pulse injected into the storage circuit transistor to induce output reversal is calculated based on the voltage and noise tolerance; again, the second SESD core threshold induced by the SESD pulse injected into the storage circuit transistor to induce storage data error is calculated according to the offset voltage of the latch structure of the storage circuit; finally, the positive SESD pulse core threshold, the first SESD core threshold and the second SESD core threshold are substituted into the minimum SESD threshold expression to calculate the minimum SESD threshold; the minimum SESD threshold is then substituted into the SESD pulse reversal threshold expression to calculate the SESD pulse reversal threshold, so as to evaluate the spatial charge and discharge induced reversal effect of the volatile interlock storage circuit.

[0036] The present invention proposes a calculation method for effectively calculating the discharge pulse threshold based on the mechanism that spatial charge-discharge effect induces data flipping of volatile storage circuits. The method quickly calculates the circuit pin discharge pulse voltage threshold that can induce storage data errors by inputting electrical parameters of the circuit under test.

[0037] Compared with the method of measuring thresholds through discharge tests using large particle accelerators, the present invention has great potential for quickly and economically evaluating the resistance of components to space charge and discharge effects. It can provide accurate, efficient and inexpensive space charge and discharge effect evaluation technology for aerospace engineering, promote the development of domestic aerospace components, and ensure the long life and highly reliable operation of spacecraft. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The drawings constituting a part of the present application are used to provide a further understanding of the present application. The illustrative embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0039] Figure 1 A schematic diagram of a volatile interlock storage circuit according to an embodiment of the present invention;

[0040] Figure 2 Schematic diagram of a space environment effect test of a volatile interlock storage circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0041] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0042] It should be noted that the steps shown in the flowcharts of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and that, although a logical order is shown in the flowcharts, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0043] First, the technical terms involved in the following embodiments are explained.

[0044] 1. Volatile interlocked storage circuit is a storage circuit based on volatile memory (such as SRAM), which is mainly used to keep data unchanged when the device is powered on, and the data is lost after power failure. SRAM (Static Random Access Memory) is a typical volatile memory, whose storage unit is built by transistors. Common structures include 6-transistor (6T) and 8-transistor (8T) structures. SRAM stores data by forming two inverters in an interlocked structure, keeping the stored data unchanged when the device is powered on, and losing the stored data after power failure.

[0045] Working principle of SRAM: The basic storage unit of SRAM consists of two inverters, forming an interlocking structure. When the output of one of the inverters is high, the output of the other inverter is low, and vice versa. This interlocking structure ensures that the data remains stable when the device is powered. When the device is powered off, the data will be lost.

[0046] Features of SRAM:

[0047] ‌Fast reading and writing speed‌: Since the reading and writing operations of SRAM mainly involve the switching operations of transistors, the reading and writing speeds are very fast.

[0048] ‌No limit on the number of read and write times‌: The read and write operations of SRAM will not cause data corruption, so there is no limit on the number of read and write times.

[0049] ‌Mature process‌: The manufacturing process of SRAM is relatively mature, and the device consistency and stability are good.

[0050] ‌High cost and low density‌: Since SRAM requires power to retain data, it consumes high power and has a low storage density under a multi-transistor cell structure, resulting in high costs.

[0051] Application scenarios: SRAM is often used for CPU cache, especially in high-speed cache. Due to its fast read and write speed, mature process, good device consistency and stability, it is suitable for scenarios that require high-speed data access.

[0052] 2. A low dropout regulator (LDO) is a linear DC regulator that is mainly used to provide a stable DC voltage supply. Compared with a general linear regulator, a low dropout regulator can operate at a smaller input and output voltage difference, and its dropout voltage is usually within 200mV.

[0053] Working principle: The working principle of the low-dropout regulator is based on negative feedback regulation. Its internal structure mainly includes a voltage-dividing sampling circuit, a reference voltage, an error amplifier circuit, and a transistor adjustment circuit. The voltage-dividing sampling circuit collects the output voltage through resistors R1 and R2; the reference voltage is usually generated by a bandgap (bandgap voltage reference) to reduce the impact of temperature changes; the error amplifier circuit compares the collected voltage with the desired output voltage and amplifies the comparison result; the transistor adjustment circuit outputs the amplified signal to the control electrode of the transistor, thereby controlling the on-voltage of the transistor.

[0054] Main features and applications:

[0055] ‌Low Noise‌: Low dropout regulators contain a small voltage drop between input and output, allowing them to operate normally even when the output voltage is very close to the input voltage, unlike linear regulators which require a huge voltage drop to operate properly, thus having lower noise.

[0056] ‌High Efficiency‌: Due to their miniature system-on-chip design with extremely low self-consumption, low-dropout regulators excel in current main channel control and are suitable for applications requiring high-efficiency power management.

[0057] ‌Protection function‌: Usually has over-current protection, over-temperature protection and other functions to ensure stable operation of the equipment.

[0058] ‌Widely used‌: Commonly used in mobile and IoT devices, especially in lithium battery applications. It is the best choice for analog circuits that require high precision and low noise.

[0059] Embodiment 1

[0060] This embodiment provides a method for evaluating the spatial charge and discharge effect of a volatile interlock storage circuit, including:

[0061] S1. According to the volatile interlock storage circuit, the SESD pulse flip threshold expression corresponding to the lowest voltage that induces the data flip of the core storage circuit is obtained;

[0062] Furthermore, the SESD pulse flip threshold expression corresponding to the lowest voltage that induces data flipping in the core storage circuit includes:

[0063] According to the volatile interlock storage circuit, a relationship expression between the SESD pulse voltage acting on the power input terminal of the storage circuit and the voltage related to the core of the storage circuit is determined;

[0064] Through the relational expression, the SESD pulse flip threshold expression corresponding to the lowest voltage that induces data flipping in the core storage circuit is obtained.

[0065] Furthermore, the relationship expression between the SESD pulse voltage acting on the power input terminal of the storage circuit and the voltage related to the storage circuit core includes:

[0066] According to the volatile interlock storage circuit, the power supply rejection ratio expression of the low dropout regulator is obtained;

[0067] According to the power supply rejection ratio expression, an expression for the relationship between the SESD pulse voltage acting on the power input terminal of the storage circuit and the core-related voltage of the storage circuit is obtained.

[0068] Furthermore, the volatile interlocking storage circuit is a complementary metal oxide semiconductor (CMOS) circuit and a digital logic circuit.

[0069] Furthermore, a dielectric discharge pulse is coupled to each pin of the volatile interlock storage circuit.

[0070] like Figure 1 As shown, the volatile interlock storage circuit, the storage unit of the circuit is composed of two cross-coupled inverters and conduction control NMOS transistors, where P11 and P12 are PMOS, and N11 N12 N13 N14 are NMOS. When the six-tube storage unit stores data '1', P11 and N12 are turned on, and N11 P12 P13 and P14 are turned off; when the six-tube storage unit stores data '0', P12 and N11 are turned on, and N12 P11 P13 and P14 are turned off.

[0071] Specifically, according to the definition of the power supply rejection ratio of the low-dropout regulator (LDO) of the volatile interlock storage circuit: , acting on the SESD pulse voltage of the LDO power supply input The pulse voltage at the LDO output The relationship is:

[0072] (1)

[0073] like The lowest voltage that can cause data flip in the core memory circuit , then the SESD pulse flip threshold for:

[0074] (2)

[0075] In the formula, is the SESD pulse flip threshold of the core circuit, is the core supply voltage, is the offset voltage, VIH is the noise tolerance upper limit and VIL is the noise tolerance lower limit.

[0076] S2, obtaining the paths of SESD-induced circuit data flipping, and obtaining the lowest SESD threshold expression for inducing data flipping through each path; wherein each path includes a first path injected from the gate of the MOS transistor and a second path injected from the source of the MOS transistor;

[0077] Specifically, for the discharge pulse generated by the spatial charge and discharge effect, there are two paths for the SESD discharge pulse to induce circuit data flipping, including two paths injected from the input gate and input source of the CMOS transistor, and the core SESD threshold is the lowest SESD threshold that induces data flipping through the two paths, so The expression is as follows:

[0078] (3)

[0079] in is the core threshold of the positive SESD pulse injected into the storage circuit by the MOS transistor gate, causing the storage node to change from a low level to a high level. is the core threshold of the negative SESD pulse injected into the storage circuit by the MOS transistor gate, causing the storage node to change from a high level to a low level. is the SESD core threshold injected from the source of the MOS transistor.

[0080] S3, obtaining a positive SESD pulse core threshold value injected into the storage circuit by the gate of the MOS transistor, causing the storage node to change from a low level to a high level;

[0081] Specifically, the SESD core threshold induced by the SESD pulse injected into the gate of the CMOS transistor to induce the output flip is calculated based on the core power supply voltage and noise margin of the inverter formed by the CMOS circuit. .

[0082] If the storage circuit node is at a low level '0', the space charge and discharge pulse acts on the gate voltage V at the input end of the CMOS circuit. gate =0 V, so that V gate+ V SESD > V IH , which causes the CMOS node voltage to flip from a low level to a high level. From this, it can be concluded that the threshold voltage of the low level flip induced by the space charge and discharge pulse injection into the gate for:

[0083] (4)

[0084] S4, calculating a first SESD core threshold value for inducing output flipping by SESD pulse injected into a transistor of the storage circuit according to the core power supply voltage and noise margin of the storage circuit;

[0085] Specifically, if the storage circuit node is at a high level '1', when the charge and discharge pulse amplitude V SESD The gate voltage V acting on the input terminal of the CMOS circuit gate =V DD After that, V gate + V SESD < V IL , which causes the storage node voltage to flip from a high level to a low level. From this, we can derive the threshold voltage of the data '0' flip induced by the space charge and discharge pulse injection into the gate for:

[0086] (5)

[0087] S5, calculating a second SESD core threshold value for causing a storage data error induced by a SESD pulse injected by a storage circuit transistor according to an offset voltage of a latch structure of the storage circuit;

[0088] Specifically, the SESD core threshold value of the storage data error induced by the SESD pulse injected into the source of the CMOS transistor is calculated according to the offset voltage Voff of the latch structure of the storage circuit constituted by the CMOS circuit. .

[0089] When a negative SESD pulse is injected into the storage circuit latch structure through the CMOS transistor source (circuit power input terminal VDD), the output voltage at both ends of the circuit will change. When the output voltage difference at both ends is less than the offset voltage Voff, the stored data will be wrong. for:

[0090] (6)

[0091] S6, substituting the positive SESD pulse kernel threshold, the first SESD kernel threshold and the second SESD kernel threshold into the minimum SESD threshold expression to calculate the minimum SESD threshold;

[0092] Specifically, the minimum SESD threshold expression can be expressed as:

[0093] (7)

[0094] S7. Substituting the minimum SESD threshold into the SESD pulse inversion threshold expression, and calculating the SESD pulse inversion threshold to evaluate the spatial charge-discharge induced inversion effect of the volatile interlocking storage circuit.

[0095] Specifically, the final flip threshold of the spatial charge-discharge effect of the volatile interlock storage circuit is:

[0096] (8)

[0097] Where PSRR is the power supply rejection ratio, is the core supply voltage, is the offset voltage, V IH is the upper limit of noise tolerance, V IL is the lower limit of noise tolerance.

[0098] like Figure 2 As shown in the figure, the space environment effect test of the volatile interlock storage circuit is carried out. During the test, an electrostatic generator is used to perform contact discharge on a grounded metal plate on the desktop to simulate the space charge and discharge environment. The circuit under test is placed on an insulating material about 200 mm away from the electrostatic generator. When the ESD generator generates excitation, the discharge transient is coupled to the pins on the device through the electromagnetic field and generates SESD transients on the pins.

[0099] After testing the basic parameters of the tested storage circuit, the noise margin and core voltage in the model are based on the chip data sheet data, and the offset voltage is less than 0.1 V. The results comparison table of the specific embodiment is shown in Table 1.

[0100] Table 1

[0101]

[0102] It can be seen from Table 1 that the charge-discharge effect flip threshold obtained by the evaluation method for the spatial charge-discharge effect of the volatile interlock storage circuit proposed in the present invention is basically consistent with the SESD threshold measured at the pins of the three SRAM devices irradiated by the electrostatic generator, especially for the state of storing data '1', the error between the two is less than 20%. Considering the uncertainty of the test, the data is completely consistent.

[0103] The method for evaluating the spatial charge-discharge effect of a volatile interlocked storage circuit mentioned in the present invention has the advantages of obtaining the spatial charge-discharge effect flip threshold of a volatile interlocked storage circuit through experimental measurement and the methods reported in existing literature and patents, mainly in that the ability of the storage circuit to resist the charge-discharge effect can be quickly evaluated through the basic parameters of the measured circuit and its spatial charge-discharge effect flip threshold can be calculated. The promotion of this evaluation method has important value. The spatial charge-discharge effect flip threshold obtained by this calculation method tends to be consistent with the experimental measurement threshold.

[0104] To sum up, the method for evaluating the spatial charge and discharge effect of a volatile interlock storage circuit involved in the present invention can realize the calculation of the data flip threshold of a volatile interlock storage circuit induced by the spatial charge and discharge effect generating an electric pulse on the device pin, under the premise of accurately determining various calculation parameters.

[0105] Embodiment 2

[0106] Based on the same inventive concept, this embodiment also provides an evaluation system for spatial charge and discharge effects of a volatile interlock storage circuit, including:

[0107] The first derivation module is used to obtain a SESD pulse flip threshold expression corresponding to the lowest voltage that induces data flipping in the core storage circuit according to the volatile interlock storage circuit;

[0108] A second derivation module is used to obtain a path of SESD-induced circuit data flipping, and obtain a minimum SESD threshold expression for inducing data flipping through each path; wherein each path includes a first path injected from the gate of the MOS transistor and a second path injected from the source of the MOS transistor;

[0109] The first calculation module is used to obtain a positive SESD pulse core threshold value injected into the storage circuit by the MOS transistor gate causing the storage node to change from a low level to a high level;

[0110] A second calculation module is used to calculate a first SESD core threshold value for inducing output flipping by injecting SESD pulses into the storage circuit transistor according to the core power supply voltage and noise margin of the storage circuit;

[0111] A third calculation module is used to calculate a second SESD core threshold value for causing a storage data error induced by a SESD pulse injected by a storage circuit transistor according to an offset voltage of a latch structure of the storage circuit;

[0112] A first substitution module is used to substitute the positive SESD pulse kernel threshold, the first SESD kernel threshold and the second SESD kernel threshold into the minimum SESD threshold expression to calculate the minimum SESD threshold;

[0113] The second substitution module is used to substitute the minimum SESD threshold into the SESD pulse flip threshold expression to calculate the SESD pulse flip threshold so as to evaluate the spatial charge-discharge induced flip effect of the volatile interlock storage circuit.

[0114] The system for evaluating the spatial charge-discharge effect of a volatile interlocking storage circuit provided by this embodiment has all the advantages of the method for evaluating the spatial charge-discharge effect of a volatile interlocking storage circuit provided by the first embodiment.

[0115] Embodiment 3

[0116] This embodiment further discloses a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of the method described in the first embodiment are implemented.

[0117] Embodiment 4

[0118] This embodiment also discloses a computer program product, including a computer program, which implements the steps of the method described in the first embodiment when executed by a processor.

[0119] The above are only preferred specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A method for evaluating the spatial charge-discharge effect of a volatile interlocking memory circuit, characterized in that: The following steps are involved: According to the volatile interlock storage circuit, the SESD pulse flip threshold expression corresponding to the lowest voltage that induces the data flip of the core storage circuit is obtained; Obtain the paths of SESD-induced circuit data flipping, and obtain the lowest SESD threshold expression for inducing data flipping through each path; wherein each of the paths comprises a first path injected from a gate of a MOS transistor and a second path injected from a source of the MOS transistor; Obtaining a positive SESD pulse core threshold injected into a storage circuit by a MOS transistor gate causing a storage node to change from a low level to a high level; Calculating a first SESD core threshold value for output flipping induced by SESD pulse injected into a transistor of the storage circuit according to the core power supply voltage and noise margin of the storage circuit; Calculating a second SESD core threshold for causing a storage data error induced by a SESD pulse injected by a storage circuit transistor according to an offset voltage of a latch structure of the storage circuit; Substituting the positive SESD pulse kernel threshold, the first SESD kernel threshold and the second SESD kernel threshold into the minimum SESD threshold expression to calculate the minimum SESD threshold; The lowest SESD threshold is substituted into the SESD pulse inversion threshold expression to calculate the SESD pulse inversion threshold so as to evaluate the spatial charge-discharge induced inversion effect of the volatile interlock storage circuit.

2. The method according to claim 1, characterized in that: The SESD pulse flip threshold expression corresponding to the lowest voltage that induces data flipping in the core storage circuit includes: According to the volatile interlock storage circuit, a relationship expression between the SESD pulse voltage acting on the power input terminal of the storage circuit and the voltage related to the core of the storage circuit is determined; Through the relational expression, the SESD pulse flip threshold expression corresponding to the lowest voltage that induces data flipping in the core storage circuit is obtained.

3. The method according to claim 2, characterized in that The expressions for determining the relationship between the SESD pulse voltage acting on the power input terminal of the storage circuit and the voltage related to the core of the storage circuit include: According to the volatile interlock storage circuit, the power supply rejection ratio expression of the low dropout regulator is obtained; According to the power supply rejection ratio expression, an expression for the relationship between the SESD pulse voltage acting on the power input terminal of the storage circuit and the core-related voltage of the storage circuit is obtained.

4. The method according to claim 1, characterized in that The volatile interlocking storage circuit is a complementary metal oxide semiconductor (CMOS) circuit and a digital logic circuit.

5. The method according to claim 1, characterized in that The SESD pulse flip threshold expression is: ； Where PSRR is the power supply rejection ratio, is the core supply voltage, is the offset voltage, V IH is the upper limit of noise tolerance, V IL is the lower limit of noise tolerance.

6. The method according to claim 1, characterized in that A dielectric discharge pulse is coupled to each pin of the volatile interlock storage circuit.

7. A system for evaluating spatial charge and discharge effects of a volatile interlocking storage circuit, characterized in that: include: The first derivation module is used to obtain a SESD pulse flip threshold expression corresponding to the lowest voltage that induces data flipping in the core storage circuit according to the volatile interlock storage circuit; The second derivation module is used to obtain the paths of SESD-induced circuit data flipping and obtain the lowest SESD threshold expression for inducing data flipping through each path; wherein each of the paths comprises a first path injected from a gate of a MOS transistor and a second path injected from a source of the MOS transistor; The first calculation module is used to obtain a positive SESD pulse core threshold value injected into the storage circuit by the MOS transistor gate causing the storage node to change from a low level to a high level; A second calculation module is used to calculate a first SESD core threshold value for inducing output flipping by injecting SESD pulses into the storage circuit transistor according to the core power supply voltage and noise margin of the storage circuit; A third calculation module is used to calculate a second SESD core threshold value for causing a storage data error induced by a SESD pulse injected by a storage circuit transistor according to an offset voltage of a latch structure of the storage circuit; A first substitution module is used to substitute the positive SESD pulse kernel threshold, the first SESD kernel threshold and the second SESD kernel threshold into the minimum SESD threshold expression to calculate the minimum SESD threshold; The second substitution module is used to substitute the minimum SESD threshold into the SESD pulse flip threshold expression to calculate the SESD pulse flip threshold so as to evaluate the spatial charge-discharge induced flip effect of the volatile interlock storage circuit.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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