EMCP chip aging test device and test method thereof

Abstract

The invention provides an eMCP chip aging test device and a test method thereof.An embedded system host in communication connection with an eMMC part and an LPDDR part is arranged, firstly, a target test scene is determined, and target test performance parameters are determined according to the target test scene; the embedded system host performs test operation on the LPDDR part according to the target test performance parameter, and stores a first test result of the LPDDR part to a database or an external memory; the eMMC controller performs test operation on the Nand Flash according to the target test performance parameter to obtain a second test result of the eMMC part; in the test operation process, the embedded system host sends the first test result to the eMMC controller, the eMMC controller integrates the first test result and the second test result, and the integrated test result is written into the Nand Flash. According to the invention, the test result of the eMCP product can be visually reflected, the tracking of the subsequent product test result is facilitated, the Bin cost can be reduced, and the influence of the aging test on the service life of the product is reduced.

Description

Technical Field

[0001] The present application relates to the field of chip testing technology, and in particular to an eMCP chip aging testing device and a testing method thereof. Background Art

[0002] In the related technology, eMCP is a memory packaged together with eMMC and LPDDR. Although the two products are packaged together, they work independently of each other, so during the mass production test, eMMC and LPDDR are also tested independently of each other. eMMC is a non-volatile storage product, so during the test process, the test results can be stored in Nand itself, and will not be lost after power failure; however, the data stored in the LPDDR product itself will be lost after power failure, so it cannot save the product test results by itself.

[0003] After packaging eMMC and LPDDR together, the two independent products should be considered as the same product. If any one of the products fails the test, the eMCP test should be considered as a failure. However, because LPDDR and eMMC are tested independently, the results are also independent. Therefore, eMMC and LPDDR need to be tested separately during testing, and the test results of eMMC and LPDDR need to be analyzed for binning. This method cannot directly reflect the test results of eMCP products, and separate testing will increase the test cost, and separate aging tests will also affect the life of the product. Summary of the invention

[0004] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes an eMCP chip aging test device and a test method thereof, which aims to intuitively reflect the test results of eMCP products, facilitate the tracking of subsequent product test results, and also reduce the binning cost and reduce the impact of aging tests on product life.

[0005] In a first aspect, an embodiment of the present application provides a test method for an eMCP chip aging test device, wherein the eMCP chip aging test device includes an embedded system host and an eMCP chip, wherein the eMCP chip includes an eMMC part and an LPDDR part, the eMMC part includes an eMMC controller and a Nand Flash, and the embedded system host is respectively connected to the eMMC part and the LPDDR part for communication; the method includes: Determine a target test scenario, and determine a target test performance parameter according to the target test scenario; The embedded system host performs a test operation on the LPDDR part according to the target test performance parameter, and stores a first test result of the LPDDR part in a database or an external memory; The eMMC controller performs a test operation on the Nand Flash according to the target test performance parameter to obtain a second test result of the eMMC part; During the test operation, the embedded system host sends the first test result to the eMMC controller, and the eMMC controller integrates the first test result and the second test result, and writes the integrated test result to the Nand Flash.

[0006] According to some embodiments of the present application, determining a target test performance parameter according to the target test scenario includes: Determine the read / write speed requirements and random read / write performance requirements according to the scenario type of the target test scenario; Determine the target test performance parameter according to the read / write speed requirement and the random read / write performance requirement; The scenario type of the target test scenario includes at least one of the following: a mobile device test scenario type, an automotive electronics test scenario type, and an industrial equipment test scenario type.

[0007] According to some embodiments of the present application, when multiple test operations are performed on the LPDDR part and the eMMC part, the method further includes: In the case of the same scenario type, for the LPDDR part, compare the current first test result with the previous first test result, obtain a first difference increment result between the current first test result and the previous first test result, and store the first difference increment result in a database or an external memory; In the case of the same scenario type, for the eMMC part, the current second test result and the previous second test result are compared to obtain a second difference increment result between the current second test result and the previous second test result.

[0008] According to some embodiments of the present application, the eMMC controller integrates the first test result and the second test result, including: The eMMC controller obtains the first difference increment result and the second difference increment result under the scene type of the same category; Integrate the first incremental difference result and the second incremental difference result to obtain a combined incremental difference result; The merged difference increment result is written into the Nand Flash to update the integrated test result stored in the Nand Flash.

[0009] According to some embodiments of the present application, the eMMC part also includes Sram, and the eMMC controller is communicatively connected with the Sram; the embedded system host sends the first test result to the eMMC controller, and the eMMC controller integrates the first test result and the second test result, and writes the integrated test result to the Nand Flash, including: The embedded system host accesses the eMMC part through the EMDC interface, and writes the first test result into the Sram; The eMMC controller integrates the first test result and the second test result written into the Sram, and writes the integrated test result into the Nand Flash.

[0010] According to some embodiments of the present application, when there are multiple target test scenarios, the method further includes: In the current target test scenario, simultaneously starting the test operation on the LPDDR part and the eMMC part; When the LPDDR part completes the test operation under the current target test scenario but the eMMC part does not complete the test operation under the current target test scenario, the eMMC part is kept to continue to execute the test operation under the current target test scenario, and at the same time, the embedded system host writes the first test result to the Sram of the eMMC part, and starts the test operation of the LPDDR part in the next target test scenario.

[0011] According to some embodiments of the present application, after starting the test operation of the LPDDR part in the next target test scenario, the method further includes: When the eMMC part completes the test operation under the current target test scenario, the eMMC controller integrates the first test result and the second test result written to the Sram, and the embedded system host keeps performing the test operation on the LPDDR part under the next target test scenario.

[0012] According to some embodiments of the present application, after the embedded system host sends the first test result to the eMMC controller, the method further includes: When the eMMC controller successfully receives the first test result sent by the embedded system host within a preset time, the eMMC controller feeds back a result reception success instruction to the embedded system host; When the eMMC controller does not receive the first test result sent by the embedded system host within a preset time, the eMMC controller feeds back a result reception failure instruction to the embedded system host; In addition, after the eMMC controller integrates the first test result and the second test result and writes the integrated test result into the Nand Flash, the method further includes: The eMMC controller generates a result merging completion instruction, and sends the result merging completion instruction to the embedded system host.

[0013] In a second aspect, an embodiment of the present application provides an eMCP chip aging test device, based on the test method of the eMCP chip aging test device of the first aspect above; the eMCP chip aging test device comprises: The eMCP chip includes an eMMC part and an LPDDR part, wherein the eMMC part includes an eMMC controller, NandFlash and Sram, and the eMMC controller is respectively connected to the NandFlash and the Sram in communication; The embedded system host is communicatively connected with the eMMC part and the LPDDR part respectively.

[0014] According to some embodiments of the present application, the embedded system host is connected to the eMMC part through an EMDC interface, and the embedded system host is connected to the LPDDR part through a DDR interface or an SDRAM interface.

[0015] In a third aspect, an embodiment of the present application provides a control device, comprising: a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor executes the test method of the eMCP chip aging test device of the first aspect mentioned above when running the computer program.

[0016] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are used to execute the test method of the eMCP chip aging test device as described in the first aspect above.

[0017] In a fifth aspect, an embodiment of the present application provides a computer program product, including a computer program or computer instructions, wherein the computer program or the computer instructions are stored in a computer-readable storage medium, and a processor of a computer device reads the computer program or the computer instructions from the computer-readable storage medium, and the processor executes the computer program or the computer instructions, so that the computer device performs the test method of the eMCP chip aging test device as described in the first aspect above.

[0018] According to the technical solution of the embodiment of the present application, at least the following beneficial effects are achieved: the embodiment of the present application sets up an embedded system host, which is respectively connected to the eMMC part and the LPDDR part for communication. First, the embodiment of the present application determines the target test scenario and determines the target test performance parameters according to the target test scenario; then, the embedded system host performs a test operation on the LPDDR part according to the target test performance parameters, and stores the first test result of the LPDDR part in a database or an external memory; then, the eMMC controller performs a test operation on the Nand Flash according to the target test performance parameters to obtain a second test result of the eMMC part; wherein, during the test operation, the embedded system host sends the first test result to the eMMC controller, the eMMC controller integrates the first test result and the second test result, and writes the integrated test result to the Nand Flash. Therefore, the embodiment of the present application can test the eMMC part and the LPDDR part of the eMCP at the same time and in the same environment, which can solve the cost and product life issues; in addition, the test results of the LPDDR part can be integrated into the test results of the eMMC part and saved to Nand Flash, so that the test results of the entire product can be bound to the product. As long as the product is not damaged, the test results will be saved, which is conducive to the tracking of subsequent product test results and reduces the Binning cost.

[0019] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings are used to provide further understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0021] Figure 1 This is a schematic diagram of the hardware architecture of an eMCP chip aging test device provided by an embodiment of the present application; Figure 2 It is a flow chart of a testing method of an eMCP chip aging testing device provided by an embodiment of the present application; Figure 3 yes Figure 2 Flow chart of sub-steps of step S210; Figure 4 is a flow chart of obtaining difference increment results in the case of multiple test operations provided by an embodiment of the present application; Figure 5is a flow chart of integrating difference increment results in the case of multiple test operations provided by an embodiment of the present application; Figure 6 yes Figure 2 Flow chart of sub-steps of step S240; Figure 7 This is a flowchart provided by an embodiment of the present application in the case where the LPDDR part ends the test operation in the current target test scenario, but the eMMC part does not end the test operation in the current target test scenario; Figure 8 This is a flowchart provided by an embodiment of the present application after the eMMC part ends the test operation in the current target test scenario, but the eMMC part does not end the test operation in the current target test scenario; Fig. 9 This is a data flow diagram of a test method of an eMCP chip aging test device provided by an embodiment of the present application; Fig.10 It is a schematic diagram of a control device for executing a test method of an eMCP chip aging test device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0022] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0023] In the description of the present application, it should be understood that descriptions involving orientation, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0024] In the description of this application, "several" means one or more, "more" means more than two, "greater than", "less than", "exceed", etc. are understood to exclude the number itself, and "above", "below", "within", etc. are understood to include the number itself. If there is a description of "first" or "second", it is only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0025] In the description of this application, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in this application based on the specific content of the technical solution.

[0026] In some cases, eMCP (Embedded Multi-Chip Package) is a memory packaged together by eMMC (Embedded Multi Media Card) and LPDDR (Low Power Double Data Rate SDRAM). Although the two products are packaged together, they work independently of each other, so during the mass production test process, eMMC and LPDDR are also tested independently of each other. eMMC is a non-volatile storage product, so during the test process, the test results can be stored in Nand itself, and will not be lost after power failure; however, the data stored in the LPDDR product itself will be lost after power failure, so it cannot save the product test results itself.

[0027] After packaging eMMC and LPDDR together, the two independent products should be considered as the same product. If any one of the products fails the test, the eMCP test should be considered as a failure. However, because LPDDR and eMMC are tested independently, the results are also independent. Therefore, eMMC and LPDDR need to be tested separately during testing, and the test results of eMMC and LPDDR need to be analyzed for binning. This method cannot directly reflect the test results of eMCP products, and separate testing will increase the test cost, and separate aging tests will also affect the life of the product.

[0028] Based on the above situation, the embodiment of the present application proposes an eMCP chip aging test device and a test method thereof, which aims to intuitively reflect the test results of the eMCP product, facilitate the tracking of subsequent product test results, and also reduce the binning cost and reduce the impact of aging testing on product life.

[0029] The following is a further description of various embodiments of the eMCP chip aging test device of the present application in conjunction with the accompanying drawings.

[0030] like Figure 1 As shown, Figure 1 It is a schematic diagram of the hardware architecture of an eMCP chip aging test device provided in one embodiment of the present application.

[0031] In one embodiment, the eMCP chip 200 aging test device includes but is not limited to an embedded system host 100 and an eMCP chip 200, wherein the eMCP chip 200 includes an eMMC part 220 and an LPDDR part 210, the eMMC part 220 includes but is not limited to an eMMC controller and Nand Flash, and the eMMC controller is communicatively connected to the Nand Flash; in addition, the embedded system host 100 is communicatively connected to the eMMC part 220 and the LPDDR part 210 respectively.

[0032] In one embodiment, the eMMC part 220 also includes but is not limited to Sram, and the eMMC controller is also in communication connection with Sram.

[0033] In one embodiment, the eMCP chip 200 aging test device further includes but is not limited to an external memory, and the embedded system host 100 is also communicatively connected to the external memory, wherein the external memory can be used to store data, such as test results.

[0034] In one embodiment, the embedded system host 100 may be provided with a database for storing data, such as test results.

[0035] In one embodiment, the embedded system host 100 is connected to the eMMC part 220 via an EMDC interface, and the embedded system host 100 is connected to the LPDDR part 210 via a DDR interface or an SDRAM interface.

[0036] It should be noted that eMMC is a standard specification of embedded memory, which packages high-density NAND Flash and eMMC controller in a BGA chip and has the following characteristics: Integration: eMMC integrates a Flash controller, which is responsible for memory management, including erase and write leveling, bad block management, ECC checking and other functions.

[0037] Simplified design: eMMC uses a unified MMC standard interface, so users do not need to worry about changes in internal Flash wafer process and technology.

[0038] Performance advantage: eMMC improves the reading and writing speed by using technologies such as Cache and Memory Array.

[0039] Save space: eMMC is packaged into a single chip, saving more space on the motherboard.

[0040] In addition, it should be noted that LPDDR is a low-power version of double data rate synchronous dynamic random access memory, and its features include: Low power design: LPDDR has strict requirements on power consumption and performance.

[0041] Multi-bank: LPDDR memory modules contain multiple banks, and data can be quickly transferred between banks.

[0042] Double Data Rate: Similar to DDR, LPDDR can transmit data twice in each clock cycle, increasing the data transfer rate.

[0043] Based on the hardware structure of the eMCP chip aging test device of each of the above-mentioned embodiments, various embodiments of the test method of the eMCP chip aging test device of the present application are respectively proposed below.

[0044] like Figure 2 As shown, Figure 2 It is a flow chart of a testing method of an eMCP chip aging testing device provided by an embodiment of the present application; the testing method of the eMCP chip aging testing device may include but is not limited to step S210, step S220, step S230 and step S240.

[0045] Step S210: determining a target test scenario, and determining a target test performance parameter according to the target test scenario; Step S220: the embedded system host performs a test operation on the LPDDR part according to the target test performance parameter, and stores a first test result of the LPDDR part in a database or an external memory; Step S230: the eMMC controller performs a test operation on the Nand Flash according to the target test performance parameter to obtain a second test result of the eMMC part; Step S240: During the test operation, the embedded system host sends the first test result to the eMMC controller, the eMMC controller integrates the first test result and the second test result, and writes the integrated test result to NandFlash.

[0046] In one embodiment, first, the embodiment of the present application determines the target test performance parameters according to the target test scenario; then, the embedded system host performs a test operation on the LPDDR part according to the target test performance parameters, and after the test is completed, the first test result of the LPDDR part is stored in a database or an external memory; at the same time, the eMMC part is tested in the form of a self-test, specifically, the eMMC controller performs a test operation on the Nand Flash according to the target test performance parameters, and after the test is completed, a second test result of the eMMC part is obtained; then, the embedded system host sends the first test result to the eMMC controller, and after receiving the first test result, the eMMC controller integrates the first test result and the second test result, and writes the integrated test result to the Nand Flash.

[0047] It is worth noting that the embodiment of the present application can test the eMMC part and the LPDDR part of the eMCP at the same time and in the same environment, which can solve the cost and product life issues; in addition, the test results of the LPDDR part can be integrated into the test results of the eMMC part and saved to Nand Flash, so that the test results of the entire product can be bound to the product. As long as the product is not damaged, the test results will be saved, which is conducive to the tracking of subsequent product test results and reduces the Binning cost.

[0048] In addition, if Figure 3 As shown, Figure 3 yes Figure 2 Sub-step flow chart of step S210; regarding the above-mentioned step S210, it may include but is not limited to step S310 and step S320.

[0049] Step S310: determining the read / write speed requirement and the random read / write performance requirement according to the scenario type of the target test scenario; wherein the scenario type of the target test scenario includes at least one of the following: a mobile device test scenario type, an automotive electronics test scenario type, and an industrial equipment test scenario type; Step S320: Determine target test performance parameters according to the read / write speed requirements and the random read / write performance requirements.

[0050] In one embodiment, since the read and write speed requirements and random read and write performance requirements corresponding to target test scenarios of different scenario types are different, the embodiment of the present application needs to first determine the read and write speed requirements and random read and write performance requirements according to the scenario type of the target test scenario, and then determine the target test performance parameters, such as read and write efficiency, error rate, etc., based on the read and write speed requirements and random read and write performance requirements.

[0051] It should be noted that for mobile device test scenarios, the read and write speed requirements, random read and write performance requirements, and application scenarios are as follows: Read and write speed requirements: Mobile devices (such as smartphones and tablets) usually have high requirements for eMMC read and write speeds, especially in scenarios such as launching applications, loading games, and playing high-definition videos. The continuous read speed of eMMC version 5.1 can reach 400MB / s, and the continuous write speed can reach 250MB / s.

[0052] Random read and write performance: In mobile devices, random read and write performance is also very important, especially when processing a large number of small files. The random read IOPS of eMMC 5.1 version can reach 8K, and the random write IOPS can reach 6K.

[0053] Application scenario: Mobile devices focus more on user experience, so low latency and high IOPS are key indicators.

[0054] In addition, it should be noted that for automotive electronics testing scenarios, the read and write speed requirements, random read and write performance requirements, and application scenarios are as follows: Read and write speed requirements: Automotive electronic systems have relatively low requirements for eMMC read and write speeds, but they focus more on reliability and durability. For example, vehicle infotainment systems and instrument panel systems usually do not require extremely high read and write speeds, but need to operate stably in extreme environments.

[0055] Random read and write performance: Automotive electronic systems have moderate requirements for random read and write performance, focusing mainly on data integrity and reliability.

[0056] Application scenarios: Automotive electronic systems focus more on long-term stability and safety rather than extreme performance.

[0057] In addition, it should be noted that for industrial equipment testing scenarios, the read and write speed requirements, random read and write performance requirements, and application scenarios are as follows: Read and write speed requirements: The read and write speed requirements of industrial equipment for eMMC vary depending on the specific application. Some industrial automation equipment may require higher read and write speeds to process large amounts of data, but they are generally not as strict as mobile devices.

[0058] Random read and write performance: Industrial equipment pays more attention to data integrity and low latency, especially in scenarios that require real-time data processing.

[0059] Application scenarios: Industrial equipment usually operates in harsh environments, so high durability and reliability requirements are placed on eMMC.

[0060] In addition, if Figure 4 As shown, Figure 4 This is a flowchart of obtaining difference increment results under multiple test operations provided by an embodiment of the present application; the method also includes but is not limited to step S410 and step S420.

[0061] Step S410: Under the same scenario type, for the LPDDR part, compare the current first test result with the previous first test result to obtain a first difference increment result between the current first test result and the previous first test result, and store the first difference increment result in a database or an external memory; Step S420: Under the same scenario type, for the eMMC part, compare the current second test result with the previous second test result to obtain a second difference increment result between the current second test result and the previous second test result.

[0062] In one embodiment, in order to reduce the amount of transmitted data and improve transmission efficiency and test efficiency, the embodiment of the present application does not need to store the first test result and the second test result completely each time, but stores the difference data of the two test results before and after, as follows: For example, under the same category of scenario types, the embedded system host performs multiple test operations on the LPDDR part. For the first test result, the embedded system host will completely record all test data; and for each subsequent test operation, the current first test result and the previous first test result will be compared to obtain the data difference between the two, and then the first difference incremental result between the current first test result and the previous first test result will be obtained. Therefore, for each subsequent test operation, the embedded system host only needs to store and record the first difference incremental result with a smaller amount of data, thereby reducing the amount of transmitted data and improving transmission efficiency and testing efficiency.

[0063] Similarly, for example, under the same category of scenario types, the eMMC part will perform multiple tests in the form of self-testing. For the first second test result, the eMMC controller will obtain complete test data, and for each subsequent test operation, the current second test result and the previous second test result will be compared to obtain the data difference between the two, and then the second difference incremental result between the current second test result and the previous second test result will be obtained. Therefore, for each subsequent test operation, the eMMC controller only needs to obtain the second difference incremental result with a smaller amount of data, thereby reducing the amount of transmitted data and improving transmission efficiency and testing efficiency.

[0064] It should be noted that the above-mentioned first difference increment result or second difference increment result can only be for the same category of scene types.

[0065] In addition, if Figure 5 As shown, Figure 5 It is a flowchart of integrating difference incremental results under multiple test operations provided by an embodiment of the present application; regarding the eMMC controller in the above-mentioned step S240 integrating the first test result and the second test result, including but not limited to step S510, step S520 and step S530.

[0066] Step S510: the eMMC controller obtains a first difference increment result and a second difference increment result under the same category of scene types; Step S520: Integrate the first difference increment result and the second difference increment result to obtain a merged difference increment result; Step S530: write the merged difference increment result to Nand Flash to update the integrated test result stored in Nand Flash.

[0067] In one embodiment, in order to reduce the amount of transmitted data and improve transmission efficiency and test efficiency, the embodiment of the present application does not need to integrate the complete data of the first test result and the second test result each time, but can integrate the first difference increment result and the second difference increment result, as follows: In the same category of scenario types, if the first difference increment result and the second difference increment are obtained, the eMMC controller will integrate the two to obtain a combined difference increment result; then write the combined difference increment result to Nand Flash to update the integrated test result stored in Nand Flash. Therefore, for each subsequent test operation, the eMMC controller only needs to merge the first difference increment result and the second difference increment result with a smaller amount of data, thereby reducing the amount of transmitted data and improving transmission efficiency and test efficiency.

[0068] In addition, if Figure 6 As shown, Figure 6 yes Figure 2 Sub-step flow chart of step S240; regarding the above-mentioned step S240, including but not limited to step S610 and step S620.

[0069] Step S610: the embedded system host accesses the eMMC part through the EMDC interface and writes the first test result into Sram; Step S620: The eMMC controller integrates the first test result and the second test result written into the Sram, and writes the integrated test result into the Nand Flash.

[0070] In one embodiment, during the test process, after the embedded system host obtains the test result of the LPDDR part, it can access the eMMC through the interface, write the test result of the LPDDR part into the Sram of the eMMC part, and the eMMC controller integrates the first test result of the LPDDR part and the second test result of the eMMC part and writes them into Nand Flash.

[0071] In addition, if Figure 7 As shown, Figure 7 This is a flowchart provided by an embodiment of the present application in which the LPDDR part completes the test operation under the current target test scenario, but the eMMC part does not complete the test operation under the current target test scenario; when there are multiple target test scenarios, the method also includes but is not limited to step S710, step S720 and step S730.

[0072] Step S710: In the current target test scenario, start testing operations on the LPDDR part and the eMMC part at the same time; Step S720: When the LPDDR part ends the test operation under the current target test scenario, but the eMMC part does not end the test operation under the current target test scenario, the eMMC part is kept to continue to perform the test operation under the current target test scenario; Step S730: At the same time, the embedded system host writes the first test result into the Sram of the eMMC part, and starts the test operation of the LPDDR part in the next target test scenario.

[0073] In one embodiment, when the test time of the LPDDR part and the test time of the eMMC part are not equal, if the embedded system host writes the first test result into the SRAM after waiting for both the LPDDR part and the eMMC part to complete the test operation, the LPDDR part or the eMMC part that completes the test earlier will have a period of idle time. In this regard, in order to improve efficiency, the embodiment of the present application can be operated as follows: In the current target test scenario, the test operation of the LPDDR part and the eMMC part is started at the same time; then, if the LPDDR part completes the test operation of the current target test scenario earlier than the eMMC part, the eMMC part will continue to perform the test operation of the current target test scenario; at the same time, the embedded system host and the LPDDR part do not need to wait for the eMMC part to complete the operation, but the embedded system host can first write the first test result to the Sram of the eMMC part, and at the same time, start the test operation of the LPDDR part in the next target test scenario. Therefore, the embodiment of the present application can save the idle time caused by the inequality of the test time of the LPDDR part and the test time of the eMMC part, thereby improving the overall test efficiency.

[0074] In addition, if Figure 8 As shown, Figure 8 It is a flowchart provided by an embodiment of the present application after the eMMC part completes the test operation under the current target test scenario, but the eMMC part does not complete the test operation under the current target test scenario; after the above step S730, the method also includes but is not limited to step S810 and step S820.

[0075] Step S810: When the eMMC part completes the test operation under the current target test scenario, the eMMC controller integrates the first test result and the second test result written to SRAM; Step S820: At the same time, the embedded system host keeps performing the test operation on the LPDDR part in the next target test scenario.

[0076] In one embodiment, after the eMMC part completes the test operation in the current target test scenario, there is no need to wait for the LPDDR part to complete the test operation in the next target test scenario, but the eMMC controller can immediately integrate the first test result and the second test result written to Sram; in addition, at the same time, the embedded system host keeps performing the test operation of the LPDDR part in the next target test scenario, that is, the eMMC controller does not affect the test operation of the LPDDR part in the next target test scenario when performing the integration operation. Therefore, the embodiment of the present application can improve the overall test efficiency.

[0077] In one embodiment, after the embedded system host sends the first test result to the eMMC controller, when the eMMC controller successfully receives the first test result sent by the embedded system host within a preset time, the eMMC controller feeds back a result reception success instruction to the embedded system host.

[0078] Alternatively, in one embodiment, after the embedded system host sends the first test result to the eMMC controller, when the eMMC controller does not receive the first test result sent by the embedded system host within a preset time period, the eMMC controller feeds back a result reception failure instruction to the embedded system host.

[0079] In addition, in one embodiment, after the eMMC controller writes the integrated test result into the Nand Flash, the eMMC controller further generates a result merging completion instruction and sends the result merging completion instruction to the embedded system host.

[0080] Based on the test methods of the eMCP chip aging test device of the above-mentioned embodiments, overall embodiments of the test methods of the eMCP chip aging test device of the present application are respectively proposed below.

[0081] In one embodiment, if Figure 1 and Fig. 9As shown in the figure, during the eMCP aging test, the Host (i.e., the embedded system host) is connected to the eMMC part and the LPDDR part through the EMDC interface and the DDR interface at the same time. During the aging test of the LPDDR part, the Host operates the LPDDR part according to the established rules. After the test is completed, the results are stored in an external memory or saved to a database. The eMMC part is tested in the form of self-test, and the Nand Flash is read, written and erased through the eMMC controller. After the test is completed, the test results are written to a specific location of the Nand Flash. Therefore, during the test, after the Host of the LPDDR part obtains the test results of the LPDDR part, it can access the eMMC part through the EMDC interface, write the test results of the LPDDR part into the Sram of the eMMC part, and the eMMC controller integrates the test results of the LPDDR part and the test results of the eMMC part and writes them into the Nand Flash.

[0082] The technical solution of the embodiment of the present application includes the following technical effects: First, testing the eMMC and LPDDR parts of the eMCP at the same time and in the same environment can solve the cost and product life issues.

[0083] Second, by integrating the test results of the LPDDR part into the test results of the eMMC part and saving them to NandFlash, the test results of the entire product can be bound to the product. As long as the product is not damaged, the test results will be saved, which is conducive to the tracking of subsequent product test results and reduces the binning cost.

[0084] Based on the test methods of the eMCP chip aging test device of the above-mentioned embodiments, various embodiments of the control device, eMCP chip aging test device, computer-readable storage medium and computer program product of the present application are respectively proposed below.

[0085] like Fig.10 As shown, Fig.10 Schematic diagram of a control device for executing a test method of an eMCP chip aging test device provided by an embodiment of the present application. The control device 300 implemented in the present application includes: a processor 310, a memory 320, and a computer program stored in the memory 320 and executable on the processor 310, wherein: Fig.10 In the figure, a processor 310 and a memory 320 are taken as an example.

[0086] The processor 310 and the memory 320 may be connected via a bus or other means. Fig.10 The example of connecting through bus is taken in the following.

[0087] The memory 320, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer executable programs. In addition, the memory 320 may include a high-speed random access memory, and may also include a non-transitory memory, such as at least one disk storage device, a flash memory device, or other non-transitory solid-state storage device. In some embodiments, the memory 320 may optionally include a memory 320 remotely arranged relative to the processor 310, and these remote memories 320 may be connected to the control device 300 via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0088] Those skilled in the art will understand that Fig.10 The device structure shown in the figure does not constitute a limitation on the control device 300, and may include more or less components than shown in the figure, or combine certain components, or arrange the components differently.

[0089] exist Fig.10 In the control device 300 shown, the processor 310 can be used to call the control program stored in the memory 320, so as to implement the test method of the eMCP chip aging test device described above. Specifically, the non-transient software program and instructions required to implement the test method of the eMCP chip aging test device of the above embodiment are stored in the memory 320, and when executed by the processor 310, the test method of the eMCP chip aging test device of the above embodiment is executed.

[0090] It is worth noting that since the control device 300 of the embodiment of the present application can execute the test method of the eMCP chip aging test device of any of the above-mentioned embodiments, the specific implementation manner and technical effects of the control device 300 of the embodiment of the present application can refer to the specific implementation manner and technical effects of the test method of the eMCP chip aging test device of any of the above-mentioned embodiments.

[0091] In addition, an embodiment of the present application further provides an eMCP chip aging test device, which includes the control device of the above embodiment.

[0092] It is worth noting that since the eMCP chip aging test device of the embodiment of the present application includes the control device of the above-mentioned embodiment, and the control device of the above-mentioned embodiment can execute the test method of the eMCP chip aging test device of any of the above-mentioned embodiments, the specific implementation manner and technical effects of the eMCP chip aging test device of the embodiment of the present application can refer to the specific implementation manner and technical effects of the test method of the eMCP chip aging test device of any of the above-mentioned embodiments.

[0093] In addition, an embodiment of the present application further provides a computer-readable storage medium, which stores computer-executable instructions, and the computer-executable instructions are used to execute the test method of the eMCP chip aging test device described above. Figures 2 to 9 The method steps in .

[0094] It is worth noting that since the computer-readable storage medium of the embodiment of the present application can execute the test method of the eMCP chip aging test device of any of the above-mentioned embodiments, the specific implementation methods and technical effects of the computer-readable storage medium of the embodiment of the present application can refer to the specific implementation methods and technical effects of the test method of the eMCP chip aging test device of any of the above-mentioned embodiments.

[0095] In addition, an embodiment of the present application further provides a computer program product, including a computer program or computer instructions, the computer program or computer instructions are stored in a computer-readable storage medium, the processor of the computer device reads the computer program or computer instructions from the computer-readable storage medium, and the processor executes the computer program or computer instructions, so that the computer device executes the test method of the eMCP chip aging test device described above. Exemplarily, the above-described Figures 2 to 9 The method steps in .

[0096] It is worth noting that since the computer program product of the embodiments of the present application can execute the test method of the eMCP chip aging test device of any of the above-mentioned embodiments, the specific implementation methods and technical effects of the computer program product of the embodiments of the present application can refer to the specific implementation methods and technical effects of the test method of the eMCP chip aging test device of any of the above-mentioned embodiments.

[0097] It will be appreciated by those skilled in the art that all or some of the steps and systems in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or transient medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically include computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0098] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0099] In several embodiments provided in the present application, it should be understood that the disclosed systems, apparatuses and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely schematic, for example, the division of units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of apparatuses or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the scheme of this embodiment.

[0100] It should also be understood that the various implementations provided in the embodiments of the present application can be combined arbitrarily to achieve different technical effects.

[0101] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the above implementation mode. Technical personnel familiar with the field can also make various equivalent modifications or substitutions under the shared conditions without violating the spirit of the present application. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present application.

Claims

1. A test method for an eMCP chip aging test device, characterized in that: The eMCP chip aging test device comprises an embedded system host and an eMCP chip, wherein the eMCP chip comprises an eMMC part and an LPDDR part, the eMMC part comprises an eMMC controller and a Nand Flash, and the embedded system host is respectively connected to the eMMC part and the LPDDR part for communication; the method comprises: Determine a target test scenario, and determine a target test performance parameter according to the target test scenario; The embedded system host performs a test operation on the LPDDR part according to the target test performance parameter, and stores a first test result of the LPDDR part in a database or an external memory; The eMMC controller performs a test operation on the Nand Flash according to the target test performance parameter to obtain a second test result of the eMMC part; During the test operation, the embedded system host sends the first test result to the eMMC controller, and the eMMC controller integrates the first test result and the second test result, and writes the integrated test result to the Nand Flash.

2. The method according to claim 1, characterized in that: Determining the target test performance parameter according to the target test scenario includes: Determine the read / write speed requirements and random read / write performance requirements according to the scenario type of the target test scenario; Determine the target test performance parameter according to the read / write speed requirement and the random read / write performance requirement; The scenario type of the target test scenario includes at least one of the following: a mobile device test scenario type, an automotive electronics test scenario type, and an industrial equipment test scenario type.

3. The method according to claim 2, characterized in that In the case where multiple test operations are performed on the LPDDR part and the eMMC part, the method further includes: In the case of the same scenario type, for the LPDDR part, compare the current first test result with the previous first test result, obtain a first difference increment result between the current first test result and the previous first test result, and store the first difference increment result in a database or an external memory; In the case of the same scenario type, for the eMMC part, the current second test result and the previous second test result are compared to obtain a second difference increment result between the current second test result and the previous second test result.

4. The method according to claim 3, characterized in that The eMMC controller integrates the first test result and the second test result, including: The eMMC controller obtains the first difference increment result and the second difference increment result under the scene type of the same category; Integrate the first incremental difference result and the second incremental difference result to obtain a combined incremental difference result; The merged difference increment result is written into the Nand Flash to update the integrated test result stored in the Nand Flash.

5. The method according to claim 1, characterized in that The eMMC part also includes Sram, and the eMMC controller is in communication with the Sram; the embedded system host sends the first test result to the eMMC controller, and the eMMC controller integrates the first test result and the second test result, and writes the integrated test result to the Nand Flash, including: The embedded system host accesses the eMMC part through the EMDC interface, and writes the first test result into the Sram; The eMMC controller integrates the first test result and the second test result written into the Sram, and writes the integrated test result into the Nand Flash.

6. The method according to claim 5, characterized in that In the case where there are multiple target test scenarios, the method further includes: In the current target test scenario, simultaneously starting the test operation on the LPDDR part and the eMMC part; When the LPDDR part completes the test operation under the current target test scenario but the eMMC part does not complete the test operation under the current target test scenario, the eMMC part is kept to continue to execute the test operation under the current target test scenario, and at the same time, the embedded system host writes the first test result to the Sram of the eMMC part, and starts the test operation of the LPDDR part in the next target test scenario.

7. The method according to claim 6, characterized in that After the initiating of the test operation of the LPDDR part in the next target test scenario, the method further includes: When the eMMC part completes the test operation under the current target test scenario, the eMMC controller integrates the first test result and the second test result written to the Sram, and the embedded system host keeps performing the test operation on the LPDDR part under the next target test scenario.

8. The method according to claim 1, characterized in that: After the embedded system host sends the first test result to the eMMC controller, the method further includes: When the eMMC controller successfully receives the first test result sent by the embedded system host within a preset time, the eMMC controller feeds back a result reception success instruction to the embedded system host; When the eMMC controller does not receive the first test result sent by the embedded system host within a preset time, the eMMC controller feeds back a result reception failure instruction to the embedded system host; In addition, after the eMMC controller integrates the first test result and the second test result and writes the integrated test result into the Nand Flash, the method further includes: The eMMC controller generates a result merging completion instruction, and sends the result merging completion instruction to the embedded system host.

9. An eMCP chip aging test device, characterized in that: A testing method based on the eMCP chip aging testing device according to any one of claims 1 to 8; The eMCP chip aging test device comprises: The eMCP chip includes an eMMC part and an LPDDR part, wherein the eMMC part includes an eMMC controller, NandFlash and Sram, and the eMMC controller is respectively connected to the NandFlash and the Sram in communication; The embedded system host is communicatively connected with the eMMC part and the LPDDR part respectively.

10. The eMCP chip aging test device according to claim 9, characterized in that: The embedded system host is connected to the eMMC part through an EMDC interface, and the embedded system host is connected to the LPDDR part through a DDR interface or an SDRAM interface.

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