Processing method of high flatness silicon wafer
Through the technology of back grinding and roughening of back surface, the problem of insufficient flatness of silicon wafers is solved, the flatness is significantly improved, the SFQR capability is improved, and the process is controlled and effective is ensured.
Patent Information
- Application Number
- CN202411707494.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-26
- Publication Date
- 2025-04-04
AI Technical Summary
In the prior art, it is difficult for the flatness of the silicon wafer to reach high standards, which affects the performance and yield of the integrated circuit.
Through the technology of back grinding and roughening of back, the flatness is significantly improved, and the SFQR capability is increased by 22.8%.
It realizes processing of high-flatness silicon wafers, improves SFQR capabilities, and has the characteristics of controllable processes and good results.
Smart Images
Figure CN119764168A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the technical field of silicon wafer processing technology, and in particular to a processing method for a high-flatness silicon wafer. Background Art
[0002] As an important parameter of silicon wafers, flatness directly affects the performance and yield of downstream integrated circuits. In the process of silicon wafer processing, silicon wafers generally need to go through multiple steps such as crystal growth, slicing, grinding, etching, polishing and cleaning. Flatness is related to multiple processing steps, and the degree of influence will accumulate with each other. Only when the surface flatness is high enough can the lithography performance and stability of complex circuit patterns be guaranteed. Summary of the invention
[0003] The present invention mainly solves the deficiencies in the prior art and provides a method for processing a high-flatness silicon wafer. The method significantly improves the flatness and improves the SFQR capability by 22.8% through the technology of back grinding and back roughening. The method has the characteristics of controllable process and good effect.
[0004] The above technical problems of the present invention are mainly solved by the following technical solutions:
[0005] A method for processing a high-flatness silicon wafer comprises the following steps:
[0006] Step 1: After the silicon single crystal is pulled, it is roller-ground to a crystal rod of specified diameter and then sliced.
[0007] Step 2: Double-sided grinding of the sliced silicon wafer.
[0008] Step 3: After double-sided grinding, acid etching is performed to remove the surface grinding damage layer. The acid etching removal amount is 20±2μm.
[0009] Step 4: After acid etching, the surface residual corrosion products are removed through a cleaning step, and then the back of the silicon wafer is ground. Back grinding eliminates the deterioration of the back flatness caused by acid corrosion and maintains a good flatness state.
[0010] Step 5: The back surface is roughened by grinding. To ensure flatness, the grinding removal amount is controlled at 0.5±0.2μm.
[0011] Step 6: Grind the front side of the silicon wafer.
[0012] Step 7: Polish the front side of the silicon wafer.
[0013] Step 8: The peeled silicon wafer is dewaxed and cleaned, and then tested for flatness on the ADE 9600.
[0014] Warp is a global characteristic of silicon wafers, which indicates the maximum deviation of the silicon wafer surface from the plane. It measures the distance between the highest point and the lowest point of the silicon wafer.
[0015] Preferably, the diameter of an 8-inch silicon wafer is generally 200.2 mm, and the silicon wafer warp after slicing is required to be less than 5 μm.
[0016] Preferably, the double-sided grinding removal amount is 65±3μm, the grinding powder particle size is 1200 mesh, and the grinding pressure is 880±30kg; the silicon wafer is placed in a carrier, the number of silicon wafers processed at one time is 25, and the TTV after double-sided grinding is required to be less than 1μm.
[0017] The thickness of silicon wafers is divided into nominal thickness and total thickness variation. The thickness (TV) at the center of the silicon wafer refers to the thickness distribution of a batch of silicon wafers. The difference between the maximum thickness and the minimum thickness in multiple thickness measurements is called the total thickness variation (TTV) of the silicon wafer.
[0018] Preferably, the etching solution is composed of a mixture of HF, HNO3 and CH3COOH, and CH3COOH serves as a buffer to improve the corrosion state and enhance the flatness.
[0019] Preferably, the corrosion temperature is 20±5°C, and the ratio of the mixed solution is HF:HNO3:CH3COOH=10wt.%:17wt.%:35wt.%.
[0020] Preferably, the grinding wheel for back grinding is 3000 mesh, the back grinding removal amount is 10±1 μm, and the TTV after back grinding is less than 0.5 μm.
[0021] Preferably, the back surface roughening grinding uses Suba400 polishing pad and 1200 mesh SiO2 grinding powder. The grinding time can be selected according to the final back surface roughness requirement and the time is controlled within 3 to 8 minutes.
[0022] Preferably, the grinding wheel for front grinding is 3000 mesh, the front grinding removal amount is 10±1 μm, and the TTV after front grinding is less than 0.3 μm.
[0023] Preferably, the front side is polished by wax polishing, the back side of the silicon wafer is waxed and pasted on a ceramic plate, 20 wafers are processed per plate, and the polishing removal amount is 5±2 μm.
[0024] The present invention can achieve the following effects:
[0025] The present invention provides a method for processing a high-flatness silicon wafer. Compared with the prior art, the flatness is significantly improved by back grinding and back roughening technology, and the SFQR capability is improved by 22.8%. The method has the characteristics of controllable process and good effect. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figure 1 It is a process flow chart of the present invention. DETAILED DESCRIPTION
[0027] The technical solution of the invention is further specifically described below through embodiments and in conjunction with the accompanying drawings.
[0028] Example: Figure 1 As shown, a method for processing a high-flatness silicon wafer includes the following steps:
[0029] Step 1: After the silicon single crystal is pulled, it is rolled and ground to a specified diameter, and then sliced. The diameter of an 8-inch silicon wafer is generally 200.2mm, and the silicon wafer warp after slicing is required to be less than 5μm.
[0030] Step 2: Double-sided grinding of the sliced silicon wafers. The double-sided grinding removal amount is 65±3μm, the grinding powder particle size is 1200 mesh, and the grinding pressure is 880±30kg; the silicon wafers are placed in a carrier, and the number of silicon wafers processed at one time is 25. After double-sided grinding, the TTV is required to be less than 1μm.
[0031] Step 3: After double-sided grinding, acid etching is performed to remove the surface grinding damage layer. The acid etching removal amount is 20±2μm. The etching solution is composed of a mixture of HF, HNO3 and CH3COOH. CH3COOH is used as a buffer to improve the corrosion state and improve the flatness.
[0032] Step 4: After acid etching, the surface residual corrosion products are removed by cleaning, and then the back of the silicon wafer is ground. The grinding wheel for back grinding is 3000 mesh, the back grinding removal is 10±1μm, and the TTV after back grinding is less than 0.5μm.
[0033] Step 5: Back surface roughening is achieved by grinding. To ensure flatness, the grinding removal amount is controlled at 0.5±0.2μm. Suba400 polishing pad and 1200 mesh SiO2 grinding powder are used for back surface roughening. The grinding time can be selected according to the final back surface roughness requirements, and the time is controlled within 3 to 8 minutes.
[0034] Step 6: Grind the front side of the silicon wafer. The grinding wheel for front grinding is 3000 mesh, the front grinding removal is 10±1μm, and the TTV after front grinding is less than 0.3μm.
[0035] Step 7: Polish the front side of the silicon wafer. The front side is polished by waxing. The back side of the silicon wafer is waxed and pasted on a ceramic plate. Each plate is processed with 20 wafers, and the polishing removal is 5±2μm.
[0036] Step 8: The peeled silicon wafer is dewaxed and cleaned, and then tested for flatness on the ADE 9600.
[0037] In summary, the processing method of the high-flatness silicon wafer significantly improves the flatness through the back grinding and back roughening technology, and the SFQR capability is improved by 22.8%, which has the characteristics of controllable process and good effect.
[0038] The above description is only a specific embodiment of the present invention, but the structural features of the present invention are not limited thereto. Any changes or modifications made by any technician in the field of the present invention are included in the patent scope of the present invention.
Claims
1. A method for processing a high-flatness silicon wafer, characterized in that The steps are as follows: Step 1: After the silicon single crystal is pulled, it is roller-grinded to a crystal rod of a specified diameter and then sliced; Step 2: Double-sided grinding of the sliced silicon wafer; Step 3: After double-sided grinding, acid etching is performed to remove the surface grinding damage layer. The acid etching removal amount is 20±2μm; Step 4: After the acid corrosion, the residual corrosion products on the surface are removed by cleaning, and then the back of the silicon wafer is ground; Step 5: The back surface is roughened by grinding. To ensure the flatness, the grinding removal amount is controlled to 0.5±0.2μm. Step 6: Grind the front side of the silicon wafer; Step 7: Polish the front side of the silicon wafer; Step 8: The peeled silicon wafer is dewaxed and cleaned, and then tested for flatness on the ADE 9600.
2. The method for processing a high-flatness silicon wafer according to claim 1, characterized in that: The diameter of an 8-inch silicon wafer is generally 200.2 mm, and the silicon wafer warp is required to be less than 5 μm after slicing.
3. The method for processing a high-flatness silicon wafer according to claim 1, characterized in that: The double-sided grinding removal amount is 65±3μm, the grinding powder particle size is 1200 mesh, and the grinding pressure is 880±30kg; the silicon wafer is placed in a carrier, the number of silicon wafers processed at one time is 25, and the TTV is required to be less than 1μm after double-sided grinding.
4. The method for processing a high-flatness silicon wafer according to claim 1, characterized in that: The etching solution is composed of a mixture of HF, HNO3 and CH3COOH. CH3COOH acts as a buffer to improve the corrosion state and improve the flatness.
5. The method for processing a high-flatness silicon wafer according to claim 4, characterized in that: The corrosion temperature is 20±5°C, and the ratio of the mixed solution is HF:HNO3:CH3COOH=10wt.%:17wt.%:35wt.%.
6. The method for processing a high-flatness silicon wafer according to claim 1, characterized in that: The grinding wheel for back grinding is 3000 mesh, the back grinding removal is 10±1μm, and the TTV after back grinding is less than 0.5μm.
7. The method for processing a high-flatness silicon wafer according to claim 1, characterized in that: Suba400 polishing pad and 1200 mesh SiO2 abrasive powder are used for back roughening. The grinding time can be selected according to the final back roughness requirements and the time is controlled within 3 to 8 minutes.
8. The method for processing a high-flatness silicon wafer according to claim 1, characterized in that: The grinding wheel for front grinding is 3000 mesh, the front grinding removal is 10±1μm, and the TTV after front grinding is less than 0.3μm.
9. The method for processing a high-flatness silicon wafer according to claim 1, characterized in that: The front side is polished by waxing. The back side of the silicon wafer is coated with wax and pasted on a ceramic plate. 20 wafers are processed on each plate, and the polishing removal amount is 5±2μm.