Encapsulation substrate and method for manufacturing the same

Abstract

The present invention provides a packaging substrate and a manufacturing method thereof. The packaging substrate includes a circuit structure having opposite ball-planting side and build-up side, a wiring structure formed on the build-up side of the circuit structure, and a fixing structure extending from the circuit structure and penetrating through the wiring structure, so as to avoid the problem of interlayer delamination of the packaging substrate and improve the yield and reliability of the packaging substrate.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor packaging technology, and particularly to a packaging substrate capable of preventing delamination and a manufacturing method thereof. Background Art

[0002] With the vigorous development of the electronics industry, electronic products tend to be thinner, lighter, shorter, and smaller in form, and in terms of function, they are developed towards high performance, high functionality, and high speed. Therefore, in order to meet the requirements of high integration and miniaturization of semiconductor devices, in the packaging process, packaging substrates designed with high-density wiring, thin-filmable, and low warpage are often used.

[0003] However, in the existing manufacturing methods of packaging substrates, in order to achieve high integration and high functionality, the packaging substrates have a multi-layer wiring structure, including a dielectric layer heterogeneous with the substrate, and there is a risk of delamination in high-temperature or humid environments. For example, due to the difference in the coefficient of thermal expansion (CTE) between the dielectric material and the substrate, uneven expansion and contraction of the material and local blistering and delamination occur after heating; or when the substrate process is heated, moisture is converted into vapor and penetrates between the substrate layers, and the internal vapor pressure weakens the bonding force between the two interfaces, which is also likely to cause delamination of the dielectric material, affecting the reliability of the substrate and the product life. Especially when mass-producing full-panel substrates (Panel), it is difficult to ensure the yield of each substrate unit (Unit).

[0004] In addition, the existing manufacturing methods of packaging substrates with a core layer generally adopt a symmetric process. In the case of adding a multi-layer wiring structure, it is difficult to meet the thinning requirements; if thinning is to be implemented and asymmetric layer addition is only carried out on one side of the core layer, problems such as substrate warping may be faced, and the different structures on the relative two sides of the core layer will increase the process difficulty, which is not conducive to reducing production costs.

[0005] Therefore, how to overcome the problems of the above-mentioned existing technologies has actually become an urgent issue to be solved currently. Summary of the Invention

[0006] The object of the present invention is to provide a packaging substrate and a manufacturing method thereof to solve at least one of the above problems.

[0007] In view of the deficiencies of the above-mentioned prior art, the present disclosure provides a packaging substrate, including: a circuit structure, a wiring structure, and a fixing structure. The circuit structure has an opposite ball-planting side and build-up side, and the circuit structure includes: a core layer having opposite first and second sides, a plurality of through holes connecting the first and second sides, and at least one fixing hole; a bonding layer formed on the first and second sides of the core layer, the inner walls of the through holes and the fixing hole; a plurality of conductive posts formed in each of the through holes; and a circuit layer formed on the opposite first and second sides of the core layer and electrically connected to the conductive posts, wherein the first side corresponds to the ball-planting side, and the second side corresponds to the build-up side. The fixing structure is formed on the build-up side of the circuit structure. The fixing structure includes a supporting portion formed in the fixing hole and an extending portion located in the wiring structure and corresponding to the supporting portion, so that the fixing structure extends from the circuit structure through the wiring structure.

[0008] In a specific embodiment of the packaging substrate of the present disclosure, the circuit structure further includes an insulating layer formed on the bonding layer and filling the plurality of through holes and the fixing hole, and wherein the plurality of conductive posts penetrate the insulating layer in the plurality of through holes, and the fixing structure penetrates the insulating layer.

[0009] In a specific embodiment of the packaging substrate of the present disclosure, the fixing structure includes a plurality of fastening portions formed on the extending portion and between the supporting portion and the extending portion, and the width of the fastening portion between the supporting portion and the extending portion is greater than the diameter of the supporting portion.

[0010] In a specific embodiment of the packaging substrate of the present disclosure, the outermost wiring layer on the build-up side has a plurality of electrical contact pads, and the width of the plurality of electrical contact pads is smaller than the width of the plurality of fastening portions.

[0011] In a specific embodiment of the packaging substrate of the present disclosure, the packaging substrate further includes a plurality of solder mask layers respectively formed on the outermost sides of the circuit structure and the wiring structure to cover the fastening portions of the outermost wiring layer.

[0012] In a specific embodiment of the packaging substrate of the present disclosure, the bonding layer is an organic coating or an inorganic coating. For example, the material forming the organic coating is a polymer, and the thickness of the organic coating is 1 nanometer to 100 micrometers. The polymer is selected from at least one of the group consisting of polyoxymethylene, polyamide, and parylene.

[0013] In a specific embodiment of the packaging substrate of the present disclosure, the material forming the inorganic coating includes silica sand with a diameter of 20 to 50 micrometers and a roughness Ra of 1 to 200 micrometers.

[0014] In a specific embodiment of the encapsulation substrate of the present disclosure, the insulating layer includes a dielectric material or an ink material. For example, the dielectric material is selected from at least one of the group consisting of polybenzoxazole (PBO), polyimide (PI), prepreg (PP), and Ajinomoto Build-up Film (ABF), and the ink material includes epoxy ink composites.

[0015] In a specific embodiment of the encapsulation substrate of the present disclosure, the viscosity of the ink material is 25 to 55 Pa·s, and it has a glass transition temperature (Tg) of 145 to 180 °C.

[0016] In a specific embodiment of the encapsulation substrate of the present disclosure, the fixing structure is in the shape of a rivet, a grid, or a frame.

[0017] The present disclosure also provides a method for manufacturing an encapsulation substrate unit, including: providing a circuit structure having opposite ball-planting sides and build-up sides; forming a wiring structure on the build-up side of the circuit structure; and forming a fixing structure. Specifically, the circuit structure includes: a core layer having opposite first and second sides, a plurality of through holes connecting the first and second sides, and at least one fixing hole; a bonding layer formed on the first and second sides of the core layer, the through holes, and the wall surfaces of the fixing holes; a plurality of conductive posts formed in each of the through holes and a supporting portion formed in the fixing hole; and a circuit layer formed on the opposite first and second sides of the core layer and electrically connected to the conductive posts, wherein the first side corresponds to the ball-planting side, and the second side corresponds to the build-up side. An extension is formed in the wiring structure corresponding to the supporting portion to constitute a fixing structure extending through the wiring structure from the circuit structure, including the supporting portion formed in the fixing hole and the extension located in the wiring structure and corresponding to the supporting portion.

[0018] In a specific embodiment of the method for manufacturing an encapsulation substrate of the present disclosure, the method further includes, before forming the wiring structure, bonding the ball-planting sides of two such circuit structures to opposite sides of a carrier, and then, after forming the wiring structure on the build-up side of the circuit structure, removing the carrier to perform a singulation process to obtain a plurality of encapsulation substrates.

[0019] In a specific embodiment of the method for manufacturing an encapsulation substrate of the present disclosure, the step of manufacturing the circuit structure includes forming a bonding layer on the first and second sides of the core layer, the through holes, and the wall surfaces of the fixing holes; forming an insulating layer on the bonding layer and filling the plurality of through holes and the fixing holes; and forming a plurality of conductive posts penetrating the insulating layer in the plurality of through holes and a supporting portion penetrating the insulating layer in the fixing hole.

[0020] In a specific embodiment of the method for manufacturing the encapsulated substrate of the present disclosure, the method further includes, after forming the support portion and after forming the extension portion, forming a plurality of fastening portions on the extension portion and between the support portion and the extension portion, and the width of the fastening portion between the support portion and the extension portion is greater than the diameter of the support portion.

[0021] In a specific embodiment of the method for manufacturing the encapsulated substrate of the present disclosure, the outermost wiring layer on the build-up side has a plurality of electrical contact pads, and the width of the plurality of electrical contact pads is less than the width of the plurality of fastening portions.

[0022] In a specific embodiment of the method for manufacturing the encapsulated substrate of the present disclosure, the method further includes forming solder mask layers on the outermost sides of the circuit structure and the wiring structure respectively to cover the fastening portions of the outermost wiring layer.

[0023] In a specific embodiment of the method for manufacturing the encapsulated substrate of the present disclosure, the bonding layer is an organic coating or an inorganic coating. For example, the material for forming the organic coating is a polymer, and the thickness of the organic coating is 1 nanometer to 100 micrometers. The polymer is selected from at least one of the group consisting of polyoxymethylene, polyamide, and poly-p-xylene.

[0024] In a specific embodiment of the method for manufacturing the encapsulated substrate of the present disclosure, the material for forming the inorganic coating includes silica sand with a diameter of 20 to 50 micrometers and a roughness Ra of 1 to 200 micrometers.

[0025] In a specific embodiment of the method for manufacturing the encapsulated substrate of the present disclosure, the insulating layer includes a dielectric material or an ink material. For example, the dielectric material is selected from at least one of the group consisting of polybenzoxazole (PBO), polyimide (PI), prepreg (PP), and Ajinomoto Build-up Film ABF, and the ink material includes epoxy ink composites.

[0026] In a specific embodiment of the method for manufacturing the encapsulated substrate of the present disclosure, the viscosity of the ink material is 25 to 55 Pa·s, and it has a glass transition temperature (Tg) of 145 to 180 °C.

[0027] In a specific embodiment of the method for manufacturing the encapsulated substrate of the present disclosure, the fixing structure is in the shape of a rivet, a grid, or a frame.

[0028] According to the present disclosure, the wiring structure includes at least one dielectric layer; at least one wiring layer formed on the dielectric layer; and a plurality of conductive blind vias disposed in the dielectric layer to electrically connect the wiring layer and the circuit layer. The extension portion is located in the dielectric layer and correspondingly formed on the support portion, and when there are multiple dielectric layers and wiring layers, extension portions that are stacked on top of each other can be formed in each dielectric layer.

[0029] In addition, the packaging substrate of the present disclosure can be a full-panel substrate, including a plurality of substrate strips or in a form where the full-panel substrate is composed of a plurality of substrate strips, and each substrate strip has a plurality of packaging substrate units arranged in an array or spaced apart. Based on this, the packaging substrate of the present disclosure can also be a substrate strip or a packaging substrate unit. The fixing structure can be formed around each packaging substrate unit, around each substrate strip, and / or around the full-panel substrate, and can also be formed between any two adjacent packaging substrate units or between any two adjacent substrate strips. In addition, the packaging substrate unit generally defines a wiring area and a peripheral area surrounding the wiring area. The fixing structure can be formed not only in the peripheral area but also in the wiring area, as long as the fixing structure is not electrically connected to the circuit layer, the conductive posts, and the wiring layer.

[0030] As can be seen from the above, in the packaging substrate and its manufacturing method of the present disclosure, the dielectric layer is mainly tightly adhered to the core layer by the fixing structure, and when the packaging substrate has multiple dielectric layers, the adhesion between the layers of the dielectric layer is enhanced, reducing the risk of dielectric layer delamination both during the production process and during reliability testing.

[0031] Secondly, the number, shape, and layout position of the fixing structure can all be configured according to the layout of the packaging substrate to achieve an excellent fastening effect.

[0032] Furthermore, the fixing structure of the present disclosure is applicable to various core layers and dielectric materials, without being limited by the substrate material. For example, the core layer can be made of organic materials, glass, ceramics, or any composite material that can form perforations; the dielectric layer can be made of PP, ABF, or any composite material that can form perforations.

[0033] In addition, the present disclosure uses the circuit structure with the core layer as the ball-planting side to reduce the number of layers of the packaging substrate. Therefore, compared with the prior art, the total thickness of the packaging substrate is conducive to thinning; and by simultaneously adding layers on both sides of the carrier, the problem of warping of the asymmetric substrate is effectively avoided, achieving double production efficiency.

[0034] In addition, the present disclosure further avoids the problem of delamination of the insulating layer by strengthening the adhesion between the insulating layer and the core layer and the surface of the perforation through the bonding layer. Description of the Drawings

[0035] Figure 1A 、 Figure 1B 、Figure 1C , Figure 1D , Figure 1E and Figure 1F are cross-sectional schematic views of the first embodiment of the manufacturing method of the encapsulation substrate unit of the present disclosure.

[0036] Figure 1A-1 is a cross-sectional schematic view showing that when the core layer is a high-hardness substrate, the bonding layer of the organic coating penetrates into the cracks of the core layer.

[0037] Figure 1E-1 is a cross-sectional schematic view of the encapsulation substrate unit with a multi-layer wiring structure according to the first embodiment of the present disclosure.

[0038] Figure 2A and Figure 2B are top views of the rivet-shaped fixing structure of the full-panel substrate and the encapsulation substrate unit of the present disclosure.

[0039] Figure 2C and Figure 2D are top views of the grid-shaped fixing structure of the full-panel substrate and the encapsulation substrate unit of the present disclosure.

[0040] Figure 2E and Figure 2F are top views of the full-panel substrate and the encapsulation substrate unit of the present disclosure with a frame-shaped fixing structure.

[0041] Figures 3A to 3C is a cross-sectional schematic view of the second embodiment of the manufacturing method of the encapsulation substrate unit of the present disclosure.

[0042] Figures 4A to 4C is a cross-sectional schematic view of the third embodiment of the manufacturing method of the encapsulation substrate unit of the present disclosure.

[0043] The reference numerals are as follows:

[0044] 1, 4, 5 Encapsulation substrate unit

[0045] 1a Circuit structure

[0046] 10 Core layer

[0047] 10a First side

[0048] 10b Second side

[0049] 100 Perforation

[0050] 101 Fixing hole

[0051] 11 Bonding layer

[0052] 120 Through hole

[0053] 121 Fixing through hole

[0054] 111 cracks

[0055] 12,42 insulating layer

[0056] 13 conductive post

[0057] 14 circuit layer

[0058] 15 wiring structure

[0059] 150 dielectric layer

[0060] 151 wiring layer

[0061] 152 conductive blind via

[0062] 16 solder mask layer

[0063] 160 opening

[0064] 17,18 electrical contact pad

[0065] 19 solder ball

[0066] 2 substrate strip

[0067] 2a,2a',2a'',2a''' fixing structure

[0068] 21 supporting part

[0069] 22 fastening part

[0070] 23 extending part

[0071] 3 full-panel substrate

[0072] 52 conductive layer

[0073] 7 carrier

[0074] D,D F ,D V width

[0075] P pitch

[0076] R,R F diameter Detailed implementation manners

[0077] The following illustrates the implementation manners of the present disclosure through specific specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present disclosure from the content disclosed in this specification.

[0078] It should be noted that the structures, proportions, sizes, etc. shown in the attached drawings of this specification are only used to cooperate with the content disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions under which the present disclosure can be implemented. Therefore, they do not have technical essential significance. Any modification of the structure, change of the proportional relationship, or adjustment of the size, without affecting the effects that the present disclosure can produce and the purposes that can be achieved, should still fall within the scope that the technical content disclosed by the present disclosure can cover. At the same time, terms such as "upper", "inner", "outer", "one", etc. cited in this specification are only for the convenience of clear narration and are not used to limit the scope in which the present disclosure can be implemented. The change or adjustment of their relative relationships, without substantial change in the technical content, should also be regarded as the scope in which the present disclosure can be implemented.

[0079] Figures 1A to 1F It is a schematic cross-sectional view of the manufacturing method of a packaging substrate taking the packaging substrate unit 1 of the present disclosure as an example.

[0080] First, according to Figure 1A and Figure 1B a circuit structure is prepared. As Figure 1A shown, a core layer 10 is provided, which has opposite first side 10a and second side 10b, a plurality of through holes 100 communicating the first side 10a and the second side 10b, and at least one fixing hole 101. To improve the adhesion between the core layer 10 and the subsequently formed insulating layer, a bonding layer 11 is first formed on the first side 10a and the second side 10b of the core layer 10, on the walls of the through holes 100 and the fixing holes 101, and then the insulating layer 12 is bonded through the bonding layer 11, and a plurality of through holes 120 corresponding to each of the through holes 100 and fixing through holes 121 corresponding to the fixing holes 101 are formed on the insulating layer 12.

[0081] In this embodiment, the core layer 10 can be made of any perforable substrate, such as organic materials or high-hardness substrates such as glass, ceramics, SiC, AlO 2 or composite materials.

[0082] Furthermore, the bonding layer 11 can be an organic coating formed by a chemical process. For example, organic polymers such as polyphenylene oxide (PPO), polyamide, or poly-dimethylbenzene (PD) are deposited. Further, a thinner organic coating can be formed by chemical vapor deposition (CVD) method to improve isolation, anti-corrosion, and protection of the surface of the core layer 10. Its thickness is, for example, 1 nanometer to 100 micrometers, and the organic coating can penetrate into cracks to limit the expansion of cracks. As Figure 1A-1As shown, the bonding layer 11 of the organic coating penetrates into the cracks 111 of, for example, the glass material core layer 10, and reduces the dielectric constant (Dk) of the core layer 10 to 2.5 to 5 (1 GHz), such as 2.5, 2.65, 2.7, 2.8, 2.9, 3.0, 3.2, 3.5, 3.7, 4.0, 4.2, 4.5, 4.7, and 5.0 (1 GHz).

[0083] On the other hand, the bonding layer 11 can also be an inorganic coating formed by a physical process to form Van der Waals force. For example, sandblasting with silica sand having a diameter of 20 to 50 microns and a roughness Ra of 1 to 200 microns can not only remove oxides and impurities on the core layer 10, but also increase the surface area of the core layer 10, thus helping to improve the adhesion of the insulating layer 12 formed on the core layer 10. Therefore, in a specific embodiment, the bonding layer 11 is formed by silica sand having a diameter of 20 to 50 microns and a roughness Ra of 1 to 200 microns.

[0084] In this embodiment, the insulating layer 12 is a dielectric material, such as polybenzoxazole (PBO), polyimide (PI), prepreg (PP), Ajinomoto Build-up Film (ABF), or other dielectric materials. The insulating layer 12 can be bonded to the bonding layer 11 by means of pressing or coating, etc., and filled into the plurality of through holes 100 and the fixing holes 101 to cover the core layer 10.

[0085] In addition, the through holes 100 and the fixing holes 101 are straight cylinders, and the through holes 120 and the fixing through holes 121 are in a double-cone hole shape such as a hourglass shape. For example, a plurality of through holes 100 and the fixing holes 101 are simultaneously formed by a laser method, and the through holes 120 and the fixing through holes 121 are simultaneously formed in the insulating layer 12 in the same way.

[0086] As Figure 1B As shown, conductive posts 13 are formed in each of the through holes 120, and a patterning process is performed to form circuit layers 14 electrically connecting the conductive posts 13 on the insulating layers 12 on opposite sides of the core layer 10, so as to fabricate a circuit structure 1a. And, a support portion 21 is formed in the fixing through hole 121 (the insulating layer 12 in the fixing hole 101), and a fastening portion 22 is formed on the insulating layer 12 corresponding to the support portion 21.

[0087] In this embodiment, the conductive posts 13 and the support portions 21 can be formed simultaneously by plating with a metal (such as copper). However, since the support portions 21 are part of the fixed structure, they need to be formed outside the layout position of the circuit layer 14 and are not electrically connected to the circuit layer 14. However, the fastening portions 22 can be formed on the support portions 21 when the support portions 21 are formed.

[0088] Furthermore, the first side 10a of the circuit structure 1a corresponds to the ball-planting side. Therefore, the circuit layer 14 on the ball-planting side serves as the electrical contact pads 17, and the second side 10b of the circuit structure 1a corresponds to the build-up side.

[0089] In addition, the diameter R of the via hole 100 can be smaller than or larger than the diameter R of the fixing hole 101 F , and the width D of the electrical contact pads 17 can also be smaller than or larger than the width D of the fastening portions 22 F . Only the fastening portions 22 need to extend from around the top of the support portions 21 and cover part of the insulating layer 12 to tightly fix the insulating layer 12 to the core layer 10.

[0090] As Figure 1C shown, two of the circuit structures 1a are respectively bonded to opposite sides of a carrier 7. Among them, the circuit structure 1a is bonded to the carrier 7 with its ball-planting side.

[0091] In this embodiment, the carrier 7 is an adhesive material with double-sided capacity (Double capacity), such as a thermally releasable film in a double-sided adhesive form, to respectively press-fit the circuit structures 1a on both sides of the carrier 7, so that the circuit layer 14 on the ball-planting side of the circuit structure 1a is buried in the carrier 7.

[0092] As Figure 1D shown, a wiring structure 15 electrically connected to the circuit layer 14 is formed on the build-up side of each of the circuit structures 1a. And, a plurality of extension portions 23 are formed in the wiring structure 15 corresponding to the support portions 21, and then a plurality of fastening portions 22 are formed corresponding to each of the extension portions 23 to constitute a fixed structure 2a extending through the wiring structure 15 from the circuit structure 1a, including the support portions 21 formed in the fixing holes 101 and the extension portions 23 located in the wiring structure 15 and formed corresponding to the support portions 21. In addition, the fixed structure 2a includes a plurality of fastening portions 22 formed on the extension portions 23 and between the support portions 21 and the extension portions 23, and the width D of the fastening portions 22 between the support portions 21 and the extension portions 23 F is larger than the diameter R of the support portions 21 or the fixing holes F , as Figure 1B shown.

[0093] In this embodiment, the wiring structure 15 includes at least one dielectric layer 150 formed on the insulating layer 12, at least one wiring layer 151 formed on the dielectric layer 150, and a plurality of conductive blind vias 152 formed in the dielectric layer 150 to electrically connect the conductive blind vias 152 to the wiring layer 151 and the circuit layer 14. For example, a build-up process is used to fabricate a wiring structure 15 with Redistribution layer (RDL) specifications by electroplating a metal (such as copper) or other means.

[0094] Furthermore, the extension portion 23 of the fixing structure 2a can be conical and can be formed simultaneously with the conductive blind via 152 by plating a metal material. However, it is only a part of the fixing structure 2a and is not electrically connected to the wiring layer 151. Moreover, when forming the extension portion 23, a fastening portion 22 can be formed thereon at the same time. The fastening portion 22 needs to extend from around the top of the extension portion 23 and cover part of the dielectric layer 150 to tightly fix the dielectric layer 150 on the insulating layer 12. In a specific embodiment, the wiring structure 15 has a plurality of dielectric layers 150. Therefore, a plurality of the extension portions 23 are formed in each dielectric layer 150, and the fastening portions 22 are formed on the extension portions 23 of each layer to tightly fix the dielectric layers 150 of each layer to each other.

[0095] In addition, the dielectric layer 150 can be made of ABF film (Ajinomoto Build-up Film) material or other dielectric materials, and its material can be the same as or different from that of the insulating layer 12. Moreover, the wiring layer 151, the extension portion 23 of the fixing structure 2a, and the fastening portion 22 are all metals such as copper.

[0096] As Figure 1E shown, the carrier 7 is removed to expose the circuit layer 14 on the ball-planting side, and then a solder mask layer 16 is formed on the outermost side of the wiring structure 15, on the circuit layer 14 on the ball-planting side, and at both ends of the outermost fastening portion 22 of the fixing structure 2a. Then, the entire surface substrate is subjected to a singulation process to obtain a plurality of packaged substrate units 1.

[0097] In this embodiment, the solder mask layer 16 is formed with a plurality of openings 160 to expose the circuit layer 14 on the ball-planting side and a part of the outermost wiring layer 151 outside the solder mask layer 16 for use as electrical contact pads 17, 18. And since the fixing structure 2a is not used for electrical connection, the fastening portion 22 is not exposed outside the solder mask layer 16. Of course, the fastening portion 22 can also be exposed outside the solder mask layer 16 as needed. In a specific embodiment, the width D of the plurality of electrical contact pads 18 on the outermost side of the wiring structure 15 Vis less than the width D of the plurality of electrical contact pads 17 of the circuit layer 14. Moreover, the width D of the outermost plurality of electrical contact pads 18 of the wiring structure 15 V is also less than the width D of the plurality of fastening portions 22 of the fixing structure 2a F to ensure that the fastening portions 22 can provide sufficient clamping force to the dielectric layer 150 to prevent delamination.

[0098] Furthermore, the electrical contact pads 17 of the circuit layer 14 are used as ball-planting pads, so that the package substrate unit 1 forms a Ball Grid Array package. For example, the specifications of the circuit structure 1a, such as the width (e.g., diameter) D of the electrical contact pads 17, the pitch P between the conductive posts 13, and the diameter R of the vias 100, etc., are designed according to the requirements of the Ball Grid Array package, that is, only the circuit layer 14 (or the electrical contact pads 17) is arranged on the side of the circuit structure 1a with the ball-planting pads, and no wiring is made above it.

[0099] Such as Figure 1E-1 shown, the fixing structure 2a can be used to fix the wiring structure 15 of the multi-layer structure, and the number of its layers can be increased according to the wiring requirements without limitation. Among them, the wiring structure 15 has a plurality of dielectric layers 150, so fastening portions 22 and extending portions 23 are formed on each corresponding layer to make the dielectric layers 150 adhere tightly to each other.

[0100] Such as Figure 1F shown, a plurality of solder balls 19 electrically connecting the outermost wiring layer 151 and the circuit layer 14 on the ball-planting side can be combined on the electrical contact pads 17, 18, so that the package substrate unit 1 is connected to an electronic device (not shown) such as a semiconductor chip, a passive component, a silicon interposer, a circuit board or other components through the solder balls 19.

[0101] Figures 2A to 2F is a top view schematic diagram of the fixing structure 2a of the entire surface substrate 3 and the package substrate unit 1 of the present disclosure.

[0102] Such as Figure 2A shown, the fixing structure 2a can be distributed at intervals around each package substrate unit 1 and at the board edge of the entire surface substrate 3 to form rivet-shaped fixing structures 2a' scattered around each package substrate unit 1 and the entire surface substrate 3.

[0103] In the mass production process, the full-panel substrate 3 is composed of multiple substrate strips 2 arranged in an array. Each substrate strip 2 is composed of multiple packaged substrate units 1. Therefore, a full-panel substrate 3 contains multiple packaged substrate units 1. That is to say, multiple packaged substrate units 1 can be manufactured simultaneously on a full-panel substrate 3. After manufacturing, a singulation process is performed to remove the edge strips of the substrate strip 2, and then the substrate strip 2 is cut to obtain multiple packaged substrate units 1.

[0104] In this embodiment, the rivet-shaped fixing structure 2a' is disposed around each substrate strip 2 and on the periphery of the full-panel substrate 3. The rivet-shaped fixing structure 2a' has flexibility in layout, and its position and quantity are not restricted and can be arbitrarily selected according to process requirements. For example, a fixing structure 2a can also be formed only on the edge of the full-panel substrate 3 to ensure the stability of the dielectric layer 150 during the manufacturing process of the packaged substrate.

[0105] Figure 2B For Figure 2A An enlarged view of the periphery of the packaged substrate unit 1 is shown in the figure. As shown, rivet-shaped fixing structures 2a' are formed inside and around each packaged substrate unit 1 to maintain the tightness of the dielectric layer 150 after the packaged substrate unit 1 is cut.

[0106] As Figure 2C shown, the fixing structure 2a'' can form a grid-shaped or strip-shaped fixing structure 2a'' on the periphery of each packaged substrate unit 1 and on the edge part of the full-panel substrate 3.

[0107] Figure 2D For Figure 2C An enlarged view of the periphery of the packaged substrate unit 1 is shown in the figure. As shown, fixing structures 2a with different shapes can be formed simultaneously. For example, the inside of the packaged substrate unit 1 is a rivet-shaped fixing structure 2a', and the periphery of the packaged substrate unit 1 is a grid-shaped fixing structure 2a'' to meet the wiring requirements inside the packaged substrate unit 1.

[0108] Different from the above, the number of the fixing structure 2a' or the fixing structure 2a'' is multiple. As Figure 2E shown, the fixing structure 2a''' is a frame, and it is completely interconnected on the periphery of each packaged substrate unit 1 and on the edge of the full-panel substrate 3 to further prevent moisture from entering the packaged substrate unit 1.

[0109] Figure 2F For Figure 2E An enlarged view of the periphery of the packaged substrate unit 1 is shown in the figure. As shown, the inside of the packaged substrate unit 1 is multiple rivet-shaped fixing structures 2a', and the periphery of the packaged substrate unit 1 is a fixing structure 2a''' in the shape of a frame.

[0110] Figures 3A to 3CThis is a cross-sectional schematic diagram of the manufacturing method of the encapsulation substrate unit 4 of the present disclosure. The difference between this embodiment and the first embodiment lies only in the material of the insulating layer, so the same parts will not be described in detail below.

[0111] As Figure 3A shown, the insulating layer 42 is an ink material formed by filling methods such as injection, plugging, or coating. For example, after injecting the paste-like ink material into the perforations 100, it is heated for several hours to crosslink the molecules in the ink material and evaporate the solvent. After the ink is cured, it is polished and leveled with a ceramic roller so that the ink is evenly coated on the surfaces of the opposite sides of the core layer 10 and tightly adheres to the bonding layer 11 on the core layer 10.

[0112] In this embodiment, the ink material mainly comprises epoxy ink composites, which have physical properties such as a viscosity of 25 to 55 Pa·s, a glass transition temperature (Tg) of 145 to 180 °C, and / or a Young's modulus of 3 to 10 GPa. Therefore, by filling the perforations 100 of the core layer 10 with injection ink (plugging ink), the consumption costs of the process and materials can be reduced.

[0113] As Figure 3B shown, following the process as Figure 1B shown, another method of obtaining the encapsulation substrate unit 4 will be obtained.

[0114] As Figure 3C shown, solder balls 19 can be bonded to the electrical contact pads 17, 18, so that the encapsulation substrate unit 4 is connected to an electronic device such as a semiconductor chip, a passive component, a silicon interposer, a circuit board, or other components (not shown in the figure) through a plurality of solder balls 19.

[0115] Figures 4A to 4C This is a cross-sectional schematic diagram of the manufacturing method of the encapsulation substrate unit 5 of the present disclosure. The difference between this embodiment and the first embodiment lies only in that this embodiment does not include an insulating layer, so the same parts will not be described in detail below.

[0116] As Figure 4A shown, a conductive layer 52 is formed on the bonding layers 11 on the opposite sides of the core layer 10 and the walls of each perforation 100. Among them, the conductive layer 52 can be a metal layer such as copper material, which is used as a barrier and a seed layer.

[0117] As Figure 4B shown, following a process similar to Figure 1B shown, however, a plurality of conductive posts 13 and support portions 21 are directly formed in each perforation 100 and fixing hole 101 to obtain the encapsulation substrate unit 5.

[0118] AsFigure 4C As shown, solder balls 19 can be bonded to the electrical contact pads 17, 18, so that the packaging substrate unit 5 is connected to an electronic device such as a semiconductor chip, a passive component, a silicon interposer, a circuit board or other components (not shown) by a plurality of solder balls 19.

[0119] Therefore, for the packaging substrate units 1, 4, 5 and their manufacturing methods of the present disclosure, the dielectric layer 150 is tightly adhered to the core layer 10 mainly by the fixing structure 2a, and the adhesion between the layers of the dielectric layer 150 is enhanced, so as to reduce the delamination risk of the dielectric layer 150 during both the production process and the reliability test.

[0120] Secondly, the number, shape and layout position of the fixing structure 2a can be configured according to the layout of the packaging substrate units 1, 4, 5. Whether it is a rivet-shaped fixing structure 2a', a grid-shaped fixing structure 2a'' or a frame-shaped fixing structure 2a''', it can surround the packaging substrate units 1, 4, 5, around the substrate strip 2 and the edges of the entire panel substrate 3 as required, achieving an excellent fastening effect.

[0121] In addition, the surface of the circuit structure 1a corresponding to the first side 10a of the core layer 10 serves as the ball mounting side to reduce the number of layers of the packaging substrate units 1, 4, 5. Therefore, compared with the prior art, the total thickness of the packaging substrate units 1, 4, 5 is beneficial to be thinned; and by simultaneously adding layers on both sides of the carrier 7, the problem of warping of the asymmetric substrate is effectively avoided, and the double production efficiency is achieved.

[0122] In addition, the present disclosure strengthens the adhesion force of the insulating layer 12 to the core layer 10 and the surface of the through hole 100 by the bonding layer 11, further avoiding the delamination problem of the insulating layer 12.

[0123] The present disclosure also provides a packaging substrate unit 1, 4, 5, including: a circuit structure 1a, a wiring structure 15 and a fixing structure 2a.

[0124] The circuit structure 1a described above includes a core layer 10 having opposite first side 10a and second side 10b, a plurality of through holes 100 connecting the first side 10a and the second side 10b, and at least one fixing hole 101, a bonding layer 11 formed on the first side 10a, the second side 10b, the wall surfaces of the through holes 100 and the fixing holes 101 of the core layer 10, a plurality of conductive posts 13 formed in each of the through holes 100, and circuit layers 14 formed on the opposite first side 10a and second side 10b of the core layer 10 and electrically connecting the conductive posts 13. Among them, the first side 10a of the circuit structure 1a corresponds to the ball mounting side, and the second side 10b corresponds to the layer adding side.

[0125] The described wiring structure 15 is disposed on the build-up side of the circuit structure 1a, and includes at least one dielectric layer 150, at least one wiring layer 151 formed on the dielectric layer 150, and a plurality of conductive blind vias 152 disposed in the dielectric layer 150, so that the conductive blind vias 152 electrically connect the wiring layer 151 and the circuit layer 14.

[0126] The described fixing structure 2a penetrates through the circuit structure 1a and the wiring structure 15, and includes a support portion 21 formed in the fixing hole 101, an extension portion 23 located in the wiring structure 15 and correspondingly formed on the support portion 21, and a plurality of fastening portions 22 formed on each of the extension portions 23 and between the support portion 21 and the extension portion 23, and the fastening portion 22 extends to a part of the dielectric layer 150 and / or the insulating layer 12.

[0127] In one embodiment, the circuit structure 1a further includes an insulating layer 12 formed on the bonding layer 11 and filled in the plurality of through holes 100 and the fixing hole 101, and the insulating layer 12 has a plurality of through holes 120 corresponding to each of the through holes 100 and a fixing through hole 121 corresponding to the fixing hole 101, so that the plurality of conductive posts 13 penetrate through the insulating layer 12 in the plurality of through holes 100, and the fixing structure 2a penetrates through the insulating layer 12 in the fixing hole 101.

[0128] In one embodiment, the circuit layer 14 on the ball-attachment side and the outermost wiring layer 151 on the build-up side respectively have a plurality of electrical contact pads 17, 18, and the width D of the plurality of electrical contact pads 18 of the outermost wiring layer 151 V is less than the width D of the plurality of electrical contact pads 17 of the circuit layer 14.

[0129] In one embodiment, the width D of the plurality of electrical contact pads 18 of the outermost wiring layer 151 V is less than the width D of the plurality of fastening portions 22 of the fixing structure 2a F .

[0130] In one embodiment, solder mask layers 16 are respectively formed on the outermost sides of the circuit structure 1a and the wiring structure 15. Among them, the plurality of electrical contact pads 17, 18 of the circuit layer 14 and the outermost wiring layer 151 are exposed from the solder mask layer 16, and the fastening portion 22 is not exposed from the solder mask layer 16. Of course, the fastening portion 22 can also be exposed from the solder mask layer 16 as needed.

[0131] In one embodiment, the bonding layer 11 is an organic coating or an inorganic coating.

[0132] In one embodiment, the material for forming the organic coating is a polymer.

[0133] In one embodiment, the polymer is selected from at least one of the group consisting of polyoxymethylene, polyamide, and parylene.

[0134] In one embodiment, the thickness of the organic coating is from 1 nanometer to 100 micrometers.

[0135] In one embodiment, the material forming the inorganic coating includes silica sand with a diameter of 20 to 50 micrometers and a roughness Ra of 1 to 200 micrometers.

[0136] In one embodiment, the insulating layers 12, 42 include a dielectric material or an ink material.

[0137] In one embodiment, the dielectric material is selected from at least one of the group consisting of polybenzoxazole (PBO), polyimide (PI), prepreg (PP), and Ajinomoto Build-up Film (ABF), and the ink material includes epoxy ink composites.

[0138] In one embodiment, the viscosity of the ink material is 25 to 55 Pa·s, and it has a glass transition temperature (Tg) of 145 to 180 °C.

[0139] In summary, in the encapsulation substrate and its manufacturing method of the present disclosure, mainly through the fixing structure, the dielectric layer is tightly adhered to the core layer. When the encapsulation substrate has multiple dielectric layers, the adhesion between the layers of the dielectric layer is enhanced, and the risk of delamination of the dielectric layer can be reduced during both the production process and the reliability test.

[0140] Secondly, the number, shape, and layout position of the fixing structure can all be configured according to the layout of the encapsulation substrate to achieve an excellent fastening effect.

[0141] Furthermore, the fixing structure of the present disclosure is applicable to various core layers and dielectric materials, without being limited by the substrate material. For example, the core layer can be made of an organic material, glass, ceramic, or any composite material that can form perforations; the dielectric layer can be made of PP, ABF film, or any composite material that can form perforations.

[0142] In addition, the present disclosure uses the circuit structure with the core layer as the ball-planting side to reduce the number of layers of the encapsulation substrate. Therefore, compared with the prior art, the total thickness of the encapsulation substrate is beneficial to be thinned; and by simultaneously adding layers on both sides of the carrier, the problem of warping of the asymmetric substrate can be effectively avoided, achieving double production efficiency.

[0143] In addition, the present disclosure further avoids the delamination problem of the insulating layer by strengthening the adhesion between the insulating layer, the core layer, and the perforated surface through the bonding layer. The above embodiments are only used to illustrate the principles and effects of the present disclosure, rather than to limit the present disclosure. Those skilled in the art can modify the above embodiments without departing from the spirit and scope of the present disclosure. Therefore, the scope of the protection of the present disclosure should be as listed in the claims.

Claims

1. A packaging substrate, characterized in that: include: A circuit structure having opposing bumping sides and build-up sides, and the circuit structure includes: A core layer having a first side and a second side opposite to each other, a plurality of through holes connecting the first side and the second side, and at least one fixing hole; A bonding layer is formed on the first side and the second side of the core layer, and on the wall surfaces of the through holes and the fixing holes; A plurality of conductive pillars formed in each of the through holes; and A circuit layer is formed on a first side and a second side of the core layer and is electrically connected to the conductive pillar, wherein the first side corresponds to the ball implantation side and the second side corresponds to the build-up layer side; a wiring structure formed on a build-up layer side of the circuit structure; and The fixing structure includes a supporting portion formed in the fixing hole and an extending portion located in the wiring structure and correspondingly formed on the supporting portion, so that the fixing structure extends from the wiring structure to penetrate the wiring structure, wherein the fixing structure is not electrically connected to the wiring layer, the conductive column and the wiring structure.

2. The packaging substrate according to claim 1, wherein: The circuit structure also includes an insulating layer formed on the bonding layer and filled into a plurality of through holes and the fixing hole, wherein a plurality of conductive columns penetrate the insulating layer in the plurality of through holes, and the fixing structure penetrates the insulating layer in the fixing hole.

3. The packaging substrate according to claim 2, wherein: The fixing structure includes a plurality of fastening parts formed on the extension part and between the support part and the extension part, and the width of the fastening part between the support part and the extension part is greater than the diameter of the support part.

4. The packaging substrate according to claim 3, characterized in that: The outermost wiring layer on the build-up layer side has a plurality of electrical contact pads, and the width of the plurality of electrical contact pads is smaller than the width of the plurality of fastening portions, and the packaging substrate also includes a plurality of solder mask layers, which are respectively formed on the outermost sides of the circuit structure and the wiring structure to cover the fastening portions of the outermost wiring layer.

5. The packaging substrate according to claim 1, wherein: The bonding layer is an organic coating or an inorganic coating, wherein the material forming the organic coating is a polymer, and the thickness of the organic coating is 1 nanometer to 100 micrometers, and the material forming the inorganic coating includes silica sand with a diameter of 20 to 50 micrometers and a roughness Ra of 1 to 200 micrometers.

6. The packaging substrate according to claim 5, characterized in that The polymer is at least one selected from the group consisting of polyoxyxylene, polyamide and polyparaxylene.

7. The packaging substrate according to claim 2, wherein: The insulating layer includes a dielectric material or an ink material.

8. The packaging substrate according to claim 7, wherein: The dielectric material is selected from at least one of the group consisting of poly(p-oxadiazole benzene), polyimide, prepreg and ABF film, and the ink material comprises epoxy ink composite material.

9. The packaging substrate according to claim 7, wherein: The ink material has a viscosity of 25 to 55 Pa.s and a glass transition temperature of 145 to 180°C.

10. The packaging substrate according to claim 1, wherein: The fixing structure is in the shape of a rivet, a grid or a frame.

11. A method for manufacturing a packaging substrate, characterized in that: include: A circuit structure is provided, having a ball implant side and a build-up layer side opposite to each other, and the circuit structure comprises: A core layer having a first side and a second side opposite to each other, a plurality of through holes connecting the first side and the second side, and at least one fixing hole; A bonding layer is formed on the first side and the second side of the core layer, and on the wall surfaces of the through holes and the fixing holes; A plurality of conductive posts formed in each of the through holes and a support portion formed in the fixing hole; and A circuit layer is formed on a first side and a second side of the core layer and electrically connected to the conductive pillar, wherein the first side corresponds to the ball implantation side and the second side corresponds to the build-up layer side; and A wiring structure is formed on the build-up layer side of the circuit structure, and an extension portion is formed in the wiring structure corresponding to the support portion to form a fixed structure extending from the circuit structure and passing through the wiring structure, including a support portion formed in the fixing hole and an extension portion located in the wiring structure and correspondingly formed on the support portion, wherein the fixed structure is not electrically connected to the circuit layer, the conductive column and the wiring structure.

12. The method for manufacturing a packaging substrate according to claim 11, wherein: The manufacturing method also includes combining the ball implanting sides of two circuit structures on opposite sides of a carrier before forming the wiring structure, and then removing the carrier after forming the wiring structure on the build-up layer side of the circuit structure to perform a singulation process to obtain multiple packaging substrates.

13. The method for manufacturing a packaging substrate according to claim 11, wherein: The steps of making the circuit structure include forming a bonding layer on the first side and the second side of the core layer, the through-holes and the wall surface of the fixing holes; forming an insulating layer on the bonding layer and filling the multiple through-holes and the fixing holes; and forming multiple conductive columns of the insulating layer passing through the multiple through-holes and forming a supporting portion of the insulating layer passing through the fixing holes.

14. The method for manufacturing a packaging substrate according to claim 11, wherein: The manufacturing method also includes forming a plurality of fastening parts on the extension part and between the support part and the extension part after forming the support part and the extension part, and the width of the fastening part between the support part and the extension part is greater than the diameter of the support part.

15. The method for manufacturing a packaging substrate according to claim 14, wherein: The outermost wiring layer on the build-up layer side has multiple electrical contact pads, and the width of the multiple electrical contact pads is smaller than the width of the multiple fastening parts. The manufacturing method also includes forming solder mask layers on the outermost sides of the circuit structure and the wiring structure to cover the fastening parts of the outermost wiring layer.

16. The method for manufacturing a packaging substrate according to claim 11, wherein: The bonding layer is an organic coating or an inorganic coating, wherein the material forming the organic coating is a polymer, and the thickness of the organic coating is 1 nanometer to 100 micrometers, and the material forming the inorganic coating includes silica sand with a diameter of 20 to 50 micrometers and a roughness Ra of 1 to 200 micrometers.

17. The method for manufacturing a packaging substrate according to claim 16, wherein: The polymer is at least one selected from the group consisting of polyoxyxylene, polyamide and polyparaxylene.

18. The method for manufacturing a packaging substrate according to claim 13, wherein: The insulating layer includes a dielectric material or an ink material.

19. The method for manufacturing a packaging substrate according to claim 18, wherein: The dielectric material is selected from at least one of the group consisting of poly(p-oxadiazole benzene), polyimide, prepreg and ABF film, and the ink material comprises epoxy ink composite material.

20. The method for manufacturing a packaging substrate according to claim 18, wherein: The ink material has a viscosity of 25 to 55 Pa.s and a glass transition temperature of 145 to 180°C.

21. The method for manufacturing a packaging substrate according to claim 11, wherein: The fixing structure is in the shape of a rivet, a grid or a frame.

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