Microelectronic assembly including solder and non-solder interconnects

Abstract

The subject matter of the invention is "microelectronic components including solder and non-solder interconnects". Microelectronic assemblies, related devices and methods are disclosed herein. In some embodiments, a microelectronic component may include a first die in a first layer, the first die having a first surface and an opposing second surface; a redistribution layer (RDL) on the first layer, wherein the RDL is electrically coupled to a second surface of the first die through a solder interconnect; and a second die in the second layer on the RDL, wherein the second die is electrically coupled to the RDL by a non-solder interconnect.

Description

This application is a divisional application of a patent application filed on August 19, 2022, with application number 202210998559.2 and invention name “Microelectronic components including solder and non-solder interconnects”. Background Art

[0001] Integrated circuit (IC) devices (e.g., dies) are often coupled together in a multi-die IC package to integrate features or functionality and facilitate connections to other components such as a package substrate. In conventional packaging, the dies may be coupled together by solder. Such packaging may be limited in the interconnect density that can be achieved by solder interconnections between dies. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The embodiments will be easily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, similar reference numerals represent similar structural elements. In the figures of the accompanying drawings, the embodiments are described by way of example rather than by way of limitation.

[0003] Figure 1 is a side cross-sectional view of an example microelectronic assembly according to various embodiments.

[0004] Figure 2 is a side cross-sectional view of an example microelectronic assembly according to various embodiments.

[0005] Figures 3A-3G According to various embodiments, Figure 1 Side cross-sectional views of various stages in an example process of microelectronic assembly.

[0006] Figures 4A-4G According to various embodiments, Figure 2 Side cross-sectional views of various stages in an example process of microelectronic assembly.

[0007] Figure 5 is a flow chart of an example method of making an example microelectronic assembly according to various embodiments.

[0008] Figure 6 is a top view of a wafer and die that can be included in a microelectronic assembly according to any of the embodiments disclosed herein.

[0009] Figure 7 is a cross-sectional side view of an IC device that can be included in a microelectronic assembly according to any of the embodiments disclosed herein.

[0010] Figure 8 is a cross-sectional side view of an IC device assembly that may include a microelectronic assembly according to any of the embodiments disclosed herein.

[0011] Fig. 9 is a block diagram of an example electrical device that may include a microelectronic assembly according to any of the embodiments disclosed herein. DETAILED DESCRIPTION

[0012] Microelectronic assemblies, related apparatus, and methods are disclosed herein. For example, in some embodiments, the microelectronic assembly may include: a first die in a first layer, the first die having a first surface and an opposing second surface; a redistribution layer (RDL) on the first layer, wherein the RDL is electrically coupled to the second surface of the first die through a solder interconnect; and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL through a non-solder interconnect.

[0013] Due to the increasingly smaller sizes of such die and the increased use of stacked die, it is challenging to pass a large number of signals between two or more die in a multi-die IC package. To achieve high interconnect density in a multi-die IC package, some conventional approaches require additional assembly operations, which increase the cost and complexity of manufacturing. The microelectronic structures and assemblies disclosed herein can achieve interconnect density as high as or higher than conventional approaches without the expense of conventional expensive manufacturing operations. In addition, the microelectronic structures and assemblies disclosed herein provide new flexibility to electronic product designers and manufacturers, allowing them to select an architecture that achieves their device goals without excess cost or manufacturing complexity.

[0014] In the following detailed description, reference is made to the accompanying drawings which form a part hereof, wherein like reference numerals denote like parts throughout, and wherein embodiments that may be implemented are shown by way of illustration. It is to be understood that other embodiments may be utilized, and that structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be construed in a limiting sense.

[0015] The various operations may be described sequentially as multiple discrete actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be considered to imply that these operations are necessarily order-dependent. In particular, these operations may not be performed in the order presented. The operations described may be performed in an order different from the described embodiments. Various additional operations may be performed and / or the operations described may be omitted in additional embodiments.

[0016] For purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The figures are not necessarily drawn to scale. Although many of the figures illustrate rectilinear structures with flat walls and right-angle corners, this is merely for ease of illustration, and actual devices made using these techniques will exhibit rounded corners, surface roughness, and other features.

[0017] The description uses the phrase "in an embodiment" or "in multiple embodiments", which can each refer to one or more embodiments in the same or different embodiments. In addition, the terms "including", "comprising", "having", etc. as used with respect to the embodiments of the present disclosure are synonymous. As used herein, "package" and "IC package" are synonymous, and "die" and "IC die" are also synonymous. The terms "top" and "bottom" may be used herein to explain various features of the figures, but these terms are merely for ease of discussion and do not imply a desired or required orientation. Unless otherwise specified, as used herein, the term "insulation" refers to "electrical insulation". Throughout the specification and in the claims, the term "coupled" refers to a direct or indirect connection, such as a direct electrical, mechanical or magnetic connection between connected things or an indirect connection through one or more passive or active intermediate devices. The meaning of "a", "an", and "said" includes plural references. The meaning of "in..." includes "in..." and "on...". Unless otherwise specified, the use of ordinal adjectives "first," "second," and "third," etc. to describe common objects merely indicates that different instances of similar objects are being referred to, and is not intended to imply that the objects so described must be in a given order in time, space, arrangement, or in any other manner.

[0018] When used to describe a range of sizes, the phrase "between X and Y" represents a range that includes X and Y. For convenience, the phrase "FIG. 3" may be used to refer to Figures 3A-3G The phrase "Figure 4" can be used to refer to a collection of figures. Figures 4A-4G Although some elements may be referred to in the singular form herein, such elements may include multiple sub-elements. For example, "insulating material" may include one or more insulating materials.

[0019] Figure 1is a side cross-sectional view of an example microelectronic assembly according to various embodiments. The microelectronic assembly 100 may include a multilayer die subassembly 104 having a first layer die 114-1 coupled by a solder interconnect 130 and a second layer die 114-2 electrically coupled by a non-solder interconnect 132. As used herein, the term "multilayer die subassembly" 104 may refer to a composite die having two or more stacked dielectric layers, with one or more die in each layer, and conductive interconnects and / or conductive pathways connecting one or more die, including die in non-adjacent layers. As used herein, the terms "multilayer die subassembly" and "composite die" may be used interchangeably. Figure 1 As shown in , the multi-layer die subassembly 104 may include a first layer 104-1 having a die 114-1 and a conductive pillar 152, a second layer 104-2 having a die 114-2 and a die 114-3, and an RDL 148 between the first layer 104-1 and the second layer 104-2, wherein the die 114-1 is electrically coupled to the RDL 148 via a solder interconnect 130 and the dies 114-2, 114-3 are electrically coupled to the RDL 148 via non-solder interconnects 132. The multi-layer die subassembly 104 may further include a die 114-4 in the first layer 104-1 within the footprint of the die 114-2, the die 114-4 having a through silicon via (TSV) 117 and electrically coupled to the RDL 148 through the solder interconnect 130. The multilayer die subassembly 104 may include a first surface 170-1 and an opposing second surface 170-2. In particular, the die 114-1, 114-4 may include a bottom surface (e.g., a surface facing the first surface 170-1) having a first conductive contact 122 and an opposing top surface (e.g., a surface facing the second surface 170-2) having a second conductive contact 124. The die 114-2, 114-3 may include the conductive contacts 122 on the bottom surface of the die (e.g., the surface facing the first surface 170-1). The RDL 148 may include a first conductive contact 172 on the bottom surface of the RDL and a second conductive contact 174 on the top surface. As used herein, a "conductive contact" may refer to a portion of a conductive material (e.g., a metal) that serves as an electrical interface between different components (e.g., a portion of a conductive interconnect); a conductive contact may be recessed into a surface of a component, flush with a surface of a component (e.g., as shown in FIG. 1 ), or may be substantially recessed from a surface of a component. Figure 2 ) or extending in a direction away from the surface of the component (e.g. Figure 1), and the conductive contact may take any suitable form (e.g., a conductive pad or socket, or a portion of a through hole or conductive line). Any conductive contact disclosed herein (e.g., conductive contacts 122, 124, 144, 146, 172, and / or 174) may include, for example, a bonding pad, a solder bump, a conductive post, or any other suitable conductive contact. Figure 1 As shown, die 114-1, 114-2, 114-3, and 114-4 are depicted as having conductive contacts extending in a direction away from the surface of the die and may be referred to herein as "bumped dies" or "micro-bumped dies." Figure 2 As shown, die 114-2, 114-3 are depicted as having conductive contacts flush with the surface of the die and may be referred to herein as "bumpless die." Die 114 may include other conductive pathways (e.g., including lines and vias) coupled to corresponding conductive contacts (e.g., conductive contacts 122, 124) on the surface of die 114 and / or to other circuitry (not shown).

[0020] The die 114-1, 114-4 in the first layer 104-1 may be coupled to the package substrate 102 through a die-to-package substrate (DTPS) interconnect 150, and may be coupled to the die 114-2, 114-3 in the second layer 104-2 through solder interconnects 130, conductive vias 196 in the RDL 148, and non-solder interconnects 132. The die 114-2, 114-3 in the second layer 104-2 may be coupled to the package substrate 102 via non-solder interconnects 132, conductive vias 196 in the RDL 148, conductive pillars 152, and DTPS interconnects 150 to form a multi-level (ML) interconnect. The ML interconnect may be a power delivery interconnect or a high-speed signal interconnect. As used herein, the term "ML interconnect" may refer to an interconnect including a conductive pillar between a first component and a second component, wherein the first component and the second component are not in adjacent layers, or the term "ML interconnect" may refer to an interconnect spanning one or more layers (e.g., an interconnect between a first die in a first layer and a second die in a third layer, or an interconnect between a package substrate and a die in a second layer). In particular, Figure 1 As shown, the DTPS interconnect 150 may include conductive contacts 146 on the top surface of the package substrate 102 , solder 134 , and conductive contacts 144 on the bottom surface of the multi-layer die subassembly 104 .

[0021] The RDL 148 may include an insulating material (e.g., a dielectric material formed in multiple layers as known in the art) and one or more conductive paths 196 (e.g., including conductive traces and / or conductive vias as shown) passing through the dielectric material. The conductive path 196 may electrically couple the first conductive contact 172 and the second conductive contact 174 on the RDL 148. In some embodiments, the insulating material of the RDL 148 may be composed of a dielectric material, a bismaleimide triazine (BT) resin, a polyimide material, an epoxy material (e.g., a glass reinforced epoxy matrix material, an epoxy deposited film, etc.), a molding material, an oxide-based material (e.g., silicon dioxide or spin-on oxide), or a low-k and ultra-low-k dielectric (e.g., a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, and an organic polymer dielectric). In some embodiments, the multi-layer die subassembly 104 may include one or more RDLs 148. In some embodiments, the one or more RDLs 148 may be at the first surface 170-1 of the first layer 104-1.

[0022] Conductive posts 152 can be formed of any suitable conductive material such as copper, silver, nickel, gold, aluminum or other metals or alloys. Conductive posts 152 can be formed using any suitable process including, for example, an additive process such as cold spray or 3D printing or a photolithography process. In some embodiments, the conductive posts 152 disclosed herein may have a spacing between 75 microns and 200 microns. As used herein, the spacing is measured center to center (e.g., from the center of the conductive post to the center of the adjacent conductive post). Conductive posts 152 can have any suitable size and shape. In some embodiments, conductive posts 152 can have a circular, rectangular or other shaped cross-section.

[0023] The tube core 114 disclosed herein may include an insulating material (e.g., a dielectric material formed in multiple layers as known in the art) and multiple conductive paths formed through the insulating material. In some embodiments, the insulating material of the tube core 114 may include a dielectric material such as silicon dioxide, silicon nitride, oxynitride, a polyimide material, a glass-reinforced epoxy resin matrix material, or a low-k or ultra-low-k dielectric (e.g., a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, an organic polymer dielectric, a photoimageable dielectric and / or a benzocyclobutene-based polymer). In some embodiments, the insulating material of the tube core 114 may include a semiconductor material such as silicon, germanium or a III-V material (e.g., gallium nitride) and one or more additional materials. For example, the insulating material may include silicon oxide or silicon nitride. The conductive paths in the tube core 114 may include conductive traces and / or conductive vias, and any conductive contacts among the conductive contacts in the tube core 114 may be connected in any suitable manner (e.g., connecting multiple conductive contacts on the same surface or different surfaces of the tube core 114). Reference is made below Figure 7 Discussion may be included in example structures in die 114 disclosed herein. Conductive paths in die 114 may be bordered with padding materials such as adhesive pads and / or barrier pads when appropriate. In some embodiments, die 114 is a wafer. In some embodiments, die 114 is a monolithic silicon, a fan-out or fan-in package die, or a die stack (e.g., wafer stacked, die stacked, or multi-layer die stacked).

[0024] In some embodiments, die 114 may include conductive pathways for routing power, ground, and / or signals to / from other die 114 included in microelectronic assembly 100. For example, die 114-1 may include TSVs (not shown) including through-holes of conductive material, such as metal vias, isolated from surrounding silicon or other semiconductor material by barrier oxides, or one or more die 114 may be “on top” of package substrate 102 and die 114-1, 114-4 (e.g., on top of the package substrate 102). Figure 1 In some embodiments, die 114-1 may not provide power and / or ground routing to die 114-2 and 114-3; instead, die 114-2, 114-3 may be directly coupled to power and / or ground lines in package substrate 102 via ML interconnects (e.g., via conductive pillars 152). In some embodiments, die 114-1 in first layer 104-1 (also referred to herein as a "base die," "interposer die," or "bridge die") may be thicker than die 114-2, 114-3 in second layer 104-2. In some embodiments, die 114 may span multiple layers of multi-layer die subassembly 104. In some embodiments, die 114-1 may be a memory device (e.g., as described below with reference to Figure 6 In some embodiments, die 114-1 may be a processing die, a radio frequency chip, a power converter, a network processor, a workload accelerator, a security encryptor, or a passive / active bridge die to provide high-bandwidth die-to-die interconnection between die 114-2 and 114-3 at low power. In some embodiments, die 114-2 and / or die 114-3 may be a processing die.

[0025] The multi-layer die subassembly 104 may include an insulating material 133 (e.g., a dielectric material formed in multiple layers as known in the art) used to form multiple layers and to embed one or more dies in the layers. In particular, the first die 114-1, 114-4 and the conductive pillar 152 may be embedded in the insulating material 133 in the first layer 104-1, and the second die 114-2 and the third die 114-3 may be embedded in the insulating material 133 in the second layer 104-2. In some embodiments, the insulating material 133 of the multi-layer die subassembly 104 may be a dielectric material, such as an organic dielectric material, a flame retardant grade 4 material (FR-4), a bismaleimide triazine (BT) resin, a polyimide material, a glass reinforced epoxy matrix material, or a low-k and ultra-low-k dielectric (e.g., a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, and an organic polymer dielectric). In some embodiments, the die 114 may be embedded in a non-uniform dielectric, such as a stacked dielectric layer (e.g., alternating layers of different inorganic dielectrics). In some embodiments, the insulating material 133 of the multilayer die subassembly 104 can be a molding material, such as an organic polymer with inorganic silica particles. The multilayer die subassembly 104 can include one or more ML interconnects (e.g., including conductive vias and / or conductive pillars as shown) passing through the dielectric material. The multilayer die subassembly 104 can have any suitable size. For example, in some embodiments, the thickness of the multilayer die subassembly 104 can be between 100 microns and 2000 microns. In some embodiments, the multilayer die subassembly 104 can include a composite die such as a stacked die. The multilayer die subassembly 104 can have any suitable number of layers, any suitable number of dies, and any suitable die arrangement. For example, in some embodiments, the multilayer die subassembly 104 can have a die layer between 3 and 20. In some embodiments, the multilayer die subassembly 104 can include a layer with a die between 2 and 50.

[0026] The package substrate 102 may include an insulating material (e.g., a dielectric material formed in multiple layers as known in the art) and one or more conductive paths (e.g., including conductive traces and / or conductive vias as shown) for routing power, ground, and signals through the dielectric material. In some embodiments, the insulating material of the package substrate 102 may be a dielectric material such as an organic dielectric material, a flame retardant grade 4 material (FR-4), a BT resin, a polyimide material, a glass-reinforced epoxy matrix material, an organic dielectric with an inorganic filler, or a low-k and ultra-low-k dielectric (e.g., a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, and an organic polymer dielectric). In particular, when the package substrate 102 is formed using a standard printed circuit board (PCB) process, the package substrate 102 may include FR-4, and the conductive paths in the package substrate 102 may be formed by patterned copper sheets separated by buildup layers of FR-4. The conductive paths in the package substrate 102 may be bordered by a pad material such as an adhesive pad and / or a barrier pad when appropriate. In some embodiments, the packaging substrate 102 may be formed using a lithographically defined through-hole packaging process. In some embodiments, the packaging substrate 102 may be manufactured using a standard organic packaging manufacturing process, and thus the packaging substrate 102 may take the form of an organic package. In some embodiments, the packaging substrate 102 may be a set of redistribution layers formed on a panel carrier by laminating or spin coating on a dielectric material and creating conductive vias and lines by laser drilling and plating. In some embodiments, the packaging substrate 102 may be formed on a removable carrier using any suitable technology such as redistribution layer technology. Any method known in the art for making the packaging substrate 102 may be used, and for the sake of brevity, such methods will not be discussed in further detail herein.

[0027] In some embodiments, the package substrate 102 may be a lower density medium, and the die 114 may be a higher density medium or have an area with a higher density medium. As used herein, the terms "lower density" and "higher density" are relative terms, indicating that the conductive paths (e.g., including conductive interconnects, conductive lines, and conductive vias) in the lower density medium are larger and / or have a larger spacing than the conductive paths in the higher density medium. In some embodiments, a higher density medium may be manufactured using a semi-additive stacking process or a modified semi-additive process with advanced photolithography (with small vertical interconnect features formed by advanced laser or photolithography processes), while the lower density medium may be a PCB manufactured using a standard PCB process (e.g., a standard subtractive process using etching chemistry to remove areas of unwanted copper, and having rough vertical interconnect features formed by a standard laser process). In other embodiments, a semiconductor manufacturing process such as a single damascene process or a dual damascene process may be used to manufacture a higher density medium. In some embodiments, an additional die may be disposed on the top surface of the die 114-2, 114-3. In some embodiments, an additional component may be disposed on the top surface of the die 114-2, 114-3. Additional passive components such as surface mount resistors, capacitors, and / or inductors may be disposed on the top or bottom surface of the package substrate 102 or embedded in the package substrate 102 .

[0028] Figure 1 The microelectronic assembly 100 may also include an underfill material 127. In some embodiments, the underfill material 127 may extend around the associated DTPS interconnect 150 between the multi-layer die subassembly 104 and the package substrate 102. In some embodiments, the underfill material 127 may extend around the associated solder interconnect 130. The underfill material 127 may be an insulating material, such as a suitable epoxy material. In some embodiments, the underfill material 127 may include a capillary underfill, a non-conductive film (NCF), or a molded underfill. In some embodiments, the underfill material 127 may include an epoxy flux that assists in soldering the multi-layer die subassembly 104 to the package substrate 102 when forming the DTPS interconnect 150 and then polymerizes and encapsulates the DTPS interconnect 150. The underfill material 127 may be selected to have a coefficient of thermal expansion (CTE) that may alleviate or minimize stress between the die 114 and the package substrate 102 caused by uneven thermal expansion in the microelectronic assembly 100. In some embodiments, the CTE of the underfill material 127 may have a value intermediate the CTE of the package substrate 102 (eg, the CTE of the dielectric material of the package substrate 102 ) and the CTE of the die 114 and / or the insulating material 133 of the multilayer die subassembly 104 .

[0029] The DTPS interconnects 150 disclosed herein may take any suitable form. In some embodiments, a set of DTPS interconnects 150 may include solder (e.g., solder bumps or balls that are subject to thermal reflow to form DTPS interconnects 150). In some embodiments, a set of DTPS interconnects 150 may include an anisotropic conductive material, such as an anisotropic conductive film or an anisotropic conductive paste. An anisotropic conductive material may include a conductive material dispersed in a non-conductive material.

[0030] The solder interconnect 130 disclosed herein can take any suitable form. In the microelectronic assembly, the solder interconnect 130 can have a finer pitch than the DTPS interconnect 150. In some embodiments, the solder interconnect 130 can include a small conductive bump (e.g., a copper bump) attached to the conductive contact 124 by solder. In some embodiments, the solder interconnect 130 disclosed herein can have a pitch between 10 microns and 100 microns. In some embodiments, the diameter of the solder is equal to about half of the minimum pitch. The solder interconnect 130 can have a pitch that is too fine to be directly coupled to the package substrate 102 (e.g., too fine to be used as a DTPS interconnect 150). In some embodiments, the solder interconnect 130 can be used as a data transfer channel, and the DTPS interconnect 150 can also be used for power lines and ground lines. In some embodiments, the solder interconnect 130 in the microelectronic assembly 100 can be a solder interconnect including a solder having a higher melting point than the solder included in some or all of the DTPS interconnect 150. For example, when forming the solder interconnect 130 in the microelectronic assembly 100 before forming the DTPS interconnect 150, the solder interconnect 130 may use a higher temperature solder (e.g., wherein the melting point is above 200 degrees Celsius), while the DTPS interconnect 150 may use a lower temperature solder (e.g., wherein the melting point is below 200 degrees Celsius). In some embodiments, the higher temperature solder may include: tin; tin and gold; or tin, silver, and copper (e.g., 96.5% tin, 3% silver, and 0.5% copper). In some embodiments, the lower temperature solder may include tin and bismuth (e.g., eutectic tin-bismuth) or tin, silver, and bismuth. In some embodiments, the lower temperature solder may include indium, indium and tin, or gallium.

[0031] The non-solder interconnects 132 disclosed herein can take any suitable form. In a microelectronic assembly, the non-solder interconnects 132 can have a finer pitch than the DTPS interconnects 150. In some embodiments, some or all of the non-solder interconnects 132 in the microelectronic assembly 100 can be metal-to-metal interconnects (e.g., copper-to-copper interconnects, or electroplated interconnects). In some embodiments, the non-solder interconnects 132 disclosed herein can have a pitch between 50 microns and 150 microns.

[0032] In the microelectronic assembly 100 disclosed herein, some or all of the DTPS interconnects 150 may have a larger pitch than some or all of the solder interconnects 130. The solder interconnects 130 may have a smaller pitch than the DTPS interconnects 150 due to the greater similarity of materials between the die 114 and the package substrate 102 on both sides of a set of DTPS interconnects 150 than between the die 114 and the RDL 148. In particular, differences in the material composition of the package substrate 102 and the die 114 may result in differential expansion and contraction of the package substrate 102 and the die 114 due to heat generated during operation (as well as heat applied during various manufacturing operations). To mitigate damage (e.g., cracking, solder bridging, etc.) caused by such differential expansion and contraction, the DTPS interconnects 150 may be formed larger and with a larger pitch than the solder interconnects 130, which may experience less thermal stress due to the greater material similarity of the die 114 and the RDL 148. In some embodiments, the DTPS interconnects 150 disclosed herein may have a pitch between 100 microns and 350 microns.

[0033] Figure 1 The microelectronic assembly 100 may also include a circuit board (not shown). The package substrate 102 may be coupled to the circuit board via a second level interconnect at the bottom surface of the package substrate 102. The second level interconnect may be any suitable second level interconnect, including solder balls for a ball grid array arrangement, pins in a pin grid array arrangement, or pads in a pad grid array arrangement. The circuit board may be, for example, a motherboard and may have other components attached to it. As is known in the art, the circuit board may include conductive pathways and other conductive contacts for routing power, ground, and signals through the circuit board. In some embodiments, the second level interconnect may not couple the package substrate 102 to the circuit board, but instead may couple the package substrate 102 to another IC package, an interposer, or any other suitable component. In some embodiments, the multilayer die subassembly 104 may not be coupled to the package substrate 102, but instead may be coupled to a circuit board such as a PCB.

[0034] although Figure 1 The multi-layer die subassembly 104 is depicted with a particular number of dies 114 coupled to the package substrate 102 and to other dies 114, but this number and arrangement is merely illustrative and the multi-layer die subassembly 104 may include any desired number and arrangement of dies 114 coupled to the package substrate 102. Figure 1Dies 114-1, 114-4 are shown as double-sided dies and dies 114-2, 114-3 are shown as single-sided dies, but die 114 can be a single-sided die or a double-sided die and can be a single-pitch die or a mixed-pitch die. In some embodiments, additional components can be disposed on the top surface of die 114-2 and / or 114-3. In this context, a double-sided die refers to a die having connections on both surfaces. In some embodiments, a double-sided die can include TSVs (e.g., TSV 117 in die 114-4) to form connections on both surfaces. Depending on the design and electrical requirements, the active surface of the double-sided die can face either direction, and the active surface is the surface containing the majority of the interconnects in one or more active devices and interconnects.

[0035] Figure 1 Many of the elements of the microelectronic assembly 100 are included in other figures in the drawings; the discussion of these elements will not be repeated when discussing these figures, and any of these elements can take any of the forms disclosed herein. In addition, multiple elements are included in other figures in the drawings; Figure 1 100, but a plurality of these elements may not be present in the microelectronic assembly 100. For example, in various embodiments, the die 114-4, the underfill material 127, and the package substrate 102 may not be included. In some embodiments, each of the microelectronic assemblies 100 disclosed herein may be used as a system-in-package (SiP), including a plurality of dies 114 having different functionalities. In such an embodiment, the microelectronic assembly 100 may be referred to as a SiP.

[0036] Figure 2 1 is a side cross-sectional view of an example microelectronic assembly according to various embodiments. The microelectronic assembly 100 may include a multi-layer die subassembly 104 having a first layer die 114-1 coupled by a solder interconnect 130 and a second layer die 114-2 electrically coupled by a non-solder interconnect 132. Figure 2As shown, the multi-layer die subassembly 104 may include a first layer 104-1 having a die 114-1 and conductive pillars 152, a second layer 104-2 having dies 114-2, 114-3 that are bumpless dies, and an RDL 148 between the first layer 104-1 and the second layer 104-2, wherein the die 114-1 is electrically coupled to the RDL 148 via solder interconnects 130 and the dies 114-2, 114-3 are electrically coupled to the RDL 148 via non-solder interconnects 132. In particular, the dies 114-2, 114-3 may include conductive contacts 122 on a bottom surface that are recessed or flush with the bottom surface such that the dies 114-2, 114-3 are bumpless dies. The die 114-1 in the first layer 104-1 may be coupled to the package substrate 102 through a die-to-package substrate (DTPS) interconnect 150, and may be coupled to the die 114-2, 114-3 in the second layer 104-2 through solder interconnects 130, conductive vias 196 in the RDL 148, and non-solder interconnects 132. The die 114-2, 114-3 in the second layer 104-2 may be coupled to the package substrate 102 via non-solder interconnects 132, conductive vias 196 in the RDL 148, conductive pillars 152, and DTPS interconnects 150.

[0037] Any suitable technique may be used to manufacture the microelectronic assembly 100 disclosed herein. For example, Figures 3A-3G According to various embodiments, Figure 1 100 of an example process of a microelectronic assembly 100. Although described in a particular order below with reference to Figures 3A-3G (and other figures in the drawings representing the manufacturing process), but these operations can be performed in any suitable order. In addition, additional operations not described can also be performed without departing from the scope of the present disclosure. Moreover, the descriptions herein about Figures 3A-3G Various of the operations discussed are used to fabricate other portions of the microelectronic assemblies 100 disclosed herein.

[0038] Figure 3AThe assembly is illustrated after mounting dies 114-2, 114-3 on a carrier 105, the dies 114-2, 114-3 having surfaces with conductive contacts 122 facing away from the carrier 105. The dies 114-2, 114-3 may be placed using any suitable method, such as automated pick and place. The carrier 105 may include any suitable material for providing mechanical stability during manufacturing operations, and in some embodiments may include a semiconductor wafer (e.g., a silicon wafer) or glass (e.g., a glass panel). The dies 114-2, 114-3 may have a die-to-die gap 119 between 1 micron and 100 microns.

[0039] Figure 3B The assembly after depositing insulating material 133 on and around the tube core 114-2, 114-3 and planarizing the top surface of the assembly to reduce the thickness (e.g., z-height) of the conductive contacts 122 and / or the insulating material 133 to form the second layer 104-2 is illustrated. The insulating material 133 can be a molding material, such as an organic polymer with inorganic silicon dioxide particles, an epoxy resin material, or a silicon and nitrogen material (e.g., in the form of silicon nitride). In some embodiments, the insulating material 133 is a dielectric material. In some embodiments, the dielectric material may include an organic dielectric material, a flame retardant grade 4 material (FR-4), a BT resin, a polyimide material, a glass reinforced epoxy resin matrix material, or a low-k and ultra-low-k dielectric (e.g., a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, and an organic polymer dielectric). The insulating material 133 can be formed using any suitable process including lamination, or slit coating and curing. In some embodiments, insulating material 133 may be spread in liquid form to flow around and conform to various shapes of components and metallizations, and insulating material 133 may then be subjected to a curing process, such as solidifying insulating material 133. In some embodiments, insulating material 133 may initially be deposited on and above the top surface of die 114-2, 114-3, and then polished back to expose the top surface of conductive contacts 122 on die 114-2, 114-3. Insulating material 133 may be removed using any suitable technique, including grinding or etching, such as wet etching, dry etching (e.g., plasma etching), wet jetting, or laser ablation (e.g., using an excimer laser). In some embodiments, the thickness of insulating material 133 may be minimized to reduce the required etching time. In some embodiments, any suitable process, such as chemical mechanical polishing (CMP), may be used to flatten the top surface of insulating material 133.

[0040] Figure 3C It explains Figure 3BThe RDL 148 is formed on the top surface of the component and the component after forming the non-solder interconnect 132. The RDL 148 may include a conductive path 196 between the first conductive contact 172 and the second conductive contact 174 on the RDL 148. The RDL 148 may be manufactured using any suitable technology, such as PCB technology or redistribution layer technology.

[0041] Figure 3D It explains Figure 3C The component after depositing a conductive material such as copper on the top surface of the component to generate the conductive pillar 152. The conductive pillar 152 can be formed on the conductive contact 174 on the RDL 148 and electrically coupled to the conductive contact 174 on the RDL 148. The conductive pillar 152 can be formed using any suitable technology such as an additive process such as cold spray or 3-dimensional printing or a photolithography process. The conductive pillar 152 can have any suitable size. In some embodiments, the conductive pillar 152 can span one or more layers. For example, in some embodiments, a single conductive pillar 152 can have an aspect ratio (height: diameter) between 1:1 and 4:1 (e.g., between 1:1 and 3:1). In some embodiments, a single conductive pillar 152 can have a diameter (e.g., a cross section) between 10 microns and 150 microns. For example, a single conductive pillar 152 can have a diameter between 50 microns and 100 microns. In some embodiments, a single conductive pillar 152 can have a height (e.g., z-height or thickness) between 50 microns and 150 microns. The conductive pillar 152 may have any suitable cross-sectional shape, such as square, triangle, and oval.

[0042] Figure 3E It is described that the tube core 114-1, 114-4 is placed Figure 3D 1, 114-4 and the assembly after solder interconnects 130 are formed between conductive contacts 172 on the dies 114-1, 114-4 and the RDL 148. The dies 114-1, 114-4 may be placed using any suitable method, such as automated pick and place. The dies 114-1, 114-4 may include first conductive contacts 122 and second conductive contacts 124. The die 114-4 may further include TSVs 117. In some embodiments, the first conductive contacts 122 may be formed on the dies 114-1, 114-4 after the dies 114-1, 114-4 are placed on the assembly. In some embodiments, the first conductive contacts 122 may be formed on the dies 114-1, 114-4 before the dies 114-1, 114-4 are placed on the assembly. Figure 3EThe assembly may be subjected to a solder reflow process during which solder components of the solder interconnects 130 melt and bond to mechanically and electrically couple the dies 114 - 1 , 114 - 4 to the RDL 148 .

[0043] Figure 3F The assembly is illustrated after insulating material 133 is deposited on and around die 114-1, 114-4 and conductive pillars 152 to form first layer 104-1. Insulating material 133 may include any suitable material and may be formed and removed using any suitable process, including as described above with reference to Figure 3B In some embodiments, the insulating material 133 in the first layer 104-1 (e.g., Figure 3F ) is deposited in the second layer 104-2 and is separated from the insulating material 133 (e.g. Figure 3B In some embodiments, the insulating material 133 in the first layer 104-1 (e.g., Figure 3F ) is deposited in the second layer 104-2 and is separated from the insulating material 133 (e.g. Figure 3B 1, 114-4). In some embodiments, the bottom fill 127 can be spread around the solder interconnect 130 before the insulating material 133 is deposited. In some embodiments, the bottom fill 127 around the solder interconnect 130 can be omitted. In some embodiments, the insulating material 133 can be initially deposited on and over the top surfaces of the conductive pillars 152 and the tube cores 114-1, 114-4, and then polished back to expose the top surfaces of the conductive pillars 152 and the first conductive contacts 122 on the tube cores 114-1, 114-4. If the insulating material 133 is formed to completely cover the tube cores 114-1, 114-4 and the conductive pillars 152, the insulating material 133 can be removed using any suitable technique, including grinding or etching, such as wet etching, dry etching (e.g., plasma etching), wet spraying, or laser ablation (e.g., using an excimer laser). In some embodiments, the thickness of the insulating material 133 can be minimized to reduce the required etching time. In some embodiments, the top surface of the insulating material 133 can be planarized using any suitable process such as CMP. In some embodiments, Figure 3F Additional RDL (not shown) is formed on the top surface of the component. The additional RDL may be formed using any suitable process, such as the process described above with reference to Figure 3C Process described.

[0044] Figure 3G Describes the components that follow the following actions: Figure 3F The assembly is inverted, the carrier 105 is removed and then Figure 3GFinishing operations are performed on the bottom surface of the component, such as forming conductive contacts 144, depositing solder resist (not shown), and depositing solder 134 on the bottom surface (e.g., at first surface 170-1). If multiple components are manufactured together, the components can be singulated after removing carrier 105. As shown in the figure, Figure 3G The component itself can be a microelectronic component 100. Figure 3G Further manufacturing operations are performed on the microelectronic assembly 100 to form other microelectronic assemblies 100; for example, Figure 1 Similar to the microelectronic assembly 100, solder 134 may be used to interconnect the microelectronic assembly 100 via the DTPS interconnect 150. Figure 3G The microelectronic assembly 100 is coupled to a package substrate 102 .

[0045] Figures 4A-4G According to various embodiments, Figure 2 1 is a side cross-sectional view of an example microelectronic assembly 100 at various stages during the process. Figure 4A The assembly is illustrated after the die 114-2, 114-3 are mounted on a first carrier 105-1, the first carrier 105-1 having a surface with conductive contacts 122 facing the first carrier 105-1. The die 114-2, 114-3 may be placed using any suitable method, such as automated pick and place. The carrier 105 may include any suitable material for providing mechanical stability during manufacturing operations, and in some embodiments, may include a semiconductor wafer (e.g., a silicon wafer) or glass (e.g., a glass panel). The die 114-2, 114-3 may have a die-to-die gap 119 between 1 micron and 100 microns.

[0046] Figure 4B The assembly is illustrated after depositing insulating material 133 on and around die 114-2, 114-3 and planarizing the top surfaces of die 114-2, 114-3 and insulating material 133 to form second layer 104-2. Insulating material 133 may include any suitable material and may be formed and removed using any suitable process, including as described above with reference to FIG.

[0047] Figure 4C The second carrier 105-2 is mounted on Figure 3B The assembly after removing the first carrier 105 - 1 and turning the assembly over is shown on the top surface of the assembly.

[0048] Figure 4D Explained in Figure 4CThe component after forming RDL 148 on the top surface of the component and forming non-solder interconnect 132. In some embodiments, any suitable process may be used to clean and planarize the component. Figure 4C The top surface of the component of the RDL 148 is polished, for example, by a dry or wet process to remove adhesive residues, followed by mechanical grinding and CMP to create an ultra-smooth, flat die surface for forming the RDL 148. The RDL 148 may include a conductive via 196 between the first conductive contact 172 and the second conductive contact 174 on the RDL 148. The RDL 148 may be manufactured using any suitable technology, such as a PCB technology or a redistribution layer technology.

[0049] Figure 4E It explains Figure 4D 14-1 and the RDL 148. The assembly after depositing a conductive material such as copper on the top surface of the assembly to generate the conductive pillars 152, placing the die 114-1, and forming the solder interconnects 130 between the die 114-1 and the RDL 148. In particular, the conductive contacts 124 on the die 114-1 can be coupled to the conductive contacts 172 on the RDL 148 by solder to form the solder interconnects 130. The die 114-1 can further include conductive contacts 122. In some embodiments, the conductive contacts 122 can be formed on the die 114-1 after the die is placed on the assembly. In some embodiments, the first conductive contacts 122 can be formed on the die 114-1 before the die is placed on the assembly. Figure 4E The assembly may be subjected to a solder reflow process during which the solder components of the solder interconnect 130 melt and combine to mechanically and electrically couple the die 114-1 to the RDL 148. The conductive pillars 152 may be formed using any suitable technique, such as an additive process such as cold spray or 3-dimensional printing, or a photolithography process. The conductive pillars 152 may have any suitable size. The die 114-1 may be placed using any suitable method, such as automated pick and place. The conductive pillars may be formed using any suitable method, such as described above with reference to FIG. 3 .

[0050] Figure 4F 1 and 152 to form the first layer 104-1. The insulating material 133 may include any suitable material and may be formed and removed using any suitable process, including as described above with reference to FIG. 3. In some embodiments, the insulating material 133 in the first layer 104-1 (e.g., Figure 4F ) is deposited in the second layer 104-2 and is separated from the insulating material 133 (e.g. Figure 4B In some embodiments, the insulating material 133 in the first layer 104-1 (e.g., Figure 4F ) is deposited in the second layer 104-2 and is separated from the insulating material 133 (e.g. Figure 4B In some embodiments, the bottom fill 127 may be spread around the solder interconnect 130 before the insulating material 133 is deposited. In some embodiments, the bottom fill 127 around the solder interconnect 130 may be omitted. In some embodiments, the bottom fill 127 around the solder interconnect 130 may be omitted. Figure 4F Additional RDL (not shown) is formed on the top surface of the component. The additional RDL may be formed using any suitable process, such as the process described above with reference to Figure 4D Describe the process.

[0051] Figure 4G Describes the components that follow the following actions: Figure 4F The assembly is inverted, the second carrier 105-2 is removed and the Figure 4G Finishing operations are performed on the bottom surface of the component, such as forming conductive contacts 144, depositing solder resist (not shown), and depositing solder 134 on the bottom surface (e.g., at first surface 170-1). If multiple components are manufactured together, the components can be singulated after removing second carrier 105-2. As shown in the figure, Figure 4G The component itself can be a microelectronic component 100. Figure 4G Further manufacturing operations are performed on the microelectronic assembly 100 to form other microelectronic assemblies 100; for example, Figure 2 Similar to the microelectronic assembly 100, solder 134 may be used to interconnect the microelectronic assembly 100 via the DTPS interconnect 150. Figure 4G The microelectronic assembly 100 is coupled to a package substrate 102 .

[0052] Figure 5 1 is a flow chart of an example method of making an example microelectronic assembly according to various embodiments. At 502, the second layer of dies 114-2, 114-3 can be attached to the carrier 105, with the conductive contacts 122 facing away from the carrier 105. The second layer of dies 114-2, 114-3 can be encapsulated with an insulating material 133 and planarized before being attached to the carrier 105 (e.g., as shown in FIG. 1 ). Figures 4A-4C ), or the second layer dies 114 - 2 , 114 - 3 may be packaged and planarized after being attached to the carrier 105 (e.g., as shown in Figure 3A and 3B shown).

[0053] At 504 , an RDL 148 is formed on the top surface of the second tier dies 114 - 2 , 114 - 3 , and the conductive contacts 174 on the RDL 148 are electrically coupled to the conductive contacts 122 on the second tier dies 114 - 2 , 114 - 3 through the non-solder interconnects 132 .

[0054] At 506 , a conductive pillar 152 is formed on a top surface of the RDL 148 , and the conductive pillar 152 is electrically coupled to a conductive contact 172 on the RDL 148 through a non-solder interconnect.

[0055] At 508, the first layer die 114-1 is attached to the top surface of the RDL 148, and the conductive contacts 172 on the RDL 148 are electrically coupled to the conductive contacts 124 on the first layer die 114-1 through the solder interconnects 130. An underfill 127 may be provided around the solder interconnects 130. The underfill process may include dispensing the underfill material in liquid form, allowing the material to flow and fill the gaps around the solder interconnects 130, and subjecting the assembly to a curing process such as baking to solidify the material.

[0056] At 510, insulating material 133 may be disposed over the first layer of dies and conductive pillars 152 using any suitable method such that insulating material 133 encapsulates first layer of dies 114-1 and conductive pillars 152. CMP or any other suitable process may be used to planarize the top surface of insulating material 133. The grinding (also referred to as back grinding) process may substantially planarize and / or smooth the top surface of the assembly, for example to enable proper attachment of a heat sink or other component. In some embodiments, additional RDLs may be formed on the top surface of the insulating material encapsulating the first layer of dies.

[0057] At 512, carrier 105 may be separated using any suitable process and surface finishing operations may be performed. In some embodiments, surface finishing operations may be performed prior to removing carrier 105. Surface finishing operations may include, for example, forming conductive contacts 144, spreading solder resist, and attaching solder balls 134 at a bottom surface of the multi-layer die assembly (e.g., at first surface 170-1).

[0058] The microelectronic assembly 100 disclosed herein can be used for any suitable application. For example, in some embodiments, the microelectronic assembly 100 can be used to enable very small form factor voltage regulation for field programmable gate arrays (FPGAs) or processing units (e.g., central processing units, graphics processing units, FPGAs, modems, application processors, etc.) used in mobile devices and small form factor devices, in particular. In another example, the die 114 in the microelectronic assembly 100 can be a processing device (e.g., central processing unit, graphics processing unit, FPGA, modem, application processor, server processor, etc.).

[0059] The microelectronic assembly 100 disclosed herein may be included in any suitable electronic component. Figure 6-9 Various examples of devices that may be included in or in any of the microelectronic assemblies 100 disclosed herein are described.

[0060] Figure 6 1 is a top view of die 1502 and wafer 1500 that may be included in any of the microelectronic assemblies 100 disclosed herein (e.g., any suitable die in die 114). Wafer 1500 may be constructed of semiconductor material and may include one or more die 1502 having IC structures formed on a surface of wafer 1500. Each of die 1502 may be a repeating unit of a semiconductor product including any suitable IC. After fabrication of the semiconductor product is completed, wafer 1500 may undergo a singulation process in which die 1502 are separated from one another to provide discrete “chips” of a semiconductor product. Die 1502 may be any of the die 114 disclosed herein. Die 1502 may include one or more transistors (e.g., as discussed below) Figure 7 Some of the transistors 1640 of the present invention), supporting circuit systems for routing electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other IC components. In some embodiments, wafer 1500 or die 1502 may include memory devices (e.g., random access memory (RAM) devices, such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive bridge RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit elements. Multiple of these devices may be combined on a single die 1502. For example, a memory array formed of multiple memory devices may be formed in conjunction with a processing device (e.g., Fig. 9The microelectronic components 100 disclosed herein may be fabricated using die-to-wafer assembly techniques, in which some of the dies 114 are attached to a wafer 1500 including other dies in the dies 114, and the wafer 1500 is subsequently singulated.

[0061] Figure 7 1 is a cross-sectional side view of an IC device 1600 that can be included in any microelectronic assembly 100 disclosed herein (e.g., in any die in die 14). One or more of the IC devices 1600 can be included in one or more die 1502 ( Figure 6 IC device 1600 may be formed on a die substrate 1602 (eg, Figure 6 of wafer 1500) and may be included in a die (e.g. Figure 6 The die 1502). The die substrate 1602 can be a semiconductor substrate composed of a semiconductor material system including, for example, an n-type or p-type material system (or a combination of the two). The die substrate 1602 can include, for example, a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the die substrate 1602 can be formed using alternative materials that may or may not be combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Additional materials classified as Group II-VI, Group III-V, or Group IV can also be used to form the die substrate 1602. Although several examples of materials that can form the die substrate 1602 are described herein, any material that can serve as the basis for the IC device 1600 can be used. The die substrate 1602 can be a die that has been cut into individual pieces (e.g., Figure 6 of a tube die 1502) or a wafer (e.g. Figure 6 A portion of chip 1500).

[0062] IC device 1600 may include one or more device layers 1604 disposed on a die substrate 1602. Device layer 1604 may include features of one or more transistors 1640 (e.g., metal oxide semiconductor field effect transistors (MOSFETs)) formed on die substrate 1602. Device layer 1604 may include, for example, one or more source and / or drain (S / D) regions 1620, a gate 1622 for controlling the flow of current in transistor 1640 between S / D regions 1620, and one or more S / D contacts 1624 for routing electrical signals to and / or from S / D regions 1620. Transistor 1640 may include additional features not depicted for clarity, such as device isolation regions, gate contacts, and the like. Transistor 1640 is not limited to Figure 7 The types and configurations depicted in the drawings and may include a variety of other types and configurations, such as, for example, planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include FinFET transistors such as dual-gate transistors or tri-gate transistors and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors.

[0063] Each transistor 1640 may include a gate 1622 formed by at least two layers (gate dielectric and gate electrode). The gate dielectric may include a layer or a stack of layers. One or more layers may include silicon oxide, silicon dioxide, silicon carbide and / or high-k dielectric materials. High-k dielectric materials may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium and zinc. Examples of high-k materials that can be used in gate dielectrics include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminate oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanate, barium titanium oxide, strontium titanate oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide and lead niobium zinc oxide. In some embodiments, when using high-k materials, an annealing process may be performed on the gate dielectric to improve its quality.

[0064] The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 1640 is to be a PMOS transistor or an NMOS transistor. In some implementations, the gate electrode may be composed of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. For other purposes, additional metal layers, such as barrier layers, may be included. For PMOS transistors, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any metal discussed below with reference to the NMOS transistor (e.g., for work function tuning). For NMOS transistors, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any metal discussed above with reference to the PMOS transistor (e.g., for work function tuning).

[0065] In some embodiments, when viewed as a cross-section of transistor 1640 along the source-channel-drain direction, the gate electrode may be comprised of a U-shaped structure including a bottom portion substantially parallel to the surface of die substrate 1602 and two sidewall portions substantially perpendicular to the top surface of die substrate 1602. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of die substrate 1602 and not including sidewall portions substantially perpendicular to the top surface of die substrate 1602. In other embodiments, the gate electrode may be comprised of a combination of U-shaped structures and planar non-U-shaped structures. For example, the gate electrode may be comprised of one or more U-shaped metal layers formed atop one or more planar non-U-shaped layers.

[0066] In some embodiments, a pair of sidewall spacers may be formed on opposite sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed of materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and typically include deposition and etching process steps. In some embodiments, multiple pairs of spacers may be used; for example, two, three, or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.

[0067] The S / D region 1620 may be formed within the die substrate 1602 adjacent to the gate 1622 of each transistor 1640. For example, the S / D region 1620 may be formed using an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion implanted into the die substrate 1602 to form the S / D region 1620. An annealing process to activate the dopants and cause them to diffuse further into the die substrate 1602 may follow the ion implantation process. In the latter process, the die substrate 1602 may first be etched to form a recess at the location of the S / D region 1620. An epitaxial deposition process may then be performed to fill the recess with the material used to make the S / D region 1620. In some implementations, the S / D region 1620 may be made using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with a dopant such as boron, arsenic, or phosphorus. In some embodiments, one or more alternative semiconductor materials such as germanium or a III-V material or alloy may be used to form S / D region 1620. In other embodiments, S / D region 1620 may be formed using one or more layers of metal and / or metal alloy.

[0068] The device layer 1604 may be provided with one or more interconnect layers (in Figure 7 The interconnect layers 1606-1610 (illustrated in the figure as interconnect layers 1606-1610) route electrical signals, such as power and / or input / output (I / O) signals, to and / or from devices (e.g., transistors 1640) of the device layer 1604. For example, conductive features (e.g., gates 1622 and S / D contacts 1624) of the device layer 1604 may be electrically coupled to interconnect structures 1628 of the interconnect layers 1606-1610. One or more interconnect layers 1606-1610 may form a metallization stack (also referred to as an "ILD stack") 1619 of the IC device 1600.

[0069] Interconnect structures 1628 may be arranged within interconnect layers 1606-1610 to route electrical signals according to a variety of designs; in particular, the arrangements are not limited to Figure 7 Although the specific configuration of interconnect structure 1628 is depicted in Figure 7 A particular number of interconnect layers 1606 - 1610 are depicted in FIG. 1 , but embodiments of the present disclosure include IC devices having more or fewer interconnect layers than depicted.

[0070] In some embodiments, the interconnect structure 1628 may include vias 1628b and / or wires 1628a filled with a conductive material such as metal. The wires 1628a may be arranged to route electrical signals in a direction substantially parallel to a plane of the surface of the die substrate 1602 on which the device layer 1604 is formed. For example, Figure 7 From the perspective of FIG. 16A , wires 1628a may route electrical signals in a direction into and out of the page. Vias 1628b may be arranged to route electrical signals in a direction substantially perpendicular to the plane of the surface of die substrate 1602 on which device layer 1604 is formed. In some embodiments, vias 1628b may electrically couple wires 1628a of different interconnect layers 1606-1610 together.

[0071] like Figure 7 As shown, interconnect layers 1606-1610 may include dielectric material 1626 disposed between interconnect structures 1628. In some embodiments, dielectric material 1626 disposed between interconnect structures 1628 in different interconnect layers of interconnect layers 1606-1610 may have different compositions; in other embodiments, the composition of dielectric material 1626 between different interconnect layers 1606-1610 may be the same.

[0072] A first interconnect layer 1606 (referred to as metal 1 or "M1") may be formed directly on the device layer 1604. In some embodiments, as shown, the first interconnect layer 1606 may include wires 1628a and / or vias 1628b. The wires 1628a of the first interconnect layer 1606 may be coupled to contacts of the device layer 1604 (e.g., S / D contacts 1624).

[0073] A second interconnect layer 1608 (referred to as metal 2 or "M2") may be formed directly on the first interconnect layer 1606. In some embodiments, the second interconnect layer 1608 may include vias 1628b for coupling lines 1628a of the second interconnect layer 1608 with lines 1628a of the first interconnect layer 1606. Although the lines 1628a and vias 1628b are structurally depicted using lines within each interconnect layer (e.g., within the second interconnect layer 1608) for clarity, in some embodiments the lines 1628a and vias 1628b may be structurally and / or materially contiguous (e.g., filled simultaneously during a dual damascene process).

[0074] A third interconnect layer 1610 (referred to as Metal 3 or "M3") (and additional interconnect layers as desired) may be formed successively on the second interconnect layer 1608 according to similar techniques and configurations as described with respect to the second interconnect layer 1608 or the first interconnect layer 1606. In some embodiments, the interconnect layers "higher up" in the metallization stack 1619 in the IC device 1600 (i.e., farther away from the device layer 1604) may be thicker.

[0075] IC device 1600 may include solder resist material 1634 (e.g., polyimide or similar material) and one or more conductive contacts 1636 formed on interconnect layers 1606-1610. Figure 7 , the conductive contacts 1636 are illustrated as taking the form of bonding pads. The conductive contacts 1636 may be electrically coupled to the interconnect structure 1628, and the conductive contacts 1636 may be configured to route the electrical signals of the transistor(s) 1640 to other external devices. For example, a solder joint may be formed on one or more of the conductive contacts 1636 to mechanically and / or electrically couple the chip including the IC device 1600 to another component (e.g., a circuit board). The IC device 1600 may include additional or alternative structures to route electrical signals from the interconnect layers 1606-1610; for example, the conductive contacts 1636 may include other similar features (e.g., terminals) that route electrical signals to external components.

[0076] In some embodiments where IC device 1600 is a double-sided die (e.g., such as die 114-1), IC device 1600 may include another metallization stack (not shown) on the opposite side of device layer(s) 1604. This metallization stack may include multiple interconnect layers as discussed above with reference to interconnect layers 1606-1610 to provide conductive pathways (e.g., including conductive lines and vias) between device layer(s) 1604 and additional conductive contacts (not shown) on the side of IC device 1600 opposite conductive contacts 1636.

[0077] In other embodiments in which the IC device 1600 is a double-sided die (e.g., such as die 114-1), the IC device 1600 may include one or more TSVs extending through the die substrate 1602; these TSVs may contact the device layer(s) 1604 and may provide a conductive path between the device layer(s) 1604 and additional conductive contacts (not shown) on a side of the IC device 1600 opposite the conductive contact 1636.

[0078] Figure 817 is a cross-sectional side view of an IC device assembly 1700 that may include any of the microelectronic assemblies 100 disclosed herein. In some embodiments, the IC device assembly 1700 may be the microelectronic assembly 100. The IC device assembly 1700 includes a plurality of components disposed on a circuit board 1702 (which may be, for example, a motherboard). The IC device assembly 1700 includes components disposed on a first side 1740 of the circuit board 1702 and an opposing second side 1742 of the circuit board 1702; typically, the components may be disposed on one or both of the sides 1740 and 1742. Any of the IC packages discussed below with reference to the IC device assembly 1700 may take the form of any suitable embodiment of the embodiments of the microelectronic assembly 100 disclosed herein.

[0079] In some embodiments, circuit board 1702 may be a PCB including multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally along with other metal layers) between components coupled to circuit board 1702. In other embodiments, circuit board 1702 may be a non-PCB substrate. In some embodiments, circuit board 1702 may be, for example, a circuit board.

[0080] Figure 8 The IC device assembly 1700 illustrated in FIG. 1 includes a package-on-interposer structure 1736 coupled to a first side 1740 of a circuit board 1702 via a coupling component 1716. The coupling component 1716 can electrically and mechanically couple the package-on-interposer structure 1736 to the circuit board 1702 and can include solder balls (e.g., Figure 8 as shown), protrusions and recesses of the socket, adhesives, bottom fill materials and / or any other suitable electrical and / or mechanical coupling structures.

[0081] Package-on-interposer structure 1736 may include IC package 1720 coupled to interposer 1704 via coupling component 1718. Coupling component 1718 may take any form suitable for the application, such as the forms discussed above with reference to coupling component 1716. Figure 8 1704, but multiple IC packages may be coupled to interposer 1704; in fact, additional interposers may be coupled to interposer 1704. Interposer 1704 may provide an intermediate substrate for bridging circuit board 1702 and IC package 1720. IC package 1720 may be or include, for example, a die ( Figure 6 1502), IC devices (e.g. Figure 71600) or any other suitable component. In general, interposer 1704 can extend connections to a wider pitch or reroute connections to different connections. For example, interposer 1704 can couple IC package 1720 (e.g., die) to a set of ball grid array (BGA) conductive contacts of coupling component 1716 for coupling to circuit board 1702. Figure 8 1704, IC package 1720 and circuit board 1702 are attached to opposite sides of interposer 1704; in other embodiments, IC package 1720 and circuit board 1702 may be attached to the same side of interposer 1704. In some embodiments, three or more components may be interconnected by way of interposer 1704.

[0082] In some embodiments, the interposer 1704 may be formed as a PCB including multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. In some embodiments, the interposer 1704 may be formed of epoxy, glass fiber reinforced epoxy, epoxy with inorganic fillers, ceramic material, or polymer material such as polyimide. In some embodiments, the interposer 1704 may be formed of alternative rigid or flexible materials, which may include the same materials described above for semiconductor substrates, such as silicon, germanium, and other III-V and IV materials. The interposer 1704 may include metal interconnects 1708 and vias 1710, including but not limited to TSVs 1706. The interposer 1704 may further include embedded devices 1714, including both passive devices and active devices. Such devices may include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices, such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices, may also be formed on interposer 1704. Package-on-interposer structure 1736 may take the form of any package-on-interposer structure known in the art.

[0083] IC device assembly 1700 may include an IC package 1724 coupled to first side 1740 of circuit board 1702 via coupling component 1722. Coupling component 1722 may take the form of any of the embodiments discussed above with reference to coupling component 1716, and IC package 1724 may take the form of any of the embodiments discussed above with reference to IC package 1720.

[0084] Figure 81700 includes a package-on-package structure 1734 coupled to a second side 1742 of a circuit board 1702 via a coupling component 1728. The package-on-package structure 1734 may include an IC package 1726 and an IC package 1732 coupled together via a coupling component 1730 such that the IC package 1726 is disposed between the circuit board 1702 and the IC package 1732. The coupling components 1728 and 1730 may take the form of any of the embodiments of the coupling component 1716 discussed above, and the IC packages 1726 and 1732 may take the form of any of the embodiments of the IC package 1720 discussed above. The package-on-package structure 1734 may be configured according to any of the package-on-package structures known in the art.

[0085] Fig. 9 1 is a block diagram of an example electrical device 1800 that may include one or more of the microelectronic assemblies 100 disclosed herein. For example, any suitable component of the components of the electrical device 1800 may include one or more of the IC device assembly 1700, IC device 1600, or die 1502 disclosed herein, and may be arranged in any of the microelectronic assemblies 100 disclosed herein. Fig. 9 1800, but any one or more of these components may be omitted or duplicated to suit the application. In some embodiments, some or all of the components included in the electrical device 1800 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated on a single system-on-chip (SoC) die.

[0086] Additionally, in various embodiments, the electrical device 1800 may not include Fig. 9 1800, but the electrical device 1800 may include interface circuitry for coupling to one or more of the components. For example, the electrical device 1800 may not include the display device 1806, but may include display device interface circuitry (e.g., connector and driver circuitry) to which the display device 1806 may be coupled. In another set of examples, the electrical device 1800 may not include the audio input device 1824 or the audio output device 1808, but may include audio input or output device interface circuitry (e.g., connector and supporting circuitry) to which the audio input device 1824 or the audio output device 1808 may be coupled.

[0087] The electrical device 1800 may include a processing device 1802 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory to transform that electronic data into other electronic data that can be stored in registers and / or memory. The processing device 1802 may include one or more digital signal processors (DSPs), application specific ICs (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (special processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing devices. The electrical device 1800 may include a memory 1804, which may itself include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard drive. In some embodiments, the memory 1804 may include a memory that shares a die with the processing device 1802. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

[0088] In some embodiments, the electrical device 1800 may include a communication chip 1812 (e.g., one or more communication chips). For example, the communication chip 1812 may be configured to manage wireless communications for transferring data to and from the electrical device 1800. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can transfer data through a non-solid medium by using modulated electromagnetic radiation. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not contain any wires.

[0089] The communication chip 1812 may implement any of a plurality of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 amendments), Long Term Evolution (LTE) projects together with any amendments, updates and / or revisions (e.g., Advanced LTE projects, Ultra Mobile Broadband (UMB) projects (also referred to as "3GPP2"), etc.). IEEE 802.16-compliant broadband wireless access (BWA) networks are commonly referred to as WiMAX networks, the acronym stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that have passed conformance and interoperability testing of the IEEE 802.16 standards. The communication chip 1812 may operate according to a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 1812 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 1812 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO), and any other wireless protocols derived therefrom and designated as 3G, 4G, 5G, and beyond. In other embodiments, the communication chip 1812 may operate in accordance with other wireless protocols. The electrical device 1800 may include an antenna 1822 to facilitate wireless communications and / or receive other wireless communications (such as AM or FM radio transmissions).

[0090] In some embodiments, the communication chip 1812 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, the communication chip 1812 may include multiple communication chips. For example, the first communication chip 1812 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and the second communication chip 1812 may be dedicated to longer-range wireless communications such as global positioning systems (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, the first communication chip 1812 may be dedicated to wireless communications, and the second communication chip 1812 may be dedicated to wired communications.

[0091] The electrical device 1800 may include a battery / power circuit system 1814. The battery / power circuit system 1814 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuit systems for coupling components of the electrical device 1800 to an energy source separate from the electrical device 1800 (e.g., AC line power).

[0092] The electrical device 1800 may include a display device 1806 (as discussed above, or corresponding interface circuitry). The display device 1806 may include any visual indicator, such as a heads-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0093] The electrical device 1800 may include an audio output device 1808 (as discussed above, or corresponding interface circuitry). The audio output device 1808 may include any device that generates an audible indicator, such as a speaker, headphones, or earbuds.

[0094] The electrical device 1800 may include an audio input device 1824 (as discussed above, or corresponding interface circuitry). The audio input device 1824 may include any device that generates a signal representative of sound, such as a microphone, a microphone array, or a digital instrument (e.g., an instrument with a Musical Instrument Digital Interface (MIDI) output).

[0095] The electrical device 1800 may include a GPS device 1818 (as discussed above, or corresponding interface circuitry). As is known in the art, the GPS device 1818 may communicate with a satellite-based system and may receive the location of the electrical device 1800.

[0096] The electrical device 1800 may include other output devices 1810 (as discussed above, or corresponding interface circuitry). Examples of other output devices 1810 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or additional storage.

[0097] The electrical device 1800 may include other input devices 1820 (as discussed above, or corresponding interface circuitry). Examples of other input devices 1820 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a barcode reader, a quick response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0098] The electrical device 1800 may have any desired form factor, such as a computing device or a handheld, portable or mobile computing device (e.g., a cell phone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, etc.), a desktop electrical device, a server, or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the electrical device 1800 may be any other electronic device that processes data.

[0099] The following paragraphs provide various examples of the embodiments disclosed herein.

[0100] Example 1 is a microelectronic assembly comprising: a first die in a first layer, the first die having a first surface and an opposing second surface; a redistribution layer (RDL) on the first layer, wherein the RDL is electrically coupled to the second surface of the first die via a solder interconnect; and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL via a non-solder interconnect.

[0101] Example 2 may include the subject matter of Example 1, and may further provide that the first die is electrically coupled to the second die via solder interconnects, conductive vias in the RDL, and non-solder interconnects.

[0102] Example 3 may include the subject matter of Example 1 or 2, and may further specify that the non-solder interconnect comprises a metal-to-metal interconnect.

[0103] Example 4 may include the subject matter of any of Examples 1-3, and may further provide that the pitch of the solder interconnects is between 10 microns and 100 microns.

[0104] Example 5 may include the subject matter of any of Examples 1-4, and may further provide that the pitch of the non-solder interconnect is between 50 microns and 150 microns.

[0105] Example 6 may include the subject matter of any of Examples 1-5, and may further provide that the first layer and the second layer include one or more insulating materials.

[0106] Example 7 may include the subject matter of any of Examples 1 to 6, and may further provide that the solder interconnect is a first solder interconnect, and the microelectronic assembly may further include a packaging substrate electrically coupled to the first surface of the first die through a second solder interconnect.

[0107] Example 8 may include the subject matter of any of Examples 1 to 7, and may further provide that the non-solder interconnect is a first non-solder interconnect, and the microelectronic assembly may further include a conductive post in the first layer, wherein the conductive post is coupled to the RDL through a second non-solder interconnect.

[0108] Example 9 may include the subject matter of any of Examples 1 to 8, and may further include a third die in the first layer within the footprint of the second die, the third die having a first surface, an opposing second surface, and a through substrate via (TSV) between the first surface and the second surface, wherein the third die is electrically coupled to the RDL via a solder interconnect.

[0109] Example 10 is a microelectronic assembly comprising: a first die in a first layer, the first die having a first surface with a first conductive contact and an opposite second surface with a second conductive contact; a redistribution layer (RDL) on the first layer, the redistribution layer (RDL) having a first surface with a third conductive contact and an opposite second surface with a fourth conductive contact, wherein the third conductive contact on the RDL is electrically coupled to the second conductive contact on the first die via a solder interconnect; and a second die in a second layer on the second surface of the RDL, the second die having a surface with a fifth conductive contact, wherein the fifth conductive contact on the second die is electrically coupled to the fourth conductive contact on the RDL via a non-solder interconnect.

[0110] Example 11 may include the subject matter of Example 10, and may further provide that the fifth conductive contact is recessed or flush with a surface of the second die.

[0111] Example 12 may include the subject matter of Example 10 or 11, and may further provide that the fifth conductive contact extends in a direction away from the surface of the second die.

[0112] Example 13 may include the subject matter of any of Examples 10 to 12, and may further provide that the first die is electrically coupled to the second die via solder interconnects, conductive vias in the RDL, and non-solder interconnects.

[0113] Example 14 may include the subject matter of any of Examples 10 to 13, and may further specify that the non-solder interconnect comprises a metal-to-metal interconnect.

[0114] Example 15 may include the subject matter of any of Examples 10 to 14, and may further provide that the pitch of the solder interconnects is between 10 microns and 100 microns.

[0115] Example 16 may include the subject matter of any of Examples 10 to 15, and may further provide that the pitch of the non-solder interconnect is between 50 microns and 150 microns.

[0116] Example 17 may include the subject matter of any of Examples 10 to 16, and may further provide that the solder interconnect is a first solder interconnect, and the microelectronic assembly may further include a packaging substrate electrically coupled to the first conductive contact of the first die through a second solder interconnect.

[0117] Example 18 may include the subject matter of any of Examples 10 to 17, and may further include a conductive pillar in the first layer, wherein the conductive pillar is coupled to a corresponding one of third conductive contacts on the RDL through a non-solder interconnect.

[0118] Example 19 may include the subject matter of any of Examples 10 to 18, and may further provide that the non-solder interconnect is a first non-solder interconnect, and the microelectronic assembly may further include a third die in the second layer, the third die having a surface with a sixth conductive contact, wherein the sixth conductive contact on the third die is electrically coupled to a fourth conductive contact on the RDL via a second non-solder interconnect.

[0119] Example 20 may include the subject matter of Example 19, and may further provide that the first die is electrically coupled to the third die via a solder interconnect, a conductive via in the RDL, and a second non-solder interconnect.

[0120] Example 21 is a method for manufacturing a microelectronic component, comprising: encapsulating a first die having a first conductive contact and a second die having a second conductive contact with an insulating material and exposing the first conductive contact and the second conductive contact; forming a redistribution layer (RDL) on the first die and the second die and electrically coupling the RDL to the first conductive contact and the second conductive contact through a non-solder interconnect; attaching a third die having a third conductive contact to the RDL and electrically coupling a third conductive contact on the third die to the RDL through a solder interconnect; and forming an insulating material around the third die.

[0121] Example 22 may include the subject matter of Example 21, and may further provide that the first conductive contact is recessed or flush with a surface of the first die.

[0122] Example 23 may include the subject matter of Example 21 or 22, and may further provide that the first conductive contact extends from a surface of the first die.

[0123] Example 24 may include the subject matter of any of Examples 21 to 23, and may further include forming a conductive pillar on the RDL before forming the insulating material around the third die; and forming the insulating material around the conductive pillar and the third die.

Claims

1. A microelectronic assembly comprising: a first die having a first surface and an opposing second surface; a plurality of conductive contacts on the first surface of the first die, wherein the first surface of the first die is between the second surface and the plurality of conductive contacts; a plurality of solder balls coupled to the plurality of conductive contacts, wherein one of the solder balls is directly on the first die; a redistribution layer (RDL) coupled to the plurality of solder balls, wherein the RDL is electrically coupled to the first die through the plurality of conductive contacts and the plurality of solder balls; and A second die is on the RDL, wherein the second die is electrically coupled to the RDL by a non-solder interconnect.

2. The microelectronic assembly of claim 1, wherein: The plurality of conductive contacts are in contact with the first surface of the first die.

3. The microelectronic assembly of claim 1, wherein: The plurality of conductive contacts are electrically coupled to the first die.

4. The microelectronic assembly of claim 1, wherein: The RDL includes a plurality of metal layers.

5. The microelectronic assembly of claim 4, wherein: The RDL includes three metal layers.

6. The microelectronic assembly of claim 1, wherein: The non-solder interconnect includes a second plurality of conductive contacts along a lower surface of the second die.

7. The microelectronic assembly of claim 1, wherein: The non-solder interconnects include bump pads or conductive pillars.

8. The microelectronic assembly of claim 1, wherein: The non-solder interconnect comprises gold.

9. The microelectronic assembly of claim 1, wherein: The first die is in a first layer, the first layer further comprising an insulating material surrounding the first die.

10. A microelectronic assembly comprising: a first layer, the first layer comprising a first die; a second layer, the second layer comprising a second die; a redistribution layer RDL between the first layer and the second layer, the RDL having a first surface and a second surface opposite to the first surface, the first surface being between the first die and the second surface; a plurality of solder balls coupled between the first surface and the first layer of the RDL; electrically coupling the plurality of solder balls and a plurality of conductive contacts of the second die; as well as A plurality of non-solder interconnects electrically couple the second die to the second surface of the RDL.

11. The microelectronic assembly of claim 10, wherein: The second layer further includes a third die, and the third die is electrically coupled to the RDL through a non-solder interconnect.

12. The microelectronic assembly of claim 11, wherein: The third die is adjacent to the second die.

13. The microelectronic assembly of claim 12, wherein: The third die is laterally spaced apart from the second die.

14. The microelectronic assembly of claim 11, wherein: The third die is stacked on the second die.

15. The microelectronic assembly of claim 10, further comprising a molding material surrounding the first die.

16. The microelectronic assembly of claim 10, wherein: The first die has an upper surface and a lower surface, the upper surface is between the RDL and the lower surface, and the plurality of conductive contacts are in contact with the upper surface of the first die.

17. The microelectronic assembly of claim 10, wherein: The plurality of solder balls are between the first die and the RDL.

18. A package comprising: Circuit boards; as well as an assembly coupled to the circuit board, the assembly comprising: a first die having a first surface and a second surface opposite the first surface; a plurality of electrically conductive contacts on the first surface of the first die and electrically coupled to the first die; a plurality of solder balls connected to the plurality of conductive contacts, wherein the plurality of solder balls are directly on the first die; a redistribution layer (RDL) having a first side and a second side opposite the first side, the first side of the RDL being coupled to the plurality of solder balls; a second die on the RDL; and The second die is coupled to a plurality of non-solder interconnects of the second side of the RDL.

19. The package of claim 18, wherein: The plurality of solder balls is a first plurality of solder balls, and the package further includes a second plurality of solder balls coupling the component to the circuit board.

20. The package of claim 19, wherein: The first die is between the first plurality of solder balls and the second plurality of solder balls.

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