An asymmetric trigger switch surge absorbing chip and a preparation method thereof

Abstract

The application relates to the technical field of semiconductor chips, in particular to an asymmetric trigger switch surge absorption chip and a preparation method thereof. The profile structure along the width direction is left-right symmetrical structure, meanwhile, the A surface structure and the B surface structure are upper-lower asymmetrical, the trigger switch has the trigger tube characteristics and the solid discharge tube characteristics, and the trigger switch is a two-end negative resistance bidirectional trigger switch based on the thyristor principle structure. The structure chip has a wide trigger voltage range, a large voltage difference span in different directions and can be adjusted according to requirements. The voltage of the structure chip is very low in the conduction state, a large current can be passed instantaneously, and once the conduction is realized, the self-locking state is formed. The chip is turned off only when the current flowing through the chip is interrupted or less than the turn-off current.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor chips, and in particular to an asymmetric trigger switch surge absorption chip and a preparation method thereof. Background Art

[0002] Transient interference is a common electronic circuit malfunction phenomenon, manifesting primarily as transient interference signals such as surge voltage, ringing voltage, and spark discharges. These interference signals are characterized by extremely short durations, high voltage amplitudes, and high transient energy, severely impacting electronic equipment, especially control systems. To ensure the proper operation of electronic equipment, effective transient interference suppression measures must be implemented. Transient interference comes from a variety of sources, including natural electromagnetic radiation, power grid fluctuations, and device switching. When these interferences act on the control system's power supply voltage, they cause voltage fluctuations, which in turn affect the control system's stability. In severe cases, transient interference can even damage internal control system equipment, leading to safety incidents.

[0003] Currently, commonly used semiconductor components use solutions such as transient voltage suppressors and discharge tubes. However, with the high-density integration of communication signal transmission circuits, the requirements for voltage control are constantly increasing, and the requirements for differential overvoltage control in different directions are required. Existing devices cannot fully meet these requirements. Therefore, the present invention proposes an asymmetric device, which can provide a better solution. Summary of the Invention

[0004] To address the above-mentioned issues, the present invention provides an asymmetric trigger switch surge absorption chip and its preparation method. The chip has a wide trigger voltage range of 8V-330V, and the conduction voltage difference in different directions can be controlled between 20V-300V, with a large span that can be adjusted as required. The surge current in one cycle can reach 20A-200A. It can also discharge a fully charged capacitor through an inductor, generating a high-energy, high-voltage pulse. The chip has a specific negative resistance characteristic. In the on-state, the voltage is very low, only about 1.5V, allowing for a large current to pass instantly. Once turned on, it is in a self-locking state and will only shut down when the current flowing through it is interrupted or less than the shutdown current. The chip has a response speed of less than 1ns.

[0005] In order to achieve the above objectives, the present invention is implemented through the following technical solutions:

[0006] An asymmetric trigger switch surge absorption chip, whose cross-sectional structure includes a first conductive type substrate, wherein two surfaces of the first conductive type substrate are defined as surface A and surface B respectively;

[0007] Four first heavily doped regions of the second conductivity type are arranged in an array in the A surface, two first doped regions of the first conductivity type are arranged axially and symmetrically outside the two first heavily doped regions of the second conductivity type at the periphery, respectively, without being connected, the third doped regions of the second conductivity type are arranged between the four first heavily doped regions of the second conductivity type, the fifth doped regions of the second conductivity type are arranged in the third doped regions of the second conductivity type between the two first heavily doped regions of the second conductivity type at the periphery, respectively, and are connected to the two first heavily doped regions of the second conductivity type at the periphery, and two first emission regions are arranged axially and symmetrically outside the two first heavily doped regions of the second conductivity type at the periphery, respectively, and are connected.

[0008] Four second heavily doped regions of the second conductivity type are arranged in an array on the first heavily doped region of the first conductivity type in the B surface, two second doped regions of the first conductivity type are arranged axially and symmetrically outside the two second heavily doped regions of the second conductivity type at the periphery, respectively, without being connected, the fourth doped regions of the second conductivity type are arranged between the four second heavily doped regions of the second conductivity type, the sixth doped regions of the second conductivity type are arranged in the fourth doped regions of the second conductivity type between the two second heavily doped regions of the second conductivity type at the periphery, respectively, and are connected to the two second heavily doped regions of the second conductivity type at the periphery, and two second emission regions are arranged axially and symmetrically outside the two second heavily doped regions of the second conductivity type at the periphery, respectively, and are connected.

[0009] Further, in the B surface, the doping depths of the second heavily doped regions of the second conductivity type, the fourth doped regions of the second conductivity type, the first heavily doped region of the first conductivity type, the sixth doped regions of the second conductivity type, and the second doped regions of the first conductivity type decrease in turn; the doping depth of the second emission region is the same as that of the second doped region of the first conductivity type.

[0010] In the A surface, the doping depths of the first heavily doped regions of the second conductivity type, the third doped regions of the second conductivity type, the fifth doped regions of the second conductivity type, and the first doped regions of the first conductivity type decrease in turn; the doping depth of the first emission region is the same as that of the first doped region of the first conductivity type.

[0011] Further, the width of the fifth doped region of the second conductivity type is 3%-5% of the total width of the chip; the width of the sixth doped region of the second conductivity type is 30%-40% of the total width of the chip.

[0012] Further, the interval between the two second heavily doped regions of the second conductivity type at the periphery of the B surface is wider than the interval between the two first heavily doped regions of the second conductivity type at the periphery of the A surface.

[0013] The spacing between the two second conductive type second heavily doped regions on the periphery of the B surface is equal to the spacing between the two second conductive type first heavily doped regions on the periphery of the A surface and corresponds in spatial position.

[0014] Furthermore, the two first conductive type second doping regions on the B surface correspond to the two first conductive type first doping regions on the A surface in spatial position.

[0015] Furthermore, the widths of the two outer second conductivity type first heavily doped regions of the A surface are wider than the widths of the two inner second conductivity type first heavily doped regions;

[0016] The widths of the two second conductive type second heavily doped regions on the outer periphery of the B surface are wider than the widths of the two second conductive type second heavily doped regions on the inner periphery. The specific dimensions of the above chips need to be specifically designed according to the device size and electrical requirements.

[0017] Furthermore, a first metal electrode is connected to the outside of the A surface; a second metal electrode is connected to the outside of the B surface; an insulating layer is connected to both sides of the first metal electrode; and an insulating layer is connected to both sides of the second metal electrode.

[0018] Furthermore, when the first conductivity type is an N-type dopant element, the second conductivity type is a P-type dopant element; and when the first conductivity type is a P-type dopant element, the second conductivity type is an N-type dopant element. For example, when a P-type substrate is selected, all first conductivity types within the surface are P-type, and all second conductivity types are N-type; when an N-type substrate is selected, all first conductivity types within the surface are N-type, and all second conductivity types are P-type.

[0019] The method for preparing the above-mentioned asymmetric trigger switch surge absorption chip comprises the following steps:

[0020] S1. Thinning or etching the first conductive type substrate, marking one of its surfaces, where the marked surface is defined as surface A and the unmarked surface is defined as surface B;

[0021] S2, then performing an oxidation treatment to form an oxide layer on both surfaces, and performing a first conductivity type implantation on the entire surface of the B surface to form a first conductivity type heavily doped region in the B surface;

[0022] S3, then performing oxidation treatment to thicken the surface oxide layer, performing photolithography treatment on both sides as required to define the diffusion area, and then performing second conductivity type diffusion to form four second conductivity type first heavily doped regions distributed in an array on the A surface, and four second conductivity type second heavily doped regions distributed in an array on the B surface;

[0023] S4, then perform oxidation treatment again, perform photolithography treatment on both sides simultaneously as required to define the implantation area, and then perform second conductivity type implantation to form three second conductivity type third doping regions in the A surface and three second conductivity type fourth doping regions in the B surface;

[0024] S5, then perform high temperature push-in (i.e. thermal annealing) treatment;

[0025] S6. Perform photolithography on both surfaces simultaneously as required to define diffusion regions for first conductivity type pre-diffusion and first conductivity type re-diffusion, thereby forming two first emitter regions and two first conductivity type first doped regions in the A surface, and forming two second emitter regions and two first conductivity type second doped regions in the B surface;

[0026] S7. Perform photolithography on both surfaces simultaneously as required to define a diffusion region for second conductivity type diffusion, forming a second conductivity type fifth doping region in the A surface and a second conductivity type sixth doping region in the B surface;

[0027] S8, CVD deposition of an insulating layer;

[0028] S9. Remove the insulating layer in the electrode area, and then perform metallization treatment to obtain a first metal electrode on the A surface and a second metal electrode on the B surface.

[0029] Furthermore, in S1, the resistivity of the first conductive type substrate is in the range of 0.002Ω·cm-50Ω·cm, and the thinning process or the etching process is performed until the thickness of the first conductive type substrate is 150μm-270μm.

[0030] Furthermore, the oxidation treatment in S2 is: treating at a temperature of 900° C. to 1100° C. for 1 h to 3 h in an oxygen atmosphere;

[0031] The oxidation treatment in S3 is: introducing hydrogen and oxygen with a volume ratio of 3:2 at a temperature of 900° C.-1100° C. for 3 h-8 h;

[0032] The oxidation treatment in S4 is: introducing hydrogen and oxygen with a volume ratio of 3:2 at a temperature of 900° C.-1100° C. for 3 h-8 h;

[0033] The temperature of the high-temperature push-bonding treatment in S5 is 900° C.-1255° C. and the time is 3 h-24 h.

[0034] Furthermore, the conditions for the first conductive type implantation in S2 are: energy 80KEV-120KEV, dose 1×10 14 -1×1016 / cm 3 ;

[0035] The second conductive type diffusion in S3 is carried out in a diffusion furnace, a second conductive type compound is carried into the diffusion furnace by nitrogen, and diffusion is carried out at a temperature of 900-1100℃ for 0.5-5h to make the sheet resistance of the diffusion area 0.2-10Ω;

[0036] The second conductive type implantation in S4 is carried out at an energy of 80-120KEV and a dose of 1×1013-1×1014 / cm2. 14 -1×1014 / cm2 16 / cm 3 ;

[0037] The first conductive type pre-diffusion in S6 is to uniformly glue a first conductive type doped latex source material to the diffusion area, and diffusion is carried out at a temperature of 850-1100℃ to make the sheet resistance of the diffusion area 1-15Ω.

[0038] The first conductive type re-diffusion in S6 is carried out at a high temperature of 900-1255℃ for 1-10h.

[0039] The second conductive type diffusion in S7 is carried out in a diffusion furnace, a second conductive type compound is carried into the diffusion furnace by nitrogen, and diffusion is carried out at a temperature of 900-1100℃ for 0.5-5h to make the sheet resistance of the diffusion area 0.2-10Ω;

[0040] Further, the structure of the insulation layer in S8 is a composite layer structure composed of a SIPOS layer and a silicon dioxide layer, wherein the SIPOS layer is laminated on the surface of the substrate, and the silicon dioxide layer is laminated on the surface of the SIPOS layer; the formation conditions of the SIPOS layer are as follows: in a low-pressure furnace tube, at a temperature of 550-700℃, SiH4 and N2O with a volume ratio of 1.5-3:1 are introduced, and the SIPOS layer with a thickness of 0.5-2μm is deposited under a vacuum pressure of 100-500mTorr;

[0041] The formation conditions of the silicon dioxide layer are as follows: in a low-pressure furnace tube, at a temperature of 600-800℃, tetraethyl orthosilicate is introduced, and the silicon dioxide layer with a thickness of 0.8-1.5μm is deposited under a vacuum pressure of 200-500mTorr.

[0042] Beneficial technical effects:

[0043] (1) The trigger voltage of the present application is high and wide, which can reach 8-330V at present;

[0044] (2) The present application has negative resistance characteristics, and the voltage in the on state is very low, only about 1.5V, so that a larger current can be passed instantaneously;

[0045] (3) The present application is a very symmetrical bidirectional trigger device, and the voltage difference in different directions can be controlled between 20V-300V, with a large span, which can be adjusted as required, and the surge current in one cycle can reach 20A-200A, or the capacitor full of electricity can be discharged through inductance to generate high-energy high-voltage pulse;

[0046] (4) Once the present application is turned on, it is in a self-locking state, and only when the current flowing through it is interrupted or less than the off current, it will be turned off;

[0047] (5) The structure chip of the present application has fast response speed, less than 1ns;

[0048] (6) The structure chip of the present application has flexible and diverse packaging forms, and can adopt various semiconductor packaging such as axial, patch, ITO, SOD, etc., which can be single-chip packaging or multi-chip packaging;

[0049] (7) The structure chip of the present application adopts planar multi-structure passivation process, has good high-temperature resistance and high reliability. BRIEF DESCRIPTION OF DRAWINGS

[0050] Figure 1 It is a structure schematic diagram of the asymmetric trigger switch surge absorption chip of Example 1;

[0051] Figure 2 It is the structure obtained after S1-S2 in the chip preparation process of Example 2;

[0052] Figure 3 It is the structure obtained after S1-S3 in the chip preparation process of Example 2;

[0053] Figure 4 It is the structure obtained after S1-S4 in the chip preparation process of Example 2;

[0054] Figure 5 It is the structure obtained after S1-S6 in the chip preparation process of Example 2;

[0055] Figure 6 It is the structure obtained after S1-S7 in the chip preparation process of Example 2;

[0056] Figure 7 It is the structure obtained after S1-S8 in the chip preparation process of Example 2;

[0057] Wherein, 101-P type substrate, 102-first N type heavily doped region, 103-third N type doped region, 104-first emission region, 105-first P type doped region, 106-fifth N type doped region, 107-P type heavily doped region, 108-fourth N type doped region, 109-second emission region, 110-second P type doped region, 111-sixth N type doped region, 112-second N type heavily doped region, 113-first metal electrode, 114-second metal electrode, 115-insulating layer, 1151-SIPOS layer, 1152-silicon dioxide layer. DETAILED DESCRIPTION

[0058] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the embodiments of the present application and the drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. The following description of at least one exemplary embodiment is merely illustrative in nature and not intended to be limiting on the application or its applications or uses. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of the present application.

[0059] Unless otherwise specifically explained, the numerical values set forth in these embodiments do not limit the scope of the present application. Techniques and methods known to those of ordinary skill in the relevant art can not be discussed in detail, but should be considered as part of the specification where appropriate. In all examples shown and discussed herein, any specific value should be interpreted as merely exemplary, and not as a limitation. Therefore, other examples of the exemplary embodiments can have different values.

[0060] In addition, it should be noted that the use of the words "first", "second", and the like to define doped regions, emitters, and the like is merely for the convenience of distinguishing the structure, and the above words have no special meaning unless otherwise stated. Therefore, it cannot be understood as a limitation on the scope of protection of the present application.

[0061] The experimental methods not specified in the following embodiments are generally determined according to the national standard; if there is no corresponding national standard, it is carried out according to the general standard requirement or general method.

[0062] Embodiment 1

[0063] An asymmetric trigger switch surge absorption chip, its cross-sectional structure along the length direction is an asymmetric structure from top to bottom, its cross-sectional structure along the width direction is a symmetric structure from left to right, its cross-sectional structure is as shown in Figure 1 The P-type substrate 101 defines two surfaces as A surface and B surface, respectively.

[0064] Four first N-type heavily doped regions 102 are arranged in an array within the A surface. Two first P-type doped regions 105 are arranged axially symmetrically and non-connected outside the two first N-type heavily doped regions 102 distributed on the periphery. A third N-type doped region 103 is arranged between the four first N-type heavily doped regions 102. A fifth N-type doped region 106 is arranged within the third N-type doped region 103 distributed between the two inner first N-type heavily doped regions 102. The fifth N-type doped region 106 is connected to the two inner first N-type heavily doped regions 102. Two first emitter regions 104 are arranged axially symmetrically and connected outside the two inner first N-type heavily doped regions 102. Within the A surface, the doping depths of the first N-type heavily doped region 102, the third N-type doped region 103, the fifth N-type doped region 106, and the first P-type doped region 105 decrease in sequence. The doping depth of the first emitter region 104 is the same as that of the first P-type doped region 105.

[0065] There are four second N-type heavily doped regions 112 distributed in an array in the B surface, two second P-type doped regions 110 are respectively arranged axially symmetrically and non-connected outside the two second N-type heavily doped regions 112 distributed on the periphery, and two P-type heavily doped regions 107 are respectively arranged axially symmetrically and connected outside the two second N-type heavily doped regions 112 distributed on the periphery, the depth of the P-type heavily doped region 107 is deeper than the depth of the second P-type doped region 110, and a fourth N-type doped region is filled between the four second N-type heavily doped regions 112

[0066] 108, a sixth N-type doping region 111 is provided in the fourth N-type doping region 108 distributed between the two inner second N-type heavily doped regions 112, the sixth N-type doping region 111 is connected to the two inner second N-type heavily doped regions 112, and two second emitter regions 109 are respectively provided axially symmetrically outside the two inner second N-type heavily doped regions 112; within the B surface: the doping depths of the second N-type heavily doped region 112, the fourth N-type doping region 108, the P-type heavily doped region 107, the sixth N-type doping region 111, and the second P-type doping region 110 decrease in sequence; the doping depth of the second emitter region 109 is the same as that of the second P-type doping region 110;

[0067] A first metal electrode 113 is connected to the outer surface of the A surface; a second metal electrode 114 is connected to the outer surface of the B surface; an insulating layer 115 is connected to both sides of the first metal electrode 113; and an insulating layer 115 is connected to both sides of the second metal electrode 114;

[0068] The two second N-type heavily doped regions 112 on the periphery of the B surface and the two first N-type heavily doped regions 102 on the periphery of the A surface are spaced equally and correspond to each other in spatial position.

[0069] The two second P-type doping regions 110 on the B surface correspond to the two first P-type doping regions 105 on the A surface in spatial position;

[0070] The widths of the two outer first N-type heavily doped regions 102 in the A surface are wider than the widths of the two inner first N-type heavily doped regions 102 ;

[0071] The widths of the two outer second N-type heavily doped regions 112 in the B surface are wider than the widths of the two inner second N-type heavily doped regions 112 ;

[0072] The width of the fifth N-type doping region 106 is 3%-5% of the total width of the chip; the width of the sixth N-type doping region 111 is 30%-40% of the total width of the chip.

[0073] Example 2

[0074] The method for preparing the asymmetric trigger switch surge absorption chip of the structure of the above-mentioned embodiment 1 comprises the following steps:

[0075] S1. Thinning or etching the P-type substrate 101 and marking one of its surfaces. The marked surface is defined as surface A, and the unmarked surface is defined as surface B.

[0076] S2, then perform oxidation treatment at a temperature of 950°C-1050°C in an oxygen atmosphere for 1h-3h to form an oxide layer on both surfaces, and perform boron implantation on the entire surface of the B surface. The implantation conditions are: energy 90KEV-110KEV, dose 1×10 14 -1×10 16 / cm 3 ; forming a P-type heavily doped region 107 in the B surface;

[0077] After the above steps, the structure obtained is as follows Figure 2 As shown (the oxide layer and photoresist outside the surface are not shown);

[0078] S3, then introducing hydrogen and oxygen with a volume ratio of 3:2 and performing water vapor oxidation treatment at a temperature of 950° C.-1050° C. for 4 h-6 h, so that the surface oxide layer becomes thicker;

[0079] The diffusion area is defined by performing photolithography on both sides simultaneously as required. The specific photolithography process is as follows: first, photoresist is coated on both sides with a thickness of 10,000 to 40,000 angstroms. It can be either positive or negative photoresist. Depending on the properties of the photoresist and the photolithographic pattern requirements, double-sided exposure is performed for 6 to 15 seconds, and the development time is 20 to 40 seconds. Then, the oxide layer in the defined diffusion area is rinsed and removed with ammonium fluoride.

[0080] Subsequently, liquid phosphorus oxychloride is introduced into a diffusion furnace at 950° C. to 1050° C. by nitrogen gas, and phosphorus diffusion is performed for 2 to 4 hours until the sheet resistance of the diffusion region is within the range of 2 Ω / sq to 8 Ω / sq, thereby forming four first N-type heavily doped regions 102 distributed in an array on the A surface and four second N-type heavily doped regions 112 distributed in an array on the B surface.

[0081] After the above steps, the structure obtained is as follows Figure 3 As shown (the oxide layer and photoresist outside the surface are not shown);

[0082] S4, then introduce hydrogen and oxygen with a volume ratio of 3:2 and perform steam oxidation treatment at a temperature of 950°C-1050°C for 4h-6h;

[0083] The implantation area is defined by performing photolithography on both sides simultaneously as required. The specific photolithography process is as follows: first, photoresist is coated on both sides with a thickness of 10,000 to 40,000 angstroms. It can be either positive or negative photoresist. Depending on the properties of the photoresist and the photolithographic pattern requirements, double-sided exposure is performed for 6 to 15 seconds, and the development time is 20 to 40 seconds. Then, the oxide layer in the defined diffusion area is rinsed and removed with ammonium fluoride.

[0084] Phosphorus was subsequently implanted under the following conditions: energy 90KEV-110KEV, dose 1×10 14 -1×10 16 / cm 3 , in this way, the gaps between the four first N-type heavily doped regions 102 in the A surface are filled to form three third N-type doped regions 103 , and the gaps between the four second N-type heavily doped regions 112 in the B surface are filled to form three fourth N-type doped regions 108 ;

[0085] After the above steps, the structure obtained is as follows Figure 4 As shown (the oxide layer and photoresist outside the surface are not shown);

[0086] S5, then carry out high temperature push-bonding treatment at 1100-1250°C for 10-18 hours;

[0087] S6. Perform photolithography on both sides simultaneously as required to define the diffusion area. The specific photolithography process is as follows: first, apply photoresist on both sides with a thickness of 10,000 to 40,000 angstroms. The photoresist can be either positive or negative. Depending on the properties of the photoresist and the photolithographic pattern requirements, double-sided exposure is performed for 6 seconds to 15 seconds, and the development time is 20 seconds to 40 seconds. Then, the oxide layer in the defined diffusion area is rinsed and removed with ammonium fluoride.

[0088] Then first boron pre-diffusion: the boron-doped source material is uniformly coated to the defined diffusion area, and diffusion is carried out at a temperature of 900-1000°C to make the sheet resistance of the diffusion area between 5Ω / sq and 12Ω / sq;

[0089] Then high-temperature bonding is carried out at 1100-1200°C to make boron re-diffuse, and the treatment time is 5-8h;

[0090] In this way, two first emitter regions 104 and two first P-type doped regions 105 are formed in the A surface, and two second emitter regions 109 and two second P-type doped regions 110 are formed in the B surface;

[0091] The structure obtained through the above steps is shown in Figure 5 (not showing the oxide layer and photoresist outside the surface);

[0092] S7. According to requirements, photoetching is carried out on both sides to define the diffusion area. The specific photoetching process is as follows: first, photoresist is coated on both sides, and the thickness is 10000-40000 angstroms. It can be positive photoresist or negative photoresist. According to the photoresist properties and photoetching pattern requirements, double-side exposure is carried out for 6-15 seconds, and development time is 20-40 seconds. Then, the oxide layer of the defined diffusion area is rinsed and removed by ammonium fluoride;

[0093] Then, liquid phosphorus oxychloride is carried into the diffusion furnace by nitrogen to carry out N-type phosphorus diffusion in the diffusion furnace at 950-1050°C for 2-4h to make the sheet resistance of the diffusion area in the range of 2Ω / sq-8Ω / sq. In this way, a fifth N-type doped region 106 is formed between the two inner first N-type heavily doped regions 102 in the A surface, and a sixth N-type doped region 111 is formed between the two inner second N-type heavily doped regions 112 in the B surface;

[0094] The structure obtained through the above steps is shown in Figure 6 (not showing the oxide layer and photoresist outside the surface);

[0095] S8. CVD double-side deposition of an insulating layer 115. The structure of the insulating layer is a composite layer structure composed of a SIPOS layer 1151 and a silicon dioxide layer 1152. The preparation process is as follows: in a low-pressure furnace tube, the temperature is 600-700°C, SiH4 and N2O with a volume ratio of 2-2.5:1 are introduced, and the vacuum pressure is 200-400mTorr to deposit the SIPOS layer with a thickness of 1-1.8μm;

[0096] Then, in a low-pressure furnace tube, the temperature is 700-800°C, tetraethyl orthosilicate is introduced, and the vacuum pressure is 350-450mTorr to deposit the silicon dioxide layer with a thickness of 1.2-1.5μm.

[0097] S9, remove the insulating layer of the electrode area, and then perform a metallization process, the metallization process is:

[0098] One method is: 80-95 ℃ nickel plating solution to the electrode area to form a 0.6-1 μm nickel layer, and then form a silicon-nickel alloy at a temperature of 600-700 ℃; then 80-95 ℃ nickel plating solution to the silicon-nickel alloy to form a 0.8-1.5 μm nickel layer;

[0099] Another method is: by metal evaporation, evaporate titanium nickel silver and other metals on both sides of the chip, and then remove the metal outside the electrode by photolithography;

[0100] By the above two different ways, to complete the chip metallization, thus obtaining the first metal electrode 113 on the A surface, and the second metal electrode 114 on the B surface, and finally obtaining the above embodiment 1 Figure 1 The asymmetric trigger switch surge absorption chip structure.

[0101] The asymmetric trigger switch surge absorption chip structure of the present application has the characteristics of both trigger tube and solid discharge tube. The working principle is: when used as a trigger tube, the corresponding sixth N-doped region 111 has a large area (the width of the sixth N-doped region 111 is 30-40% of the total width of the chip) and high concentration. Once the PN junction of the third N-doped region 103 and the P-type substrate 101 breaks down, the breakdown current flows from the P-type substrate 101 region, and the breakdown voltage of the PN junction cannot be maintained, resulting in a negative resistance phenomenon. When used as a solid discharge tube, the fifth N-doped region 106 has a small area (the width of the fifth N-doped region 106 is 3-5% of the total width of the chip) and high concentration, and the blocking voltage rises. Due to the presence of the P-type heavily doped region 107, the breakdown voltage is low, and the breakdown current will produce a voltage drop on the fourth N-doped region 108. When it reaches a certain degree, the PN junction at the second emitter region 109 is turned on, and when it reaches a certain degree, it is in a fully conductive state.

[0102] ​​​​​​​​​​​​The chip has a trigger voltage in a wide range of 8V-330V, and the difference of conduction voltage in different directions can be controlled between 20V-300V, the span is large and can be adjusted as required, the surge current in one cycle can reach 20A-200A, and the capacitor which has been fully charged can be discharged through inductance to generate high-energy high-voltage pulse; the chip has specific negative resistance characteristics, the voltage in the conduction state is very low, only about 1.5V, and a large current can be passed in an instant, and once the conduction is turned on, it is in a self-locking state, and only when the current flowing through itself is interrupted or less than the off current, the chip will be turned off; the response speed of the chip is less than 1ns. The chip is a two-terminal negative resistance device based on the principle structure of a thyristor, and the voltage drop between the two terminals when triggered is only about 1.5V, so the working state of the device is similar to a switch, so the chip is also a bidirectional trigger switch. Once the voltage applied to the two ends of the chip exceeds the breakdown voltage, it will immediately turn to the conduction state through a negative resistance region. The low conduction voltage drop makes it have very low power loss and can provide a large current in an instant. Only when the current flowing through the chip is interrupted or lower than the off current, the chip will automatically turn from the conduction state to the cutoff state.

[0103] The above case takes a P-type substrate as an example, and in other implementation cases, an N-type substrate can also be selected. When the N-type substrate is selected, the conductive doping types of the A surface and the B surface are interchanged.

[0104] The above is only a preferred specific embodiment of the present application, and in other implementation cases, the selection of parameters can achieve corresponding effects within the scope of the present application, but the protection scope of the present application is not limited thereto, any person skilled in the art can make equivalent replacement or change according to the technical solution and the inventive concept of the present application within the technical range disclosed by the present application, which should be covered within the protection scope of the present application.

Claims

1. An asymmetric trigger switch surge absorption chip, characterized in that: Its cross-sectional structure includes a first conductive type substrate, wherein two surfaces of the first conductive type substrate are defined as surface A and surface B respectively; Four second conductivity type first heavily doped regions are arranged in an array within the surface A, two first conductivity type first doped regions are arranged axially symmetrically and non-connected outside the two second conductivity type first heavily doped regions distributed on the periphery, a second conductivity type third doped region is arranged between the four second conductivity type first heavily doped regions, a second conductivity type fifth doped region is arranged within the second conductivity type third doped region between the two second conductivity type first heavily doped regions distributed on the inner periphery, the second conductivity type fifth doped region is connected to the two second conductivity type first heavily doped regions on the inner periphery, and two first emitter regions are arranged axially symmetrically and connected outside the two second conductivity type first heavily doped regions distributed on the inner periphery; The B surface has an entire surface of a heavily doped region of the first conductivity type, four second heavily doped regions of the second conductivity type are connected to the first heavily doped region and arranged in an array, two second heavily doped regions of the first conductivity type are arranged axially symmetrically and non-connected outside the two second heavily doped regions of the second conductivity type distributed on the periphery, a fourth doped region of the second conductivity type is filled between the four second heavily doped regions of the second conductivity type, a sixth doped region of the second conductivity type is arranged in the fourth doped region of the second conductivity type distributed between the two second heavily doped regions of the second conductivity type distributed in the inner periphery, the sixth doped region of the second conductivity type is connected to the two second heavily doped regions of the second conductivity type distributed in the inner periphery, and two second emitter regions are arranged axially symmetrically and connected outside the two second heavily doped regions of the second conductivity type distributed in the inner periphery; The width of the fifth doped region of the second conductivity type is 3%-5% of the total width of the chip; The width of the sixth doping region of the second conductivity type is 30%-40% of the total width of the chip.

2. The asymmetric trigger switch surge absorption chip according to claim 1, characterized in that: In the B surface, the doping depths of the second conductive type second heavily doped region, the second conductive type fourth doped region, the first conductive type heavily doped region, the second conductive type sixth doped region, and the first conductive type second doped region decrease in sequence; the second emitter region has the same doping depth as the first conductive type second doped region; Within the A surface: the doping depths of the second conductive type first heavily doped region, the second conductive type third doped region, the second conductive type fifth doped region, and the first conductive type first doped region decrease in sequence; the first emitter region has the same doping depth as the first conductive type first doped region.

3. The asymmetric trigger switch surge absorption chip according to claim 1, characterized in that: The distance between the two second conductive type second heavily doped regions in the inner periphery of the B surface is wider than the distance between the two second conductive type first heavily doped regions in the inner periphery of the A surface; The spacing between the two second heavily doped regions of the second conductivity type on the periphery of the B surface is equal to the spacing between the two first heavily doped regions of the second conductivity type on the periphery of the A surface and corresponds in spatial position; The two first conductive type second doping regions in the B surface correspond to the two first conductive type first doping regions in the A surface in spatial position; The widths of the two outer second conductivity type first heavily doped regions within the A surface are wider than the widths of the two inner second conductivity type first heavily doped regions; The widths of the two outer second-conductivity-type second heavily doped regions within the B surface are wider than the widths of the two inner second-conductivity-type second heavily doped regions.

4. The asymmetric trigger switch surge absorption chip according to claim 1, characterized in that: A first metal electrode is connected to the outside of the A surface; a second metal electrode is connected to the outside of the B surface; an insulating layer is connected to both sides of the first metal electrode; and an insulating layer is connected to both sides of the second metal electrode.

5. The asymmetric trigger switch surge absorption chip according to any one of claims 1 to 4, characterized in that: When the first conductivity type is an N-type doping element, the second conductivity type is a P-type doping element; when the first conductivity type is a P-type doping element, the second conductivity type is an N-type doping element.

6. A method for preparing the asymmetric trigger switch surge absorption chip according to any one of claims 1 to 5, comprising the following steps: S1. Thinning or etching the first conductive type substrate, marking one of its surfaces, where the marked surface is defined as surface A and the unmarked surface is defined as surface B; S2, then performing an oxidation treatment to form an oxide layer on both surfaces, and performing a first conductivity type implantation on the entire surface of the B surface to form a first conductivity type heavily doped region in the B surface; S3, then performing oxidation treatment to thicken the surface oxide layer, performing photolithography treatment on both sides as required to define the diffusion area, and then performing second conductivity type diffusion to form four second conductivity type first heavily doped regions distributed in an array on the A surface and four second conductivity type second heavily doped regions distributed in an array on the B surface; S4, then perform oxidation treatment, perform photolithography treatment on both sides simultaneously as required to define the implantation area, and then perform second conductivity type implantation to form three second conductivity type third doping regions in the A surface and three second conductivity type fourth doping regions in the B surface; S5, then carry out high temperature pushing treatment; S6. Perform photolithography on both surfaces simultaneously as required to define diffusion regions for first conductivity type pre-diffusion and first conductivity type re-diffusion, thereby forming two first emitter regions and two first conductivity type first doped regions in surface A, and forming two second emitter regions and two first conductivity type second doped regions in surface B; S7. Perform photolithography on both surfaces simultaneously as required to define diffusion regions for second conductivity type diffusion, thereby forming a fifth doping region of the second conductivity type in the A surface and a sixth doping region of the second conductivity type in the B surface; S8, CVD deposition of an insulating layer; S9. Remove the insulating layer in the electrode area, and then perform metallization treatment to obtain a first metal electrode on the A surface and a second metal electrode on the B surface.

7. The method for preparing the asymmetric trigger switch surge absorption chip according to claim 6, characterized in that: In S1, the resistivity of the first conductive type substrate is in the range of 0.002 Ω·cm-50 Ω·cm, and the thinning process or the etching process is performed until the thickness of the first conductive type substrate is 150 μm-270 μm; The oxidation treatment in S2 is: treating at a temperature of 900° C. to 1100° C. for 1 h to 3 h in an oxygen atmosphere; The oxidation treatment in S3 is: introducing hydrogen and oxygen with a volume ratio of 3:2 at a temperature of 900° C.-1100° C. for 3 h-8 h; The oxidation treatment in S4 is: introducing hydrogen and oxygen with a volume ratio of 3:2 at a temperature of 900° C.-1100° C. for 3 h-8 h; The temperature of the high-temperature push-bonding treatment in S5 is 900° C.-1255° C. and the time is 3 h-24 h.

8. The method for preparing the asymmetric trigger switch surge absorption chip according to claim 6, characterized in that: The conditions for the first conductive type implantation in S2 are: energy 80KEV-120KEV, dose 1×10 14 -1×10 16 / cm 3 ; The second conductivity type diffusion in S3 is performed in a diffusion furnace, wherein the compound containing the second conductivity type is brought into the diffusion furnace by nitrogen and diffused at a temperature of 900° C. to 1100° C. for 0.5 h to 5 h, so that the sheet resistance of the diffusion area is 0.2 Ω to 10 Ω; The conditions for the second conductivity type implantation in S4 are: energy 80KEV-120KEV, dose 1×10 14 -1×10 16 / cm 3 ; The first conductive type pre-diffusion in S6 is to spread the latex source material doped with the first conductive type onto the diffusion region and diffuse it at a temperature of 850° C. to 1100° C. until the sheet resistance of the diffusion region is between 1Ω and 15Ω. In S6, the first conductive type re-diffusion is performed at a high temperature of 900° C. to 1255° C. for 1 h to 10 h; The second conductivity type diffusion in S7 is performed in a diffusion furnace, wherein the compound containing the second conductivity type is brought into the diffusion furnace by nitrogen and diffused at a temperature of 900° C. to 1100° C. for 0.5 h to 5 h, so that the sheet resistance of the diffusion area is 0.2 Ω to 10 Ω; 9. The method for preparing the asymmetric trigger switch surge absorption chip according to claim 6, characterized in that: The structure of the insulating layer in S8 is a composite layer structure composed of a SIPOS layer and a silicon dioxide layer, wherein the SIPOS layer is stacked on the surface of the substrate, and the silicon dioxide layer is stacked on the surface of the SIPOS layer; The formation conditions of the SIPOS layer are as follows: in a low-pressure furnace tube, at a temperature of 550° C. to 700° C., SiH 4 and N 2 O are introduced in a volume ratio of 1.5 to 3:1, and the SIPOS layer with a thickness of 0.5 μm to 2 μm is deposited under a vacuum pressure of 100 mTorr to 500 mTorr; The formation conditions of the silicon dioxide layer are as follows: in a low-pressure furnace tube, the temperature is 600° C.-800° C., ethyl orthosilicate is introduced, and the silicon dioxide layer with a thickness of 0.8 μm-1.5 μm is deposited under a vacuum pressure of 200 mTorr to 500 mTorr.

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