High-voltage integrated driving chip integrated with overvoltage protection function

Abstract

The invention relates to the technical field of integrated circuits, in particular to a high-voltage integrated driving chip integrated with an overvoltage protection function. Comprising an RC filter, a plurality of Schmidt circuits, a plurality of filters, a level conversion circuit, a dead zone interlocking circuit, a pulse circuit, a time delay circuit, a bootstrap circuit, an undervoltage circuit, a temperature protection circuit, an ITRIP current protection circuit, a fault logic circuit, a fault output circuit, an RS trigger, an output circuit, an AND gate and an overvoltage protection circuit. The chip circuit structure can directly detect and protect the power supply voltage of the driving chip in a traditional power module, the high-voltage driving chip is prevented from being burnt out due to the too high power supply voltage, the service life of the high-voltage driving chip is prolonged, meanwhile, the overvoltage protection circuit integrated with the chip does not need a voltage-regulator tube, power consumption can be reduced, the anti-noise capability is improved, and the power supply voltage is reduced. And the product stability and adaptability are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a high-voltage integrated driver chip with an integrated overvoltage protection function. Background Art

[0002] High voltage integrated circuit, or HVIC, is an integrated circuit product that converts MCU signals into driving IGBT or MOS signals. HVIC integrates PMOS tubes, NMOS tubes, triodes, diodes, voltage regulator tubes, resistors, and capacitors to form Schmitt, low voltage LEVELSHIFT, high voltage LEVELSHIFT, pulse generation circuit, delay circuit, filter circuit, overcurrent protection circuit, overheat protection circuit, undervoltage protection circuit, bootstrap circuit and other circuits. The single pulse GEN circuit in the high-side drive circuit of the existing HVIC generates pulses at the rising and falling edges of the HIN signal to drive DMOS. The pulse width is generally several hundred nanoseconds, so that HIN corresponds to HO. The basic high-side drive topology of the existing HVIC is as follows: Figure 1 shown.

[0003] The existing high-voltage integrated chip HVIC does not have an overvoltage detection and protection circuit for the power supply voltage VCC, which may cause the chip to burn out due to the power supply voltage VCC being too high. Therefore, an overvoltage protection circuit that can detect the power supply voltage VCC in real time and discharge it in time is needed. Summary of the invention

[0004] The present invention aims to provide a high-voltage integrated driving chip with an integrated overvoltage protection function, so as to solve the problem that the existing high-voltage integrated chip does not perform overvoltage detection on the power supply voltage VCC.

[0005] In order to solve the above technical problems, the present invention provides a high-voltage integrated driver chip with integrated overvoltage protection function, including an RC filter, multiple Schmitt circuits, multiple filters, a level conversion circuit, a dead zone interlocking circuit, a pulse circuit, a delay circuit, a bootstrap circuit, an undervoltage circuit, a temperature protection circuit, an ITRIP current protection circuit, a fault logic circuit, a fault output circuit, an RS trigger, an output circuit, an AND gate and an overvoltage protection circuit, wherein:

[0006] The RC filter is connected to the high-level driving signal HIN and the low-level driving signal LIN, and is successively output to the dead zone interlocking circuit through the Schmitt circuit, the filter, and the level conversion circuit, and the dead zone interlocking circuit outputs a high-level pulse signal HINa to the first input end of the pulse circuit, and outputs a low-level pulse signal LINa to the delay circuit;

[0007] The pulse circuit outputs ON_PLUSE / SET and OFF_PLUSE / RESET short pulse signals respectively according to the rising edge and falling edge of the high-level pulse signal HINa to drive the high-voltage LDMOS. The high-voltage LDMOS turns on and off to trigger the RS trigger, and controls the output circuit to output the high-level driving pulse signal HO;

[0008] The delay circuit outputs the low level pulse signal LINa to the first input terminal of the AND gate, and the output terminal of the AND gate controls the output circuit to output the low level driving pulse signal LO;

[0009] The input end of the undervoltage protection circuit is connected to the VCC power supply voltage, and the output end of the undervoltage protection circuit is connected to the first input end of the fault logic circuit;

[0010] The input end of the bootstrap circuit is connected to the VCC power supply voltage, and the output end of the bootstrap circuit is connected to the high-voltage LDMOS and the output circuit to provide a bootstrap voltage;

[0011] The input end of the temperature protection circuit is connected to the transient voltage suppressor TVC through the level conversion circuit, the filter and the Schmitt circuit;

[0012] The input end of the ITRIP current protection circuit is connected to the trigger current ITRIP through the level conversion circuit, the filter and the Schmitt circuit, and the output end of the ITRIP current protection circuit is connected to the second input end of the fault logic circuit;

[0013] The first output terminal of the fault logic circuit is connected to the second input terminal of the pulse circuit and the second input terminal of the AND gate, and the second input terminal of the fault logic circuit is connected to the fault output circuit;

[0014] The input end of the overvoltage protection circuit is connected to the VCC power supply voltage, and the output end of the overvoltage protection circuit is connected to the third input end of the fault logic circuit. The overvoltage protection circuit is used to output a high-level signal to the fault logic circuit when the VCC power supply voltage exceeds the preset operating range of the high-voltage integrated driver chip, so as to control the fault logic circuit to cut off the output of the high-level drive pulse signal HO and the low-level drive pulse signal LO through the pulse circuit and the AND gate.

[0015] Furthermore, the overvoltage protection circuit includes a sampling module, a reference module, a comparison module, a startup module and a discharge module, and two ends of each of the sampling module, the reference module, the comparison module, the startup module and the discharge module are connected to a VCC power supply voltage and ground respectively, wherein:

[0016] The sampling module is used to obtain a sampled voltage Va and send the sampled voltage Va to the comparison module, wherein the sampled voltage Va is positively correlated with the voltage of the VCC power supply voltage;

[0017] The reference module is used to output a reference voltage Vd to the comparison module;

[0018] The comparison module is used to compare the difference between the sampled voltage Va and the reference voltage Vd, and output a comparison voltage Ve;

[0019] The startup module is used to access the reference voltage Vd and feed back the output to the reference module;

[0020] The discharge module is used for comparing and judging the buffer voltage Vb with the comparison voltage Ve, and when the comparison voltage Ve is at a high level and the buffer voltage Vb is at a low level, discharging the voltage of the VCC power supply voltage through the ground terminal.

[0021] Furthermore, the sampling module includes a resistor R1 and a resistor R2, the first end of the resistor R1 is connected to the VCC power supply voltage, the second end of the resistor R1 is connected to the first end of the resistor R2, the second end of the resistor R2 is grounded, the sampling voltage Va is the voltage of the second end of the resistor R1, and the sampling voltage V a＝ R2*VCC / (R1+R2).

[0022] Furthermore, the reference module includes a MOS tube M5, a MOS tube M6, a MOS tube M7, a MOS tube M8 and a resistor R3, wherein the MOS tube M5 and the MOS tube M6 are NMOS tubes with the same length and width, and the MOS tube M7 and the MOS tube M8 are PMOS tubes with the same length and width;

[0023] The drain of the MOS tube M5 is connected to the drain of the MOS tube M7, the gate of the MOS tube M5 is connected to the drain of the MOS tube M7 and the gate of the MOS tube M6, and the source of the MOS tube M5 is grounded;

[0024] The drain of the MOS tube M6 is connected to the drain of the MOS tube M8 and the gate of the MOS tube M8 at the same time, and the source of the MOS tube M6 is connected to the first end of the resistor R3;

[0025] The second end of the resistor R3 is grounded;

[0026] The source of the MOS tube M7 is connected to the VCC power supply voltage, and the gate of the MOS tube M7 is connected to the gate of the MOS tube M8;

[0027] The source of the MOS tube M8 is connected to the VCC power supply voltage;

[0028] The reference voltage Vd is the voltage of the drain of the MOS tube M6. d =2(R3+r O6 ) / u n C ox (W / L)6R3R3, where r O Indicates the equivalent internal resistance of the MOS tube, u n , C ox They represent the electron mobility and gate oxide capacitance per unit area of ​​the MOS tube respectively, and W and L are the channel width and length of the MOS tube respectively.

[0029] Furthermore, the comparison module includes a MOS tube M9, a MOS tube M10, a MOS tube M11, a MOS tube M12 and a MOS tube M13, wherein the MOS tube M9, the MOS tube M10 and the MOS tube M11 are NMOS tubes, and the MOS tube M12 and the MOS tube M13 are PMOS tubes;

[0030] The source of the MOS tube M9 is grounded, the gate of the MOS tube M9 is connected to the drain of the MOS tube M6 to access the reference voltage Vd, and the drain of the MOS tube M9 is connected to the source of the MOS tube M10 and the source of the MOS tube M11;

[0031] The gate of the MOS tube M10 is connected to the drain of the MOS tube M6 to access the reference voltage Vd, and the drain of the MOS tube M10 is simultaneously connected to the drain of the MOS tube M12 and the gate of the MOS tube M12;

[0032] The gate of the MOS tube M11 is connected to the second end of the resistor R1 to access the sampling voltage Va, and the drain of the MOS tube M11 is connected to the drain of the MOS tube M13;

[0033] The gate of the MOS tube M12 is connected to the gate of the MOS tube M13, and the source of the MOS tube M12 is connected to the VCC power supply voltage;

[0034] The source of the MOS tube M13 is connected to the VCC power supply voltage;

[0035] The comparison voltage Ve is the voltage of the drain of the MOS tube M11. e =g m11 (r O11 / / r O13 )(V a- V d ), where g mIndicates the transconductance of the MOS tube.

[0036] Furthermore, the startup module includes a MOS tube M4, a MOS tube M2 and a MOS tube M3, wherein the MOS tube M4 is a PMOS tube, and the MOS tube M2 and the MOS tube M3 are NMOS tubes;

[0037] The source of the MOS tube M4 is connected to the VCC power supply voltage, the drain of the MOS tube M4 is connected to the drain and gate of the MOS tube M2, and the gate of the MOS tube M4 is connected to the reference voltage Vd;

[0038] The source of the MOS tube M2 is grounded, and the gate of the MOS tube M2 is connected to the gate of the MOS tube M3;

[0039] The source of the MOS tube M3 is grounded, and the drain of the MOS tube M3 is connected to the gate and drain of the MOS tube M8 at the same time.

[0040] Furthermore, the discharge module includes a MOS tube M14, a MOS tube M15, a MOS tube M16, a MOS tube M1, a fourth resistor R4 and a fifth resistor R5, wherein the MOS tube M14 and the MOS tube M15 are NMOS tubes, and the MOS tube M16 and the MOS tube M1 are PMOS tubes;

[0041] The source of the MOS tube M14 is connected to the first end of the fourth resistor R4, the drain of the MOS tube M14 is connected to the source and gate of the MOS tube M15, and the gate of the MOS tube M14 is connected to the drain of the MOS tube M11 to access the comparison voltage Ve;

[0042] The second end of the fourth resistor R4 is grounded;

[0043] The gate of the MOS tube M15 is connected to the gate of the MOS tube M16, and the source of the MOS tube M15 is connected to the power supply voltage VCC;

[0044] The source of the MOS tube M16 is connected to the VCC power supply voltage, and the drain of the MOS tube M16 is connected to the first end of the fifth resistor R5;

[0045] The second end of the fifth resistor R5 is grounded;

[0046] The gate of the MOS tube M1 is connected to the drain of the MOS tube M16, the source of the MOS tube M1 is grounded, and the drain of the MOS tube M1 is connected to the VCC power supply voltage;

[0047] The buffer voltage Vb is the voltage of the drain of the MOS tube M16.

[0048] The beneficial effect achieved by the present invention is that a high-voltage integrated driver chip with an integrated overvoltage protection circuit is proposed. The chip circuit structure can directly detect and protect the power supply voltage of the driver chip in the traditional power module, avoiding the high-voltage driver chip from burning out due to excessive power supply voltage, thereby extending the life of the high-voltage driver chip. At the same time, the overvoltage protection circuit integrated in the chip does not require a voltage regulator tube, which can reduce power consumption, improve noise resistance, and improve product stability and adaptability. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 It is a schematic diagram of the topological structure of a high-voltage integrated driver chip in the prior art;

[0050] Figure 2 is a schematic diagram of the structure of a high-voltage integrated driver chip with integrated overvoltage protection function provided by an embodiment of the present invention;

[0051] Figure 3 is a schematic diagram of a pulse signal provided by an embodiment of the present invention;

[0052] Figure 4 Schematic diagram of an implementation method of an RS trigger provided by an embodiment of the present invention;

[0053] Figure 5 Schematic diagram of the circuit structure of the overvoltage protection circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0055] Please refer to Figure 2 , Figure 2 1 is a schematic diagram of the structure of a high-voltage integrated driver chip with an integrated overvoltage protection function provided by an embodiment of the present invention. The high-voltage integrated driver chip 101 includes an RC filter 102, multiple Schmitt circuits 103, multiple filters 104, a level conversion circuit 105, a dead zone interlock circuit 106, a pulse circuit 107, a delay circuit 108, a bootstrap circuit 109, an undervoltage circuit 110, a temperature protection circuit 111, an ITRIP current protection circuit 112, a fault logic circuit 113, a fault output circuit 114, an RS trigger 115, an output circuit 116, an AND gate 117 and an overvoltage protection circuit 118, wherein:

[0056] The RC filter 102 receives the high-level driving signal HIN and the low-level driving signal LIN, and successively passes through the Schmitt circuit 103, the filter 104, and the level conversion circuit 105 to output to the dead zone interlocking circuit 106, and enables the dead zone interlocking circuit 106 to output the high-level pulse signal HINa to the first input terminal of the pulse circuit 107, and output the low-level pulse signal LINa to the delay circuit 108;

[0057] The pulse circuit 107 outputs ON_PLUSE / SET and OFF_PLUSE / RESET short pulse signals respectively according to the rising edge and falling edge of the high-level pulse signal HINa to drive the high-voltage LDMOS. The high-voltage LDMOS is turned on and off to trigger the RS trigger 115, and the output circuit 116 is controlled to output the high-level driving pulse signal HO;

[0058] The delay circuit 108 outputs the low level pulse signal LINa to the first input terminal of the AND gate 117, and the output terminal of the AND gate 117 controls the output circuit 116 to output the low level driving pulse signal LO;

[0059] The input end of the undervoltage protection circuit is connected to the VCC power supply voltage, and the output end of the undervoltage protection circuit is connected to the first input end of the fault logic circuit 113;

[0060] The input end of the bootstrap circuit 109 is connected to the VCC power supply voltage, and the output end of the bootstrap circuit 109 is connected to the high-voltage LDMOS and the output circuit 116 to provide a bootstrap voltage;

[0061] The input end of the temperature protection circuit 111 is connected to the transient voltage suppressor TVC through the level conversion circuit 105, the filter 104 and the Schmitt circuit 103;

[0062] The input end of the ITRIP current protection circuit 112 is connected to the trigger current ITRIP through the level conversion circuit 105, the filter 104 and the Schmitt circuit 103, and the output end of the ITRIP current protection circuit 112 is connected to the second input end of the fault logic circuit 113;

[0063] The first output terminal of the fault logic circuit 113 is connected to the second input terminal of the pulse circuit 107 and the second input terminal of the AND gate 117, and the second input terminal of the fault logic circuit 113 is connected to the fault output circuit 114;

[0064] The input terminal of the overvoltage protection circuit 118 is connected to the VCC power supply voltage, and the output terminal of the overvoltage protection circuit 118 is connected to the third input terminal of the fault logic circuit 113. The overvoltage protection circuit 118 is used to output a high-level signal to the fault logic circuit 113 when the VCC power supply voltage exceeds the preset working range of the high-voltage integrated driver chip, so as to control the fault logic circuit 113 to cut off the output of the high-level drive pulse signal HO and the low-level drive pulse signal LO through the pulse circuit 107 and the AND gate 117.

[0065] Specifically, the traditional HVIC driver chip (refer to Figure 1 In order to realize the signal conversion from the low voltage domain to the high voltage domain of VCCA-VS, the laterally diffused metal oxide semiconductor (LDMOS) device in the high and low voltage integration process is usually used for level shifting. However, since LDMOS is directly connected between the high voltage power supply and the ground, and is in a short circuit state (i.e., the drain has a high voltage and a large current) during normal operation, it is easy to cause thermal breakdown damage to the device. Therefore, in the HVIC driver chip structure, the rising edge and the falling edge of the input signal are usually converted into two narrow pulse signals respectively, and the two narrow pulse signals are used to drive the two LDMOS to transfer the signal to the high voltage area, such as Figure 1 As shown in the upper right frame, the use of narrow pulses to control the on and off of the high-voltage level shift circuit can effectively reduce the conduction time of the LDMOS in the high-voltage level shift circuit, thereby reducing the loss during conduction and preventing the LDMOS from generating excessive heat due to long-term conduction, thereby affecting the normal operation of the chip.

[0066] The high voltage level shift circuit will output two inverted pulse signals in response to the input narrow pulse signal. At this time, the voltage domain has been transformed from VDD-GND to VDDA-Vs. Figure 3 As shown, in order to restore the two narrow pulse signals output by the high-voltage level shift circuit to signals with the same width as the chip output signal, it is necessary to meet Figure 3 The working process shown in a, where A1 and A2 are two narrow pulse signals output by the high-voltage level shift circuit, and OUT is the level signal after recovery; Figure 3 From the truth table of b, we can see that an RS flip-flop can be used to implement pulse recovery, where A1 is the low-level valid SET terminal and A2 is the low-level valid RESET terminal.

[0067] Figure 4 There are two types of RS flip-flops that can be used to achieve the desired function. Figure 4In the figure a, an RS flip-flop is constructed using a NAND gate. Figure 4 b is an RS flip-flop constructed using a NOR gate. Both of these RS flip-flops can satisfy Figure 3 The truth table of b in Fig. 1 is similar to that of the RS flip-flop, but they also have the inherent disadvantages of the RS flip-flop, that is, there is an invalid input response, that is, when A1=0, A2=0, OUT=1. This working state does not exist in the narrow pulse recovery process under ideal working conditions, because the high-voltage level shift circuit under ideal conditions will not simultaneously produce two outputs of low potential (VCCA-VS, voltage domain). However, in actual operation, the high-voltage level shift circuit will produce this invalid input due to the influence of high-voltage transient noise. In addition, due to the influence of process deviation, the high-voltage level shift circuit under actual working conditions will have a short set or reset state time (A1=0, A2=1 or A1=1, A2=0) at the beginning and end of this invalid input state (A1=0, A2=0), thereby changing the latch state of the RS flip-flop.

[0068] For details, please refer to Figure 5 , Figure 5 1 is a schematic diagram of the circuit structure of an overvoltage protection circuit provided in an embodiment of the present invention. The overvoltage protection circuit 118 includes a sampling module 1181, a reference module 1182, a comparison module 1183, a start module 1184 and a discharge module 1185. The two ends of each of the sampling module 1181, the reference module 1182, the comparison module 1183, the start module 1184 and the discharge module 1185 are connected to the VCC power supply voltage and the ground respectively, wherein:

[0069] The sampling module 1181 is used to obtain a sampled voltage Va and send the sampled voltage Va to the comparison module 1183, wherein the sampled voltage Va is positively correlated with the voltage of the VCC power supply voltage;

[0070] The reference module 1182 is used to output a reference voltage Vd to the comparison module 1183;

[0071] The comparison module 1183 is used to compare the difference between the sample voltage Va and the reference voltage Vd, and output a comparison voltage Ve;

[0072] The startup module 1184 is used to access the reference voltage Vd and feed back the output to the reference module 1182;

[0073] The discharge module 1185 is used to compare and determine based on the buffer voltage Vb and the comparison voltage Ve, and when the comparison voltage Ve is at a high level and the buffer voltage Vb is at a low level, discharge the voltage of the VCC power supply voltage through the ground terminal.

[0074] The sampling module 1181 includes a resistor R1 and a resistor R2, wherein a first end of the resistor R1 is connected to the VCC power supply voltage, a second end of the resistor R1 is connected to a first end of the resistor R2, and a second end of the resistor R2 is grounded. The sampling voltage Va is the voltage at the second end of the resistor R1. Figure 5 In the example, the access point of the sampling voltage Va is equivalent to point a, and the sampling voltage V a＝ R2*VCC / (R1+R2). Based on this relationship, it can be seen that when the VCC voltage increases, the sampling voltage Va at point a will also increase.

[0075] Furthermore, the reference module 1182 includes a MOS transistor M5, a MOS transistor M6, a MOS transistor M7, a MOS transistor M8 and a resistor R3, wherein the MOS transistor M5 and the MOS transistor M6 are NMOS transistors with the same length and width, and the MOS transistor M7 and the MOS transistor M8 are PMOS transistors with the same length and width;

[0076] The drain of the MOS tube M5 is connected to the drain of the MOS tube M7, the gate of the MOS tube M5 is connected to the drain of the MOS tube M7 and the gate of the MOS tube M6, and the source of the MOS tube M5 is grounded;

[0077] The drain of the MOS tube M6 is connected to the drain of the MOS tube M8 and the gate of the MOS tube M8 at the same time, and the source of the MOS tube M6 is connected to the first end of the resistor R3;

[0078] The second end of the resistor R3 is grounded;

[0079] The source of the MOS tube M7 is connected to the VCC power supply voltage, and the gate of the MOS tube M7 is connected to the gate of the MOS tube M8;

[0080] The source of the MOS tube M8 is connected to the VCC power supply voltage;

[0081] The reference voltage Vd is the voltage of the drain of the MOS tube M6. Figure 5 In the example, the access point of the reference voltage Vd is equivalent to point d, and the reference voltage V d =2(R3+r O6 ) / u n C ox (W / L)6R3R3, where r O Indicates the equivalent internal resistance of the MOS tube, u n , C oxThey represent the electron mobility and gate oxide capacitance per unit area of ​​the MOS tube, respectively, and W and L represent the channel width and length of the MOS tube, respectively. Based on this relationship, it can be seen that the output reference voltage Vd at point d is a fixed value and is not affected by the power supply voltage VCC.

[0082] Furthermore, the comparison module 1183 includes a MOS transistor M9, a MOS transistor M10, a MOS transistor M11, a MOS transistor M12, and a MOS transistor M13, wherein the MOS transistor M9, the MOS transistor M10, and the MOS transistor M11 are NMOS transistors, and the MOS transistor M12 and the MOS transistor M13 are PMOS transistors;

[0083] The source of the MOS tube M9 is grounded, the gate of the MOS tube M9 is connected to the drain of the MOS tube M6 to access the reference voltage Vd, and the drain of the MOS tube M9 is connected to the source of the MOS tube M10 and the source of the MOS tube M11;

[0084] The gate of the MOS tube M10 is connected to the drain of the MOS tube M6 to access the reference voltage Vd, and the drain of the MOS tube M10 is simultaneously connected to the drain of the MOS tube M12 and the gate of the MOS tube M12;

[0085] The gate of the MOS tube M11 is connected to the second end of the resistor R1 to access the sampling voltage Va, and the drain of the MOS tube M11 is connected to the drain of the MOS tube M13;

[0086] The gate of the MOS tube M12 is connected to the gate of the MOS tube M13, and the source of the MOS tube M12 is connected to the VCC power supply voltage;

[0087] The source of the MOS tube M13 is connected to the VCC power supply voltage;

[0088] The comparison voltage Ve is the voltage of the drain of the MOS tube M11. Figure 5 In the example, the access point of the comparison voltage Ve is equivalent to point e, and the comparison voltage V e =g m11 (r O11 / / r O13 )(V a- V d ), where g m The comparison module 1183 is a differential amplifier circuit, which can amplify and output the difference between the gate voltage Va of M11 and the gate voltage Vd of M10 from point e. From the above relationship, it can be seen that when the sampling voltage Va at point a increases, the comparison voltage Ve at point e will also increase.

[0089] Furthermore, the startup module 1184 includes a MOS transistor M4, a MOS transistor M2 and a MOS transistor M3, wherein the MOS transistor M4 is a PMOS transistor, and the MOS transistor M2 and the MOS transistor M3 are NMOS transistors;

[0090] The source of the MOS tube M4 is connected to the VCC power supply voltage, the drain of the MOS tube M4 is connected to the drain and gate of the MOS tube M2, and the gate of the MOS tube M4 is connected to the reference voltage Vd;

[0091] The source of the MOS tube M2 is grounded, and the gate of the MOS tube M2 is connected to the gate of the MOS tube M3;

[0092] The source of the MOS tube M3 is grounded, and the drain of the MOS tube M3 is connected to the gate and drain of the MOS tube M8 at the same time.

[0093] Figure 5 In FIG. 1 , the point where the drain of the MOS tube M3 is connected to the reference module 1182 is equivalent to point c.

[0094] The discharge module 1185 includes a MOS tube M14, a MOS tube M15, a MOS tube M16, a MOS tube M1, a fourth resistor R4 and a fifth resistor R5, wherein the MOS tube M14 and the MOS tube M15 are NMOS tubes, and the MOS tube M16 and the MOS tube M1 are PMOS tubes;

[0095] The source of the MOS tube M14 is connected to the first end of the fourth resistor R4, the drain of the MOS tube M14 is connected to the source and gate of the MOS tube M15, and the gate of the MOS tube M14 is connected to the drain of the MOS tube M11 to access the comparison voltage Ve;

[0096] The second end of the fourth resistor R4 is grounded;

[0097] The gate of the MOS tube M15 is connected to the gate of the MOS tube M16, and the source of the MOS tube M15 is connected to the power supply voltage VCC;

[0098] The source of the MOS tube M16 is connected to the VCC power supply voltage, and the drain of the MOS tube M16 is connected to the first end of the fifth resistor R5;

[0099] The second end of the fifth resistor R5 is grounded;

[0100] The gate of the MOS tube M1 is connected to the drain of the MOS tube M16, the source of the MOS tube M1 is grounded, and the drain of the MOS tube M1 is connected to the VCC power supply voltage;

[0101] The buffer voltage Vb is the voltage of the drain of the MOS tube M16. Figure 5 In the discharge module 1185, the access point of the cache voltage Vb is equivalent to point b. In the discharge module 1185, the PMOS tubes M15 and M16 form a current mirror with the same size to reduce the gain, increase the bandwidth, and improve the circuit response speed. When the NMOS tube M14 is turned on, the M14, M15 and R4 branches generate current, which is copied to the M16 and R5 branches through the current mirror. Since the current flows through the resistor R5, the voltage at point b increases, that is, the gate voltage of M1 increases, M1 is turned on, and the VCC voltage is directly discharged to GND.

[0102] In the above-mentioned overvoltage protection circuit 118, when VCC is a normal voltage, the voltage of the sampling module 1181a is at a low level at this time, and the output voltage Vd of the reference module 1182 is fixed. It can be seen from the expression of the comparison voltage Ve that the voltage at point e is at a low level at this time, that is, the gate voltage of the NOMS tube M14 of the discharge module 1185 is at a low level, and the voltage Vb at point b is at a low level, M14 is in the off state, and the discharge module 1185 does not work. At this time, the OUT terminal outputs a low level.

[0103] When VCC rises, the voltage at point a also rises, and the output voltage Vd of the reference module 1182 remains unchanged. From the expression of the comparison voltage Ve, it can be seen that the voltage Ve at the output voltage point e of the comparison module 1183 also rises. When VCC rises and exceeds the threshold value VCC1, the voltage Ve at point e rises and exceeds the turn-on threshold voltage Vth of the NMOS tube M14 of the discharge module 1185. The discharge module 1185 starts to work, and the voltage Vb at point b becomes a high level. The NMOS tube M1 is turned on, and the VCC voltage is directly discharged to GND, entering the overvoltage lock state to prevent damage to other circuits. At this time, the OUT terminal outputs a high level;

[0104] When VCC decreases, the voltage at point a also decreases, and the output voltage Vd of the reference module 1182 remains unchanged. From the expression of the comparison voltage Ve, it can be seen that the output voltage Ve at point e of the comparison module 1183 also decreases. When VCC decreases below the threshold value VCC1, the voltage Ve at point e decreases below the turn-on threshold voltage Vth of the NMOS tube M14 of the discharge module 1185.

[0105] The discharge module 1185 stops working, the voltage Vb at point b becomes low level, the NMOS tube M1 is turned off, and the overvoltage lock state is released. At this time, the OUT terminal outputs a low level.

[0106] According to the output of the overvoltage protection circuit 118, when the VCC voltage is within the normal working range, the voltage at the output end of the overvoltage protection circuit 118 is at a low level, has no effect on the fault logic control circuit, and does not perform overvoltage protection;

[0107] When the VCC voltage exceeds the normal operating range, the voltage at the output end of the overvoltage protection circuit 118 is at a high level, thereby controlling the operation of the fault logic control circuit. The fault logic control circuit controls the outputs of the chip HO and LO to be turned off simultaneously through the pulse circuit 107 and the AND gate 117.

[0108] The beneficial effect achieved by the present invention is that a high-voltage integrated driver chip with an integrated overvoltage protection circuit is proposed. The chip circuit structure can directly detect and protect the power supply voltage of the driver chip in the traditional power module, avoiding the high-voltage driver chip from burning out due to excessive power supply voltage, thereby extending the life of the high-voltage driver chip. At the same time, the overvoltage protection circuit integrated in the chip does not require a voltage regulator tube, which can reduce power consumption, improve noise resistance, and improve product stability and adaptability.

[0109] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0110] The embodiments of the present invention are described above in conjunction with the accompanying drawings. What is disclosed is only the preferred embodiment of the present invention. However, the present invention is not limited to the above-mentioned specific implementation manner. The above-mentioned specific implementation manner is only illustrative rather than restrictive. Under the enlightenment of the present invention, ordinary technicians in this field can also make many forms and equivalent changes without departing from the scope of protection of the purpose of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A high-voltage integrated driver chip with integrated overvoltage protection function, characterized in that: It includes RC filter, multiple Schmitt circuits, multiple filters, level conversion circuit, dead zone interlock circuit, pulse circuit, delay circuit, bootstrap circuit, undervoltage circuit, temperature protection circuit, ITRIP current protection circuit, fault logic circuit, fault output circuit, RS trigger, output circuit, AND gate and overvoltage protection circuit, among which: The RC filter is connected to the high-level driving signal HIN and the low-level driving signal LIN, and is successively output to the dead zone interlocking circuit through the Schmitt circuit, the filter, and the level conversion circuit, and the dead zone interlocking circuit outputs a high-level pulse signal HINa to the first input end of the pulse circuit, and outputs a low-level pulse signal LINa to the delay circuit; The pulse circuit outputs ON_PLUSE / SET and OFF_PLUSE / RESET short pulse signals respectively according to the rising edge and falling edge of the high-level pulse signal HINa to drive the high-voltage LDMOS. The high-voltage LDMOS turns on and off to trigger the RS trigger, and controls the output circuit to output the high-level driving pulse signal HO; The delay circuit outputs the low level pulse signal LINa to the first input terminal of the AND gate, and the output terminal of the AND gate controls the output circuit to output the low level driving pulse signal LO; The input end of the undervoltage protection circuit is connected to the VCC power supply voltage, and the output end of the undervoltage protection circuit is connected to the first input end of the fault logic circuit; The input end of the bootstrap circuit is connected to the VCC power supply voltage, and the output end of the bootstrap circuit is connected to the high-voltage LDMOS and the output circuit to provide a bootstrap voltage; The input end of the temperature protection circuit is connected to the transient voltage suppressor TVC through the level conversion circuit, the filter and the Schmitt circuit; The input end of the ITRIP current protection circuit is connected to the trigger current ITRIP through the level conversion circuit, the filter and the Schmitt circuit, and the output end of the ITRIP current protection circuit is connected to the second input end of the fault logic circuit; The first output terminal of the fault logic circuit is connected to the second input terminal of the pulse circuit and the second input terminal of the AND gate, and the second input terminal of the fault logic circuit is connected to the fault output circuit; The input end of the overvoltage protection circuit is connected to the VCC power supply voltage, and the output end of the overvoltage protection circuit is connected to the third input end of the fault logic circuit. The overvoltage protection circuit is used to output a high-level signal to the fault logic circuit when the VCC power supply voltage exceeds the preset operating range of the high-voltage integrated driver chip, so as to control the fault logic circuit to cut off the output of the high-level drive pulse signal HO and the low-level drive pulse signal LO through the pulse circuit and the AND gate.

2. The high-voltage integrated driver chip with integrated overvoltage protection function according to claim 1, characterized in that: The overvoltage protection circuit includes a sampling module, a reference module, a comparison module, a startup module and a discharge module, wherein two ends of each of the sampling module, the reference module, the comparison module, the startup module and the discharge module are connected to a VCC power supply voltage and ground respectively, wherein: The sampling module is used to obtain a sampled voltage Va and send the sampled voltage Va to the comparison module, wherein the sampled voltage Va is positively correlated with the voltage of the VCC power supply voltage; The reference module is used to output a reference voltage Vd to the comparison module; The comparison module is used to compare the difference between the sampled voltage Va and the reference voltage Vd, and output a comparison voltage Ve; The startup module is used to access the reference voltage Vd and feed back the output to the reference module; The discharge module is used for comparing and judging the buffer voltage Vb with the comparison voltage Ve, and when the comparison voltage Ve is at a high level and the buffer voltage Vb is at a low level, discharging the voltage of the VCC power supply voltage through the ground terminal.

3. The high-voltage integrated driver chip with integrated overvoltage protection function according to claim 2, characterized in that: The sampling module includes a resistor R1 and a resistor R2, wherein the first end of the resistor R1 is connected to the VCC power supply voltage, the second end of the resistor R1 is connected to the first end of the resistor R2, and the second end of the resistor R2 is grounded. The sampling voltage Va is the voltage at the second end of the resistor R1. a＝ R2*VCC / (R1+R2).

4. The high-voltage integrated driver chip with integrated overvoltage protection function according to claim 3, characterized in that: The reference module includes a MOS tube M5, a MOS tube M6, a MOS tube M7, a MOS tube M8 and a resistor R3, wherein the MOS tube M5 and the MOS tube M6 are NMOS tubes with the same length and width, and the MOS tube M7 and the MOS tube M8 are PMOS tubes with the same length and width; The drain of the MOS tube M5 is connected to the drain of the MOS tube M7, the gate of the MOS tube M5 is connected to the drain of the MOS tube M7 and the gate of the MOS tube M6, and the source of the MOS tube M5 is grounded; The drain of the MOS tube M6 is connected to the drain of the MOS tube M8 and the gate of the MOS tube M8 at the same time, and the source of the MOS tube M6 is connected to the first end of the resistor R3; The second end of the resistor R3 is grounded; The source of the MOS tube M7 is connected to the VCC power supply voltage, and the gate of the MOS tube M7 is connected to the gate of the MOS tube M8; The source of the MOS tube M8 is connected to the VCC power supply voltage; The reference voltage Vd is the voltage of the drain of the MOS tube M6. d =2(R3+r O6 ) / u n C ox (W / L)6R3R3, where r O Indicates the equivalent internal resistance of the MOS tube, u n , C ox They represent the electron mobility and gate oxide capacitance per unit area of ​​the MOS tube respectively, and W and L are the channel width and length of the MOS tube respectively.

5. The high-voltage integrated driver chip with integrated overvoltage protection function according to claim 4, characterized in that: The comparison module includes a MOS tube M9, a MOS tube M10, a MOS tube M11, a MOS tube M12 and a MOS tube M13, wherein the MOS tube M9, the MOS tube M10 and the MOS tube M11 are NMOS tubes, and the MOS tube M12 and the MOS tube M13 are PMOS tubes; The source of the MOS tube M9 is grounded, the gate of the MOS tube M9 is connected to the drain of the MOS tube M6 to access the reference voltage Vd, and the drain of the MOS tube M9 is connected to the source of the MOS tube M10 and the source of the MOS tube M11; The gate of the MOS tube M10 is connected to the drain of the MOS tube M6 to access the reference voltage Vd, and the drain of the MOS tube M10 is simultaneously connected to the drain of the MOS tube M12 and the gate of the MOS tube M12; The gate of the MOS tube M11 is connected to the second end of the resistor R1 to access the sampling voltage Va, and the drain of the MOS tube M11 is connected to the drain of the MOS tube M13; The gate of the MOS tube M12 is connected to the gate of the MOS tube M13, and the source of the MOS tube M12 is connected to the VCC power supply voltage; The source of the MOS tube M13 is connected to the VCC power supply voltage; The comparison voltage Ve is the voltage of the drain of the MOS tube M11. e =g m11 (r O11 / / r O13 )(V a -V d ), where g m Indicates the transconductance of the MOS tube.

6. The high-voltage integrated driver chip with integrated overvoltage protection function according to claim 5, characterized in that: The startup module includes a MOS tube M4, a MOS tube M2 and a MOS tube M3, wherein the MOS tube M4 is a PMOS tube, and the MOS tube M2 and the MOS tube M3 are NMOS tubes; The source of the MOS tube M4 is connected to the VCC power supply voltage, the drain of the MOS tube M4 is connected to the drain and gate of the MOS tube M2, and the gate of the MOS tube M4 is connected to the reference voltage Vd; The source of the MOS tube M2 is grounded, and the gate of the MOS tube M2 is connected to the gate of the MOS tube M3; The source of the MOS tube M3 is grounded, and the drain of the MOS tube M3 is connected to the gate and drain of the MOS tube M8 at the same time.

7. The high-voltage integrated driver chip with integrated overvoltage protection function according to claim 6, characterized in that: The discharge module includes a MOS tube M14, a MOS tube M15, a MOS tube M16, a MOS tube M1, a fourth resistor R4 and a fifth resistor R5, wherein the MOS tube M14 and the MOS tube M15 are NMOS tubes, and the MOS tube M16 and the MOS tube M1 are PMOS tubes; The source of the MOS tube M14 is connected to the first end of the fourth resistor R4, the drain of the MOS tube M14 is connected to the source and gate of the MOS tube M15, and the gate of the MOS tube M14 is connected to the drain of the MOS tube M11 to access the comparison voltage Ve; The second end of the fourth resistor R4 is grounded; The gate of the MOS tube M15 is connected to the gate of the MOS tube M16, and the source of the MOS tube M15 is connected to the power supply voltage VCC; The source of the MOS tube M16 is connected to the VCC power supply voltage, and the drain of the MOS tube M16 is connected to the first end of the fifth resistor R5; The second end of the fifth resistor R5 is grounded; The gate of the MOS tube M1 is connected to the drain of the MOS tube M16, the source of the MOS tube M1 is grounded, and the drain of the MOS tube M1 is connected to the VCC power supply voltage; The buffer voltage Vb is the voltage of the drain of the MOS tube M16.

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