High-voltage integrated driving chip with integrated overvoltage protection function

Abstract

The application relates to the technical field of integrated circuits, in particular to a high-voltage integrated driving chip integrated with an overvoltage protection function, which comprises an RC filter, multiple Schmidt circuits, multiple filters, a level conversion circuit, a dead zone interlocking circuit, a pulse circuit, a delay circuit, a bootstrap circuit, an under-voltage circuit, a temperature protection circuit, an ITRIP current protection circuit, a fault logic circuit, a fault output circuit, an RS flip-flop, an output circuit, an AND gate and an overvoltage protection circuit. The chip circuit structure can directly detect and protect the power supply voltage of a driving chip in a traditional power module, avoids burning the high-voltage driving chip due to excessively high power supply voltage, prolongs the service life of the high-voltage driving chip, meanwhile, the overvoltage protection circuit integrated in the chip does not need a stabilizing tube, can reduce power consumption, improve noise resistance, and improves product stability and adaptability.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit technology, and particularly relates to a high-voltage integrated driving chip integrated with overvoltage protection function. BACKGROUND

[0002] High-voltage integrated circuit, namely HVIC, is an integrated circuit product for converting MCU signal into driving IGBT or MOS signal. HVIC integrates PMOS, NMOS, triode, diode, voltage stabilizing tube, resistor and capacitor together to form Smith, low-voltage LEVELSHIFT, high-voltage LEVELSHIFT, pulse generating circuit, delay circuit, filter circuit, overcurrent protection circuit and overheat protection circuit, under-voltage protection circuit and bootstrap circuit. The single-pulse GEN circuit in the high-side driving circuit of the existing HVIC generates pulses at the rising and falling edges of HIN signal respectively, which are used to drive DMOS, and the pulse width is generally several hundred nanoseconds, so as to make HIN correspond to HO. The basic high-side driving topology structure of the existing HVIC is shown in Figure 1 .

[0003] The existing high-voltage integrated chip HVIC does not have overvoltage detection and protection circuit for power supply voltage VCC, which may cause chip burnout due to excessively high power supply voltage VCC. Therefore, an overvoltage protection circuit capable of detecting power supply voltage VCC in real time and discharging in time is needed. SUMMARY

[0004] The present application aims to provide a high-voltage integrated driving chip integrated with overvoltage protection function to solve the problem that the existing high-voltage integrated chip does not have overvoltage detection for power supply voltage VCC.

[0005] To solve the above technical problems, the present application provides a high-voltage integrated driving chip integrated with overvoltage protection function, which comprises an RC filter, a plurality of Smith circuits, a plurality of filters, a level conversion circuit, a dead zone interlocking circuit, a pulse circuit, a delay circuit, a bootstrap circuit, an under-voltage circuit, a temperature protection circuit, an ITRIP current protection circuit, a fault logic circuit, a fault output circuit, an RS flip-flop, an output circuit, an AND gate and an overvoltage protection circuit, wherein:

[0006] The RC filter inputs high-level driving signal HIN and low-level driving signal LIN, and outputs to the dead zone interlocking circuit through the Smith circuit, the filter and the level conversion circuit in sequence, and makes the dead zone interlocking circuit output high-level pulse signal HINa to the first input end of the pulse circuit and output low-level pulse signal LINa to the delay circuit.

[0007] The pulse circuit outputs ON_PLUSE / SET and OFF_PLUSE / RESET short pulse signals according to rising and falling edges of the high-level pulse signal HINa to drive the high-voltage LDMOS, and the high-voltage LDMOS turns on and off to trigger the RS flip-flop and control the output circuit to output a high-level driving pulse signal HO.

[0008] The delay circuit outputs the low-level pulse signal LINa to the first input end of the AND gate, and controls the output circuit to output a low-level driving pulse signal LO through the output end of the AND gate.

[0009] The input end of the under-voltage protection circuit is connected to the VCC power voltage, and the output end of the under-voltage protection circuit is connected to the first input end of the fault logic circuit.

[0010] The input end of the bootstrap circuit is connected to the VCC power voltage, and the output end of the bootstrap circuit is connected to the high-voltage LDMOS and the output circuit to provide a bootstrap voltage.

[0011] The input end of the temperature protection circuit is connected to the transient voltage suppressor TVC through the level conversion circuit, the filter and the Schmidt circuit.

[0012] The input end of the ITRIP current protection circuit is connected to the trigger current ITRIP through the level conversion circuit, the filter and the Schmidt circuit, and the output end of the ITRIP current protection circuit is connected to the second input end of the fault logic circuit.

[0013] The first output end of the fault logic circuit is connected to the second input end of the pulse circuit and the second input end of the AND gate, and the second input end of the fault logic circuit is connected to the fault output circuit.

[0014] The input end of the over-voltage protection circuit is connected to the VCC power voltage, and the output end of the over-voltage protection circuit is connected to the third input end of the fault logic circuit, and the over-voltage protection circuit is used to output a high-level signal to the fault logic circuit when the VCC power voltage exceeds the preset working range of the high-voltage integrated drive chip, so as to control the fault logic circuit to cut off the output of the high-level driving pulse signal HO and the low-level driving pulse signal LO through the pulse circuit and the AND gate.

[0015] Further, the over-voltage protection circuit comprises a sampling module, a reference module, a comparison module, a start-up module and a bleeder module, and two ends of each of the sampling module, the reference module, the comparison module, the start-up module and the bleeder module are respectively connected to the VCC power voltage and the ground.

[0016] The sampling module is configured to obtain a sampling voltage Va and send the sampling voltage Va to the comparison module, wherein the sampling voltage Va is positively correlated with the voltage of the VCC power supply voltage;

[0017] The reference module is configured to output a reference voltage Vd to the comparison module;

[0018] The comparison module is configured to compare the difference between the sampling voltage Va and the reference voltage Vd and output a comparison voltage Ve;

[0019] The starting module is configured to access the reference voltage Vd and feed back the output to the reference module;

[0020] The bleeding module is configured to compare the buffer voltage Vb with the comparison voltage Ve, and when the comparison voltage Ve is high and the buffer voltage Vb is low, the voltage of the VCC power supply voltage is discharged through the ground terminal.

[0021] Further, the sampling module includes a resistor R1 and a resistor R2, a first end of the resistor R1 is connected to the VCC power supply voltage, a second end of the resistor R1 is connected to a first end of the resistor R2, a second end of the resistor R2 is grounded, the sampling voltage Va is the voltage of the second end of the resistor R1, and the sampling voltage V a＝ R2*VCC / (R1+R2).

[0022] Further, the reference module includes a MOS tube M5, a MOS tube M6, a MOS tube M7, a MOS tube M8, and a resistor R3, wherein the MOS tube M5 and the MOS tube M6 are NMOS tubes with the same length and width, and the MOS tube M7 and the MOS tube M8 are PMOS tubes with the same length and width;

[0023] The drain of the MOS tube M5 is connected to the drain of the MOS tube M7, the gate of the MOS tube M5 is connected to the drain of the MOS tube M7 and the gate of the MOS tube M6, and the source of the MOS tube M5 is grounded;

[0024] The drain of the MOS tube M6 is connected to the drain of the MOS tube M8 and the gate of the MOS tube M8, and the source of the MOS tube M6 is connected to a first end of the resistor R3;

[0025] A second end of the resistor R3 is grounded;

[0026] The source of the MOS tube M7 is connected to the VCC power supply voltage, and the gate of the MOS tube M7 is connected to the gate of the MOS tube M8;

[0027] The source of the MOS tube M8 is connected to the VCC power voltage;

[0028] The reference voltage Vd is the voltage of the drain of the MOS tube M6, and the reference voltage V d = 2(R3 + r O6 ) / u n C ox (W / L)6R3R3, wherein r O represents the equivalent internal resistance of the MOS tube, u n , C ox respectively represent the electron mobility and the unit area gate oxide layer capacitance of the MOS tube, and W and L respectively represent the channel width and length of the MOS tube.

[0029] Further, the comparison module comprises MOS tubes M9, M10, M11, M12 and M13, wherein the MOS tubes M9, M10 and M11 are NMOS tubes, and the MOS tubes M12 and M13 are PMOS tubes;

[0030] The source of the MOS tube M9 is grounded, the gate of the MOS tube M9 is connected to the drain of the MOS tube M6 to access the reference voltage Vd, and the drain of the MOS tube M9 is simultaneously connected to the sources of the MOS tubes M10 and M11;

[0031] The gate of the MOS tube M10 is connected to the drain of the MOS tube M6 to access the reference voltage Vd, and the drain of the MOS tube M10 is simultaneously connected to the drain of the MOS tube M12 and the gate of the MOS tube M12;

[0032] The gate of the MOS tube M11 is connected to the second end of the resistor R1 to access the sampling voltage Va, and the drain of the MOS tube M11 is connected to the drain of the MOS tube M13;

[0033] The gate of the MOS tube M12 is connected to the gate of the MOS tube M13, and the source of the MOS tube M12 is connected to the VCC power voltage;

[0034] The source of the MOS tube M13 is connected to the VCC power voltage;

[0035] The comparison voltage Ve is the voltage of the drain of the MOS tube M11, and the comparison voltage V e = g m11 (r O11 / / r O13 )(V a- V d ), wherein g mTransconductance of a MOS transistor.

[0036] Further, the starting module comprises a MOS transistor M4, a MOS transistor M2 and a MOS transistor M3, wherein the MOS transistor M4 is a PMOS transistor, and the MOS transistor M2 and the MOS transistor M3 are NMOS transistors.

[0037] The source of the MOS transistor M4 is connected to the VCC power voltage, the drain of the MOS transistor M4 is connected to the drain and the gate of the MOS transistor M2, and the gate of the MOS transistor M4 is connected to the reference voltage Vd.

[0038] The source of the MOS transistor M2 is grounded, and the gate of the MOS transistor M2 is connected to the gate of the MOS transistor M3.

[0039] The source of the MOS transistor M3 is grounded, and the drain of the MOS transistor M3 is connected to the gate and the drain of the MOS transistor M8.

[0040] Further, the starting module comprises a MOS transistor M4, a MOS transistor M2 and a MOS transistor M3, wherein the MOS transistor M4 is a PMOS transistor, and the MOS transistor M2 and the MOS transistor M3 are NMOS transistors.

[0041] The source of the MOS transistor M14 is connected to the first end of the fourth resistor R4, the drain of the MOS transistor M14 is connected to the source and the gate of the MOS transistor M15, and the gate of the MOS transistor M14 is connected to the drain of the MOS transistor M11 to access the comparison voltage Ve.

[0042] The second end of the fourth resistor R4 is grounded.

[0043] The gate of the MOS transistor M15 is connected to the gate of the MOS transistor M16, and the source of the MOS transistor M15 is connected to the power voltage VCC.

[0044] The source of the MOS transistor M16 is connected to the VCC power voltage, and the drain of the MOS transistor M16 is connected to the first end of the fifth resistor R5.

[0045] The second end of the fifth resistor R5 is grounded.

[0046] The gate of the MOS transistor M1 is connected to the drain of the MOS transistor M16, the source of the MOS transistor M1 is grounded, and the drain of the MOS transistor M1 is connected to the VCC power voltage.

[0047] The buffer voltage Vb is the voltage of the drain of the MOS transistor M16.

[0048] The application has the advantages that the high-voltage integrated drive chip with integrated overvoltage protection circuit can directly detect and protect the power supply voltage of the drive chip in the traditional power module, avoids the high-voltage drive chip from being burnt due to the excessively high power supply voltage, prolongs the service life of the high-voltage drive chip, the overvoltage protection circuit integrated in the chip does not need a voltage stabilizing tube, can reduce power consumption, improve noise resistance, and improve product stability and adaptability. BRIEF DESCRIPTION OF DRAWINGS

[0049] Figure 1 is a topological structure diagram of a high-voltage integrated drive chip of the prior art;

[0050] Figure 2 is a structure diagram of a high-voltage integrated drive chip with integrated overvoltage protection function provided by the embodiment of the application;

[0051] Figure 3 is a pulse signal diagram provided by the embodiment of the application;

[0052] Figure 4 is a schematic diagram of an RS flip-flop implementation provided by the embodiment of the application;

[0053] Figure 5 is a circuit structure diagram of an overvoltage protection circuit provided by the embodiment of the application. DETAILED DESCRIPTION

[0054] In order to make the objectives, technical solutions and advantages of the application clearer, the application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the application and do not limit the application.

[0055] Please refer to Figure 2 , Figure 2 is a structure diagram of a high-voltage integrated drive chip with integrated overvoltage protection function provided by the embodiment of the application, the high-voltage integrated drive chip 101 includes an RC filter 102, a plurality of Schmidt circuits 103, a plurality of filters 104, a level conversion circuit 105, a dead zone interlocking circuit 106, a pulse circuit 107, a delay circuit 108, a bootstrap circuit 109, an under-voltage circuit 110, a temperature protection circuit 111, an ITRIP current protection circuit 112, a fault logic circuit 113, a fault output circuit 114, an RS flip-flop 115, an output circuit 116, an AND gate 117, and an overvoltage protection circuit 118, wherein:

[0056] The RC filter 102 accesses the high-level driving signal HIN and the low-level driving signal LIN, and outputs to the dead-zone interlocking circuit 106 through the Schmitt trigger circuit 103, the filter 104 and the level conversion circuit 105 in sequence, and makes the dead-zone interlocking circuit 106 output the high-level pulse signal HINa to the first input end of the pulse circuit 107 and output the low-level pulse signal LINa to the delay circuit 108;

[0057] The pulse circuit 107 outputs the ON_PLUSE / SET and OFF_PLUSE / RESET short pulse signals according to the rising and falling edges of the high-level pulse signal HINa to drive the high-voltage LDMOS, and the high-voltage LDMOS turns on and off to trigger the RS flip-flop 115 and control the output circuit 116 to output the high-level driving pulse signal HO;

[0058] The delay circuit 108 outputs the low-level pulse signal LINa to the first input end of the AND gate 117, and controls the output circuit 116 to output the low-level driving pulse signal LO through the output end of the AND gate 117;

[0059] The input end of the under-voltage protection circuit accesses the VCC power voltage, and the output end of the under-voltage protection circuit accesses the first input end of the fault logic circuit 113;

[0060] The input end of the bootstrap circuit 109 accesses the VCC power voltage, and the output end of the bootstrap circuit 109 accesses the high-voltage LDMOS and the output circuit 116 to provide a bootstrap voltage;

[0061] The input end of the temperature protection circuit 111 accesses the transient voltage suppressor TVC through the level conversion circuit 105, the filter 104 and the Schmitt trigger circuit 103;

[0062] The input end of the ITRIP current protection circuit 112 accesses the trigger current ITRIP through the level conversion circuit 105, the filter 104 and the Schmitt trigger circuit 103, and the output end of the ITRIP current protection circuit 112 accesses the second input end of the fault logic circuit 113;

[0063] The first output end of the fault logic circuit 113 accesses the second input end of the pulse circuit 107 and the second input end of the AND gate 117, and the second input end of the fault logic circuit 113 accesses the fault output circuit 114;

[0064] The input end of the overvoltage protection circuit 118 is connected with the VCC power voltage, the output end of the overvoltage protection circuit 118 is connected with the third input end of the fault logic circuit 113, and the overvoltage protection circuit 118 is used for outputting a high level signal to the fault logic circuit 113 when the VCC power voltage exceeds the preset working range of the high voltage integrated drive chip, so as to control the fault logic circuit 113 to cut off the output of the high level drive pulse signal HO and the low level drive pulse signal LO through the pulse circuit 107 and the AND gate 117.

[0065] Specifically, the drive signal of the conventional HVIC drive chip (as shown in Figure 1 The drive signal of the conventional HVIC drive chip (as shown in Figure 1 The drive signal of the conventional HVIC drive chip (as shown in The drive signal of the conventional HVIC drive chip (as shown in

[0066] The drive signal of the conventional HVIC drive chip (as shown in Figure 3 The drive signal of the conventional HVIC drive chip (as shown in Figure 3 The drive signal of the conventional HVIC drive chip (as shown in Figure 3 The drive signal of the conventional HVIC drive chip (as shown in The drive signal of the conventional HVIC drive chip (as shown in

[0067] The drive signal of the conventional HVIC drive chip (as shown in Figure 4 The drive signal of the conventional HVIC drive chip (as shown in Figure 4The RS flip-flop a is constituted by using a NAND gate, Figure 4 The RS flip-flop b is constituted by using a NOR gate. Both of the RS flip-flops can satisfy Figure 3 The truth table of the RS flip-flop b, but both of them have the inherent disadvantages of the RS flip-flop, that is, there is an invalid input response, that is, when A1=0, A2=0, OUT=1. This working state does not exist in the narrow pulse recovery process under the ideal working condition, because the high voltage level shift circuit under the ideal condition will not produce two low voltage outputs (VCCA-VS, voltage domain) at the same time. However, in actual work, the high voltage level shift circuit will produce this invalid input due to the influence of high voltage transient noise. In addition, due to the influence of process deviation, the high voltage level shift circuit under the actual working condition will appear a short setting or resetting state time (A1=0, A2=1 or A1=1, A2=0) at the beginning and end of this invalid input state, so as to change the latch state of the RS flip-flop.

[0068] Specifically, please refer to Figure 5 , Figure 5 The overvoltage protection circuit 118 provided by the embodiment of the present application, the circuit structure schematic diagram of the overvoltage protection circuit is shown in Figure 1, the overvoltage protection circuit 118 includes a sampling module 1181, a reference module 1182, a comparison module 1183, a starting module 1184 and a discharge module 1185, the two ends of the sampling module 1181, the reference module 1182, the comparison module 1183, the starting module 1184 and the discharge module 1185 are respectively connected with VCC power voltage and ground, wherein:

[0069] The sampling module 1181 is used for obtaining a sampling voltage Va and sending the sampling voltage Va to the comparison module 1183, and the sampling voltage Va is positively related to the voltage of the VCC power voltage;

[0070] The reference module 1182 is used for outputting a reference voltage Vd to the comparison module 1183;

[0071] The comparison module 1183 is used for comparing the difference between the sampling voltage Va and the reference voltage Vd and outputting a comparison voltage Ve;

[0072] The starting module 1184 is used for accessing the reference voltage Vd and outputting feedback to the reference module 1182;

[0073] The discharge module 1185 is used for comparing and judging according to the comparison voltage Ve and the buffer voltage Vb, and when the comparison voltage Ve is high and the buffer voltage Vb is low, the voltage of the VCC power voltage is discharged through the ground end.

[0074] The sampling module 1181 includes a resistor R1 and a resistor R2, a first end of the resistor R1 is connected to the VCC power voltage, a second end of the resistor R1 is connected to a first end of the resistor R2, a second end of the resistor R2 is grounded, and the sampling voltage Va is a voltage of the second end of the resistor R1, Figure 5 In the formula, an access point of the sampling voltage Va is equivalent to point a, and the sampling voltage Va is equivalent to a voltage of point a. a＝ R2*VCC / (R1+R2). Based on the relationship, it can be seen that the VCC voltage rises, and the sampling voltage Va of point a also rises.

[0075] Further, the reference module 1182 includes MOS tubes M5, M6, M7, M8 and a resistor R3, wherein the MOS tubes M5 and M6 are NMOS tubes with the same length and width, and the MOS tubes M7 and M8 are PMOS tubes with the same length and width.

[0076] The drain of the MOS tube M5 is connected to the drain of the MOS tube M7, the gate of the MOS tube M5 is connected to the drain of the MOS tube M7 and the gate of the MOS tube M6, and the source of the MOS tube M5 is grounded.

[0077] The drain of the MOS tube M6 is connected to the drain of the MOS tube M8 and the gate of the MOS tube M8, and the source of the MOS tube M6 is connected to a first end of the resistor R3.

[0078] A second end of the resistor R3 is grounded.

[0079] The source of the MOS tube M7 is connected to the VCC power voltage, and the gate of the MOS tube M7 is connected to the gate of the MOS tube M8.

[0080] The source of the MOS tube M8 is connected to the VCC power voltage.

[0081] The reference voltage Vd is a voltage of the drain of the MOS tube M6, Figure 5 In the formula, an access point of the reference voltage Vd is equivalent to point d, and the reference voltage Vd is equivalent to a voltage of point d. d =2(R3+r O6 ) / u n C ox (W / L)6R3R3, wherein r O represents the equivalent resistance of the MOS tube, u n , C oxThe MOS transistor's electron mobility and the unit area gate oxide layer capacitance are represented by μ and C0X, respectively. The channel width and length of the MOS transistor are represented by W and L, respectively. Based on the relationship, it can be seen that the d-point output reference voltage Vd is a fixed value and is not affected by the power supply voltage VCC.

[0082] Further, the comparison module 1183 comprises MOS transistor M9, MOS transistor M10, MOS transistor M11, MOS transistor M12 and MOS transistor M13, wherein the MOS transistor M9, the MOS transistor M10 and the MOS transistor M11 are NMOS transistors, and the MOS transistor M12 and the MOS transistor M13 are PMOS transistors.

[0083] The source of the MOS transistor M9 is grounded, the gate of the MOS transistor M9 is connected to the drain of the MOS transistor M6 to access the reference voltage Vd, and the drain of the MOS transistor M9 is connected to the sources of the MOS transistor M10 and the MOS transistor M11.

[0084] The gate of the MOS transistor M10 is connected to the drain of the MOS transistor M6 to access the reference voltage Vd, and the drain of the MOS transistor M10 is connected to the drain of the MOS transistor M12 and the gate of the MOS transistor M12.

[0085] The gate of the MOS transistor M11 is connected to the second end of the resistor R1 to access the sampling voltage Va, and the drain of the MOS transistor M11 is connected to the drain of the MOS transistor M13.

[0086] The gate of the MOS transistor M12 is connected to the gate of the MOS transistor M13, and the source of the MOS transistor M12 is connected to the VCC power supply voltage.

[0087] The source of the MOS transistor M13 is connected to the VCC power supply voltage.

[0088] The comparison voltage Ve is the voltage at the drain of the MOS transistor M11, Figure 5 wherein the access point of the comparison voltage Ve is equivalent to the e point, and the comparison voltage V e = g m11 (r O11 / / r O13 )(V a- V d ), wherein g m represents the transconductance of the MOS transistor. The comparison module 1183 is a differential amplification circuit, which can amplify and output the difference between the gate voltage Va of M11 and the gate voltage Vd of M10 from the e point. As can be seen from the above relationship, the sampling voltage Va at point a rises, and the comparison voltage Ve at point e also rises.

[0089] Further, the starting module 1184 comprises a MOS tube M4, a MOS tube M2 and a MOS tube M3, wherein the MOS tube M4 is a PMOS tube, and the MOS tube M2 and the MOS tube M3 are NMOS tubes;

[0090] The source of the MOS tube M4 is connected to the VCC power voltage, the drain of the MOS tube M4 is connected to the drain and the gate of the MOS tube M2, and the gate of the MOS tube M4 is connected to the reference voltage Vd;

[0091] The source of the MOS tube M2 is grounded, and the gate of the MOS tube M2 is connected to the gate of the MOS tube M3;

[0092] The source of the MOS tube M3 is grounded, and the drain of the MOS tube M3 is connected to the gate and the drain of the MOS tube M8.

[0093] Figure 5 In the embodiment, the drain of the MOS tube M3 is connected to the point in the reference module 1182, which is equivalent to point c.

[0094] The bleeding module 1185 comprises a MOS tube M14, a MOS tube M15, a MOS tube M16, a MOS tube M1, a fourth resistor R4 and a fifth resistor R5, wherein the MOS tube M14 and the MOS tube M15 are NMOS tubes, and the MOS tube M16 and the MOS tube M1 are PMOS tubes;

[0095] The source of the MOS tube M14 is connected to the first end of the fourth resistor R4, the drain of the MOS tube M14 is connected to the source and the gate of the MOS tube M15, and the gate of the MOS tube M14 is connected to the drain of the MOS tube M11 to access the comparison voltage Ve;

[0096] The second end of the fourth resistor R4 is grounded;

[0097] The gate of the MOS tube M15 is connected to the gate of the MOS tube M16, and the source of the MOS tube M15 is connected to the power voltage VCC;

[0098] The source of the MOS tube M16 is connected to the VCC power voltage, and the drain of the MOS tube M16 is connected to the first end of the fifth resistor R5;

[0099] The second end of the fifth resistor R5 is grounded;

[0100] The gate of the MOS tube M1 is connected to the drain of the MOS tube M16, the source of the MOS tube M1 is grounded, and the drain of the MOS tube M1 is connected to the VCC power voltage;

[0101] The buffer voltage Vb is the voltage of the drain of the MOS transistor M16. Figure 5 In the buffer voltage Vb, the access point is equivalent to point b. In the discharge module 1185, the PMOS transistors M15 and M16 constitute a current mirror, which has the same size to reduce the gain, increase the bandwidth, and improve the response speed of the circuit. When the NMOS transistor M14 is turned on, the M14, M15 and R4 branch generate a current, which is copied to the M16 and R5 branch through the current mirror. Since there is a current flowing through the resistor R5, the voltage at point b rises, that is, the voltage at the gate of M1 rises, M1 is turned on, and the VCC voltage is directly discharged to GND.

[0102] In the overvoltage protection circuit 118, when VCC is a normal voltage, the voltage of the sampling module 1181a at this time is low, the output voltage Vd of the reference module 1182 is fixed, and the expression of the comparison voltage Ve shows that the voltage at point e is low at this time, that is, the gate voltage of the NMOS transistor M14 of the discharge module 1185 is low, the voltage at point b Vb is low, and M14 is in the off state. At this time, the OUT terminal outputs a low level.

[0103] When VCC rises, the voltage at point a also rises, the output voltage Vd of the reference module 1182 does not change, and the expression of the comparison voltage Ve shows that the output voltage Ve at point e of the comparison module 1183 also rises. When VCC rises above the threshold VCC1, the voltage Ve at point e rises above the threshold voltage Vth of the NMOS transistor M14 of the discharge module 1185, the discharge module 1185 starts to work, the voltage Vb at point b becomes high, the NMOS transistor M1 is turned on, the VCC voltage is directly discharged to GND, and the overvoltage locking state is entered to prevent damage to other circuits. At this time, the OUT terminal outputs a high level.

[0104] When VCC falls, the voltage at point a also falls, the output voltage Vd of the reference module 1182 does not change, and the expression of the comparison voltage Ve shows that the output voltage Ve at point e of the comparison module 1183 also falls. When VCC falls below the threshold VCC1, the voltage Ve at point e falls below the threshold voltage Vth of the NMOS transistor M14 of the discharge module 1185.

[0105] The discharge module 1185 stops working, the voltage Vb at point b becomes low, the NMOS transistor M1 is turned off, and the overvoltage locking state is released. At this time, the OUT terminal outputs a low level.

[0106] According to the output of the overvoltage protection circuit 118, when the VCC voltage is in the normal working range, the voltage at the output end of the overvoltage protection circuit 118 is low, which has no effect on the fault logic control circuit and does not perform overvoltage protection.

[0107] When the VCC voltage is out of the normal working range, the voltage at the output end of the overvoltage protection circuit 118 is high, thereby controlling the fault logic control circuit to work, and the fault logic control circuit controls the simultaneous turn-off of the outputs of the chips HO and LO through the pulse circuit 107 and the AND gate 117.

[0108] The application has the advantages that the high-voltage integrated drive chip with integrated overvoltage protection circuit is provided, the circuit structure of the chip can directly detect and protect the power supply voltage of the drive chip in the traditional power module, the high-voltage drive chip is prevented from being burnt due to the excessively high power supply voltage, the service life of the high-voltage drive chip is prolonged, the overvoltage protection circuit integrated in the chip does not need a voltage stabilizing tube, the power consumption can be reduced, the anti-noise capability is improved, and the product stability and adaptability are improved.

[0109] It should be noted that in this document, the terms "comprising", "including", or any other variant thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements in the list, but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without more limitations, an element defined by the phrase "comprising a" does not exclude the existence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0110] The embodiments of the application are described above in conjunction with the drawings, and the disclosed are only the preferred embodiments of the application, but the application is not limited to the specific embodiments described above, and the specific embodiments described above are only illustrative, but not restrictive, and those skilled in the art can make many equivalent changes under the inspiration of the application without departing from the purpose of the application and the scope of the claims, and all the equivalent changes are within the protection of the application.

Claims

1. A high voltage integrated driver chip integrated with overvoltage protection function, characterized in that, The RC filter, a plurality of Schmidt circuits, a plurality of filters, a level conversion circuit, a dead zone interlocking circuit, a pulse circuit, a delay circuit, a bootstrap circuit, an under-voltage protection circuit, a temperature protection circuit, an ITRIP current protection circuit, a fault logic circuit, a fault output circuit, an RS flip-flop, an output circuit, an AND gate, and an over-voltage protection circuit, wherein: The RC filter accesses a high-level driving signal HIN and a low-level driving signal LIN, and sequentially passes through the Schmidt circuit, the filter, and the level conversion circuit to output to the dead zone interlocking circuit, and makes the dead zone interlocking circuit output a high-level pulse signal HINa to a first input end of the pulse circuit and a low-level pulse signal LINa to the delay circuit; The pulse circuit outputs ON_PLUSE / SET and OFF_PLUSE / RESET short pulse signals according to rising and falling edges of the high-level pulse signal HINa to drive a high-voltage LDMOS, and the high-voltage LDMOS triggers the RS flip-flop to turn on and off and controls the output circuit to output a high-level driving pulse signal HO; The delay circuit outputs the low-level pulse signal LINa to a first input end of the AND gate, and controls the output circuit to output a low-level driving pulse signal LO through an output end of the AND gate; An input end of the under-voltage protection circuit accesses a VCC power supply voltage, and an output end of the under-voltage protection circuit accesses a first input end of the fault logic circuit; An input end of the bootstrap circuit accesses the VCC power supply voltage, and an output end of the bootstrap circuit accesses the high-voltage LDMOS and the output circuit to provide a bootstrap voltage; An input end of the temperature protection circuit accesses a transient voltage suppressor TVC through the level conversion circuit, the filter, and the Schmidt circuit; An input end of the ITRIP current protection circuit accesses a trigger current ITRIP through the level conversion circuit, the filter, and the Schmidt circuit, and an output end of the ITRIP current protection circuit accesses a second input end of the fault logic circuit; A first output end of the fault logic circuit accesses a second input end of the pulse circuit and a second input end of the AND gate, and a second input end of the fault logic circuit accesses the fault output circuit; An input end of the over-voltage protection circuit accesses the VCC power supply voltage, and an output end of the over-voltage protection circuit accesses a third input end of the fault logic circuit, and the over-voltage protection circuit is used to output a high-level signal to the fault logic circuit when the VCC power supply voltage exceeds a preset working range of the high-voltage integrated driving chip, so as to control the fault logic circuit to cut off the output of the high-level driving pulse signal HO and the low-level driving pulse signal LO through the pulse circuit and the AND gate; The over-voltage protection circuit comprises a sampling module, a reference module, a comparison module, a starting module, and a bleeding module, and two ends of each of the sampling module, the reference module, the comparison module, the starting module, and the bleeding module are connected with the VCC power supply voltage and the ground, respectively, wherein: The sampling module is configured to obtain a sampling voltage Va and send the sampling voltage Va to the comparison module, the sampling voltage Va being positively correlated with the voltage of the VCC power supply voltage; The reference module is configured to output a reference voltage Vd to the comparison module; The comparison module is configured to compare the difference between the sampling voltage Va and the reference voltage Vd and output a comparison voltage Ve; The starting module is configured to access the reference voltage Vd and feed back the output to the reference module; The bleeding module is configured to compare the buffer voltage Vb with the comparison voltage Ve, and when the comparison voltage Ve is high and the buffer voltage Vb is low, the voltage of the VCC power supply voltage is discharged through the ground terminal.

2. The high voltage integrated driver IC integrated with overvoltage protection function according to claim 1, characterized in that, The sampling module comprises a resistor R1 and a resistor R2, a first end of the resistor R1 is connected to the VCC power voltage, a second end of the resistor R1 is connected to a first end of the resistor R2, a second end of the resistor R2 is grounded, the sampling voltage Va is a voltage of the second end of the resistor R1, and the sampling voltage .

3. The high voltage integrated driver IC with integrated overvoltage protection function according to claim 2, characterized in that, The reference module comprises MOS tubes M5, M6, M7, M8 and a resistor R3, wherein the MOS tubes M5 and M6 are NMOS tubes with the same length and width, and the MOS tubes M7 and M8 are PMOS tubes with the same length and width; The drain of the MOS tube M5 is connected to the drain of the MOS tube M7, the gate of the MOS tube M5 is connected to the drain of the MOS tube M7 and the gate of the MOS tube M6, and the source of the MOS tube M5 is grounded; The drain of the MOS tube M6 is connected to the drain and gate of the MOS tube M8, and the source of the MOS tube M6 is connected to the first end of the resistor R3; The second end of the resistor R3 is grounded; The source of the MOS tube M7 is connected to the VCC power supply voltage, and the gate of the MOS tube M7 is connected to the gate of the MOS tube M8; The source of the MOS tube M8 is connected to the VCC power supply voltage; The reference voltage Vd is the voltage of the drain of the MOS transistor M6, and the reference voltage wherein, represents the equivalent internal resistance of the MOS transistor, , respectively represent the electron mobility and the unit-area gate-oxide-capacitance of the MOS transistor, and W and L are respectively the channel width and the length of the MOS transistor.

4. The high voltage integrated driver IC with integrated overvoltage protection function according to claim 3, characterized in that, The comparison module comprises MOS tubes M9, M10, M11, M12 and M13, wherein the MOS tubes M9, M10 and M11 are NMOS tubes, and the MOS tubes M12 and M13 are PMOS tubes; The source of the MOS tube M9 is grounded, the gate of the MOS tube M9 is connected to the drain of the MOS tube M6 to access the reference voltage Vd, and the drain of the MOS tube M9 is connected to the sources of the MOS tubes M10 and M11; The gate of the MOS tube M10 is connected to the drain of the MOS tube M6 to access the reference voltage Vd, and the drain of the MOS tube M10 is connected to the drain and gate of the MOS tube M12; The gate of the MOS tube M11 is connected to the second end of the resistor R1 to access the sampling voltage Va, and the drain of the MOS tube M11 is connected to the drain of the MOS tube M13; The gate of the MOS tube M12 is connected to the gate of the MOS tube M13, and the source of the MOS tube M12 is connected to the VCC power supply voltage; The source of the MOS tube M13 is connected to the VCC power supply voltage; The comparison voltage Ve is the voltage of the drain of the MOS transistor M11. The comparison voltage wherein, denotes the transconductance of the MOS transistor.

5. The high voltage integrated driver IC with integrated overvoltage protection function according to claim 4, characterized in that, The starting module comprises MOS tubes M4, M2 and M3, wherein the MOS tube M4 is a PMOS tube, and the MOS tubes M2 and M3 are NMOS tubes; The source of the MOS tube M4 is connected to the VCC power voltage, the drain of the MOS tube M4 is connected to the drain and gate of the MOS tube M2, and the gate of the MOS tube M4 is connected to the reference voltage Vd; The source of the MOS tube M2 is grounded, and the gate of the MOS tube M2 is connected to the gate of the MOS tube M3; The source of the MOS tube M3 is grounded, and the drain of the MOS tube M3 is connected to the gate and drain of the MOS tube M8.

6. The high voltage integrated driver IC with integrated overvoltage protection function according to claim 5, characterized in that, The bleeder module comprises MOS tubes M14, M15, M16, M1, a fourth resistor R4 and a fifth resistor R5, wherein the MOS tubes M14 and M15 are NMOS tubes, and the MOS tubes M16 and M1 are PMOS tubes; The source of the MOS tube M14 is connected to the first end of the fourth resistor R4, the drain of the MOS tube M14 is connected to the source and gate of the MOS tube M15, and the gate of the MOS tube M14 is connected to the drain of the MOS tube M11 to be connected to the comparison voltage Ve; The second end of the fourth resistor R4 is grounded; The gate of the MOS tube M15 is connected to the gate of the MOS tube M16, and the source of the MOS tube M15 is connected to the power voltage VCC; The source of the MOS tube M16 is connected to the VCC power voltage, and the drain of the MOS tube M16 is connected to the first end of the fifth resistor R5; The second end of the fifth resistor R5 is grounded; The gate of the MOS tube M1 is connected to the drain of the MOS tube M16, the source of the MOS tube M1 is grounded, and the drain of the MOS tube M1 is connected to the VCC power voltage; The buffer voltage Vb is the voltage of the drain of the MOS tube M16.

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