Variable voltage type active gate driver and driving method

Abstract

The invention discloses a variable voltage type active gate driver, which relates to the technical field of gate drivers and comprises a controller, a gate voltage monitoring circuit, a gate driving circuit, a gate voltage adjusting circuit and a target MOSFET DUT. The output end of the controller is connected with the grid of the transistor of the grid driving circuit and the grid of the transistor of the grid voltage adjusting circuit, and the input end is connected with the output end of the grid voltage monitoring circuit; the grid electrode of the target MOSFET DUT is connected with the grid electrode voltage monitoring circuit, the grid electrode driving circuit and the grid electrode voltage adjusting circuit, and the source electrode of the target MOSFET DUT is connected with the grid electrode voltage monitoring circuit and the grid electrode driving circuit. According to the invention, the gate-source voltage of the target MOSFET DUT is monitored in real time through the controller, the operation of the gate driving circuit and the gate voltage adjusting circuit is controlled at different switching-on and switching-off stages of the target MOSFET DUT, controllable gate driving voltage is provided, and source-drain voltage of the MOSFET and overshoot and oscillation of current are effectively reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of gate drivers, and more specifically, to a variable voltage active gate driver and a driving method. Background Art

[0002] Nowadays, the power density of power conversion modules is getting higher and higher, and the operating voltage and current of power devices are also getting higher and higher, which makes the drain-source overshoot voltage and overshoot current of power devices increasingly serious, and even affects the safety of system operation. Taking Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) as an example, the overshoot current of MOSFET occurs in the turn-on stage of the power device. Due to the parasitic capacitance of MOSFET and other reasons, the drain-source current of the power device exceeds the load current in a short time. The overshoot voltage of MOSFET occurs in the turn-off stage of the power device. Due to the parasitic inductance of MOSFET and circuit and the high drain-source current change rate of the device, the instantaneous voltage across the drain and source of MOSFET exceeds the bus voltage. The overshoot voltage and overshoot current of the power device are unstable factors in the circuit. In severe cases, they may even exceed the maximum voltage and current of the device in the circuit, causing device damage and threatening the safety of system operation. Therefore, the research on how to reduce the overshoot voltage and overshoot current of power devices is also increasing.

[0003] Traditional optimization methods focus on increasing drive resistance, optimizing circuit layout, etc., and the improvement effect of such methods is limited. Active gate drive technology can effectively improve this problem. During the switching process of MOSFET, the active gate driver can dynamically adjust the parameters of the gate drive circuit according to different switching stages and circuit states, thereby controlling the charge and discharge rate of the gate capacitance and realizing the shaping and optimization of the switching waveform. However, the active gate drive technology currently used to optimize the overshoot voltage and overshoot current of power devices is relatively complex, and it is difficult to simply and effectively reduce the overshoot voltage and overshoot current of power devices, and cannot adapt to various application scenarios. Summary of the invention

[0004] The purpose of the present invention is to overcome the problems existing in the prior art and to provide a variable voltage active gate driver and a driving method which can control the gate voltage of MOSFET at specific stages of MOSFET turning on and off, and effectively reduce the overshoot voltage and overshoot current of the power device.

[0005] The present invention aims to solve the above technical problems at least to a certain extent.

[0006] To achieve the above object, the technical solution of the present invention is as follows:

[0007] A variable voltage active gate driver, comprising:

[0008] A controller, a gate voltage monitoring circuit, a gate driving circuit, a gate voltage adjustment circuit and a target MOSFET DUT, wherein the control signal output end of the controller is respectively connected to the output end of the gate voltage monitoring circuit, the gate of the transistor of the gate driving circuit, and the gate of the transistor of the gate voltage adjustment circuit, the gate of the target MOSFET DUT is respectively connected to the gate voltage monitoring circuit, the gate driving circuit, and the gate voltage adjustment circuit, and the source of the target MOSFET DUT is respectively connected to the gate voltage monitoring circuit and the gate driving circuit.

[0009] Preferably, the controller U1 includes a processor unit, an isolation drive unit and a gate voltage processing unit, pin 3 of the controller U1 is an input pin, which is internally connected to the gate voltage processing unit, pins 1, 2, 4, and 5 of the controller U1 are output pins, which are internally connected to the isolation drive unit, and the processor unit is connected to the isolation drive unit and the gate voltage processing unit.

[0010] Preferably, the controller U1 processes and monitors the gate-source voltage of the target MOSFET DUT in real time through the gate voltage processing unit, and outputs gate control signals of the first transistor Q1, the second transistor Q2, the third transistor Q3 and the fourth transistor Q4 through the isolation driving unit to control the switching of each transistor.

[0011] Preferably, the gate drive circuit includes a positive power supply VDD, a negative power supply VSS, a first transistor Q1, a second transistor Q2, a first resistor R1 and a second resistor R2, the positive output end of the positive power supply VDD is connected to the drain of the first transistor Q1, the gate of the first transistor Q1 is connected to pin 4 of the controller U1, the source of the first transistor Q1 is connected to one end of the first resistor R1, the other end of the first resistor R1 is connected to one end of the second resistor R2, the other end of the second resistor R2 is connected to the drain of the second transistor Q2, the gate of the second transistor Q2 is connected to pin 2 of the controller U1, the source of the second transistor Q2 is connected to the negative output end of the negative power supply VSS, and the negative output end of the positive power supply VDD is connected to the positive output end of the negative power supply VSS.

[0012] Preferably, the gate voltage adjustment circuit includes a third transistor Q3, a fourth transistor Q4, a third resistor R3, a fourth resistor R4, a first capacitor C1 and a second capacitor C2, the gate of the third transistor Q3 is connected to the pin 5 of the controller U1, the drain of the third transistor Q3 is connected to the positive output end of the positive power supply VDD and the drain of the first transistor Q1, the source of the third transistor Q3 is connected to one end of the third resistor R3 and one end of the first capacitor C1, the other end of the third resistor R3 is connected to one end of the fourth resistor R4, the other end of the first capacitor C1 is connected to one end of the second capacitor C2, the other end of the fourth resistor R4 and the other end of the second capacitor C2 are connected to the drain of the fourth transistor Q4, the gate of the fourth transistor Q4 is connected to the pin 1 of the controller U1, and the source of the fourth transistor Q4 is connected to the negative output end of the negative power supply VSS and the source of the second transistor Q2.

[0013] Preferably, the gate voltage monitoring circuit is an isolation amplifier circuit, comprising an operational amplifier U2, wherein the output pin 1 of the operational amplifier U2 is connected to the pin 3 of the controller U1, the positive input pin 2 of the operational amplifier U2 is connected to the other end of the first resistor R1, one end of the second resistor R2, the other end of the third resistor R3, one end of the fourth resistor R4, the other end of the first capacitor C1, and one end of the second capacitor C2, and the negative input pin 3 of the operational amplifier U2 is connected to the negative output end of the positive power supply VDD and the positive output end of the negative power supply VSS.

[0014] Preferably, the gate of the target MOSFET DUT is connected to the other end of the first capacitor C1, one end of the second capacitor C2, the other end of the third resistor R3, one end of the fourth resistor R4, the other end of the first resistor R1, one end of the second resistor R2, and the positive input pin 2 of the operational amplifier U2, and the source of the target MOSFET DUT is connected to the negative output end of the positive power supply VDD, the positive output end of the negative power supply VSS, and the negative input pin 3 of the operational amplifier U2.

[0015] Preferably, the gate voltage monitoring circuit is an isolation amplifier circuit, which is used to monitor the voltage across the gate and source of the target MOSFET DUT in real time, and convert the gate-source voltage of the target MOSFET DUT into a signal that can be received and processed by the controller U1. The controller U1 controls the switching of each transistor according to the receivable and processable signal to control the gate voltage, thereby adjusting the circuit operation.

[0016] To achieve the purpose of the invention, the present invention also provides a variable voltage active gate driver driving method, which is applied to a variable voltage active gate driver of the above technical solution, and the driving method includes a turn-on process and a turn-off process;

[0017] The turn-on process includes the following steps: Step S11: the controller U1 controls the first transistor Q1 to turn on, charging the gate of the target MOSFET DUT;

[0018] Step S12: when the gate-source voltage of the target MOSFET DUT enters the Miller platform stage, the controller U1 controls the fourth transistor Q4 to turn on to reduce the gate-source voltage of the target MOSFET DUT;

[0019] Step S13: when the gate-source voltage of the target MOSFET DUT ends the Miller platform stage, the controller U1 controls the fourth transistor Q4 to turn off, so that the target MOSFET DUT is fully turned on;

[0020] The shutdown process includes the following steps: Step S21: the controller U1 controls the second transistor Q2 to turn on to discharge the gate of the target MOSFET DUT;

[0021] Step S22: when the drain-source voltage of the target MOSFET DUT ends the Miller platform stage, the controller U1 controls the third transistor Q3 to turn on, so as to increase the gate-source voltage of the target MOSFET DUT;

[0022] Step S23: When the target MOSFET DUT is fully turned on, the controller U1 controls the third transistor Q3 to turn off.

[0023] Preferably, the first capacitor C1 and the second capacitor C2 are used to provide a low impedance path for the gate current of the target MOSFET DUT at the moment when the third transistor Q3 and the fourth transistor Q4 are turned on, thereby improving the reaction speed of the circuit.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] The present invention monitors the gate-source voltage of the target MOSFET DUT in real time through the controller U1, controls the operation of the gate drive circuit and the gate voltage adjustment circuit at different stages of turning on and off the target MOSFET DUT, provides a controlled gate drive voltage for the MOSFET, reduces the complexity of the circuit structure and the driving method, and effectively reduces the source-drain voltage of the MOSFET and the overshoot and oscillation of the current. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A circuit schematic diagram of a variable voltage active gate driver according to Embodiment 1 of the present application;

[0027] Figure 2 This is a waveform diagram of the switching process of a variable voltage active gate driver according to Example 2 of the present application. DETAILED DESCRIPTION

[0028] In order to more clearly understand the above-mentioned purpose, features and advantages of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the embodiments of the present application and the features in the embodiments can be combined with each other without conflict.

[0029] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the protection scope of the present invention is not limited to the specific embodiments disclosed below.

[0030] Example 1

[0031] See also Figure 1 Embodiment 1 of the present application provides a variable voltage active gate driver, including a controller, a gate voltage monitoring circuit, a gate driving circuit, a gate voltage adjustment circuit and a target MOSFET DUT (Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), Device Under Test (DUT)), wherein the control signal output end of the controller is respectively connected to the output end of the gate voltage monitoring circuit, the gate of the transistor of the gate driving circuit, and the gate of the transistor of the gate voltage adjustment circuit, the gate of the target MOSFET DUT is respectively connected to the gate voltage monitoring circuit, the gate driving circuit, and the gate voltage adjustment circuit, and the source of the target MOSFET DUT is respectively connected to the gate voltage monitoring circuit and the gate driving circuit.

[0032] The controller U1 includes a processor unit, an isolation drive unit and a gate voltage processing unit. Pin 3 of the controller U1 is an input pin, which is internally connected to the gate voltage processing unit. Pins 1, 2, 4 and 5 of the controller U1 are output pins, which are internally connected to the isolation drive unit. The processor unit is connected to the isolation drive unit and the gate voltage processing unit. The controller U1 processes and monitors the gate-source voltage of the target MOSFET DUT in real time through the gate voltage processing unit, and outputs gate control signals of the first transistor Q1, the second transistor Q2, the third transistor Q3 and the fourth transistor Q4 through the isolation drive unit to control the switching of each transistor.

[0033] The gate drive circuit includes a positive power supply VDD, a negative power supply VSS, a first transistor Q1, a second transistor Q2, a first resistor R1 and a second resistor R2. The positive output terminal of the positive power supply VDD is connected to the drain of the first transistor Q1, the gate of the first transistor Q1 is connected to pin 4 of the controller U1, the source of the first transistor Q1 is connected to one end of the first resistor R1, the other end of the first resistor R1 is connected to one end of the second resistor R2, the other end of the second resistor R2 is connected to the drain of the second transistor Q2, the gate of the second transistor Q2 is connected to pin 2 of the controller U1, the source of the second transistor Q2 is connected to the negative output terminal of the negative power supply VSS, and the negative output terminal of the positive power supply VDD is connected to the positive output terminal of the negative power supply VSS.

[0034] The gate voltage adjustment circuit includes a third transistor Q3, a fourth transistor Q4, a third resistor R3, a fourth resistor R4, a first capacitor C1 and a second capacitor C2. The gate of the third transistor Q3 is connected to pin 5 of the controller U1, the drain of the third transistor Q3 is connected to the positive output end of the positive power supply VDD and the drain of the first transistor Q1, the source of the third transistor Q3 is connected to one end of the third resistor R3 and one end of the first capacitor C1, the other end of the third resistor R3 is connected to one end of the fourth resistor R4, the other end of the first capacitor C1 is connected to one end of the second capacitor C2, the other end of the fourth resistor R4 and the other end of the second capacitor C2 are connected to the drain of the fourth transistor Q4, the gate of the fourth transistor Q4 is connected to pin 1 of the controller U1, and the source of the fourth transistor Q4 is connected to the negative output end of the negative power supply VSS and the source of the second transistor Q2.

[0035] The gate voltage monitoring circuit is an isolation amplifier circuit, including an operational amplifier U2, wherein the output pin 1 of the operational amplifier U2 is connected to the pin 3 of the controller U1, the positive input pin 2 of the operational amplifier U2 is connected to the other end of the first resistor R1, one end of the second resistor R2, the other end of the third resistor R3, one end of the fourth resistor R4, the other end of the first capacitor C1, and one end of the second capacitor C2, and the negative input pin 3 of the operational amplifier U2 is connected to the negative output end of the positive power supply VDD and the positive output end of the negative power supply VSS.

[0036] The gate of the target MOSFET DUT is connected to the other end of the first capacitor C1, one end of the second capacitor C2, the other end of the third resistor R3, one end of the fourth resistor R4, the other end of the first resistor R1, one end of the second resistor R2, and the positive input pin 2 of the operational amplifier U2, and the source of the target MOSFET DUT is connected to the negative output end of the positive power supply VDD, the positive output end of the negative power supply VSS, and the negative input pin 3 of the operational amplifier U2. The gate voltage monitoring circuit is an isolation amplifier circuit, which is used to monitor the voltage across the gate and source of the target MOSFET DUT in real time, and convert the gate-source voltage of the target MOSFET DUT into a signal that can be received and processed by the controller U1. The controller U1 controls the switches of each transistor according to the signal that can be received and processed to control the gate voltage, thereby adjusting the circuit operation and reducing the source-drain voltage of the MOSFET and the overshoot and oscillation of the current. The first capacitor C1 and the second capacitor C2 are used to provide a low-impedance path for the gate current of the target MOSFET DUT at the moment when the third transistor Q3 and the fourth transistor Q4 are turned on, thereby improving the reaction speed of the circuit.

[0037] Example 2

[0038] Based on Embodiment 1, Embodiment 2 provides a variable voltage active gate driver driving method, which is applied to a variable voltage active gate driver in Embodiment 1. The driving method is specifically as follows:

[0039] The driving method includes a turn-on process and a turn-off process;

[0040] The opening process includes the following steps:

[0041] Step S11: the controller U1 controls the first transistor Q1 to turn on, and charges the gate of the target MOSFET DUT;

[0042] Step S12: when the gate-source voltage of the target MOSFET DUT enters the Miller platform stage, the controller U1 controls the fourth transistor Q4 to turn on to reduce the gate-source voltage of the target MOSFET DUT;

[0043] Step S13: When the gate-source voltage of the target MOSFET DUT ends the Miller platform stage, the controller U1 controls the fourth transistor Q4 to turn off, so that the target MOSFET DUT is fully turned on.

[0044] The shutdown process includes the following steps:

[0045] Step S21: the controller U1 controls the second transistor Q2 to turn on, discharging the gate of the target MOSFET DUT;

[0046] Step S22: when the drain-source voltage of the target MOSFET DUT ends the Miller platform stage, the controller U1 controls the third transistor Q3 to turn on to increase the gate-source voltage of the target MOSFET DUT;

[0047] Step S23: When the target MOSFET DUT is fully turned on, the controller U1 controls the third transistor Q3 to be turned off.

[0048] See also Figure 2 , Figure 2 It is a waveform diagram of the switching process of a variable voltage active gate driver of this embodiment 2. The following is a detailed description of some states of the waveform diagram:

[0049] Opening process:

[0050] t1-t2: The gate current charges the capacitor Cgs until the voltage Vgs reaches the MOSFET threshold voltage.

[0051] t2-t3: When Vgs reaches the threshold voltage, the current I D starts to rise, and V DS There is a slight decrease due to the change in current through the parasitic inductance of the component.

[0052] t3-t5: The DUT device enters the Miller platform stage. The gate current Ig mainly charges the capacitor Cdg, and the gate voltage Vgs is almost maintained. At this time, V DS Start to lower, I D To reduce the gate voltage Vgs, reduce I D peak, transistor Q4 is turned on during t3-t5.

[0053] t5-t6: Transistor Q4 is turned off, V DS drops to zero and Vgs rises to VDD.

[0054] Shutdown process:

[0055] t7-t9: Turn-off delay, the gate current discharges the capacitor Cgs, and the gate voltage begins to drop;

[0056] t9-t11 :The device enters the Miller platform stage, the gate current discharges the capacitor Cdg, Vds starts to rise, and the current I D Slightly down;

[0057] t 11 -t 12 :The Miller phase ends, the gate voltage Vgs continues to decrease to the threshold voltage, and the current I D Rapidly drops to zero, causing V DS To increase the gate voltage Vgs, reduce V DS peak, transistor Q3 is turned on at t11-t12.

[0058] t 12 -t 13 : Transistor Q3 is turned off, V DS Rising to the bus voltage, Vgs decreases to VSS.

[0059] Other technical details of this embodiment 2 are the same as those of embodiment 1 and will not be repeated here.

[0060] Example 3

[0061] This embodiment 3 is based on embodiment 1 and embodiment 2, and further discloses the following contents:

[0062] During the Miller platform phase of the MOSFET’s turn-on process, the gate current begins to feed the gate-drain capacitance C GD Charging, drain-source voltage v DS starts to decrease. At the same time, due to C GD Ratio gate-source capacitance C GS Much larger, the gate drive power supply v GS remains almost constant, resulting in the Miller platform phenomenon. In the above process, due to the junction capacitance C of the anti-parallel diode DH The reverse recovery current i D The parasitic inductance in the main power circuit will also cause the capacitor C DH The resonance and i D Oscillation on C DH The charging current can be expressed as:

[0063]

[0064] where v DH It is C DH The voltage across the two ends. The rate of change of drain-source voltage is:

[0065]

[0066] Among them, i g is the gate current of the MOSFET. In order to reduce iD The current spike on the DH This can be achieved by reducing the gate drive voltage v GS to achieve effectively.

[0067] Therefore, the above analysis shows that the drain-source overshoot current of MOSFET can be controlled by controlling the gate drive voltage in the Miller platform stage. The present invention adjusts the gate drive voltage during the MOSFET turn-on process by adding a low-voltage control branch.

[0068] In combination with the variable voltage active gate driver proposed in Example 1, the following method can be applied to effectively reduce the drain-source overshoot current during the MOSFET turn-on process:

[0069] Step 1: The controller U1 controls the first transistor Q1 to turn on, charging the gate of the target MOSFET DUT, and the controller continuously monitors the MOSFET gate-source voltage;

[0070] Step 2: When the gate-source voltage of the target MOSFET enters the Miller platform stage, the controller U1 controls the fourth transistor Q4 to turn on to reduce the gate-source voltage of the target MOSFET and reduce v DH The rising speed of the current indirectly reduces the drain-source overshoot current.

[0071] Step 3: When the gate-source voltage of the target MOSFET ends the Miller platform stage, the controller U1 controls the fourth transistor Q4 to turn off, so that the target MOSFET is fully turned on.

[0072] After the Miller platform phase of the MOSFET turn-off process ends, the drain-source voltage reaches the bus voltage. At the same time, the drain-source current begins to decrease. However, due to the parasitic inductance in the MOSFET device and circuit, a reverse electromotive force is generated at both ends of the MOSFET drain-source to prevent the current from decreasing. This reverse electromotive force causes the drain-source voltage of the MOSFET to exceed the bus voltage, forming an overshoot voltage. The voltage loop expression is:

[0073]

[0074] Among them, L p is the loop parasitic inductance. The rate of change of drain-source current is:

[0075]

[0076] where g fs is the transconductance of the MOSFET, C iss is the input resistance of the MOSFET. In order to reduce the voltage overshoot, it is necessary to control and reduce i D This can be effectively achieved by increasing the gate drive voltage.

[0077] The above analysis shows that the drain-source overshoot voltage of MOSFET can be controlled by controlling the gate current after the Miller platform stage. The present invention adjusts the gate drive voltage during the MOSFET shutdown process by adding a high-voltage control branch.

[0078] Combined with the proposed variable resistor active gate driver, the following method can be used to effectively reduce the drain-source overshoot voltage during the MOSFET turn-off process:

[0079] Step 1: The controller U1 controls the second transistor Q2 to turn on, discharging the gate of the target MOSFET, while the controller continuously monitors the gate-source voltage of the MOSFET;

[0080] Step 2: When the drain-source voltage of the target MOSFET DUT ends the Miller platform stage, the controller U1 controls the third transistor Q3 to turn on to increase the gate-source voltage of the target MOSFET DUT and reduce i D The falling speed of the supply voltage can be reduced, which indirectly reduces the drain-source overshoot voltage.

[0081] In the third step, when the target MOSFET DUT is fully turned on, the controller U1 controls the third transistor to turn off.

[0082] Other technical details of this embodiment 3 are the same as those of embodiment 1 or embodiment 2 and will not be repeated here.

[0083] In summary, the present invention is designed to include a controller U1, a gate voltage monitoring circuit U2, a gate drive circuit, a gate voltage adjustment circuit and a variable voltage active gate driver of a target MOSFET DUT. The controller U1 monitors the gate-source voltage of the target MOSFET DUT in real time, controls the operation of the gate drive circuit and the gate voltage adjustment circuit at different stages of turning on and off the target MOSFET DUT, and dynamically adjusts the parameters of the gate drive circuit to control the charge and discharge rate of the gate capacitance, thereby achieving the shaping and optimization of the switching waveform, and effectively reducing the source-drain voltage of the MOSFET and the overshoot and oscillation of the current.

[0084] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the embodiments here. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the claims of the present invention.

Claims

1. A variable voltage active gate driver, characterized in that: It includes a controller, a gate voltage monitoring circuit, a gate driving circuit, a gate voltage adjustment circuit and a target MOSFET DUT. The control signal output end of the controller is connected to the gate of the transistor of the gate driving circuit and the gate of the transistor of the gate voltage adjustment circuit. The signal input end of the controller is connected to the output end of the gate voltage monitoring circuit. The gate of the target MOSFET DUT is respectively connected to the gate voltage monitoring circuit, the gate driving circuit and the gate voltage adjustment circuit. The source of the target MOSFET DUT is respectively connected to the gate voltage monitoring circuit and the gate driving circuit.

2. A variable voltage active gate driver according to claim 1, characterized in that: The controller U1 includes a processor unit, an isolation drive unit and a gate voltage processing unit. Pin 3 of the controller U1 is an input pin, which is internally connected to the gate voltage processing unit. Pins 1, 2, 4, and 5 of the controller U1 are all output pins, which are internally connected to the isolation drive unit. The processor unit is connected to the isolation drive unit and the gate voltage processing unit.

3. A variable voltage active gate driver according to claim 2, characterized in that: The controller U1 processes and monitors the gate-source voltage of the target MOSFET DUT in real time through the gate voltage processing unit, and outputs gate control signals of the first transistor Q1, the second transistor Q2, the third transistor Q3 and the fourth transistor Q4 through the isolation driving unit to control the switching of each transistor.

4. The variable voltage active gate driver according to claim 2, characterized in that: The gate drive circuit includes a positive power supply VDD, a negative power supply VSS, a first transistor Q1, a second transistor Q2, a first resistor R1 and a second resistor R2. The positive output end of the positive power supply VDD is connected to the drain of the first transistor Q1, the gate of the first transistor Q1 is connected to pin 4 of the controller U1, the source of the first transistor Q1 is connected to one end of the first resistor R1, the other end of the first resistor R1 is connected to one end of the second resistor R2, the other end of the second resistor R2 is connected to the drain of the second transistor Q2, the gate of the second transistor Q2 is connected to pin 2 of the controller U1, the source of the second transistor Q2 is connected to the negative output end of the negative power supply VSS, and the negative output end of the positive power supply VDD is connected to the positive output end of the negative power supply VSS.

5. The variable voltage active gate driver according to claim 4, characterized in that: The gate voltage adjustment circuit includes a third transistor Q3, a fourth transistor Q4, a third resistor R3, a fourth resistor R4, a first capacitor C1 and a second capacitor C2. The gate of the third transistor Q3 is connected to the pin 5 of the controller U1, the drain of the third transistor Q3 is connected to the positive output end of the positive power supply VDD and the drain of the first transistor Q1, the source of the third transistor Q3 is connected to one end of the third resistor R3 and one end of the first capacitor C1, the other end of the third resistor R3 is connected to one end of the fourth resistor R4, the other end of the first capacitor C1 is connected to one end of the second capacitor C2, the other end of the fourth resistor R4 and the other end of the second capacitor C2 are connected to the drain of the fourth transistor Q4, the gate of the fourth transistor Q4 is connected to the pin 1 of the controller U1, and the source of the fourth transistor Q4 is connected to the negative output end of the negative power supply VSS and the source of the second transistor Q2.

6. A variable voltage active gate driver according to claim 5, characterized in that: The gate voltage monitoring circuit includes an operational amplifier U2, wherein the output pin 1 of the operational amplifier U2 is connected to the pin 3 of the controller U1, the positive input pin 2 of the operational amplifier U2 is connected to the other end of the first resistor R1, one end of the second resistor R2, the other end of the third resistor R3, one end of the fourth resistor R4, the other end of the first capacitor C1, and one end of the second capacitor C2, and the negative input pin 3 of the operational amplifier U2 is connected to the negative output end of the positive power supply VDD and the positive output end of the negative power supply VSS.

7. The variable voltage active gate driver according to claim 6, characterized in that: The gate of the target MOSFET DUT is connected to the other end of the first capacitor C1, one end of the second capacitor C2, the other end of the third resistor R3, one end of the fourth resistor R4, the other end of the first resistor R1, one end of the second resistor R2, and the positive input pin 2 of the operational amplifier U2, and the source of the target MOSFET DUT is connected to the negative output end of the positive power supply VDD, the positive output end of the negative power supply VSS, and the negative input pin 3 of the operational amplifier U2.

8. The variable voltage active gate driver according to claim 1, characterized in that: The gate voltage monitoring circuit is an isolation amplifier circuit, which is used to monitor the voltage across the gate and source of the target MOSFET DUT in real time, and convert the gate-source voltage of the target MOSFET DUT into a signal that can be received and processed by the controller U1. The controller U1 controls the switching of each transistor according to the receivable and processable signal to control the gate voltage, thereby adjusting the circuit operation.

9. A variable voltage active gate driver driving method, applied to a variable voltage active gate driver such as any one of claims 1 to 8, characterized in that: The driving method includes a switching process and a switching process; The opening process comprises the following steps: Step S11: the controller U1 controls the first transistor Q1 to turn on, and charges the gate of the target MOSFET DUT; Step S12: when the gate-source voltage of the target MOSFET DUT enters the Miller platform stage, the controller U1 controls the fourth transistor Q4 to turn on to reduce the gate-source voltage of the target MOSFET DUT; Step S13: when the gate-source voltage of the target MOSFET DUT ends the Miller platform stage, the controller U1 controls the fourth transistor Q4 to turn off, so that the target MOSFET DUT is fully turned on; The shutdown process includes the following steps: Step S21: the controller U1 controls the second transistor Q2 to turn on to discharge the gate of the target MOSFET DUT; Step S22: when the drain-source voltage of the target MOSFET DUT ends the Miller platform stage, the controller U1 controls the third transistor Q3 to turn on, so as to increase the gate-source voltage of the target MOSFET DUT; Step S23: When the target MOSFET DUT is fully turned on, the controller U1 controls the third transistor Q3 to be turned off.

10. A variable voltage active gate driver driving method according to claim 9, characterized in that: The first capacitor C1 and the second capacitor C2 are used to provide a low impedance path for the gate current of the target MOSFET DUT at the moment when the third transistor Q3 and the fourth transistor Q4 are turned on, thereby improving the response speed of the circuit.

Images