A DSP power supply system for spaceborne detection payloads

Abstract

The present application provides a DSP power supply system for a satellite-borne detection payload, including a DSP processor, the DSP processor is connected to an input voltage source through a first output power supply circuit to provide an adjustable core voltage to the DSP processor, and the adjustable core voltage is a CVDD core voltage; the DSP processor is also connected to the input voltage source through a second output power supply circuit to provide a fixed core voltage and a fixed interface voltage to the DSP processor, the fixed core voltage includes a CVDD 1.0V voltage, and the fixed interface voltage includes a DVDD1.5V and a DVDD1.8V voltage; the first output power supply circuit is connected to the second output power supply circuit, and the enable signal and the state indication signal of the control circuit are used to sequentially supply power to the voltages of the DSP processor. The present application can realize reliable control of the power-on timing of the voltages of the DSP processor at each level, and ensure the operational stability and reliability of the satellite-borne satellite detection payload.

Description

Technical Field

[0001] The present application belongs to the technical field of satellite-borne detection payloads, and in particular relates to a DSP power supply system applied to satellite-borne detection payloads. Background Art

[0002] DSP (Digital Signal Processor) is a high-performance digital signal processor with ultra-large-scale integration, good embeddability and programmability, and rich peripheral interfaces. Therefore, it can be seamlessly integrated with traditional on-board processors to share the computing pressure of traditional on-board data processors.

[0003] However, the power supply system design for DSP chips is complex, with numerous supply voltage types, high power consumption, and strict power-up sequencing requirements. Conventional DSPs use up to 14 different power supply voltages. Furthermore, the variable core voltage requires adaptive voltage compensation due to the differences in die and wafer size used in different chips, making it impossible to provide a fixed voltage like traditional power supply methods. Furthermore, the processor internally distinguishes between analog and digital power supply areas, further complicating the design of the power supply system for DSP processors. Summary of the Invention

[0004] In view of this, the present application aims to propose a DSP power supply system for a satellite-borne detection payload to solve at least one of the above problems.

[0005] To achieve the above objectives, the technical solution of this application is implemented as follows: The present application provides a DSP power supply system for a spaceborne detection payload, comprising a DSP processor, wherein the DSP processor is connected to an input voltage source via a first output power supply circuit to provide an adjustable core voltage to the DSP processor, wherein the adjustable core voltage is a CVDD core voltage; The DSP processor is further connected to an input voltage source via a second output power supply circuit to provide a fixed core voltage and a fixed interface voltage to the DSP processor, wherein the fixed core voltage includes a CVDD 1.0V voltage, and the fixed interface voltages include DVDD 1.5V and DVDD 1.8V voltages; The first output power supply circuit and the second output power supply circuit are connected to each other, and the voltage levels of the DSP processor are sequentially supplied with power through the enable signal and status indication signal of the control circuit; The first output power supply circuit and the second output power supply circuit are both equipped with a current monitoring module for monitoring the consumption current of the adjustable core voltage, the fixed core voltage and the fixed interface voltage, and sending the monitored current in the form of voltage to the central data processing unit for real-time monitoring.

[0006] Furthermore, the first output power supply circuit is composed of a first voltage conversion chip and a coding sensing conversion chip, wherein the power supply voltage pin of the coding sensing conversion chip is connected to the power supply voltage source through a first parallel resistor pair, the sensing current output pin of the coding sensing conversion chip is connected to the voltage output feedback pin of the first voltage conversion chip through a first resistor, and the voltage identification pin of the coding sensing conversion chip is configured to obtain the VID code of the DSP processor; The enable pin of the first voltage conversion chip is connected to the central data processing unit through a second resistor to receive an enable signal output by the central data processing unit, and the SW pin of the first voltage conversion chip is connected to the DSP processor through an auxiliary voltage stabilization circuit.

[0007] Furthermore, a Snubber circuit is provided between the SW pin and the Boot pin of the first voltage conversion chip, and a Snubber circuit is also provided between the SW pin and the ground.

[0008] Furthermore, the coding perception conversion chip adopts LM10011 model chip.

[0009] Furthermore, the second output power supply circuit includes a second voltage conversion chip, the main body of the second voltage conversion chip adopts a dual-channel output CVDD1.0V voltage, and adopts two channels to independently output DVDD1.5V voltage and DVDD1.8V voltage; The RUN3 pin and RUN4 pin of the second voltage conversion chip are correspondingly connected to the voltage status indication pin of the first voltage conversion chip, the PGOOD1 pin of the second voltage conversion chip is correspondingly connected to its RUN2 pin and INTVCC1 pin, and the PGOOD4 pin of the second voltage conversion chip is correspondingly connected to its RUN1 pin and INTVCC4 pin.

[0010] Furthermore, the current monitoring module is provided on the connection lines between the first voltage conversion chip and the input voltage source and between the second voltage conversion chip and the input voltage source; The current monitoring module is composed of a current monitoring chip, a second parallel resistor pair, a third resistor and a first voltage regulator diode. The second parallel resistor pair is connected between the power input pin of the voltage conversion chip and the input voltage source. The fourth pin and the fifth pin of the current monitoring chip are connected to the second parallel resistor pair. One end of the third resistor is connected to the third pin of the current monitoring chip, and the other end is connected to the DSP processor. The third resistor and the DSP processor are grounded through the first voltage regulator diode.

[0011] Furthermore, the current monitoring chip adopts the MAX9938HEUK model chip.

[0012] Furthermore, in response to supplying the analog area voltage, the voltage is filtered through two parallel current beads via the CVDD 1.0V voltage channel, the DVDD 1.5V voltage channel, and the DVDD 1.8V voltage channel.

[0013] Furthermore, the first voltage conversion chip adopts a TPS56121 DC / DC conversion chip, which supports a maximum output current of 15A and an input voltage range of 4.5V~14V; The second voltage conversion chip uses the LTM4644 DC / DC conversion chip, which supports a maximum output current of 16A and an input voltage range of 4V~14V.

[0014] Compared with the prior art, the DSP power supply system for spaceborne detection payloads described in this application has the following beneficial effects: The DSP power supply system described in this application is applied to a spaceborne detection payload and can perform power-on in a sequential manner according to the required power supply voltage type, thereby meeting the power supply requirements of the DSP processor, and can realize reliable control of the power-on timing of each voltage level of the DSP processor, thereby solving the power supply design problem of the DSP processor and ensuring the operational stability and reliability of the spaceborne satellite detection payload. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings, which constitute part of this application, are intended to provide a further understanding of this application. The exemplary embodiments and descriptions of this application are intended to explain this application and do not constitute an improper limitation on this application. In the accompanying drawings: Figure 1 This is a block diagram of the overall power supply for the detection payload described in an embodiment of the present application; Figure 2 This is a block diagram of the complete power supply system for the DSP processor described in an embodiment of the present application; Figure 3 This is a power-on timing diagram of each voltage of the DSP processor described in the embodiment of the present application; Figure 4 This is a circuit diagram of the voltage control pins of the DSP processor described in an embodiment of the present application; Figure 5 This is a circuit diagram of a variable core voltage code conversion circuit according to an embodiment of the present application; Figure 6 This is a CVDD output power supply circuit diagram described in an embodiment of the present application; Figure 7 This is a diagram of the CVDD1, DVDD1.5 and DVDD1.8 output power supply circuits described in an embodiment of the present application. DETAILED DESCRIPTION

[0016] In order to make the objectives, technical solutions and advantages of this application more clear, this application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0017] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should have the usual meanings understood by people with ordinary skills in the field to which this application belongs. The "first", "second" and similar words used in the embodiments of the present application do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0018] As described in the above background technology, the DSP processor used in this application is the TMS320C66XX series chip, which is the mainstream DSP processor chip in the current commercial aerospace field. The power supply system design scheme of this application is based on this series of processors. If other types of DSP processors are used, the design ideas and design methods of this application can also meet the corresponding power supply requirements.

[0019] like Figure 1 As shown in the figure, the DSP processor, as a key component of the onboard detection payload, is also powered by the initial primary power provided by the entire satellite platform. It then passes through the necessary short-circuit protection unit and overvoltage protection unit to ensure the stability of the single-unit power supply voltage. It then passes through the surge suppression unit to suppress the large initial power-on current to prevent high current latch-up in the single-unit payload, which may cause the fuse to blow. After passing through the surge suppression circuit, the primary power is supplied to the voltage conversion unit to complete the conversion between the primary and secondary power supplies. Generally, the primary power supply of the entire satellite platform is 28V. The function of the voltage conversion unit is to convert the 28V primary power supply into a 12V secondary power supply. The converted secondary power supply is then supplied to the secondary power conversion module, and the subsequent DCDC and LDO complete the conversion of the various power supply voltages of the DSP processor.

[0020] In particular, the present application adds a voltage monitoring module at the position where the primary power supply is converted to the secondary power supply, and sends the secondary power supply voltage to the entire satellite platform for real-time monitoring. Because the entire payload is based on this power supply, when the power supply is abnormal, the entire satellite platform can cut off or add power through the corresponding judgment strategy to ensure the reliability of the payload power supply. The specific monitoring strategy of the present application is implemented as follows: the rated value of the secondary voltage analog telemetry value of the satellite-borne detection payload is 2.4V, and the acquisition frequency of the entire satellite platform is 5Hz (i.e., 5 times per second). When the entire satellite platform monitors that the voltage exceeds 3V or is lower than 1.8V twice in a row, the entire satellite platform needs to immediately cut off the power to the satellite-borne detection payload and save the abnormal information. It will be transmitted to the ground during transit, and after the ground judges the abnormal situation, it will determine whether to power on.

[0021] Figure 2 This is the block diagram of the overall power supply system of the DSP processor. After the secondary power conversion is completed, it is supplied to the voltage conversion chips at each level. For each power supply voltage of the DSP processor, the power supply voltage and function description required by the DSP processor are divided into the following categories: First, the CVDD core voltage, which is the variable core voltage of the DSP processor, needs to be powered by adaptive scaling; CVDD1 is the memory array voltage of the DSP, which needs to provide a fixed voltage of 1V; VDDT1 and VDDT2 are respectively used to power the Hyperlink and SGMII / SRIO / PCIE interfaces of the DSP. Since they are high-speed serial interfaces with data rates of up to several Gbps, they have special requirements for power supply voltage stability. Therefore, they need to be provided through CVDD1 after filtering; DVDD15 is DDR3 The controller's IO power supply, Vrefsstl is the 0.75V reference voltage of DDR3; DVDD18 is the common IO of the DSP processor, including the power supply of GPIO, IIC, SPI and UART interfaces; AVDD1, AVDD2 and AVDD3 are the main phase-locked loop PLL voltage of the DSP, the PLL voltage of DDR3 and the PASS module respectively. Since these three voltages are provided to the PLL module, they also have special requirements for power supply voltage stability. Therefore, they need to be provided through DVDD18 after filtering.

[0022] The above voltages of DSP processor have strict power-on sequence, as shown in the timing diagram. Figure 3 As shown, the specific power-on timing sequence is CVDD>CVDD1, VDDT1-2>DVDD18, AVDD1-3>DVDD15, VDDR1-4>VREFSSTL, and the time interval between powering on each voltage is about 10ms.

[0023] Based on this, this embodiment provides a DSP power supply system for a spaceborne detection payload, including a DSP processor, wherein the DSP processor is connected to an input voltage source via a first output power supply circuit to provide an adjustable core voltage to the DSP processor, wherein the adjustable core voltage is a CVDD core voltage; The DSP processor is further connected to the input voltage source through the second output power supply circuit to provide a fixed core voltage and a fixed interface voltage to the DSP processor, wherein the fixed core voltage includes a CVDD 1.0V voltage, and the fixed interface voltages include DVDD 1.5V and DVDD 1.8V voltages; The first output power supply circuit is connected to the second output power supply circuit, and the voltage levels of the DSP processor are sequentially supplied with power through the enable signal and status indication signal of the control circuit; The first output power supply circuit and the second output power supply circuit are both equipped with a current monitoring module to monitor the consumption current of the adjustable core voltage, fixed core voltage and fixed interface voltage, and send the monitored current in the form of voltage to the central data processing unit for real-time monitoring.

[0024] The power supply system described in this embodiment can perform power-on in a timed manner according to the required power supply voltage type, thereby meeting the power supply requirements of the DSP processor, and can achieve reliable control of the power-on timing of each voltage level of the DSP processor, thereby solving the power supply design problem of the DSP processor and ensuring the operational stability and reliability of the onboard satellite detection payload.

[0025] The sequential power-up of each voltage level of the DSP processor is specifically achieved through the enable and status indication signals of each voltage generation module. This embodiment is described in detail below in conjunction with the module design of each voltage.

[0026] First, the variable core voltage power supply method of the DSP processor is explained. Considering the special characteristics of the CVDD variable core voltage power supply, the DSP processor chip will use a unique 6-bit code to indicate the optimal CVDD voltage level of the chip based on the test results during manufacturing and shipment. Figure 4The following is a diagram showing the connection of the CVDD voltage control pins of the DSP. The DSP processor has four VCNTL (voltage control) pins for connecting to external code sensors, namely VCNTL0, VCNTL1, VCNTL2, and VCNTL3. These four pins are open-drain output pins and need to be pulled up to 1.8V through pull-up resistors. In the TMS320C66XX series DSP, VCNTL[2:0] is a 3-bit data bus, and VCNTL[3] acts as a Strobe signal. When VCNTL[3] is pulled low and then high from the initial default high state, the VCNTL[2:0] data bus will start sending the lower 3-bit VID code, and then continuously send the upper 3-bit VID code.

[0027] Figure 5 The LM10011 is a code sensing conversion chip directly connected to the DSP processor's VCNTL[3:0] pins. Its function is to communicate with the DSP processor, obtain the DSP's 6-bit VID code, and convert it into a corresponding sensing current. Its function is equivalent to a DAC: it receives digital signals from the DSP chip, converts them into analog currents, and sends them to the voltage output feedback pin FB (feedback) of the DC / DC converter that provides the variable core voltage, thereby regulating the CVDD voltage. Pin 2 of the chip is the sensing current output pin, and pin 3 is the chip's supply voltage pin, which uses 3.3V. Two 0603 0R resistors are added to the power input pin to facilitate chip supply voltage verification and troubleshooting. Pin 5 is the VID Mode select pin. Grounding indicates 6-bit VID mode, so grounding is required. Pin 6 is the initial current output pin. Connecting different external ground resistors will result in different initial output current values. In the initial power-on state, since communication with the DSP processor to obtain the VID code has not yet begun, the initial output current needs to be limited to 0, and the resistance value of the external ground resistor is selected to be 301K.

[0028] Figure 6 For the CVDD variable core voltage output power supply design, the selected DC / DC converter model is the TPS56121. This DC / DC converter supports a maximum output current of 15A and an input voltage range of 4.5V to 14V. It uses a secondary power supply of 12V as the chip input voltage source. A current monitoring module is added between the power supply and the chip voltage input pin. The current monitoring unit consists of R709, R710, U49, R720, and D7. Its basic function is to monitor the actual current consumption of the CVDD voltage and send the monitored current in the form of voltage to the central data processing unit for real-time monitoring.

[0029] R709 and R710 are current detection resistors, model WSL2010R0500FEA, with a resistance of 0.05Ω. The current detection chip is MAX9938HEUK, which amplifies the voltage across the detection resistor by 100 times and outputs it through pin 3 of the chip. R720 acts as a current limiting resistor, limiting the current in the detection output path to the working area of ​​the voltage regulator diode to prevent large current from burning the voltage regulator diode, causing a short circuit and affecting the safety of the entire satellite.

[0030] D7 is a 2CW4620 Zener diode, designed to limit excessive detection voltage output. If this occurs, the Zener diode will enter a regulated state, preventing excessive voltage from being transmitted to the processor pins and threatening safe operation. For example, when the actual CVDD current consumption is 10A and the CVDD output voltage is 1V, the actual load power consumption P = UI = 1V * 10A = 10W. For the TPS56121, when the output current is 10A, the DC / DC converter efficiency is approximately 90%. Based on the law of conservation of energy, the power at the DC / DC input can be calculated as 10W / 90% = 11.11W. According to P=UI, when the input voltage is 12V, the input current is I=P / U=11.11W / 12V=0.93A. Given a 0.025Ω monitoring resistor and a 100x amplification factor for the monitoring chip, the output voltage of the current monitoring is: 0.93A×0.025Ω×100=2.325V. This is because the voltage output from the current detection module to the processor is 2.325V, which is less than the processor's maximum input voltage range of 3.3V. When the monitored current deviates from the normal data range, the chip can be powered off by disconnecting the chip enable, ensuring rapid action when an anomaly occurs and preventing further damage.

[0031] Pin 21 of TPS56121 is a common pin for enable and soft start. When only the soft start capacitor is connected to the pin, the internal pull-up resistor will enable the chip. Since the power-on timing of the chip must be strictly controlled, the initial state is to turn off the enable through a 10K pull-down resistor. The enable signal is output through the central data processing unit, that is, the PG_3V3_SOC signal is connected to R1088 and then to the enable pin. When the DSP is ready to be turned on, the PG_3V3_SOC signal is pulled high to start the chip.

[0032] Pin 4 of the chip is the Boot pin, which is the gate voltage control pin of the internal high-side MOS. A snubber circuit needs to be added between it and the SW pin to reduce the inherent ringing and EMI problems of the switching power supply itself. In addition, in order to further reduce the ringing of the SW pin, an additional snubber circuit is added between the SW pin and the ground. The resistors and capacitors R711 and C1128 of the snubber between Boot and SW are selected as 5.1R and 0.1uf respectively, and the resistors and capacitors R939 and C1277 of the snubber between SW and ground are selected as 1R and 1nf respectively.

[0033] Among them, it should be noted that SW is the power output pin, and an external power inductor L40 needs to be added to meet the needs of electrical energy storage and release. The inductor model selected is the 0.47uH power inductor IHLP-3232DZ-A1-0.47uH, packaged as 3232, and its rated saturation current is 31.5A, which meets the design requirement of outputting 10A current and also meets the derating design requirements.

[0034] In particular, the DSP processor chip TMS32C06678 requires that the initial power-up voltage of the variable core voltage CVDD be maintained at 1.1V, and then adjusted accordingly based on the VID code identification chip. Therefore, the two voltage-regulating resistors R714 and R718 of the TPS56121 need to be set to meet the initial power-up output voltage of 1.1V. Among them, the feedback resistors R714 and R718 are voltage-regulating resistors, and the resistance value of R714 should be selected between 10K and 50K. This can achieve balanced feedback current and better noise suppression.

[0035] Pin 1 of this chip is a compensation pin. The external resistors and capacitors are set based on typical loop stability conditions: C1130 = 2200pF, R713 = 7.87K, C1129 = 100pF, R716 = 1K, and C1132 = 680pF. Pin 22 is a voltage status indicator pin. When pulled high, it indicates that CVDD has reached a stable state. This indicator signal completes the power-up timing requirements of the DSP processor voltage levels. Since this pin is an open-drain output, it needs to be pulled up to 3.3V via a pull-up resistor. The 3.3V voltage is derived from the 3.3V power supply that powers the LM10011.

[0036] Figure 7 This is the power supply design for CVDD1, DVDD1.5, and DVDD1.8 in this application. It uses the LTM4644 DC / DC converter chip, with a single 4A output current and support for parallel design. The main body uses a dual-channel output for CVDD1, and the other two channels independently output DVDD1.5V and DVDD1.8V.

[0037] In the power-on timing part, after the TPS56121 is powered on, it outputs a high-level PG_CVDD signal, which pulls up the enable pin of the LTM4644 output CVDD1 fixed voltage, and then the channel can be opened. Figure 7 As shown, PC_CVDD is connected to the Run3 and Run4 pins via two 0R resistors. Similarly, when CVDD1 is outputting normally, the CVDD1 output status indicator, PG_CVDD1, is connected via the 33R resistor R751. Since this signal is an open-drain output, it must first be connected to the INTVCC pin of that channel through a pull-up resistor. INTVCC is the output pin of the channel's built-in LDO, rated at 3.3V. PG_CVDD1 is then connected to the DVDD 1.8V channel as the DVDD 1.8V enable signal. Similarly, the channel status indicator, PG_1V8, is connected to the DVDD 1.5V channel as the DVDD 1.5V enable signal. After DVDD 1.5V is powered up, the VREFSSTL voltage is generated using precision resistors (1% accuracy). This ensures reliable control of the power-up timing of the various voltages in the DSP processor.

[0038] In addition, for the analog area voltage, three types of voltages, namely VDDT1-2, AVDD1-3, and VDDR1-4, are provided through CVDD1, DVDD1.8, and DVDD1.5 respectively, and then filtered by two parallel high-current magnetic beads.

[0039] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present invention, and they should all be included in the scope of the claims and description of the present invention.

[0040] The embodiments of the present application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the scope of protection of this application.

Claims

1. A DSP power supply system for a satellite-borne detection payload, characterized in that: The DSP processor includes a DSP processor connected to an input voltage source through a first output power supply circuit to provide an adjustable core voltage to the DSP processor, wherein the adjustable core voltage is a CVDD core voltage; The DSP processor is also connected to an input voltage source through a second output power supply circuit to provide a fixed core voltage and a fixed interface voltage to the DSP processor, wherein the fixed core voltage includes a CVDD 1.0V voltage, and the fixed interface voltage includes a DVDD1.5V and a DVDD1.8V voltage; The first output power supply circuit is connected to the second output power supply circuit, and the voltage levels of the DSP processor are sequentially powered by the enable signal and the state indication signal of the control circuit; The first output power supply circuit and the second output power supply circuit are both configured with a current monitoring module for monitoring the consumption current of the adjustable core voltage, the fixed core voltage and the fixed interface voltage, and sending the monitored current in the form of voltage to the central data processing unit for real-time monitoring.

2. The DSP power supply system for a satellite-borne detection payload according to claim 1, characterized in that: The first output power supply circuit is composed of a first voltage conversion chip and a coding sensing conversion chip, wherein the power supply voltage pin of the coding sensing conversion chip is connected to the power supply voltage source through a first parallel resistor pair, the sensing current output pin of the coding sensing conversion chip is connected to the voltage output feedback pin of the first voltage conversion chip through a first resistor, and the voltage identification pin of the coding sensing conversion chip is configured to obtain the VID code of the DSP processor; The enable pin of the first voltage conversion chip is connected to the central data processing unit through a second resistor to receive an enable signal output by the central data processing unit, and the SW pin of the first voltage conversion chip is connected to the DSP processor through an auxiliary voltage stabilization circuit.

3. The DSP power supply system for a satellite-borne detection payload according to claim 2, characterized in that: A Snubber circuit is provided between the SW pin and the Boot pin of the first voltage conversion chip, and a Snubber circuit is also provided between the SW pin and the ground.

4. The DSP power supply system for a spaceborne detection payload according to claim 3, characterized in that: The coding perception conversion chip adopts the LM10011 chip.

5. The DSP power supply system for a spaceborne detection payload according to claim 2, characterized in that: The second output power supply circuit includes a second voltage conversion chip, the main body of the second voltage conversion chip adopts a dual-channel output CVDD1.0V voltage, and adopts two channels to independently output DVDD1.5V voltage and DVDD1.8V voltage; The RUN3 pin and RUN4 pin of the second voltage conversion chip are correspondingly connected to the voltage status indication pin of the first voltage conversion chip, the PGOOD1 pin of the second voltage conversion chip is correspondingly connected to its RUN2 pin and INTVCC1 pin, and the PGOOD4 pin of the second voltage conversion chip is correspondingly connected to its RUN1 pin and INTVCC4 pin.

6. The DSP power supply system for a spaceborne detection payload according to claim 5, characterized in that: The current monitoring module is arranged on the connection line between the first voltage conversion chip and the input voltage source and between the second voltage conversion chip and the input voltage source; The current monitoring module is composed of a current monitoring chip, a second parallel resistor pair, a third resistor and a first voltage regulator diode. The second parallel resistor pair is connected between the power input pin of the voltage conversion chip and the input voltage source, the fourth pin and the fifth pin of the current monitoring chip are connected to the second parallel resistor pair, one end of the third resistor is connected to the third pin of the current monitoring chip, and the other end is connected to the DSP processor, and the third resistor is grounded to the DSP processor through the first voltage regulator diode.

7. The DSP power supply system for a spaceborne detection payload according to claim 6, characterized in that: The current monitoring chip adopts the MAX9938HEUK chip.

8. The DSP power supply system for a spaceborne detection payload according to claim 6, characterized in that: In response to supplying the analog region voltage, it is provided after filtering through two parallel current beads via the CVDD 1.0V voltage channel, the DVDD 1.5V voltage channel, and the DVDD 1.8V voltage channel.

9. The DSP power supply system for a spaceborne detection payload according to claim 6, characterized in that: The first voltage conversion chip adopts a TPS56121 DC / DC conversion chip, which supports a maximum output current of 15A and an input voltage range of 4.5V~14V; The second voltage conversion chip adopts the LTM4644 DC / DC conversion chip, which supports a maximum output current of 16A and an input voltage range of 4V~14V.

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