Amplifier device with tunable element and method thereof

Abstract

The amplifier device includes: an input port; an output port; a first amplifier including a first input electrically coupled to the input port and a first output electrically coupled to the output port; and a second amplifier including a second input electrically coupled to the input port and a second output electrically coupled to the output port. A first network including a first tunable element is electrically coupled to the first output and to a combining node. Comprising a second tunable element is electrically coupled to the combining node and to the output port.

Description

Technical Field

[0001] Embodiments of the subject matter described herein relate generally to RF amplifiers. Background Art

[0002] Radio frequency (RF) amplifiers are increasingly used in communications applications. These RF amplifiers are popular because system size and cost are lower due to low cooling requirements, and because less energy is required to power these systems. Conventional RF amplifiers (e.g., tuned class AB) operate at a constant supply voltage. In addition, conventional RF amplifiers operate under back-off power conditions. This back-off power condition reduces amplifier efficiency.

[0003] Conventional RF amplifiers may experience periods of low flow conditions. This generally means that the efficiency of the amplifier is reduced due to an increased amount of amplifier back-off. This reduced efficiency results in excessive energy usage. Therefore, there is a need for an amplifier arrangement with improved efficiency. Summary of the invention

[0004] In one aspect, an embodiment includes an amplifier device that may include: an input port; an output port; a first amplifier including a first input electrically coupled to the input port and a first output electrically coupled to the output port; and a second amplifier including a second input electrically coupled to the input port and a second output electrically coupled to the output port. In an embodiment, a first network including a first tunable element may be electrically coupled to the first output and may be electrically coupled to a combining node. According to an embodiment, a second network including a second tunable element may be electrically coupled to the combining node and electrically coupled to the output port.

[0005] An embodiment may include a splitter network including a splitter input, a first splitter output, and a second splitter output, the splitter network electrically coupling an input port to the first input at the first splitter output and electrically coupling the input port to the second input at the second splitter output, wherein a first insertion phase between the splitter input and the first splitter output and a second insertion phase between the splitter input and the second splitter output have a phase difference between 60 degrees and 120 degrees. A phase shift network may be electrically coupled between the second output and the combining node.

[0006] According to an embodiment, the first amplifier may be configured as a carrier amplifier and the second amplifier may be configured as a peaking amplifier.

[0007] According to an embodiment, the first amplifier may be configured as a peaking amplifier and the second amplifier may be configured as a carrier amplifier.

[0008] According to an embodiment, the first network may include a first resonator, the first resonator including a first shunt element, wherein the first resonator may be electrically coupled to the first amplifier via the first shunt element, and the second shunt element may be electrically coupled to the first shunt element and to ground potential. In an embodiment, the first series element may be electrically coupled to the first resonator. The first network may include a second resonator, the second resonator including a third shunt element and a fourth shunt element, wherein the fourth shunt element may be electrically coupled to ground potential, wherein the third shunt element may be electrically coupled to the first series element.

[0009] In an embodiment, the first shunt element may include a third tunable element.In an embodiment, the first tunable element may electrically couple the third shunt element of the second resonator to the combining node.

[0010] In an embodiment, the first shunt element may include a first inductor, the second shunt element may include a capacitor, the first series element may include a second inductor, the third shunt element may include a third inductor, and the fourth shunt element may include a capacitor.

[0011] In an embodiment, the first tunable element may include a first voltage variable capacitor.

[0012] In an embodiment, the third tunable element may include a voltage variable inductor.

[0013] According to an embodiment, one or more of the first inductor, the second inductor, and the third inductor may include a variable inductor.

[0014] In an embodiment, the first tunable element may include a voltage variable capacitor, wherein the voltage variable capacitor may include one or more varactor diodes, one or more micro-electromechanical switches, and one or more PIN diodes. The first inductor may include a micro-electromechanical switch and a field effect transistor switch.

[0015] In an embodiment, the second network may include a voltage variable impedance transmission line.

[0016] According to an embodiment, a voltage variable impedance transmission line may include a voltage variable capacitor electrically coupling the transmission line to ground potential.

[0017] According to an embodiment, the voltage variable capacitor may be selected from the list consisting of: a varactor diode, a micro-electromechanical switch, a barium strontium titanate device, a switched capacitor, and one or more PIN diodes.

[0018] In another aspect, an embodiment may include an apparatus comprising: a base substrate; an input port coupled to the base substrate and an output port coupled to the base substrate; a first amplifier die coupled to the base substrate and electrically coupled to the first input and the first output; and a second amplifier die coupled to the base substrate and electrically coupled to the second input and the second output. According to an embodiment, a splitter device may be coupled to the base substrate, the splitter device electrically coupling the input port to the first input and the second input. In an embodiment, an output matching network may be coupled to the base substrate. According to an embodiment, the output matching network may include a first tunable element. In an embodiment, the output matching network may be electrically coupled to the first output and electrically coupled to the combining node. In an embodiment, a reconfigurable impedance transformer may be coupled to the base substrate. The reconfigurable impedance transformer may include a second tunable element coupled to the combining node and the output port.

[0019] In an embodiment, the reconfigurable impedance transformer may include a voltage variable impedance transmission line including a voltage variable capacitor electrically coupling the transmission line to ground potential.

[0020] In yet another aspect, an embodiment may include a method of operating an amplifier device. An embodiment of the method may include: providing an input signal to an input port of the amplifier device; coupling a first portion of the input signal to a first input of a first amplifier and coupling a second portion of the input signal to a second input of a second amplifier; amplifying the first portion of the input signal with the first amplifier to produce a first amplified signal at a first output of the first amplifier; and amplifying the second portion of the input signal with the second amplifier to produce a second amplified signal at a second output of the second amplifier. An embodiment of the method may further include combining the first amplified signal and the second amplified signal at a combining node to produce a combined signal at the combining node. According to an embodiment, the method may further include: changing the impedance at the first output of the first amplifier by an output matching network electrically coupled to the first output and electrically coupled to the combining node including a first tunable element; and further changing the impedance at the combining node by an impedance transformer, the impedance transformer including a second tunable element electrically coupled to the combining node and an output port. The method may also include passing the combined signal to a load electrically coupled to the output port.

[0021] In an embodiment of the method, changing the impedance at the first output end of the first amplifier may include: realizing a first tuned impedance through an output matching network and realizing a second tuned impedance through an impedance converter to operate the first amplifier and the second amplifier in a first state; and realizing a third tuned impedance through the output matching network and realizing a fourth tuned impedance through an impedance converter to operate the first amplifier and the second amplifier in a second state.

[0022] In an embodiment of the method, the first state may comprise a high power state and the second state may comprise a low power state.

[0023] In an embodiment of the method, coupling a first portion of the input signal to a first input of the first amplifier and coupling a second portion of the input signal to a second input of the second amplifier may include splitting the input signal using a splitter device, wherein the first portion and the second portion of the input signal are offset by a phase difference between 60 degrees and 120 degrees. According to an embodiment, combining the first amplified signal and the second amplified signal includes routing the first amplified signal and the second amplified signal through a phase shift network having an insertion phase within 20% of the phase difference. In an embodiment, amplifying the first portion of the input signal may include operating the first amplifier device in a configuration selected from a list including a peaking amplifier and a carrier amplifier. Furthermore, according to an embodiment, amplifying the second portion of the input signal may include operating the second amplifier device in a configuration selected from a list including a peaking amplifier and a carrier amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] A more complete understanding of the subject matter may be obtained by referring to the detailed description and claims considered in conjunction with the following figures, wherein like reference numerals refer to similar elements throughout the figures.

[0025] Figure 1 is a schematic diagram of a conventional amplifier arrangement;

[0026] Figure 2A and Figure 2B is a schematic diagram of an amplifier arrangement according to an example embodiment;

[0027] Figure 3A and Figure 3B is a schematic diagram of an output matching network (OMN) according to an embodiment;

[0028] Figure 4 is a schematic diagram of an impedance converter according to an embodiment;

[0029] Figure 5A and Figure 5B It is a depiction Figure 2A A graphical representation of the operation of the amplifier device;

[0030] Figure 6 is a top view of a device 600 according to an embodiment;

[0031] Figure 7 to Figure 8 is an enlarged view of a device 600 according to an embodiment; and

[0032] Fig. 9 is a flow chart of an operating method of an amplifier device according to an embodiment. DETAILED DESCRIPTION

[0033] Embodiments of the subject matter of the invention relating to amplifier devices and described herein include amplifier devices configured as Doherty power amplifiers, which may include a reconfigurable network enabled by microelectromechanical systems (MEMS) switches, voltage variable components fabricated using barium strontium titanate (BST) or similar materials, which are electrically coupled to a combination of Doherty power amplifiers.

[0034] The amplifier device embodiments provided herein can overcome some or all of the aforementioned problems with a high efficiency amplifier. Specifically, the amplifier device embodiments described herein allow reconfiguration of the matching impedance presented to a peaking amplifier in a Doherty configuration to allow improved efficiency for low power operation.

[0035] The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and use of such embodiments. As used herein, the words "exemplary" and "example" mean "serving as an example, instance, or illustration." Any embodiment described herein as exemplary or example is not necessarily to be construed as preferred or advantageous over other embodiments. In addition, it is not intended to be bound by any explicit or implicit theory present in the foregoing technical field, background technology, or the following detailed description.

[0036] Figure 1 is a schematic diagram of a Doherty amplifier arrangement 100. The Doherty amplifier arrangement 100 may include an input port 102, an output port 104, a peaking amplifier 110, a carrier amplifier 120, a splitter arrangement 130, a transmission line 140, and an impedance transformer 150.

[0037] For the Doherty amplifier arrangement 100, the input port 102 is connected to an input 132 of a splitter arrangement 130. A first output 134 of the splitter arrangement 130 is connected to a first input 112 of a peaking amplifier 110. A second output 136 of the splitter arrangement 130 is connected to a second input 122 of a carrier amplifier 120. A first output 114 of the peaking amplifier 110 is connected to a transmission line 140 at a combining node 144. A second output 124 of the carrier amplifier 120 is connected to the transmission line 140. An output impedance transformer 150 couples the combining node 144 to the output port 104 and the output load 106.

[0038] The peaking amplifier 110 may include, for example, a GaN HFET device, wherein the first gate bias 116Vgp of the peaking amplifier 120 is set to achieve a Class C bias. As used herein, the term "Class C bias" means that the final transistor stage of the amplifier is biased in an off state such that the final stage has a gate bias value that is more than 100 mV lower than the threshold voltage of the final stage transistor. In this case, I DQ is limited by the transistor’s leakage current. In this example, for Class C operation, I DQ Less than 1 mA / mm. In this example, the peaking amplifier 110 has an output stage comprising a GaN HFET with a total gate periphery of approximately 4 mm.

[0039] Likewise, the carrier amplifier 120 may include a radio frequency transistor (e.g., a gallium nitride (GaN) heterojunction field effect transistor (HFET)). During operation, the second gate bias 126 Vgc of the carrier amplifier 120 is set to achieve class AB bias. As used herein, the term "class AB bias" means that the final transistor stage of the amplifier is biased in a forward active mode so that the quiescent current (I DQ ) exceeds 0.5% of the maximum current of the final stage. In this example, the output stage of the carrier amplifier 120 includes a GaN HFET with a total gate periphery of approximately 2 mm. The current density of the GaN HFET is approximately 1 ampere per millimeter of gate periphery (i.e., 1A / mm). The maximum current of the output stage transistor is approximately 2 amperes. Therefore, when the I DQ Above 5 mA / mm or 10 mA of the total drain current, the carrier amplifier 120 is biased in class AB.

[0040] The peaking amplifier 110 and the carrier amplifier 120 are typically designed to have an asymmetry ratio given by the following equation:

[0041]

[0042] In this example, the value of β is 2.

[0043] During operation of the Doherty amplifier 100, the carrier amplifier 120 amplifies the portion of the signal applied to the input port 102 that reaches the first splitter output 136. When the signal strength is low enough to make the peaking amplifier 110 inactive, only the carrier amplifier 120 amplifies the signal. In this case, the impedance presented to the carrier amplifier depends on the characteristic impedance Z of the transmission line 140. INV and the combined node impedance Z seen at the combined node 144 N The impedance Z seen at the combined node 144 is C Given by the following equation

[0044]

[0045] When the input signal presented to the second input 112 of the peaking amplifier 110 is large enough to turn on the class C bias transistor, the peaking amplifier 110 will amplify the signal. At full power, the impedance Z seen by the peaking amplifier 110 is p Given by the following equation

[0046]

[0047] The impedance Z seen at the combined node 144 N Given by the following equation

[0048]

[0049] The impedance of the transformer 150 is given by

[0050]

[0051] Figure 2A2 is a schematic diagram of an amplifier device 200 according to an example embodiment. The amplifier device 200 may include: an input port 202; an output port 204; a peaking amplifier 210 (i.e., a "first amplifier") including a first input terminal 212 electrically coupled to the input port 202 and a first output terminal 214 electrically coupled to the output port 204 and the output load 206; and a carrier amplifier 220 (i.e., a second amplifier) ​​including a second input terminal 222 electrically coupled to the input port 202 and a second output terminal 224 electrically coupled to the output port 204 and the output load 206. By including a reconfigurable output matching network (OMN) 260 (i.e., a "first network") and a reconfigurable impedance transformer 280 (i.e., a "second network"), the amplifier device 200 achieves high efficiency at a lower average power during low flow periods. In an embodiment, the reconfigurable OMN 260 may be electrically coupled to the first output terminal 214 and may be electrically coupled to the combining node 244. According to an embodiment, reconfigurable impedance transformer 280 may be electrically coupled to combining node 244 and to output port 204 .

[0052] The peaking amplifier 210 may include, for example, a GaN HFET device, wherein the first gate bias 216Vgp of the peaking amplifier 210 is set to achieve a Class C bias. In this case, I DQ is limited by the transistor’s leakage current. In this example, for Class C operation, I DQ Less than 1 mA / mm. In this example, the peaking amplifier 210 has an output stage comprising a GaN HFET with a total gate periphery of approximately 4 mm.

[0053] The carrier amplifier 220 may include a radio frequency transistor (eg, a gallium nitride (GaN) heterojunction field effect transistor (HFET)). During operation, the second gate bias 226V of the carrier amplifier 220 may be set gc To achieve class AB biasing. In this example, the output stage of the carrier amplifier 220 includes a GaN HFET with a total gate periphery of approximately 2 mm. The maximum current of the output stage transistor can be approximately 2 amps. Therefore, when the I DQ Above 5 mA / mm or 10 mA of the total drain current, the carrier amplifier 220 is biased in class AB.

[0054] An embodiment may include a splitter network 230 including a splitter input 232, a first splitter output 234, and a second splitter output 236, the splitter network 230 electrically coupling the input port 202 to the first input 212 at the first splitter output 234 and electrically coupling the input power to the second input 222 at the second splitter output 236, wherein a first insertion phase between the splitter input 232 and the first splitter output 234 and a second insertion phase between the splitter input and the second splitter output may have a phase difference between 60 degrees and 120 degrees. An impedance inverter network 240 (i.e., a "phase shift network") may be electrically coupled between the first output 214 and a combining node 244.

[0055] To reduce the Doherty amplifier power by a factor of n, the optimum impedance is increased by a factor of n, and thus the power of the carrier amplifier 210 and the peaking amplifier 220 is reduced by a factor of n. Thus, in an embodiment, for a power level P that is reduced by a factor of n, out or P out / n, according to equation (2), the carrier amplifier impedance is given by

[0056]

[0057] in In order to maintain the same power ratio between the peaking amplifier 210 and the carrier amplifier 220, according to an embodiment, the impedance of the peaking amplifier 210 should be increased by a factor of n:

[0058]

[0059] In an embodiment, the peaking path impedance on the combining node side at reduced power is given by the following equation:

[0060]

[0061] To achieve an n-fold increase in carrier optimum impedance and peaking optimum impedance, the combining node needs to be reduced by n, so the impedance seen at the combining node 244 at reduced power is given by

[0062]

[0063] The reduced characteristic impedance of the reconfigurable impedance transformer 280 is given by

[0064]

[0065] In an embodiment, the reduced impedance Z of the low power state is achieved by reducing the impedance of the reconfigurable OMN 260 to satisfy the condition of equation (7). PPnIn order to satisfy the condition of equation (10), according to an embodiment, the impedance of the reconfigurable impedance transformer 280 is reduced.

[0066] In an example embodiment, the amplifier device 200 is implemented using parameters for a full power mode and a mode 3 dB less than the full power mode.

[0067]

[0068] In the example embodiments discussed above, the first amplifier 210 is configured as a peaking amplifier and the second amplifier 220 is configured as a carrier amplifier. Figure 2B As shown in , according to an embodiment, the first amplifier 211 can be configured as a carrier amplifier and the second amplifier 221 can be configured as a peaking amplifier. In these other embodiments, another transmission line 245 or other phase delay device with, for example, a 90-degree phase shift can be placed between the first amplifier 211 and the OMN 260. In these embodiments, the phase shift associated with the phase shift network 247 can be approximately 180 degrees. In still other embodiments, the phase shift associated with the phase shift network 247 can be approximately zero degrees (i.e., the phase shift network is omitted or implemented only as a network with zero phase shift). In these still other embodiments, when the first amplifier 211 is configured as a carrier amplifier and the second amplifier 221 is configured as a peaking amplifier, the phase delay element 233 (e.g., 90 degrees) of the splitter device 230 can be omitted, and the phase delay element 237 can be placed between the splitter input 232 and the second splitter output 236 of the splitter device 230. In these other embodiments and still other embodiments, the phase shift presented by the reconfigurable impedance transformer 280 at Z N The impedance at and the impedance Z presented to the first amplifier 211 when implemented as a carrier amplifier C can be increased in low power mode. In these other embodiments, other components such as phase shift network 247 and OMN 260 can be optimized to take into account the higher optimal impedance Z of carrier amplifier 211, for example. C and the higher optimum impedance Z of the peaking amplifier 221 P and other differences between carrier and peaking amplifiers.

[0069] Figure 3A and Figure 3B is a schematic diagram of an output matching network (OMN) 260 according to an embodiment. Figure 3A and Figure 3B , best understood by the following description.

[0070] According to an embodiment, the reconfigurable OMN 260 may include an input 302, an output 304, a first resonator 310, a series element 320, a second resonator 330, and an output element 350. According to an embodiment, the input 302 may be electrically coupled to the first resonator 310, the first resonator 310 may be electrically coupled to the series element 320, the series element 320 may be electrically coupled to the second resonator 330, and the second resonator 330 may be electrically coupled to the output element 350.

[0071] In an embodiment, the first resonator 310 may include a first resonator inductor 312 (i.e., a "first shunt element") L1 coupled to the input 302 and a first capacitor 316 (i.e., a "second shunt element") C2, wherein the first capacitor 316 couples the first resonator inductor 312 to ground 319A / B. In an embodiment, the output capacitance 311C of the active device ds (e.g., the final transistor output capacitance of the first amplifier 210) may be coupled to the reconfigurable OMN 260 at the input 302 and may be considered in the design of the reconfigurable OMN 260. The first resonator inductor 312 may include a first variable inductor 313A / B (i.e., a “third tunable element”). Figure 3B As seen in the example embodiment of , variable inductor 313A / B may include first fixed inductor 313AL1F coupled to first capacitor 316C2. First variable inductor 313B L1' may be coupled to input 302 via capacitor 317C4. According to an embodiment, first switch 318 may couple first variable inductor 313B L1' to ground 319B. In other embodiments (not shown), alternative topologies for implementing first resonator inductance 312 may be used without limitation.

[0072] According to an embodiment, the first resonator inductance 312L1 may have an upper tuning range value between about 2 nanohenries (nH) and about 10 nH (eg, between about 10 nH and about 2 nH). Figure 3B In other embodiments, the first resonator inductance 312L1 may have an upper tuning range value between about 0.1 nanohenry (nH) and about 50 nH, although other higher or lower values ​​may be used, depending on the embodiment. In an embodiment, the first resonator inductance 312L1 may have a lower tuning range value between about 0.2 nanohenry (nH) and about 1 nH, depending on the embodiment (e.g., between about 0.1 nanohenry (nH) and about 50 nH). Figure 3BIn an embodiment of the present invention, when the first switch 318 is closed and the value of the first resonator inductor 312L1 is approximated by the parallel combination of the first fixed inductor 313A=L1F and the first variable inductor 313B L1′. In other embodiments, the first resonator inductor 312L1 can have a lower tuning range value between about 0.01 nanohenry (nH) and about 10 nH, although other higher or lower values ​​can be used, depending on the embodiment.

[0073] In an embodiment, the series element 320L2 may electrically couple the first resonator 310 to the second resonator 330. In an embodiment, the series element 320 may include an inductor 321. According to an embodiment, a bond wire inductor 326A / B Lwb may be included in the series element 320. In other embodiments (e.g., an integrally integrated embodiment), the bond wire inductor 326A / B may be omitted.

[0074] In an embodiment, the second resonator 330 can be electrically coupled to the series element 320 and can include a second resonator inductor 332 (i.e., a "third shunt element") L3 coupled to the input 302 through the series element 320 and a second capacitor 338 (i.e., a "fourth shunt element") C3, wherein the second capacitor 338 can couple the second resonator inductor 332 to ground 339A / B. The second resonator inductor 332 can include a second variable inductor 333A / B. As in Figure 3B As seen in the example embodiment of , the second variable inductor 333A / B may include a first fixed inductor 333B L3F coupled to a second capacitor 338C3. The first variable inductor 333AL3' may be coupled to the input 302 via the series element 320. According to an embodiment, the second switch 339 may couple the first variable inductor 333AL3' to ground 339B. In other embodiments (not shown), alternative topologies using various series and / or parallel combinations of inductors and / or capacitors for implementing the first resonator inductance 332 may be used without limitation.

[0075] According to an embodiment, the second resonator inductance 332L3 may have an upper tuning range value between about 2 nanohenries (nH) and about 10 nH (eg, between about 10 nH and about 2 nH). Figure 3B In other embodiments, the second resonator inductance 332L3 may have an upper tuning range value between about 0.1 nanohenry (nH) and about 50 nH, although other higher or lower values ​​may be used, depending on the embodiment. In an embodiment, the second resonator inductance 332L3 may have a lower tuning range value between about 0.2 nanohenry (nH) and about 1 nH (e.g., between about 0.1 nanohenry (nH) and about 50 nH, depending on the embodiment. Figure 3BIn an embodiment of the present invention, when the second switch 339 is closed and the value of the second resonator inductance 332L3 is approximated by the parallel combination of the second fixed inductor 333B L3F and the second variable inductor 333AL3'). In other embodiments, the first resonator inductance 332L3 can have a lower tuning range value between about 0.01 nanohenry (nH) and about 10 nH, although other higher or lower values ​​can be used, depending on the embodiment.

[0076] In an embodiment, the output element 350 (i.e., the "first tunable element") can electrically couple the second resonator 330 to the output 304 and the combining node 244. The output element 350 may include a capacitive element 352C1. In an embodiment, the capacitive element 352C1 may include a fixed capacitor 353AC1F. According to an embodiment, when the third switch 358 is closed, the variable capacitor 353BC1' may be coupled to the output 304 and may be electrically coupled in parallel with the fixed capacitor 353AC1F. In an embodiment, the total capacitance value of the output element 350 may be switched between C1F when the third switch 358 is open and C1F+C1' when the third switch 358 is closed.

[0077] According to an embodiment, the capacitive element 352C1 may have a lower tuning range value between about 0.2 pF (pF) and about 10 pF (e.g., between Figure 3B In an embodiment, when the third switch 358 is open and the value is defined by the first fixed capacitor 353A1F). In other embodiments, the capacitive element 352C1 can have a lower tuning range value between about 0.01 pF and about 100 pF, depending on the embodiment, although other higher or lower values ​​can be used. In an embodiment, the capacitive element 352C1 can have an upper tuning range value between about 0.5 pF and about 20 pF (e.g., between about 100 pF and about 200 pF), depending on the embodiment. Figure 3B In an embodiment, when third switch 358 is closed and the value of capacitive element 352C1 is approximated by the parallel combination of fixed capacitor 353A1F and variable capacitor 353B C1′. In other embodiments, capacitive element 352 may have an upper tuning range value between about 0.1 pF and about 100 pF, although other higher or lower values ​​may be used, depending on the embodiment.

[0078] According to an embodiment, the variable capacitor 352 and the first resonator inductor 312 and the second resonator inductor 332 can be implemented using micro-electromechanical switches to implement switches 318, 339, 358. In other embodiments, transistor switches can be used to implement the switching elements. In still other embodiments, according to an embodiment, the voltage variable capacitor can be implemented using a varactor diode, a switched capacitor, and one or more PIN diodes.

[0079] In an exemplary embodiment, the R presented to the first amplifier 210 and the combining node 244 by the reconfigurable OMN 260 in the full power mode and the half power mode s , R L And insert the value of the phase Iph to take the value in the following table, which is calculated by circuit simulation in full power mode to half power mode.

[0080]

[0081] Figure 4 is a schematic diagram of a reconfigurable impedance transformer 280 (ie, a "second network") according to an embodiment. In an embodiment, the reconfigurable impedance transformer 280 may be implemented using a voltage variable transmission line.

[0082] According to an embodiment, the reconfigurable impedance transformer 280 may include an input 402, a short transmission line segment 410, a voltage variable capacitor 430 (i.e., a "second tunable element") C1T that electrically couples the transmission line 420 to a ground potential 432, and a fixed capacitor 440C2T. A series capacitor 450C3T may be used to couple the "pi" network of the voltage variable capacitor 430, the transmission line 420, and the fixed capacitor 440 to the output 404.

[0083] In an embodiment, the voltage variable capacitor 430C1T may include a fixed capacitor 434C1TF. According to an embodiment, when the switch 438 is closed, the variable capacitor 436C1T' may be electrically coupled in parallel with the fixed capacitor 434C1F. In an embodiment, the total capacitance value of the voltage variable capacitor may be switched between C1TF when the switch 438 is open and C1TF+C1T' when the switch 438 is closed.

[0084] According to an embodiment, the voltage variable capacitor 430CIT may be implemented using a micro-electromechanical switch to implement the switch 438. In other embodiments, according to an embodiment, the voltage variable capacitor 430CIT may be implemented using a varactor diode, a switched capacitor, and one or more PIN diodes.

[0085] According to an embodiment, according to an embodiment, the voltage variable capacitor 430C1T may have a lower tuning range value between about 0.2 pico-farads (pF) and about 10 pF (e.g., when the switch 438 is open and the value is defined by the first fixed capacitor 434C1TF). In other embodiments, the voltage variable capacitor 430C1T may have a lower tuning range value between about 0.01 pF and about 100 pF, although other higher or lower values ​​may be used. In an embodiment, according to an embodiment, the voltage variable capacitor C1T may have an upper tuning range value between about 0.5 pF and about 20 pF (e.g., when the switch 438 is closed and the value of the voltage variable capacitor C1T is approximated by the parallel combination of the fixed capacitor 434C1F and the variable capacitor 430C1T'). In other embodiments, according to an embodiment, the voltage variable capacitor 430 may have an upper tuning range value between about 0.1 pF and about 100 pF, although other higher or lower values ​​may be used.

[0086] In the exemplary embodiment, the R presented to the combination node 244 s The values ​​of the insertion phase IPh of the reconfigurable impedance transformer 280 take the values ​​in the following table, which are calculated by simulating the components of the reconfigurable impedance transformer 280 in full power mode and half power mode.

[0087]

[0088] Figure 5A and Figure 5B It is a depiction Figure 2A 500, 502 of the operation of the amplifier device 200. By viewing Figure 5A and Figure 5B , the performance of the amplifier device 200 can be best understood.

[0089] Figure 5A The simulated drain efficiency 510 is plotted versus average output power 520. Traces 530 and 535 depict the drain efficiency of the amplifier device 200 in high power mode and low power mode, respectively. Likewise, traces 570 and 575 depict the simulated gain 550 versus average output power 560 of the amplifier device 200 in high power mode and low power mode, respectively. As seen by comparing traces 530, 535, an efficiency improvement of approximately 10 percentage points 540 is seen for the low power mode at a power level of 37 dBm, in accordance with an embodiment. As seen by comparing traces 570, 575, a gain reduction of approximately 1.5 dB 580 is seen for the low power mode at a power level of 37 dBm, in accordance with an embodiment.

[0090] Figure 6 is a top view of a device 600 according to an embodiment. Figure 7 and Figure 8 Show Figure 6 Details within areas 7 and 8. When combined with Figure 7 and Figure 8 can be best understood when viewed simultaneously Figure 6 . An embodiment of the device 600 may include: a base substrate 601; an input port 602 coupled to the base substrate 601; an output port 604 coupled to the base substrate 601; a peaking amplifier die 610 (i.e., a "first amplifier die") coupled to the base substrate 601 and electrically coupled to a first input terminal 612 and a first output terminal 614; and a carrier amplifier die 620 (i.e., a "second amplifier die") coupled to the base substrate 601 and electrically coupled to a second input terminal 622 and a second output terminal 624. According to an embodiment, a splitter device 630 including a splitter input 632 and splitter outputs 633, 634 may be coupled to the base substrate 601, the base substrate 601 electrically coupling the input port 602 to the first input terminal 612 and the second input terminal 622. In an embodiment, a reconfigurable output matching network (OMN) 660 may be coupled to the base substrate 601. In an embodiment, the reconfigurable OMN 660 may be electrically coupled to the first output terminal 614 and to the combining node 644. In an embodiment, a voltage impedance transformer 680 may be coupled to the base substrate 601. The impedance transformer 680 may include a voltage variable capacitor 830 (i.e., a "second tunable element") electrically coupled to the combining node 644 and the output port 604. In an embodiment, a bias network 650 including a choke 652 and a bypass capacitor 654 may be used to supply a carrier drain bias 656V to the carrier amplifier die 620. D_C Likewise, in an embodiment, the peaking drain bias 662 VD_P may be supplied by the reconfigurable OMN 660 .

[0091] Figure 7 A detailed view of a reconfigurable OMN 660 and its electrical connections to a peaking amplifier die 610 according to an embodiment is shown. According to an embodiment, the reconfigurable OMN 660 may include an output element 750. In an embodiment, the output element 750 may include a first voltage variable capacitor 752 (ie, a "first tunable element").

[0092] According to an embodiment, the reconfigurable OMN 660 may include a first resonator 710, a series element 720, a second resonator 730, and an output element 750. According to an embodiment, the first resonator 710 may be electrically coupled to the series element 720, the series element 720 may be electrically coupled to the second resonator 730, and the second resonator 730 may be electrically coupled to the output element 750.

[0093] According to an embodiment, the first resonator 710 may include a first tunable inductor 712 and a first capacitor 716. According to an embodiment, a peaking amplifier drain bias 662 may be applied to the peaking amplifier die through the first tunable inductor 712 and the bond wire 726B, wherein the first capacitor 716 may be used to decouple a DC bias supply (not shown) supplying the peaking amplifier drain bias 662 from the first tunable inductor 712.

[0094] In an embodiment, the series element 720 may include an inductor component 721L2, and may electrically couple the first resonator 710 to the second resonator 730. According to an embodiment, bonding wires 726A / B may be included in the series element 720. In other embodiments (e.g., monolithically integrated embodiments), the bonding wires 726A / B may be omitted.

[0095] In an embodiment, the second resonator 730 can be electrically coupled to the series element 720 and can include a second tunable inductor 732 (i.e., a “third shunt element”) L3 and a second capacitor component 736 (i.e., a “fourth shunt element”) C3, wherein the second capacitor component 736 can couple the second resonator inductor component 732 to ground.

[0096] In an embodiment, the output element 750 may electrically couple the second resonator 330 to the output 304. The output element 750 may include a capacitive element 752C1. In an embodiment, the capacitive element 752 may be a voltage variable capacitor.

[0097] In an embodiment, the voltage variable capacitor 752C1T may be implemented using a micro-electromechanical switch according to an embodiment. In other embodiments, the voltage variable capacitor 752C1T may be implemented using a barium strontium titanate (BST) based capacitor, a barium strontium zirconate (BZT) based capacitor, a varactor diode, a switch capacitor, and one or more PIN diodes according to an embodiment. In an embodiment, a control circuit system (not shown) may be used to control the capacitance of the voltage variable capacitor 752.

[0098] Figure 8 A detailed view of a reconfigurable impedance transformer 680 (ie, a "second network") according to an embodiment is shown. In an embodiment, the reconfigurable impedance transformer 680 may include a transmission line 820 including a voltage variable capacitor 830C1T that electrically couples the transmission line 820 to ground potential.

[0099] According to an embodiment, the reconfigurable impedance transformer 680 may include an input transmission line segment 810, a variable capacitor 830C1T that electrically couples the transmission line 820 to a ground potential 832, and a fixed capacitor 840C2T. A series capacitor 850C3T may be used to couple a “pi” network of voltage variable capacitor 830, transmission line 820, and fixed capacitor 840.

[0100] The voltage variable capacitor 830C1T may be implemented using a micro-electromechanical switch according to an embodiment. In other embodiments, the voltage variable capacitor 430CIT may be implemented using a barium strontium titanate (BST) based capacitor, a barium strontium zirconate (BZT) based capacitor, a varactor diode, a switch capacitor, and one or more PIN diodes according to an embodiment.

[0101] Fig. 9 is a flow chart of an operating method of the amplifier device 200 according to an embodiment. Fig. 9 and Figures 2A to 4 , the method can be best understood.

[0102] In boxes 910 to 940, embodiments of the method may include: providing an input signal to an input port 202 of an amplifier device 200; coupling a first portion of the input signal to a first input 212 of a peaking amplifier 210 (i.e., a “first amplifier”) and coupling a second portion of the input signal to a second input 222 of a carrier amplifier 220 (i.e., a “second amplifier”); amplifying the first portion of the input signal with the peaking amplifier 210 to produce a first amplified signal at a first output terminal 214 of the peaking amplifier 210; and amplifying the second portion of the input signal with the carrier amplifier 220 to produce a second amplified signal at a second output terminal 224 of the carrier amplifier.

[0103] In block 950 , embodiments of the method may additionally include combining the first amplified signal and the second amplified signal at the combining node 244 to produce a combined signal at the combining node.

[0104] In block 960, the method may additionally include, according to an embodiment, changing the impedance at the peaking amplifier output 214 by a reconfigurable OMN 260 electrically coupled to the first output terminal and electrically coupled to a combining node 244, the combining node 244 including an output element 350 including a first voltage variable capacitor 353 (i.e., a “first tunable element”); and additionally changing the impedance at the combining node 244 by a reconfigurable impedance transformer 280 including a second voltage variable capacitor 430 (i.e., a “second tunable element”) electrically coupled to the combining node 244 and the output port 404. It should be appreciated that, according to an embodiment, changing the impedance at the peaking amplifier output 214 by the reconfigurable OMN 260 may include changing the impedance at the carrier amplifier output 224.

[0105] Still refer to Fig. 9 , block 960, in an embodiment of the method, changing the impedance at the combining node 244 may include: implementing a first tuned impedance through the reconfigurable OMN 260 and a second tuned impedance through the reconfigurable impedance transformer 280 to operate the peaking amplifier 210 and the carrier amplifier 220 in a full power mode (i.e., a “first state”); and implementing a third tuned impedance through the reconfigurable OMN 260 and a fourth tuned impedance through the impedance transformer 280 to operate the peaking amplifier 210 and the carrier amplifier 220 in a low power mode (i.e., a “second state”). Reference Fig. 9 , block 970, the method may also include transmitting the combined signal to a Figure 2A The output port 204 is loaded with a load 206 .

[0106] Reference again Fig. 9 , block 920, in an embodiment of the method, coupling the first portion of the input signal to the first input of the first amplifier and coupling the second portion of the input signal to the second input of the second amplifier may include splitting the input signal using a splitter device 230, wherein the first portion and the second portion of the input signal are offset by a phase difference between 60 degrees and 120 degrees. According to an embodiment, combining the first amplified signal and the second amplified signal includes routing the first amplified signal and the second amplified signal through an impedance inverter network 240 having an insertion phase within 20% of the phase difference.

[0107] Reference again Fig. 9 , blocks 930 to 940, in an embodiment, amplifying the first portion of the input signal may include operating the first amplifier device 210 as a peaking amplifier 210 or a carrier amplifier 220. Additionally, according to an embodiment, amplifying the second portion of the input signal may include operating the second amplifier 220 as a peaking amplifier or a carrier amplifier.

[0108] For the sake of brevity, certain terminology may also be used herein for reference purposes only and are thus not intended to be limiting, and the terms "first," "second," and other such numerical terms referring to structures do not imply a sequential order or sequence unless the context clearly indicates otherwise.

[0109] As used herein, "node" means any internal or external reference point, connection point, junction, signal line, conductive element, etc., at which a given signal, logic level, voltage, data pattern, current or quantity exists. In addition, two or more nodes may be implemented by one physical element (and two or more signals may be multiplexed, modulated, or otherwise distinguished despite being received or output at a common node).

[0110] The above description refers to elements or nodes or features being "connected" or "coupled" together. As used herein, unless otherwise explicitly stated, "connected" means that one element is directly joined to another element (or directly communicates with another element), and not necessarily mechanically joined. Similarly, unless otherwise explicitly stated, "coupled" means that one element is directly or indirectly joined to another element (or directly or indirectly communicates with another element), and not necessarily mechanically joined. Therefore, although the schematic diagrams shown in the figures depict an exemplary arrangement of elements, additional intervening elements, devices, features, or components may exist in the embodiments of the depicted subject matter.

[0111] Although at least one exemplary embodiment has been presented in the above detailed description, it should be understood that there are a large number of variations. It should also be understood that one or more exemplary embodiments described herein are not intended to limit the scope, applicability, or configuration of the claimed subject matter in any way. In fact, the above detailed description will provide a convenient guide for implementing one or more of the described embodiments to those skilled in the art. It should be understood that various changes can be made to the function and arrangement of elements without departing from the scope defined by the claims, and the scope defined by the claims includes known equivalents and foreseeable equivalents at the time of filing this patent application.

Claims

1. An amplifier device, characterized in that: include: Input port; Output port; a first amplifier including a first input terminal electrically coupled to the input port and a first output terminal electrically coupled to the output port; a second amplifier including a second input terminal electrically coupled to the input port and a second output terminal electrically coupled to the output port; a first network including a first tunable element electrically coupled to the first output terminal and to a combining node; as well as A second network includes a second tunable element electrically coupled to the combining node and to the output port.

2. The amplifier device according to claim 1, characterized in that The amplifier device is configured as a Doherty amplifier, the Doherty amplifier comprising: a splitter network comprising a splitter input, a first splitter output, and a second splitter output, the splitter network electrically coupling the input port to the first input at the first splitter output and electrically coupling the input port to the second input at the second splitter output, wherein a first insertion phase between the splitter input and the first splitter output and a second insertion phase between the splitter input and the second splitter output have a phase difference between 60 degrees and 120 degrees; and A phase shift network is electrically coupled between the second output terminal and the combining node.

3. The amplifier device according to claim 2, characterized in that The first amplifier is configured as a peaking amplifier and the second amplifier is configured as a carrier amplifier.

4. The amplifier device according to claim 2, characterized in that The first amplifier is configured as a carrier amplifier and the second amplifier is configured as a peaking amplifier.

5. The amplifier device according to claim 1, characterized in that The first tunable element includes a first voltage variable capacitor.

6. The amplifier device according to claim 1, characterized in that The first network includes: a first resonator comprising a first shunt element, wherein the first resonator is electrically coupled to the first amplifier through the first shunt element; a second shunt element electrically coupled to the first shunt element and to ground potential; a first series element electrically coupled to the first resonator; a second resonator comprising a third shunt element, wherein the third shunt element is electrically coupled to the first series element; and A fourth shunt element is electrically coupled to ground potential.

7. The amplifier device according to claim 6, characterized in that: The first shunt element includes a third tunable element; and The first tunable element electrically couples the third shunt element of the second resonator to the combining node.

8. The amplifier device according to claim 1, characterized in that The second network includes a voltage variable impedance transmission line.

9. A device, characterized in that: include: base substrate; an input port coupled to the base substrate and an output port coupled to the base substrate; a first amplifier die coupled to the base substrate and electrically coupled to a first input and a first output; a second amplifier die coupled to the base substrate and electrically coupled to a second input and a second output; a splitter device coupled to the base substrate, the splitter device electrically coupling the input port to the first input and the second input; an output matching network coupled to the base substrate, the output matching network comprising a first tunable element, wherein the output matching network is electrically coupled to the first output terminal and to a combining node; as well as A reconfigurable impedance transformer is coupled to the base substrate, the reconfigurable impedance transformer comprising a second tunable element coupled to the combining node and the output port.

10. A method of operating an amplifier device, characterized in that The method comprises the following steps: providing an input signal to an input port of said amplifier device; coupling a first portion of the input signal to a first input of a first amplifier and coupling a second portion of the input signal to a second input of a second amplifier; amplifying the first portion of the input signal with the first amplifier to produce a first amplified signal at a first output terminal of the first amplifier; amplifying the second portion of the input signal with the second amplifier to produce a second amplified signal at a second output terminal of the second amplifier; combining the first amplified signal and the second amplified signal at a combining node to produce a combined signal at the combining node; varying an impedance at the first output terminal of the first amplifier by an output matching network electrically coupled to the first output terminal and to the combining node including a first tunable element, and additionally varying the impedance at the combining node by an impedance transformer including a second tunable element electrically coupled to the combining node and an output port; The combined signal is delivered to a load electrically coupled to the output port.

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