Wide dynamic range high performance low phase noise PLL

Abstract

According to the wide-dynamic-range high-performance low-phase-noise PLL provided by the invention, the phase noise of the PLL can be reduced and the purity and the stability of an output signal can be improved by optimizing the design and parameter selection of the loop filter and adopting the high-performance annular voltage-controlled oscillator. The ultra-large frequency adjusting range can be achieved, so that the flexibility of the system is improved, and different frequency requirements and working scenes can be met. The loop parameters of the PLL have a multi-gear adjusting function, so that the stability of the loop can be ensured while the high KVCO characteristic is maintained, the dynamic performance is optimized, and particularly, stable frequency response can be provided during rapid frequency switching. Meanwhile, the advantages of a high-speed loop and a low-speed loop are combined, high-performance indexes such as rapid locking, high precision and low phase noise are achieved, and the high-speed loop is suitable for application scenes with high requirements for frequency synthesis, clock recovery, signal demodulation and the like.

Description

Technical Field

[0001] The present application relates to the field of PLL technology, and in particular to a PLL with wide dynamic range, high performance and low phase noise. Background Art

[0002] PLL (Phase-Locked Loop) is a technology that achieves frequency and phase synchronization through feedback control. It can multiply, divide or adjust the phase of the input reference clock signal to output a stable and accurate clock signal. In MCU, the clock signal is the basis of system operation. It determines the operation speed of MCU, the operating frequency of peripherals and the overall performance of the system. Therefore, PLL plays a vital role in MCU. It can provide a stable and accurate clock source for MCU.

[0003] The demand for wide dynamic range frequency synthesis in high-performance electronic systems is particularly evident in applications such as communications, signal processing, and microcontrollers (MCUs). MCUs require precise frequency control to support clock management of high-speed processors while also taking into account the requirements of low power consumption, wide frequency range adjustment, and low phase noise.

[0004] However, in traditional PLL designs, it is usually difficult to strike a balance between a wide frequency adjustment range and low power consumption and low phase noise. Common problems with existing technologies include: limited frequency adjustment range, high phase noise, high power consumption, and poor dynamic response. Especially when it is necessary to support both high-band and low-band signals, traditional PLLs are difficult to achieve compatibility between high flexibility and low power consumption. Summary of the invention

[0005] The present application aims to solve the problems of limited frequency adjustment range, high phase noise, high power consumption, poor dynamic response, and difficulty in achieving compatibility of high flexibility and low power consumption in existing PLL designs, and provides a high-performance, low-phase-noise PLL with a wide dynamic range, including: a high-speed loop and a low-speed loop, wherein the high-speed loop is connected in parallel with the low-speed loop;

[0006] The low-speed loop includes a second frequency divider, which is configured to receive a reference signal, divide the reference signal and output a low-frequency voltage signal;

[0007] The high-speed loop includes: a phase detector, a charge pump, a loop filter, a first frequency divider and a ring voltage-controlled oscillator;

[0008] The output end of the phase detector is connected to the input end of the charge pump, the output end of the charge pump is connected to the input end of the loop filter, and the output end of the loop filter is connected to the input end of the ring voltage controlled oscillator;

[0009] The phase detector is configured to: receive the reference signal and the feedback signal, and output a control signal to the charge pump according to the phase difference between the reference signal and the feedback signal, wherein the control signal is a voltage signal containing phase error information;

[0010] The charge pump is configured to: receive the control signal, control the direction and magnitude of the current according to the control signal, and output a current pulse to the loop filter;

[0011] The loop filter is configured to: receive the current pulse, filter the current pulse and then output a control voltage signal to the ring voltage controlled oscillator;

[0012] The input end of the first frequency divider is connected to the output end of the ring voltage controlled oscillator, and the output end of the first frequency divider is connected to the input end of the phase detector;

[0013] The first frequency divider is configured to: receive the high-frequency feedback signal, perform frequency division processing on the high-frequency feedback signal to obtain the low-frequency feedback signal, and output the feedback signal to the phase detector;

[0014] The ring voltage-controlled oscillator comprises: an input voltage conversion circuit, a 4-Tap delay unit and an output voltage conversion circuit;

[0015] The input end of the input voltage conversion circuit is connected to the output end of the loop filter, the output end of the input voltage conversion circuit is connected to the input end of the 4-Tap delay unit, and the output end of the 4-Tap delay unit is connected to the input end of the output voltage conversion circuit;

[0016] The input voltage conversion circuit is configured to: receive the control voltage signal, convert the control voltage signal into two signals, and output the two signals to the 4-Tap delay unit;

[0017] The 4-Tap delay unit is configured to: receive the two signals, adjust the delay according to the two signals, and output a CML signal of a corresponding frequency to the output voltage conversion circuit;

[0018] The output voltage conversion circuit is configured to: receive the CML signal, convert the CML signal into a CMOS signal, and then output a high-frequency feedback signal voltage.

[0019] In a feasible implementation manner, the frequency division ratio of the first frequency divider covers a range of 9 to 767, and the step size of the first frequency divider is 1.

[0020] In a feasible implementation, the frequency division ratio of the second frequency divider covers a range of 2 to 15, and the step size of the second frequency divider is 1.

[0021] In a feasible implementation, the phase detector includes: two D flip-flops and a multi-stage delay unit;

[0022] The input ends of the two D flip-flops are respectively connected to the output end of the reference clock and the output end of the feedback clock;

[0023] The output ends of the two D flip-flops are both connected to the input end of the multi-stage delay unit, and the output end of the multi-stage delay unit is connected to the input end of the charge pump;

[0024] The two D flip-flops are configured to: respectively receive the reference signal and the feedback signal, process to obtain an initial control signal, and output the initial control signal to the multi-stage delay unit and the charge pump;

[0025] The multi-stage delay unit is configured to perform delay processing after receiving the initial control signal to avoid a dead zone effect of the phase detector.

[0026] In a feasible implementation, the control signal includes: a high-frequency error component and a low-frequency control voltage component;

[0027] The loop filter is further configured to remove the high-frequency error component in the current pulse and retain the low-frequency control voltage component.

[0028] In a feasible implementation, the two signals include: a first signal and a second signal;

[0029] The first signal is configured to: adjust the load resistance value of the 4-Tap delay unit to adjust the delay time of the delay unit;

[0030] The second signal is configured to adjust the current of the tail current source of the 4-Tap delay unit to adjust the delay time of the delay unit.

[0031] In a feasible implementation, the charge pump includes: a current mirror and a CMOS switch;

[0032] The input end of the CMOS switch is connected to the two output ends of the D flip-flop;

[0033] The current mirror is configured to: provide current sources of different magnitudes according to preset parameters, adjust the current according to the opening or closing of the CMOS switch, and output the current to the loop filter;

[0034] The CMOS switch is configured to receive the control signal, open or close the current path according to the control signal, form the current pulse, and output the current pulse to the loop filter.

[0035] In a feasible implementation, the charge pump further includes: a full-swing operational amplifier;

[0036] The positive input terminal of the full-swing operational amplifier is connected to the output terminal of the current mirror, the output terminal of the swing operational amplifier is connected to the negative input terminal of the full-swing operational amplifier, the output terminal of the swing operational amplifier is also connected to the source stages of the two CMOS switches, and the full-swing operational amplifier is configured to reduce the current mismatch.

[0037] In a feasible implementation, the output voltage conversion circuit includes a five-transistor operational amplifier and a multi-stage buffer;

[0038] The five-tube operational amplifier is configured to: amplify the output differential signal of the delay unit;

[0039] The multi-stage buffer will be configured to convert the output signal of the five-transistor operational amplifier from a CML signal into a CMOS signal.

[0040] In a feasible implementation, the current of the charge pump is 3-bit adjustable, and the current range is 40uA to 320uA; the loop filter is a second-order passive low-pass filter, the resistance of the loop filter is 3-bit adjustable, and the capacitance of the loop filter is 2-bit adjustable.

[0041] The wide dynamic range, high performance, low phase noise PLL provided by the present application can reduce the phase noise of the PLL and improve the purity and stability of the output signal by optimizing the design and parameter selection of the loop filter and adopting a high-performance ring voltage-controlled oscillator. It can achieve an ultra-large frequency adjustment range, thereby improving the flexibility of the system and being able to adapt to different frequency requirements and working scenarios. The loop parameters of the PLL have a multi-speed adjustment function, which enables it to ensure the stability of the loop while maintaining high KVCO characteristics, optimize dynamic performance, and provide a smooth frequency response, especially when the frequency is switched quickly. At the same time, it combines the advantages of high-speed loops and low-speed loops to achieve high performance indicators such as fast locking, high precision and low phase noise, and is suitable for application scenarios with high requirements such as frequency synthesis, clock recovery and signal demodulation. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The accompanying drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the implementation of the present invention, and together with the specification are used to explain the principles of the embodiments of the present invention. Obviously, the accompanying drawings described below are only some embodiments of the implementation of the present invention, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0043] Figure 1 It is a schematic diagram of the structure of a wide dynamic range, high performance, low phase noise PLL shown in an exemplary embodiment of the present application;

[0044] Figure 2 is a structural schematic diagram of a ring voltage-controlled oscillator shown in another exemplary embodiment of the present application;

[0045] Figure 3 It is a schematic diagram of KVCO parameters obtained based on Cadence Virtuoso platform system simulation and performance testing according to an exemplary embodiment of the present application;

[0046] Figure 4 It is a schematic diagram of phase noise parameters obtained based on Cadence Virtuoso platform system simulation and performance testing, shown in an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0047] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the embodiments of the present invention will be more comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, many specific details are provided to provide a full understanding of the implementation of the embodiments of the present invention.

[0048] For MCU, precise frequency control is the core of its clock management system. MCU needs to support high-speed processor operation while maintaining low power consumption to extend battery life. The wide frequency range adjustment capability enables MCU to flexibly adjust the clock frequency in different operating modes to optimize the balance between performance and power consumption. In addition, low phase noise is critical to reducing system interference and maintaining data integrity. However, traditional phase-locked loop (PLL) designs often have an irreconcilable contradiction between wide frequency adjustment range and low power consumption and low phase noise. Traditional PLLs usually use fixed loop parameters and filter designs, which limits their frequency adjustment range. In order to widen the frequency range, it may be necessary to add additional circuit elements or adjust loop parameters, but this usually leads to increased power consumption and worsening phase noise.

[0049] To solve the above problems, the present application provides a wide dynamic range, high performance, low phase noise PLL, referring to Figure 1 As shown, it includes: a high-speed loop and a low-speed loop, and the high-speed loop is connected in parallel with the low-speed loop.

[0050] The low-speed loop includes a second frequency divider; the second frequency divider is configured to receive a reference signal, perform frequency division processing on the reference signal, and output a low-frequency voltage signal.

[0051] As the core component of the low-speed loop, the second divider is responsible for receiving a stable reference signal (usually from an external crystal or high-precision clock source). By dividing the reference signal, it generates a lower frequency output voltage. The low-speed loop is simple to design, with a small area and low power consumption, which contributes to the low-power design of the overall system.

[0052] The high-speed loop includes: a phase detector, a charge pump, a loop filter, a first frequency divider and a ring voltage-controlled oscillator; the output end of the phase detector is connected to the input end of the charge pump, the output end of the charge pump is connected to the input end of the loop filter, and the output end of the loop filter is connected to the input end of the ring voltage-controlled oscillator.

[0053] The phase detector is configured to receive a reference signal and a feedback signal, and output a control signal to the charge pump according to the phase difference between the reference signal and the feedback signal, wherein the control signal is a voltage signal or a current signal containing phase error information.

[0054] The phase detector is a key component in the PLL, responsible for comparing the phase difference between the reference signal and the high-frequency feedback signal from the ring voltage-controlled oscillator. Depending on the size and direction of the phase difference, the phase detector outputs a voltage signal or current signal containing phase error information to the charge pump. Accurate phase detection is the basis for achieving low phase noise. By adjusting the phase error in real time, the phase detector ensures that the PLL can respond quickly and lock to the target frequency while maintaining low phase noise.

[0055] The charge pump is configured to receive a control signal, control the direction and size of the current according to the control signal, and output a current pulse to the loop filter. The charge pump receives a control signal from the phase detector and controls the direction and size of the current according to the control signal. It outputs a current pulse to the loop filter, and the current pulse reflects the size and direction of the phase error. The design of the charge pump allows the PLL system to adjust its output frequency in response to the phase error in an efficient manner. By precisely controlling the direction and size of the current, the charge pump helps achieve fast and stable frequency lock while maintaining low power consumption.

[0056] The loop filter is configured to receive current pulses, filter the current pulses, and output a control voltage signal to the ring voltage controlled oscillator. The loop filter receives current pulses from the charge pump and filters the current pulses to eliminate high-frequency noise and interference. The filtered signal is converted into a control voltage signal, which is then sent to the ring voltage controlled oscillator. The loop filter ensures the stability and accuracy of the control voltage signal, thereby improving the stability and accuracy of the output frequency of the PLL.

[0057] The input end of the first frequency divider is connected to the output end of the ring voltage controlled oscillator, and the output end of the first frequency divider is connected to the input end of the phase detector; the first frequency divider is configured to: receive a high-frequency feedback signal, perform frequency division processing on the high-frequency feedback signal to obtain a low-frequency feedback signal, and output the feedback signal to the phase detector.

[0058] In high-speed mode, the frequency division ratio can be adjusted by the first frequency divider to flexibly adjust the output frequency to meet different application requirements. For example, in a communication system, different operating frequencies may be required to support different communication standards or frequency bands.

[0059] The ring voltage-controlled oscillator comprises: an input voltage conversion circuit, a multi-stage delay unit and an output voltage conversion circuit; the input end of the input voltage conversion circuit is connected to the output end of the loop filter, the output end of the input voltage conversion circuit is connected to the input end of the multi-stage delay unit, and the output end of the multi-stage delay unit is connected to the input end of the output voltage conversion circuit.

[0060] Specifically, refer to Figure 2 As shown, the ring voltage-controlled oscillator of the present application is a dual-path adjustable 4-Tap cross-coupled Ring voltage-controlled oscillator, which combines the cross-coupling technology and the structure of the Ring VCO (voltage-controlled oscillator) and has the characteristic of dual-path adjustment. The Ring VCO is usually composed of a plurality of delay units cascaded to form a ring oscillator. This structure enables the RingVCO to have higher frequency stability and better phase noise performance. The cross-coupling technology is to obtain a large gain by using a cross-coupled transistor pair in the voltage-controlled oscillator, and obtain a high frequency output range. This technology helps to improve the oscillation stability and frequency adjustment range of the voltage-controlled oscillator.

[0061] 4-Tap means that four taps are set in the feedback path of the Ring VCO, each of which can be used as an output or for frequency adjustment. This structure provides more frequency adjustment points, making the frequency adjustment of the voltage-controlled oscillator more flexible and precise. Dual-path adjustable means that the voltage-controlled oscillator has two independent control inputs that can adjust the frequency of the voltage-controlled oscillator separately. This is usually achieved by changing the gate voltage of the cross-coupled transistor pair and the value of the tail current source.

[0062] When the power is turned on, the delay unit in the Ring VCO starts to work and forms a ring oscillation. The cross-coupled transistor pair provides negative resistance to compensate for the energy loss during the oscillation process, thereby maintaining a stable oscillation. By changing any one of the two-way control inputs or both at the same time, the gate voltage of the cross-coupled transistor pair or the component value in the Ring VCO can be adjusted to change the oscillation frequency of the voltage-controlled oscillator. The 4-Tap structure provides multiple frequency adjustment points, making the frequency adjustment more precise and flexible. The output signal of the voltage-controlled oscillator is a sine wave generated by the ring oscillator, and its frequency is determined by the two-way control input.

[0063] Therefore, the ring voltage-controlled oscillator of the present application can achieve an ultra-large frequency adjustment range, thereby improving the flexibility of the system and being able to adapt to different frequency requirements and working scenarios. The loop parameters of the PLL have a multi-level adjustment function, so that it can maintain a high KVCO (voltage-controlled oscillator gain) characteristic while ensuring the stability of the loop, optimizing dynamic performance, and providing a smooth frequency response, especially when the frequency is switched quickly.

[0064] Specifically, in an embodiment of the present application, the input voltage conversion circuit is configured to: receive a control voltage signal, and convert the control voltage signal into two signals, and output the two signals to a 4-Tap delay unit; the 4-Tap delay unit is configured to: receive two signals, adjust the delay according to the two signals, and output a CML signal of a corresponding frequency to the output voltage conversion circuit; the output voltage conversion circuit is configured to: receive a CML signal, convert the CML signal into a CMOS signal, and then output a high-frequency feedback signal voltage.

[0065] Specifically, the input voltage conversion circuit converts the output voltage of the low-pass filter into two signals, and adjusts the load and tail current source of the delay unit at the same time to achieve wide frequency adjustment. By adjusting the load and tail current source of the 4-Tap delay unit, the operating characteristics of the delay unit, such as delay time, stability, etc., can be affected, thereby achieving wide frequency adjustment. This adjustment mechanism enables the PLL to flexibly adjust the clock frequency in different operating modes and optimize the balance between performance and power consumption.

[0066] In some embodiments of the present application, the two signals include: a first signal and a second signal; the first signal is configured to: adjust the load resistance value of the delay unit to adjust the delay time of the 4-Tap delay unit; the second signal is configured to: change the current size of the tail current source of the delay unit to adjust the oscillation characteristics of the 4-Tap delay unit.

[0067] The 4-Tap delay unit receives the signal from the input voltage conversion circuit and delays it to generate a high-frequency oscillation signal. The 4-Tap delay unit adopts an adjustable load structure, which means that its load can be adjusted as needed. This design enables the delay unit to maintain stable performance under different operating conditions while reducing phase noise. By precisely controlling the size of the load, the delay time and phase noise performance of the 4-Tap delay unit can be optimized. The first signal is to adjust the delay time of the 4-Tap delay unit by adjusting the load resistance value of the delay unit. Changes in load resistance affect the flow of current in the circuit, thereby affecting the time required for the signal to pass through the delay unit.

[0068] The tail current source is a component in the delay unit that provides the operating current. By changing the current size of the tail current source, the oscillation characteristics of the delay unit can be adjusted. This includes parameters such as oscillation frequency, amplitude, and phase. The second signal can expand the dynamic range of the delay unit by adjusting the current size of the tail current source. This means that the delay unit can maintain stable performance over a wider frequency range, thus adapting to different application scenarios. Appropriate tail current source current size selection can also help manage the power consumption of the delay unit. In applications that require low power consumption, power consumption can be reduced by reducing the current size of the tail current source; in applications that require high performance, performance can be improved by increasing the current size of the tail current source.

[0069] The 4-Tap delay unit also further reduces phase noise by maintaining the symmetry of the rising and falling edges. This symmetry helps reduce distortion and interference of the signal during transmission, thereby improving the output quality of the PLL. The delay unit receives the signal from the input voltage conversion circuit and delays it to generate a high-frequency oscillation signal. The main function of the output circuit is to convert the CML (non-full-swing voltage) signal output by the delay unit into a CMOS (full-swing voltage) signal, and then output a high-frequency feedback signal and output voltage. This conversion process ensures the compatibility and stability of the signal. The design of the ring voltage-controlled oscillator allows the PLL to flexibly adjust the output frequency over a wide frequency range while maintaining low phase noise and low power consumption. By optimizing the design of the delay unit and the voltage conversion circuit, the ring voltage-controlled oscillator can efficiently respond to changes in the control voltage signal, thereby achieving fast and stable frequency locking.

[0070] The wide dynamic range, high performance, low phase noise PLL proposed in this application achieves a balance between a wide frequency adjustment range, low power consumption and low phase noise by combining the design of a low-speed loop and a high-speed loop. The low-speed loop provides a stable reference for the system, while the high-speed loop ensures that the PLL can respond quickly and lock to the target frequency while maintaining low phase noise and low power consumption through precise phase detection, efficient charge pump control, stable loop filtering and flexible ring voltage-controlled oscillator design. This design not only solves the contradiction between the wide frequency adjustment range and low power consumption and low phase noise of the traditional PLL, but also provides a more flexible, efficient and reliable clock management solution for embedded systems such as MCUs.

[0071] In some embodiments of the present application, the frequency division ratio of the first frequency divider covers a range of 9 to 767, and the step size of the first frequency divider is 1.

[0072] The first frequency divider in the embodiment of the present application provides a wide range of frequency division options, allowing the system to operate in different frequency ranges. When the PLL chooses to use the high-speed loop, the output frequency range covers 100MHz~1GHz, the integer divider division ratio covers 9~767, and the divider step is 1. In this mode, the total power consumption is less than 6mW when the output frequency is 400M, and the phase noise @1MHz=-105.35dBc / Hz, which is suitable for high-frequency application scenarios, such as MCU master clock generation, wireless communication equipment, FPGA high-speed interface, network router synchronization clock, etc. By adjusting the division ratio in steps of 1, the output frequency can be accurately controlled to improve the frequency resolution and stability of the system.

[0073] In some embodiments of the present application, the frequency division ratio of the second frequency divider covers a range of 2 to 15, and the step size of the second frequency divider is 1.

[0074] Specifically, when the PLL selects the low-speed loop, the high-speed loop will be closed. In low-speed mode, the second divider receives a high-frequency reference signal. The second divider can reduce the frequency of the input signal to between 1 / 2 and 1 / 15 of the original frequency. After dividing the reference signal, it outputs a lower frequency voltage signal. The output frequency range covers 200KHz to 1MHz, and the integer divider division ratio covers 2 to 15. In this mode, the total power consumption is less than 50uW, which is suitable for low-frequency application scenarios. In order to reduce power consumption, all loops in high-speed mode will be closed in low-speed mode, and the reference clock will be directly divided and output, which is suitable for clock management in low-power mode of MCU.

[0075] The frequency division ratio can be finely adjusted in units of 1, which provides a high degree of flexibility and resolution, and provides the system with a variety of frequency division options, allowing the system to be adjusted in different steps within different frequency ranges. This increases the flexibility and adaptability of the system.

[0076] In some embodiments of the present application, the phase detector includes: two D flip-flops and a multi-stage delay unit; the input ends of the two D flip-flops are respectively connected to the output end of the reference clock and the output end of the feedback clock; the output ends of the two D flip-flops are both connected to the input end of the multi-stage delay unit, and the output end of the multi-stage delay unit is connected to the input end of the charge pump.

[0077] The two D flip-flops are configured to respectively receive a reference signal and a feedback signal, process the signal to obtain an initial control signal, and output the initial control signal to a multi-stage delay unit; the multi-stage delay unit is configured to perform delay processing after receiving the initial control signal to avoid the dead zone effect of the phase detector.

[0078] The two D flip-flops receive a reference signal and a feedback signal respectively. These signals usually come from different clock sources, such as a reference clock and a divided signal of the output of a ring voltage-controlled oscillator.

[0079] The D flip-flop generates initial control signals based on the received signals. These signals contain information about the phase difference between the reference signal and the feedback signal. The multi-stage delay unit receives the initial control signals from the two D flip-flops and performs delay processing. The charge pump adjusts the control voltage of the ring voltage controlled oscillator based on the received control signal, thereby changing the output frequency of the ring voltage controlled oscillator to achieve phase locking or frequency matching.

[0080] In some embodiments of the present application, the control signal includes: a high-frequency error component and a low-frequency control voltage component; the loop filter is also configured to: remove the high-frequency error component in the current pulse and retain the low-frequency control voltage component.

[0081] Among them, the high-frequency error components are usually high-frequency components in the control signal output by the phase detector, which may be caused by noise, interference or non-ideal factors in the phase detection process. The low-frequency control voltage component reflects the true phase difference between the reference signal and the feedback signal, and is the target that the system needs to adjust and lock. The loop filter is designed to have a low-pass filtering characteristic, that is, it allows low-frequency signals to pass and blocks high-frequency signals. Therefore, it can effectively remove the high-frequency error components in the control signal. While removing the high-frequency error components, the loop filter ensures that the low-frequency control voltage components are retained.

[0082] By removing high-frequency error components, the loop filter can reduce the impact of external noise and interference on system performance. Retaining the low-frequency control voltage component helps the system more accurately adjust the output frequency of the ring voltage-controlled oscillator to achieve stable phase lock. In a frequency synthesizer, this configuration of the loop filter helps generate a more accurate and stable output frequency.

[0083] In some embodiments of the present application, the charge pump includes: a current mirror and a CMOS switch; the input end of the CMOS switch is connected to the two output ends of the D trigger; the CMOS switch is configured to: receive the control signal, and open or close the current path according to the control signal, form a current pulse, and output the current pulse to the loop filter; the current mirror is configured to: provide current sources of different sizes according to preset parameters, adjust the current according to the opening or closing of the CMOS switch, and output the current to the loop filter.

[0084] CMOS switches receive control signals from multi-stage delay units. These signals contain information about the phase difference between the reference signal and the feedback signal. The current mirror adjusts the current at its output according to the input gear.

[0085] If the loop bandwidth needs to be increased, the current mirror increases the output current; if the loop bandwidth needs to be decreased, the current mirror decreases the output current.

[0086] The CMOS switch opens or closes the current path according to the control signal. When the switch is turned on, the current provided by the current mirror passes through the CMOS switch and forms a current pulse; when the switch is turned off, the current path is cut off and the current pulse ends. The generated current pulse is then sent to the loop filter for filtering. The loop filter removes the high-frequency components in the current pulse, retains the low-frequency components, and uses the filtered signal to adjust the control voltage of the ring voltage-controlled oscillator.

[0087] In this embodiment, the charge pump can quickly respond to changes in the control signal and generate corresponding current pulses to adjust the output frequency of the ring voltage controlled oscillator. By adjusting the current size and the switch state, the charge pump can achieve precise control of the output frequency of the ring voltage controlled oscillator. The coordinated work of the charge pump and the loop filter helps to ensure the stability of the system.

[0088] In some embodiments of the present application, the charge pump also includes: a full-swing operational amplifier; the positive input terminal of the full-swing operational amplifier is connected to the output terminal of the current mirror, the output terminal of the swing operational amplifier is connected to the negative input terminal of the full-swing operational amplifier, the output terminal of the swing operational amplifier is also connected to the source stage of two CMOS switches, and the full-swing operational amplifier is configured to: reduce current mismatch.

[0089] The rail-to-rail op amp monitors the voltage signal at the output of the current mirror and adjusts its output as needed to clamp the source voltage of the CMOS switches on both sides. This helps to reduce current mismatch and improve the stability and performance of the charge pump.

[0090] In some embodiments of the present application, the output voltage conversion circuit includes a five-tube operational amplifier and a multi-stage buffer; the five-tube operational amplifier is configured to: amplify the delayed signal; the multi-stage buffer will be configured to: buffer the delayed signal.

[0091] Operational amplifiers are usually based on a differential input and single-ended output structure. Through the adjustment of the internal circuit and the gain setting, they can amplify the input signal. The five-tube operational amplifier adopts a specific circuit design to ensure the best amplification effect on the delayed signal. The amplification function of the five-tube operational amplifier helps to increase the strength of the signal, which can be used in scenarios where weak signals need to be processed or long-distance transmission signals need to be transmitted.

[0092] A multi-stage buffer is usually composed of multiple buffer units cascaded together, each of which can amplify and shape the input signal to a certain extent. By cascading multiple buffer units, multiple amplification and shaping of the input signal can be achieved, thereby improving the stability and reliability of the signal. The buffering function of the multi-stage buffer helps to reduce signal loss and interference during transmission.

[0093] In some embodiments of the present application, the current is 3-bit adjustable, and the current range is 40uA to 320uA; the loop filter is a second-order passive low-pass filter, the resistance of the loop filter is 3-bit adjustable, and the capacitance of the loop filter is 2-bit adjustable.

[0094] Specifically, the current can be adjusted in steps from 40uA to 320uA. Since the current is 3-bit adjustable, it can have 2^3=8 different settings. Considering that the current range is from 40uA to 320uA, it can be inferred that the step size of the current is (320uA-40uA) / 7=40uA (assuming that the current is evenly spaced). Therefore, the current can be set to any value of 40uA, 80uA, 120uA, 160uA, 200uA, 240uA, 280uA or 320uA.

[0095] A second-order passive low-pass filter is a circuit used to filter out high-frequency noise and allow low-frequency signals to pass. In this embodiment, both the resistance and capacitance of the filter are adjustable, which allows fine adjustment of the filter's cutoff frequency. Since the resistance is 3-bit adjustable, it can have 2^3=8 different settings. This allows a certain degree of adjustment of the filter's impedance and frequency response. The capacitance is 2-bit adjustable, so it can have 2^2=4 different settings. Adjustment of the capacitance can further affect the filter's cutoff frequency and phase response.

[0096] It is understood that the cutoff frequency of a loop filter is the point at which the filter begins to significantly attenuate the frequency of the input signal. In a second-order passive low-pass filter, the cutoff frequency is determined by the values ​​of the resistor and capacitor. Since both the resistor and capacitor are adjustable, the cutoff frequency is also adjustable. By adjusting the values ​​of the resistor and capacitor, fine control of the cutoff frequency can be achieved, thereby optimizing the performance of the filter to meet the needs of a specific application.

[0097] In order to verify the performance of the system, system simulation and performance testing were carried out on the Cadence Virtuoso platform. The parameters were scanned to obtain KVCO, such as Figure 3 and Figure 4 As shown. Then through Pss (Periodic SteadyState) and Pnoise (Phase Noise) simulation, the phase noise power spectrum density of the ring voltage controlled oscillator can be obtained. The frequency range of the ring voltage controlled oscillator is 2MHz to 1.02GHz, and multiple process corners are analyzed. The results show that the frequency range can reach more than 900MHz. The power consumption at 400MHz is 5.89mW, and the phase noise @1MHz = -106.12dBc / Hz.

[0098] The phase noise power spectrum density of each module is obtained by simulation, and then the simulation data is imported into MATLAB to calculate the transfer function of each module to the PLL output. Based on these transfer functions, the contribution of each module to the phase noise power spectrum density of the PLL output can be determined. By superimposing the phase noise power spectrum density contributed by each module, the phase noise power spectrum density of the entire PLL is finally obtained, and the phase noise @1MHz = -105.35dBc / Hz.

[0099] Refer to Table 1, which shows the key performance parameters of the PLL in the frequency range of 200MHz to 1GHz. As the frequency increases, the bandwidth, phase margin, and lock time of the PLL remain stable, ensuring the stability and fast response of the system. At the same time, the ripple value increases slightly, but remains at a low level, indicating the high accuracy of the output signal. The power consumption increases linearly with the increase in frequency, indicating that the increase in power consumption at high frequencies is an expected phenomenon. Overall, the PLL shows excellent stability and energy efficiency in a wide frequency range, and is suitable for scenarios with high requirements on power consumption and performance.

[0100] Table 1 Performance parameter analysis of PLL at different frequencies

[0101] FRE Loop Bandwidth Phase Margin Lock time (us) Ripple(mV) Power consumption (mW) 200M 186.87k 60.98° 14.5 0.15 2.42 400M 186.87k 60.98° 15.2 0.18 5.89 600M 171.68k 62.41° 16.6 0.16 6.76 800M 191.72k 60.23° 15.1 0.25 8.23 1G 208.12k 59.67° 15.6 0.28 10.12

[0102] It can be seen from the above embodiments that the wide dynamic range, high performance, low phase noise PLL of the present application can be selected in high speed mode or low speed mode according to application requirements when in use.

[0103] In high-speed mode, configure the division ratio of the integer divider to ensure that the output frequency is between 100MHz and 1GHz, and the divider step is 1 to meet the accuracy requirements of high-frequency application scenarios. In high-speed mode, the PLL compares the phase difference between the reference signal and the feedback signal through the phase detector to generate an error signal. After the error signal is filtered by the loop filter, the frequency of the ring voltage-controlled oscillator is controlled to synchronize the output clock with the reference clock and minimize the phase difference. During the adjustment process, the second divider divides the high-frequency feedback signal to obtain a feedback signal to match the frequency range of the reference signal.

[0104] In high-speed mode, PLL ensures high accuracy and stability of the output clock through precise phase detection and frequency adjustment. It is very important to be applied to high-frequency application scenarios, such as the main clock generation of MCU and the RF circuit of wireless communication equipment, which can reduce clock jitter and phase noise and improve system performance and stability.

[0105] In low-speed mode, the division ratio of the integer divider is configured so that the output frequency is between 200KHz and 1MHz, which is suitable for low-power and low-frequency applications. In low-speed mode, in order to reduce power consumption, the PLL turns off the phase detector, loop filter and ring voltage-controlled oscillator circuit in the high-speed loop. The first divider is used directly to divide the reference clock and output the required low-frequency signal.

[0106] In low-speed mode, PLL significantly reduces power consumption by shutting down some circuits in the high-speed loop. This makes PLL more advantageous in low-power devices such as MCUs, where it can ensure clock accuracy while maintaining the same clock speed.

[0107] PLL outputs a stable clock signal to drive the main clock of the MCU, the RF circuit of wireless communication equipment, the high-speed interface of the FPGA, or the synchronous clock of the network router. PLL supports both high-speed and low-speed modes and can be flexibly configured according to application requirements. This allows PLL to be widely used in various scenarios, such as wireless communication, FPGA, network routers, etc., to meet the clock requirements of different devices.

[0108] The loop parameters of the PLL have a multi-level adjustment function, which enables it to ensure the stability of the loop while maintaining high KVCO characteristics, optimize dynamic performance, and provide a smooth frequency response, especially when the frequency is switched quickly. At the same time, it combines the advantages of high-speed loops and low-speed loops to achieve high performance indicators such as fast locking, high precision and low phase noise, and is suitable for application scenarios with high requirements such as frequency synthesis, clock recovery and signal demodulation.

[0109] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the disclosure of the specification and the examples. This application is intended to cover any modifications, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not disclosed in the present disclosure.

Claims

1. Wide dynamic range high performance low phase noise PLL, characterized by, include: A high-speed loop and a low-speed loop, wherein the high-speed loop is connected in parallel with the low-speed loop; The low speed loop includes a second frequency divider; The second frequency divider is configured to receive a reference signal, perform frequency division processing on the reference signal and then output a low-frequency voltage signal; The high-speed loop includes: a phase detector, a charge pump, a loop filter, a first frequency divider and a ring voltage-controlled oscillator; The output end of the phase detector is connected to the input end of the charge pump, the output end of the charge pump is connected to the input end of the loop filter, and the output end of the loop filter is connected to the input end of the ring voltage controlled oscillator; The phase detector is configured to: receive the reference signal and the feedback signal, and output a control signal to the charge pump according to the phase difference between the reference signal and the feedback signal, wherein the control signal is a voltage signal containing phase error information; The charge pump is configured to: receive the control signal, control the direction and magnitude of the current according to the control signal, and output a current pulse to the loop filter; The loop filter is configured to: receive the current pulse, filter the current pulse and then output a control voltage signal to the ring voltage controlled oscillator; The input end of the first frequency divider is connected to the output end of the ring voltage controlled oscillator, and the output end of the first frequency divider is connected to the input end of the phase detector; The first frequency divider is configured to: receive the high-frequency feedback signal, perform frequency division processing on the high-frequency feedback signal to obtain the low-frequency feedback signal, and output the feedback signal to the phase detector; The ring voltage-controlled oscillator comprises: an input voltage conversion circuit, a 4-Tap delay unit and an output voltage conversion circuit; The input end of the input voltage conversion circuit is connected to the output end of the loop filter, the output end of the input voltage conversion circuit is connected to the input end of the 4-Tap delay unit, and the output end of the 4-Tap delay unit is connected to the input end of the output voltage conversion circuit; The input voltage conversion circuit is configured to: receive the control voltage signal, convert the control voltage signal into two signals, and output the two signals to the 4-Tap delay unit; The 4-Tap delay unit is configured to: receive the two signals, adjust the delay according to the two signals, and output a CML signal of a corresponding frequency to the output voltage conversion circuit; The output voltage conversion circuit is configured to: receive the CML signal, convert the CML signal into a CMOS signal, and then output a high-frequency feedback signal voltage.

2. The wide dynamic range, high performance, low phase noise PLL according to claim 1, characterized in that: The frequency division ratio of the first frequency divider covers a range of 9 to 767, and the step size of the first frequency divider is 1.

3. The wide dynamic range, high performance, low phase noise PLL according to claim 1, characterized in that: The frequency division ratio of the second frequency divider covers a range of 2 to 15, and the step size of the second frequency divider is 1.

4. The wide dynamic range, high performance, low phase noise PLL according to claim 1, characterized in that: The phase detector comprises: two D flip-flops and a multi-stage delay unit; The input ends of the two D flip-flops are respectively connected to the output end of the reference clock and the output end of the feedback clock; The output ends of the two D flip-flops are both connected to the input end of the multi-stage delay unit, and the output end of the multi-stage delay unit is connected to the input end of the charge pump; The two D flip-flops are configured to: respectively receive the reference signal and the feedback signal, process to obtain an initial control signal, and output the initial control signal to the multi-stage delay unit and the charge pump; The multi-stage delay unit is configured to perform delay processing after receiving the initial control signal to avoid a dead zone effect of the phase detector.

5. The wide dynamic range, high performance, low phase noise PLL according to claim 2, characterized in that: The control signal includes: a high-frequency error component and a low-frequency control voltage component; The loop filter is further configured to remove the high-frequency error component in the current pulse and retain the low-frequency control voltage component.

6. The wide dynamic range, high performance, low phase noise PLL according to claim 1, characterized in that: The two signals include: a first signal and a second signal; The first signal is configured to: adjust the load resistance value of the 4-Tap delay unit to adjust the delay time of the delay unit; The second signal is configured to adjust the current of the tail current source of the 4-Tap delay unit to adjust the delay time of the delay unit.

7. The wide dynamic range, high performance, low phase noise PLL according to claim 4, characterized in that: The charge pump comprises: a current mirror and a CMOS switch; The input end of the CMOS switch is connected to the two output ends of the D flip-flop; The CMOS switch is configured to: receive the control signal, and open or close the current path according to the control signal to form the current pulse, and output the current pulse to the loop filter; The current mirror is configured to provide current sources of different sizes according to preset parameters, adjust the current according to the opening or closing of the CMOS switch, and output the current to the loop filter.

8. The wide dynamic range, high performance, low phase noise PLL according to claim 5, characterized in that: The charge pump further includes: a rail-to-rail operational amplifier; The positive input terminal of the full-swing operational amplifier is connected to the output terminal of the current mirror, the output terminal of the swing operational amplifier is connected to the negative input terminal of the full-swing operational amplifier, the output terminal of the swing operational amplifier is also connected to the source stages of the two CMOS switches, and the full-swing operational amplifier is configured to reduce the current mismatch.

9. The wide dynamic range, high performance, low phase noise PLL according to claim 1, characterized in that: The output voltage conversion circuit includes a five-tube operational amplifier and a multi-stage buffer; The five-tube operational amplifier is configured to: amplify the output differential signal of the delay unit; The multi-stage buffer will be configured to convert the output signal of the five-transistor operational amplifier from a CML signal into a CMOS signal.

10. The wide dynamic range, high performance, low phase noise PLL according to any one of claims 1 to 9, characterized in that: The current of the charge pump is 3-bit adjustable, and the current range is 40uA to 320uA; the loop filter is a second-order passive low-pass filter, the resistance of the loop filter is 3-bit adjustable, and the capacitance of the loop filter is 2-bit adjustable.

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