Wide dynamic range high performance low phase noise pll

Abstract

The application provides a wide dynamic range high-performance low phase noise PLL, which can reduce the phase noise of the PLL, improve the purity and stability of the output signal by optimizing the design and parameter selection of the loop filter, and adopting a high-performance ring voltage-controlled oscillator. It can realize ultra-large frequency adjustment range, thereby improving the flexibility of the system, and can adapt to different frequency requirements and working scenes. The loop parameters of the PLL have a multi-gear adjustment function, which can ensure the stability of the loop while maintaining high KVCO characteristics, optimize the dynamic performance, and provide smooth frequency response especially during fast frequency switching. At the same time, the advantages of high-speed loop and low-speed loop are combined to realize high-performance indicators such as fast locking, high precision and low phase noise, which are suitable for application scenes with high requirements for frequency synthesis, clock recovery and signal demodulation.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of PLL, in particular to a wide dynamic range high-performance low-phase-noise PLL. BACKGROUND

[0002] PLL (Phase-Locked Loop) is a technology that achieves frequency and phase synchronization through feedback control. It can multiply, divide or adjust the phase of the input reference clock signal to output a stable and accurate clock signal. In MCUs, the clock signal is the basis for system operation, which determines the operation speed of the MCU, the working frequency of the peripheral device and the overall performance of the system. Therefore, PLL plays a crucial role in MCU, which can provide a stable and accurate clock source for MCU.

[0003] The demand for wide dynamic range frequency synthesis in high-performance electronic systems, especially in communication, signal processing and microcontroller (MCU) application scenarios. MCU needs accurate frequency control to support clock management of high-speed processors, while considering low power consumption, wide frequency range adjustment and low phase noise requirements.

[0004] However, in traditional PLL design, it is usually difficult to balance between wide frequency adjustment range and low power consumption, low phase noise. Common problems in existing technology include: limited frequency adjustment range, high phase noise, high power consumption, poor dynamic response. Especially when high-frequency and low-frequency signals need to be supported at the same time, traditional PLL is difficult to achieve high flexibility and low power consumption compatibility. SUMMARY

[0005] To solve the problems of limited frequency adjustment range, high phase noise, high power consumption, poor dynamic response, and difficulty in achieving high flexibility and low power consumption compatibility in existing PLL design, a wide dynamic range high-performance low-phase-noise PLL is provided, which includes: a high-speed loop and a low-speed loop, the high-speed loop and the low-speed loop are connected in parallel;

[0006] The low-speed loop includes a second frequency divider, which is configured to receive a reference signal, and output a low-frequency voltage signal after frequency division processing of the reference signal;

[0007] The high-speed loop includes a phase detector, a charge pump, a loop filter, a first frequency divider and a ring voltage-controlled oscillator;

[0008] The output end of the phase detector is connected to the input end of the charge pump, the output end of the charge pump is connected to the input end of the loop filter, and the output end of the loop filter is connected to the input end of the ring voltage-controlled oscillator;

[0009] The phase detector is configured to receive the reference signal and the feedback signal, output a control signal to the charge pump according to a phase difference between the reference signal and the feedback signal, the control signal being a voltage signal containing phase error information;

[0010] The charge pump is configured to receive the control signal, and control the flow direction and size of the current according to the control signal, and output a current pulse to the loop filter;

[0011] The loop filter is configured to receive the current pulse, filter the current pulse, and output a control voltage signal to the ring voltage-controlled oscillator;

[0012] The input end of the first frequency divider is connected to the output end of the ring voltage-controlled oscillator, and the output end of the first frequency divider is connected to the input end of the phase detector;

[0013] The first frequency divider is configured to accept the high-frequency feedback signal, perform frequency division processing on the high-frequency feedback signal to obtain a low-frequency feedback signal, and output the feedback signal to the phase detector;

[0014] The ring voltage-controlled oscillator includes an input voltage conversion circuit, a 4-Tap delay unit, and an output voltage conversion circuit;

[0015] The input end of the input voltage conversion circuit is connected to the output end of the loop filter, the output end of the input voltage conversion circuit is connected to the input end of the 4-Tap delay unit, and the output end of the 4-Tap delay unit is connected to the input end of the output voltage conversion circuit;

[0016] The input voltage conversion circuit is configured to receive the control voltage signal and convert the control voltage signal into two signals, and output the two signals to the 4-Tap delay unit;

[0017] The 4-Tap delay unit is configured to receive the two signals, adjust the delay according to the two signals, and output a CML signal of a corresponding frequency to the output voltage conversion circuit;

[0018] The output voltage conversion circuit is configured to receive the CML signal, convert the CML signal into a CMOS signal, and output a high-frequency feedback signal voltage.

[0019] In a possible implementation, the frequency division ratio coverage range of the first frequency divider is 9-767, and the step of the first frequency divider is 1.

[0020] In a possible implementation, the frequency division ratio coverage range of the second frequency divider is 2-15, and the step of the second frequency divider is 1.

[0021] In an implementation, the phase detector comprises two D flip-flops and a multi-stage delay unit;

[0022] The input terminals of the two D flip-flops are connected to the output terminals of the reference clock and the feedback clock respectively;

[0023] The output terminals of the two D flip-flops are connected to the input terminal of the multi-stage delay unit, and the output terminal of the multi-stage delay unit is connected to the input terminal of the charge pump;

[0024] The two D flip-flops are configured to receive the reference signal and the feedback signal respectively, process to obtain an initial control signal, and output the initial control signal to the multi-stage delay unit and the charge pump;

[0025] The multi-stage delay unit is configured to perform delay processing after receiving the initial control signal to avoid dead zone effect of the phase detector.

[0026] In an implementation, the control signal comprises a high-frequency error component and a low-frequency control voltage component;

[0027] The loop filter is further configured to remove the high-frequency error component in the current pulse and retain the low-frequency control voltage component.

[0028] In an implementation, the two signals comprise a first signal and a second signal;

[0029] The first signal is configured to adjust the load resistance value of the 4-Tap delay unit to adjust the delay time of the delay unit;

[0030] The second signal is configured to adjust the current size of the tail current source of the 4-Tap delay unit to adjust the delay time of the delay unit.

[0031] In an implementation, the charge pump comprises a current mirror and a CMOS switch;

[0032] The input terminal of the CMOS switch is connected to the output terminals of the two D flip-flops;

[0033] The current mirror is configured to provide different size current sources according to preset parameters, adjust the current according to the opening and closing of the CMOS switch, and output the current to the loop filter;

[0034] The CMOS switch is configured to receive the control signal and open or close the current path according to the control signal to form the current pulse and output the current pulse to the loop filter.

[0035] In a possible implementation, the charge pump further includes a full swing operational amplifier.

[0036] The input positive terminal of the full swing operational amplifier is connected to the output terminal of the current mirror, the output terminal of the swing operational amplifier is connected to the input negative terminal of the full swing operational amplifier, and the output terminal of the swing operational amplifier is further connected to the source level of the two CMOS switches, and the full swing operational amplifier is configured to reduce the current mismatch.

[0037] In a possible implementation, the output voltage conversion circuit includes a five-tube operational amplifier and a multi-stage buffer.

[0038] The five-tube operational amplifier is configured to amplify the output differential signal of the delay unit.

[0039] The multi-stage buffer is configured to convert the CMOS signal output by the five-tube operational amplifier into a CML signal.

[0040] In a possible implementation, the current of the charge pump is 3-bit adjustable, and the current range is 40uA to 320uA; the loop filter is a second-order passive low-pass filter, the resistance of the loop filter is 3-bit adjustable, and the capacitance of the loop filter is 2-bit adjustable.

[0041] The wide dynamic range high-performance low-phase noise PLL provided in the application can reduce the phase noise of the PLL and improve the purity and stability of the output signal by optimizing the design and parameter selection of the loop filter and using a high-performance ring voltage-controlled oscillator. It can achieve a super large frequency adjustment range, thereby improving the flexibility of the system and adapting to different frequency requirements and working scenarios. The loop parameters of the PLL have a multi-gear adjustment function, which can ensure the stability of the loop while maintaining high KVCO characteristics, optimize dynamic performance, and provide smooth frequency response especially during fast frequency switching. At the same time, the advantages of high-speed loop and low-speed loop are combined to achieve high-performance indicators such as fast locking, high precision and low phase noise, which are suitable for application scenarios with high requirements for frequency synthesis, clock recovery and signal demodulation. BRIEF DESCRIPTION OF DRAWINGS

[0042] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments consistent with the present application and, together with the description, further serve to explain the principles of embodiments of the application. It is to be understood that the figures are merely schematic representations of some embodiments of the application, and that the present application as described below can be applied to other embodiments that will be apparent to those of ordinary skill in the art without departing from the scope of the present application.

[0043] Figure 1 is a structural schematic diagram of a wide dynamic range high performance low phase noise PLL according to an example embodiment of the present application;

[0044] Figure 2 is a structural schematic diagram of a ring voltage controlled oscillator according to another example embodiment of the present application;

[0045] Figure 3 is a parameter diagram of KVCO obtained based on system simulation and performance test on Cadence Virtuoso platform according to an example embodiment of the present application;

[0046] Figure 4 is a parameter diagram of phase noise obtained based on system simulation and performance test on Cadence Virtuoso platform according to an example embodiment of the present application. DETAILED DESCRIPTION

[0047] Example implementations will now be described more fully with reference to the accompanying drawings. Example implementations can be implemented in any number of ways, and are not limited to the examples described herein. Rather, examples of implementations are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example implementations to those skilled in the art. The described features, structures, or characteristics can be combined in any suitable manner in one or more implementations. In the following description, numerous specific details are provided to give a thorough understanding of implementations of the present application.

[0048] For MCUs, accurate frequency control is the core of its clock management system. MCUs need to support the operation of high-speed processors while maintaining low power consumption to prolong battery life. The wide frequency range adjustment capability enables MCUs to flexibly adjust the clock frequency in different working modes, optimizing the balance between performance and power consumption. In addition, low phase noise is crucial for reducing system interference and maintaining data integrity. However, traditional phase-locked loop (PLL) designs often face a difficult trade-off between wide frequency adjustment range and low power consumption, low phase noise. Traditional PLLs usually use fixed loop parameters and filter designs, which limit their frequency adjustment range. In order to widen the frequency range, additional circuit elements or adjustment of loop parameters may be needed, but this often leads to an increase in power consumption and deterioration of phase noise.

[0049] To solve the above problems, the application provides a wide dynamic range high performance low phase noise PLL, referring to Figure 1 As shown in the figure, it comprises a high-speed loop and a low-speed loop, and the high-speed loop and the low-speed loop are connected in parallel.

[0050] The low-speed loop comprises a second frequency divider; the second frequency divider is configured to receive a reference signal and output a low-frequency voltage signal after frequency division processing of the reference signal.

[0051] As the core component of the low-speed loop, the second frequency divider is responsible for receiving a stable reference signal (usually from an external crystal oscillator or a high-precision clock source). By frequency division processing of the reference signal, it generates a lower frequency output voltage. The design of the low-speed loop is simple, small in area and low in power consumption, which is helpful for the low-power design of the overall system.

[0052] The high-speed loop comprises a phase detector, a charge pump, a loop filter, a first frequency divider and a ring voltage-controlled oscillator; the output end of the phase detector is connected to the input end of the charge pump, the output end of the charge pump is connected to the input end of the loop filter, and the output end of the loop filter is connected to the input end of the ring voltage-controlled oscillator.

[0053] The phase detector is configured to receive a reference signal and a feedback signal, and output a control signal to the charge pump according to the phase difference between the reference signal and the feedback signal, the control signal being a voltage signal or a current signal containing phase error information.

[0054] The phase detector is a key component in the PLL, responsible for comparing the phase difference between the reference signal and the high-frequency feedback signal from the ring voltage-controlled oscillator. According to the size and direction of the phase difference, the phase detector outputs a voltage signal or a current signal containing phase error information to the charge pump. Accurate phase detection is the basis for achieving low phase noise. By adjusting the phase error in real time, the phase detector ensures that the PLL can quickly respond and lock to the target frequency while maintaining low phase noise.

[0055] The charge pump is configured to receive the control signal and control the direction and size of the current according to the control signal, and output current pulses to the loop filter. The charge pump receives the control signal from the phase detector and controls the direction and size of the current according to the control signal. It outputs current pulses to the loop filter, and the current pulses reflect the size and direction of the phase error. The design of the charge pump allows the PLL system to adjust its output frequency in an efficient way to respond to the phase error. By precisely controlling the direction and size of the current, the charge pump helps to achieve fast and stable frequency locking while maintaining low power consumption.

[0056] The loop filter is configured to receive the current pulse, filter the current pulse, and output a control voltage signal to the ring voltage-controlled oscillator. The loop filter receives the current pulse from the charge pump and filters the current pulse to remove high-frequency noise and interference. The filtered signal is converted into a control voltage signal, which is then sent to the ring voltage-controlled oscillator. The loop filter ensures the stability and accuracy of the control voltage signal, thereby improving the stability and precision of the output frequency of the PLL.

[0057] The input end of the first frequency divider is connected to the output end of the ring voltage-controlled oscillator, and the output end of the first frequency divider is connected to the input end of the phase detector. The first frequency divider is configured to accept the high-frequency feedback signal, divide the high-frequency feedback signal to obtain a low-frequency feedback signal, and output the feedback signal to the phase detector.

[0058] In high-speed mode, the frequency division ratio can be adjusted through the first frequency divider, allowing flexible adjustment of the output frequency to meet different application requirements. For example, in a communication system, different operating frequencies may be required to support different communication standards or frequency bands.

[0059] The ring voltage-controlled oscillator includes an input voltage conversion circuit, a multi-stage delay unit, and an output voltage conversion circuit. The input end of the input voltage conversion circuit is connected to the output end of the loop filter, the output end of the input voltage conversion circuit is connected to the input end of the multi-stage delay unit, and the output end of the multi-stage delay unit is connected to the input end of the output voltage conversion circuit.

[0060] Specifically, referring to Figure 2 The ring voltage-controlled oscillator of the present application is a dual-tunable 4-Tap cross-coupled Ring VCO, combining the cross-coupled technology and the structure of Ring VCO, and having the characteristics of dual-tunable. Ring VCO is usually composed of multiple delay units in cascade to form a ring oscillator. This structure makes Ring VCO have higher frequency stability and better phase noise performance. Cross-coupled technology is to obtain large gain by using cross-coupled transistor pairs in the voltage-controlled oscillator, and to obtain high frequency output range. This technology helps to improve the oscillation stability and frequency adjustment range of the voltage-controlled oscillator.

[0061] 4-Tap means that four taps are set in the feedback path of the Ring VCO, each of which can be used as an output or for frequency adjustment. This structure provides more frequency adjustment points, making the frequency adjustment of the voltage-controlled oscillator more flexible and accurate. Dual-tunable means that the voltage-controlled oscillator has two independent control inputs, which can adjust the frequency of the voltage-controlled oscillator respectively. This is usually achieved by changing the gate voltage of the cross-coupled transistor pair and the value of the tail current source.

[0062] When the power is turned on, the delay cells in the Ring VCO start to work and form a ring oscillator. The cross-coupled transistor pair provides negative resistance to compensate for energy loss during oscillation, thereby maintaining stable oscillation. By changing either or both of the two-path control inputs simultaneously, the gate voltages of the cross-coupled transistor pair or the element values in the Ring VCO can be adjusted, thereby changing the oscillation frequency of the voltage-controlled oscillator. The 4-Tap structure provides multiple frequency adjustment points, making frequency adjustment more accurate and flexible. The output signal of the voltage-controlled oscillator is a sinusoidal wave generated by the ring oscillator, and its frequency is determined by the two-path control inputs.

[0063] Therefore, the ring voltage-controlled oscillator of the present application can achieve a super large frequency adjustment range, thereby improving the flexibility of the system and being able to adapt to different frequency requirements and working scenarios. The loop parameters of the PLL have a multi-gear adjustment function, which can ensure the stability of the loop while maintaining high KVCO (Voltage-Controlled Oscillator Gain) characteristics, optimize dynamic performance, and especially provide smooth frequency response when the frequency is quickly switched.

[0064] Specifically, in the embodiments of the present application, the input voltage conversion circuit is configured to receive a control voltage signal and convert the control voltage signal into two-path signals, and output the two-path signals to the 4-Tap delay cell; the 4-Tap delay cell is configured to receive the two-path signals, adjust the delay according to the two-path signals, and output a CML signal of a corresponding frequency to the output voltage conversion circuit; and the output voltage conversion circuit is configured to receive the CML signal and output a high-frequency feedback signal voltage after converting the CML signal into a CMOS signal.

[0065] Specifically, the input voltage conversion circuit converts the output voltage of the low-pass filter into two-path signals, and adjusts the load and tail current source of the delay cell, thereby achieving wide frequency adjustment. By adjusting the load and tail current source of the 4-Tap delay cell, the working characteristics of the delay cell, such as delay time and stability, can be affected, thereby achieving wide frequency adjustment. This adjustment mechanism enables the PLL to flexibly adjust the clock frequency in different working modes, optimizing the balance between performance and power consumption.

[0066] In some embodiments of the present application, the two-path signals include a first-path signal and a second-path signal; the first-path signal is configured to adjust the load resistance value of the delay cell to adjust the delay time of the 4-Tap delay cell; and the second-path signal is configured to change the current size of the tail current source of the delay cell to adjust the oscillation characteristics of the 4-Tap delay cell.

[0067] The 4-Tap delay cell receives the signal from the input voltage conversion circuit and performs delay processing to generate a high-frequency oscillation signal. The 4-Tap delay cell adopts an adjustable load structure, which means that its load can be adjusted as needed. This design allows the delay cell to maintain stable performance under different operating conditions while reducing phase noise. By precisely controlling the size of the load, the delay time and phase noise performance of the 4-Tap delay cell can be optimized. The first signal is used to adjust the delay time of the 4-Tap delay cell by adjusting the load resistance value of the delay cell. Changes in load resistance affect the flow of current in the circuit, which in turn affects the time it takes for the signal to pass through the delay cell.

[0068] The tail current source is a component in the delay cell that provides operating current. By changing the current size of the tail current source, the oscillation characteristics of the delay cell can be adjusted. This includes parameters such as oscillation frequency, amplitude, and phase. The second signal is used to expand the dynamic range of the delay cell by adjusting the current size of the tail current source. This means that the delay cell can maintain stable performance over a wider frequency range, making it suitable for different application scenarios. Proper selection of tail current source current size can also help manage the power consumption of the delay cell. In applications requiring low power consumption, power consumption can be reduced by reducing the current size of the tail current source; while in applications requiring high performance, performance can be improved by increasing the current size of the tail current source.

[0069] The 4-Tap delay cell also reduces phase noise by maintaining symmetry of rising and falling edges. This symmetry helps reduce distortion and interference in the signal during transmission, thereby improving the output quality of the PLL. The delay cell receives the signal from the input voltage conversion circuit and performs delay processing to generate a high-frequency oscillation signal. The main function of the output circuit is to convert the CML (non-full swing voltage) signal output by the delay cell into a CMOS (full swing voltage) signal, and then output a high-frequency feedback signal and an output voltage. This conversion process ensures signal compatibility and stability. The design of the ring voltage-controlled oscillator allows the PLL to flexibly adjust the output frequency over a wide frequency range while maintaining low phase noise and low power consumption. By optimizing the design of the delay cell and voltage conversion circuit, the ring voltage-controlled oscillator can efficiently respond to changes in the control voltage signal, thereby achieving fast and stable frequency locking.

[0070] The wide dynamic range high-performance low phase noise PLL proposed in the application balances between wide frequency regulation range, low power consumption and low phase noise by combining the design of low-speed loop and high-speed loop. The low-speed loop provides a stable reference for the system, while the high-speed loop ensures that the PLL can quickly respond and lock to the target frequency while maintaining low phase noise and low power consumption through precise phase detection, efficient charge pump control, stable loop filtering and flexible ring voltage-controlled oscillator design. This design not only solves the contradiction between wide frequency regulation range and low power consumption, low phase noise of traditional PLL, but also provides a more flexible, efficient and reliable clock management solution for embedded systems such as MCUs.

[0071] In some embodiments of the application, the frequency division ratio coverage range of the first frequency divider is 9-767, and the step of the first frequency divider is 1.

[0072] The first frequency divider in the embodiments of the application provides a wide range of frequency division selection, enabling the system to work in different frequency ranges. When the PLL selects the high-speed loop, the output frequency range covers 100MHz-1GHz, the integer frequency divider frequency division ratio covers 9-767, and the frequency divider step is 1. In this mode, the total power consumption is less than 6mW when the output frequency is 400M, and the phase noise @1MHz is -105.35dBc / Hz, which is suitable for high-frequency application scenarios such as MCU main clock generation, wireless communication equipment, FPGA high-speed interface, network router synchronization clock, etc. By adjusting the frequency division ratio with a step of 1, the output frequency can be accurately controlled, improving the frequency resolution and stability of the system.

[0073] In some embodiments of the application, the frequency division ratio coverage range of the second frequency divider is 2-15, and the step of the second frequency divider is 1.

[0074] Specifically, when the PLL selects the low-speed loop, the high-speed loop is turned off. In the low-speed mode, the second frequency divider receives a high-frequency reference signal, and the second frequency divider can reduce the frequency of the input signal to between 1 / 2 and 1 / 15 of the original frequency. After frequency division processing on the reference signal, a lower frequency voltage signal is output. The output frequency range covers 200KHz-1MHz, and the integer frequency divider frequency division ratio covers 2-15. In this mode, the total power consumption is less than 50uW, which is suitable for low-frequency application scenarios. In order to reduce power consumption, all loops in the high-speed mode are turned off in the low-speed mode, and the reference clock is directly frequency-divided and output, which is suitable for clock management in low-power mode of MCU.

[0075] The frequency division ratio can be finely adjusted in units of 1, thereby providing high flexibility and resolution, and providing multiple frequency division options for the system, enabling the system to adjust in different frequency ranges with different steps. This increases the flexibility and adaptability of the system.

[0076] In some embodiments of the present application, the phase detector comprises two D flip-flops and a multi-stage delay unit; the input terminals of the two D flip-flops are respectively connected to the output terminals of the reference clock and the feedback clock; the output terminals of the two D flip-flops are both connected to the input terminal of the multi-stage delay unit, and the output terminal of the multi-stage delay unit is connected to the input terminal of the charge pump.

[0077] The two D flip-flops are configured to respectively receive the reference signal and the feedback signal, process to obtain an initial control signal, and output the initial control signal to the multi-stage delay unit; the multi-stage delay unit is configured to perform delay processing after receiving the initial control signal to avoid the dead zone effect of the phase detector.

[0078] The two D flip-flops respectively receive the reference signal and the feedback signal. These signals are usually from different clock sources, such as the output of the reference clock and the output of the ring voltage-controlled oscillator after frequency division.

[0079] The D flip-flops generate initial control signals according to the received signals. These signals contain information about the phase difference between the reference signal and the feedback signal. The multi-stage delay unit receives the initial control signals from the two D flip-flops and performs delay processing. The charge pump adjusts the control voltage of the ring voltage-controlled oscillator according to the received control signal, thereby changing the output frequency of the ring voltage-controlled oscillator to achieve phase locking or frequency matching.

[0080] In some embodiments of the present application, the control signal includes a high-frequency error component and a low-frequency control voltage component; the loop filter is further configured to remove the high-frequency error component in the current pulse and retain the low-frequency control voltage component.

[0081] The high-frequency error component is usually the high-frequency component in the control signal output by the phase detector, which may be caused by noise, interference or non-ideal factors in the phase detection process. The low-frequency control voltage component reflects the real phase difference between the reference signal and the feedback signal, which is the target that the system needs to adjust and lock. The loop filter is designed to have low-pass filtering characteristics, i.e. to allow low-frequency signals to pass while blocking high-frequency signals. Therefore, it can effectively remove the high-frequency error component in the control signal. While removing the high-frequency error component, the loop filter ensures that the low-frequency control voltage component is retained.

[0082] By removing the high-frequency error component, the loop filter can reduce the impact of external noise and interference on system performance. Retaining the low-frequency control voltage component helps the system more accurately adjust the output frequency of the ring voltage-controlled oscillator, thereby achieving stable phase locking. In a frequency synthesizer, this configuration of the loop filter helps generate a more accurate and stable output frequency.

[0083] In some embodiments of the present application, the charge pump comprises: a current mirror and a CMOS switch; the input end of the CMOS switch is connected to the output end of the two D flip-flops; the CMOS switch is configured to receive the control signal and open or close the current path according to the control signal to form a current pulse and output the current pulse to the loop filter; the current mirror is configured to provide different sizes of current sources according to preset parameters, adjust the current according to the opening and closing of the CMOS switch, and output the current to the loop filter.

[0084] The CMOS switch receives control signals from the multi-stage delay unit. These signals contain information about the phase difference between the reference signal and the feedback signal. The current mirror adjusts the size of the current it outputs according to the input gear.

[0085] If the loop bandwidth needs to be increased, the current mirror will increase the output current; if the loop bandwidth needs to be reduced, the current mirror will reduce the output current.

[0086] The CMOS switch opens or closes the current path according to the control signal. When the switch is open, the current provided by the current mirror will pass through the CMOS switch and form a current pulse; when the switch is closed, the current path is cut off and the current pulse ends. The generated current pulse is then sent to the loop filter for filtering processing. The loop filter removes the high-frequency components in the current pulse and retains the low-frequency components, and uses the filtered signal to adjust the control voltage of the ring voltage-controlled oscillator.

[0087] In this embodiment, the charge pump can quickly respond to changes in the control signal and generate corresponding current pulses to adjust the output frequency of the ring voltage-controlled oscillator. By adjusting the current size and switch state, the charge pump can achieve precise control of the output frequency of the ring voltage-controlled oscillator. The cooperative work of the charge pump and the loop filter helps to ensure the stability of the system.

[0088] In some embodiments of the present application, the charge pump further comprises: a full swing operational amplifier; the output end of the current mirror is connected to the input positive end of the full swing operational amplifier, the output end of the swing operational amplifier is connected to the input negative end of the full swing operational amplifier, and the output end of the swing operational amplifier is also connected to the source stage of the two CMOS switches; the full swing operational amplifier is configured to reduce current mismatch.

[0089] The full swing operational amplifier adjusts its output as needed to clamp the source voltage of the CMOS switches on both sides by monitoring the voltage signal output by the current mirror. This helps to reduce current mismatch and improve the stability and performance of the charge pump.

[0090] In some embodiments of the present application, the output voltage conversion circuit includes a five-tube operational amplifier and a multi-stage buffer. The five-tube operational amplifier is configured to amplify the delay signal, and the multi-stage buffer is configured to buffer the delay signal.

[0091] The operational amplifier is typically based on a structure with differential input and single-ended output, and through internal circuit adjustment and gain setting, it can amplify the input signal. The five-tube operational amplifier adopts a specific circuit design to ensure the best amplification effect on the delay signal. The amplification function of the five-tube operational amplifier helps to increase the strength of the signal and can be applied in scenarios that require processing of weak signals or long-distance transmission of signals.

[0092] The multi-stage buffer is typically composed of multiple buffer units cascaded together, each of which can amplify and shape the input signal to a certain extent. By cascading multiple buffer units, multiple amplification and shaping of the input signal can be achieved, thereby improving the stability and reliability of the signal. The buffering function of the multi-stage buffer helps to reduce the loss and interference of the signal during transmission.

[0093] In some embodiments of the present application, the current is 3-bit adjustable, and the current range is 40uA to 320uA; the loop filter is a second-order passive low-pass filter, the resistance of the loop filter is 3-bit adjustable, and the capacitance of the loop filter is 2-bit adjustable.

[0094] Specifically, the current can be adjusted within the range of 40uA to 320uA with a certain step size. Since the current is 3-bit adjustable, it can have 2^3=8 different settings. Considering that the current range is from 40uA to 320uA, it can be inferred that the step size of the current is (320uA-40uA) / 7=40uA (assuming the current is equally spaced). Therefore, the current can be set to any value of 40uA, 80uA, 120uA, 160uA, 200uA, 240uA, 280uA, or 320uA.

[0095] A second-order passive low-pass filter is a circuit used to filter out high-frequency noise and allow low-frequency signals to pass. In this embodiment, both the resistance and capacitance of the filter are adjustable, which allows for fine-tuning of the cutoff frequency of the filter. Since the resistance is 3-bit adjustable, it can have 2^3 = 8 different settings. This allows for some degree of adjustment of the impedance and frequency response of the filter. The capacitance is 2-bit adjustable, so it can have 2^2 = 4 different settings. Adjustment of the capacitance can further affect the cutoff frequency and phase response of the filter.

[0096] It can be understood that the cutoff frequency of the loop filter is the point at which the filter begins to significantly attenuate the input signal frequency. In a second-order passive low-pass filter, the cutoff frequency depends on the values of resistance and capacitance. Since both resistance and capacitance are adjustable, the cutoff frequency is also adjustable. By adjusting the values of resistance and capacitance, fine control of the cutoff frequency can be achieved, thereby optimizing the performance of the filter to meet the needs of a particular application.

[0097] To verify the performance of the system, system simulation and performance testing were carried out based on the Cadence Virtuoso platform. The scanning parameters obtained KVCO, as shown in Figure 3 and Figure 4 By Pss (i.e. Periodic Steady State) and Pnoise (Phase Noise) simulation, the phase noise power spectrum density of the ring voltage-controlled oscillator can be obtained. The frequency range of the ring voltage-controlled oscillator is 2MHz to 1.02GHz, and multiple process angles are analyzed, and the results show that the frequency range can reach more than 900MHz. The power consumption at 400MHz is 5.89mW, and the phase noise @1MHz = -106.12dBc / Hz.

[0098] The simulation obtained the phase noise power spectrum density of each module, and then the simulation data was imported into MATLAB to calculate the transfer function of each module to the PLL output. According to these transfer functions, the contribution of each module to the phase noise power spectrum density of the PLL output can be determined. By superimposing the phase noise power spectrum density contributed by each module, the phase noise power spectrum density of the entire PLL is finally obtained, and the phase noise @1MHz = -105.35dBc / Hz.

[0099] Referring to Table 1, which shows the key performance parameters of the PLL in the frequency range from 200 MHz to 1 GHz. As the frequency increases, the bandwidth, phase margin, and lock-in time of the PLL remain stable, ensuring the stability and fast response of the system. At the same time, the ripple value increases slightly, but still maintains a low level, indicating the high accuracy of the output signal. The power consumption shows a linear growth trend as the frequency rises, indicating that the increase in power consumption at high frequencies is expected. Overall, the PLL exhibits excellent stability and energy efficiency in a wide frequency range, making it suitable for applications that require high performance and low power consumption.

[0100] Table 1 Performance parameter analysis of PLL at different frequencies

[0101] FRE Loop bandwidth Phase margin Lock time (us) Ripple (mV) Power consumption (mW) 200M 186.87k 60.98° 14.5 0.15 2.42 400M 186.87k 60.98° 15.2 0.18 5.89 600M 171.68k 62.41° 16.6 0.16 6.76 800M 191.72k 60.23° 15.1 0.25 8.23 1G 208.12k 59.67° 15.6 0.28 10.12

[0102] From the above embodiment content, the wide dynamic range high performance low phase noise PLL of the application can select high speed mode or low speed mode according to application requirements.

[0103] In high speed mode, the frequency division ratio of the integer frequency divider is configured to ensure that the output frequency is between 100 MHz and 1 GHz, and the frequency divider step is 1 to meet the accuracy requirements of high frequency application scenarios. In high speed mode, the PLL compares the phase difference between the reference signal and the feedback signal through the phase detector to generate an error signal. After filtering by the loop filter, the frequency of the ring voltage-controlled oscillator is controlled to make the output clock and the reference clock keep synchronization, and the phase difference is minimized. During the adjustment process, the second frequency divider divides the high frequency feedback signal to obtain the feedback signal to match the frequency range of the reference signal.

[0104] In high speed mode, the PLL ensures the high accuracy and stability of the output clock through accurate phase detection and frequency adjustment. It is crucial for high frequency application scenarios such as MCU main clock generation, radio frequency circuit of wireless communication equipment, etc., which can reduce clock jitter and phase noise, and improve the performance and stability of the system.

[0105] In low speed mode, the frequency division ratio of the integer frequency divider is configured to make the output frequency between 200 KHz and 1 MHz, suitable for low power consumption and low frequency application scenarios. In low speed mode, in order to reduce power consumption, the PLL closes the phase detector, loop filter and ring voltage-controlled oscillator circuit in the high speed loop. Directly use the first frequency divider to divide the reference clock to output the required low frequency signal.

[0106] In low speed mode, the PLL significantly reduces power consumption by closing part of the circuit in the high speed loop. This makes the PLL more advantageous in low power consumption devices such as MCUs, which can ensure clock accuracy while reducing power consumption.

[0107] The PLL outputs a stable clock signal, which is used to drive the main clock of the MCU, the radio frequency circuit of the wireless communication device, the high-speed interface of the FPGA, or the synchronous clock of the network router, etc. The PLL supports both high-speed and low-speed modes, which can be flexibly configured according to application requirements. This makes the PLL widely applicable to various scenarios, such as wireless communication, FPGA, network router, etc., to meet the clock requirements of different devices.

[0108] The loop parameters of the PLL have a multi-gear adjustment function, which enables it to maintain high KVCO characteristics while ensuring the stability of the loop, optimizing the dynamic performance, and providing a smooth frequency response especially during fast frequency switching. At the same time, it combines the advantages of high-speed and low-speed loops, achieving high-performance indicators such as fast locking, high precision, and low phase noise, and is suitable for application scenarios with high requirements for frequency synthesis, clock recovery, and signal demodulation, etc.

[0109] Other embodiments of the present disclosure will be readily apparent to those skilled in the art upon considering the disclosure herein, particularly the description and embodiments. The present application is intended to cover any variations, uses, or adaptations of the present disclosure that follow, in general, the principles of the present disclosure and include other known ins and customary technical practices not specifically disclosed in the present disclosure.

Claims

1. A wide dynamic range high performance low phase noise PLL characterized in that, The application relates to a phase-locked loop circuit. The phase-locked loop circuit comprises a high-speed loop and a low-speed loop, wherein the high-speed loop is connected in parallel with the low-speed loop. The low-speed loop comprises a second frequency divider. The second frequency divider is configured to receive a reference signal, divide the reference signal, and output a low-frequency voltage signal. The high-speed loop comprises a phase detector, a charge pump, a loop filter, a first frequency divider, and a ring voltage-controlled oscillator. An output end of the phase detector is connected to an input end of the charge pump, an output end of the charge pump is connected to an input end of the loop filter, and an output end of the loop filter is connected to an input end of the ring voltage-controlled oscillator. The phase detector is configured to receive the reference signal and a feedback signal, output a control signal to the charge pump according to a phase difference between the reference signal and the feedback signal, and the control signal is a voltage signal containing phase error information. The charge pump is configured to receive the control signal, control the flow direction and size of a current according to the control signal, and output a current pulse to the loop filter. The loop filter is configured to receive the current pulse, filter the current pulse, and output a control voltage signal to the ring voltage-controlled oscillator. An input end of the first frequency divider is connected to an output end of the ring voltage-controlled oscillator, and an output end of the first frequency divider is connected to an input end of the phase detector. The first frequency divider is configured to receive a high-frequency feedback signal, divide the high-frequency feedback signal, obtain a low-frequency feedback signal, and output the feedback signal to the phase detector. The ring voltage-controlled oscillator comprises an input voltage conversion circuit, a 4-Tap delay unit, and an output voltage conversion circuit. An input end of the input voltage conversion circuit is connected to an output end of the loop filter, an output end of the input voltage conversion circuit is connected to an input end of the 4-Tap delay unit, and an output end of the 4-Tap delay unit is connected to an input end of the output voltage conversion circuit. The input voltage conversion circuit is configured to receive the control voltage signal, convert the control voltage signal into two signals, and output the two signals to the 4-Tap delay unit. The 4-Tap delay unit is configured to receive the two signals, adjust the delay according to the two signals, and output a CML signal of a corresponding frequency to the output voltage conversion circuit. The output voltage conversion circuit is configured to receive the CML signal, convert the CML signal into a CMOS signal, and output a high-frequency feedback signal voltage.

2. The wide dynamic range high performance low phase noise PLL of claim 1, wherein, The frequency division ratio coverage range of the first frequency divider is 9-767, and the step of the first frequency divider is 1.

3. The wide dynamic range high performance low phase noise PLL of claim 1, wherein, The frequency division ratio coverage range of the second frequency divider is 2-15, and the step of the second frequency divider is 1.

4. The wide dynamic range high performance low phase noise PLL of claim 1, wherein, The phase detector comprises two D flip-flops and a multi-stage delay unit. Input ends of the two D flip-flops are respectively connected to output ends of a reference clock and a feedback clock. Output ends of the two D flip-flops are connected to an input end of the multi-stage delay unit, and an output end of the multi-stage delay unit is connected to an input end of the charge pump. The two D flip-flops are configured to: respectively receive the reference signal and the feedback signal, process them to obtain an initial control signal, and output the initial control signal to the multi-stage delay unit and the charge pump; The multi-stage delay unit is configured to perform delay processing after receiving the initial control signal to avoid a dead zone effect of the phase detector.

5. The wide dynamic range high performance low phase noise PLL of claim 2, wherein, The control signal includes: a high-frequency error component and a low-frequency control voltage component; The loop filter is further configured to remove the high-frequency error component in the current pulse and retain the low-frequency control voltage component.

6. The wide dynamic range high performance low phase noise PLL of claim 1, wherein, The two signals include: a first signal and a second signal; The first signal is configured to: adjust the load resistance value of the 4-Tap delay unit to adjust the delay time of the delay unit; The second signal is configured to adjust the current of the tail current source of the 4-Tap delay unit to adjust the delay time of the delay unit.

7. The wide dynamic range high performance low phase noise PLL of claim 4, wherein, The charge pump includes: a current mirror and a CMOS switch; The input end of the CMOS switch is connected to the two output ends of the D flip-flop; The CMOS switch is configured to: receive the control signal, and open or close the current path according to the control signal to form the current pulse, and output the current pulse to the loop filter; The current mirror is configured to provide current sources of different magnitudes according to preset parameters, adjust the current according to the opening or closing of the CMOS switch, and output the current to the loop filter.

8. The wide dynamic range high performance low phase noise PLL of claim 5, wherein, The charge pump further includes: a rail-to-rail operational amplifier; The positive input terminal of the full-swing operational amplifier is connected to the output terminal of the current mirror, the output terminal of the swing operational amplifier is connected to the negative input terminal of the full-swing operational amplifier, and the output terminal of the swing operational amplifier is also connected to the source stages of two CMOS switches. The full-swing operational amplifier is configured to reduce the current mismatch.

9. The wide dynamic range high performance low phase noise PLL of claim 1, wherein, The output voltage conversion circuit includes a five-transistor operational amplifier and a multi-stage buffer; The five-tube operational amplifier is configured to: amplify the output differential signal of the delay unit; The multi-stage buffer is configured to convert the output signal of the five-transistor operational amplifier from a CML signal to a CMOS signal.

10. The wide dynamic range high performance low phase noise PLL of any of claims 1-9, wherein, The current of the charge pump is 3-bit adjustable, and the current range is 40uA to 320uA; the loop filter is a second-order passive low-pass filter, the resistance of the loop filter is 3-bit adjustable, and the capacitance of the loop filter is 2-bit adjustable.

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