Communication system and transceiver and contact cleaning method for use therein

Abstract

A communication system and transceiver and a contact cleaning method for use therein. One example is disclosed a transceiver circuit that includes circuitry for cleaning oxidation from an input pin and an output pin. During a first phase of the cleaning operation, the first cleaner circuit may maintain the floating input pin at a voltage level less than a cleaning voltage that is greater than the operating supply voltage. During a second phase of the cleaning operation, the first cleaner circuit may couple the input pins to a ground supply node. During the first phase of the cleaning operation, a second cleaner circuit may couple the output pins to the cleaning voltage. During the second phase of the cleaning operation, the second cleaner circuit may supply respective currents to the output pins.

Description

Technical Field

[0001] The present disclosure relates to communication systems, and more particularly to cleaning oxides from connectors, and even more particularly to cleaning connectors for differential buses. Background Art

[0002] In some applications, parts of an electrical or computer system may be coupled together using multiple signal lines. Such signal lines may be coupled to the components of the electrical or computer system using a two-part connector, wherein a first part of the connector is inserted into a second part of the connector to form an electrical connection.

[0003] Exposure to air, water, etc. can cause oxides to form at the interface between the first and second portions of the connector. The oxides can increase the impedance between the first portion of the connector and the second portion of the connector, making it difficult for electrical signals to be transmitted through the connector, which can cause malfunctions in electrical or computer systems. To limit the formation of oxides, some connectors are made of materials that resist oxidation, such as gold. Summary of the invention

[0004] Various embodiments of transceiver circuits including cleaning circuits are disclosed. Broadly speaking, a transceiver circuit may include a logic block and a receiver circuit that may be configured to receive data via a plurality of receiver pins and send the received data to the circuit block. The transceiver circuit may also include a first cleaner circuit that may be configured to maintain a floating receiver pin of the plurality of receiver pins at a corresponding voltage level less than a cleaning voltage during a first phase of the cleaning mode in response to activation of a cleaning mode. The first cleaner circuit may be further configured to couple the plurality of receiver pins to a ground supply node using a second phase of the cleaning mode.

[0005] In another embodiment, the transceiver circuit may further include a transmitter circuit that may be configured to receive transmit data from the logic block and transmit the transmit data via a plurality of transmit pins. The transceiver circuit may further include a second cleaner circuit that may be configured to couple the plurality of transmit pins to the clean voltage greater than the operating supply voltage during the first phase of the clean mode in response to the activation of the clean mode, and to supply corresponding currents to the plurality of transmit pins during the second phase of the clean mode.

[0006] One example is a transceiver device, the transceiver device comprising: a logic circuit; a first circuit cleaner; and a receiver circuit. The receiver circuit can be configured to: receive data via a plurality of receiver pins; and send the received data to the logic circuit. The first cleaner circuit can be configured to maintain a receiver pin of the plurality of receiver pins at a corresponding voltage level during a first phase of the cleaning mode in response to activation of the cleaning mode, wherein the corresponding voltage level is less than a cleaning voltage; and during a second phase of the cleaning mode, couple the plurality of receiver pins to a ground supply node.

[0007] The exemplary transceiver device may also include: a transmitter circuit; and a second cleaner circuit. The transmitter circuit may be configured to: receive transmit data from the logic circuit; and transmit the transmit data via a plurality of transmit pins. The second cleaner circuit may be configured to perform the following operations in response to the activation of the cleaning mode: during the first phase of the cleaning mode, couple the plurality of transmit pins to the clean voltage; and during the second phase of the cleaning mode, supply the corresponding current to the plurality of transmit pins. The logic circuit, the receiver circuit, the transmitter circuit, the first cleaner circuit, and the second cleaner circuit may be included in the transceiver circuit. The first cleaner circuit may be included in the receiver circuit, and the second cleaner circuit may be included in the transmitter circuit. In the exemplary transceiver circuit, in order to couple the plurality of transmit pins to the clean voltage during the second phase of the cleaning mode, the second cleaner circuit may be further configured to activate a plurality of transistors coupled between a power supply node and corresponding transmit pins among the plurality of transmit pins within a predetermined time period, wherein the voltage of the power supply node is the clean voltage.

[0008] In an exemplary transceiver device, the receiver circuit may be configured to receive a plurality of control bits, and wherein the transmitter circuit is configured to relay at least a portion of the plurality of control bits.

[0009] In an exemplary transceiver device, to maintain the receiver pins at the respective voltage levels, the receiver circuit may be further configured to maintain the receiver pins at their respective voltage levels using corresponding transistors of the plurality of diode-connected transistors.

[0010] In an exemplary transceiver device, in order to couple the multiple receiver pins to the ground supply node during the second phase of the cleaning mode, the first cleaner circuit may be further configured to activate multiple transistors coupled between the ground supply node and corresponding receiver pins of the multiple receiver pins in response to receiving a control bit.

[0011] Yet another example is a contact cleaning method comprising: activating a cleaning mode for a transceiver circuit; maintaining, by the transceiver circuit, respective voltage levels of a plurality of receiver pins at corresponding voltage levels less than a cleaning voltage during a first phase of the cleaning mode; and coupling, by the transceiver circuit, the plurality of receiver pins to a ground supply node during a second phase of the cleaning mode, wherein the second phase of the cleaning mode is subsequent to the first phase of the cleaning mode.

[0012] The exemplary method may also include: coupling, by the transceiver circuit, a plurality of transmit pins to the clean voltage during the first phase of the clean mode; and supplying, by the transceiver circuit, corresponding currents to the plurality of transmit pins during the second phase of the clean mode. The exemplary method may also include transmitting at least a portion of a plurality of previously received control bits via the plurality of transmit pins.

[0013] In an exemplary method, coupling the plurality of emission pins to the clean voltage includes activating a plurality of transistors coupled between a high voltage power supply node and corresponding emission pins of the plurality of emission pins for a predetermined period of time, wherein the voltage of the high voltage power supply node is the clean voltage.

[0014] The exemplary method may also include activating, by the transceiver circuitry, the second phase in response to determining that a predetermined period of time has elapsed since activating the first phase.

[0015] The exemplary method may also include maintaining the respective voltage levels of the plurality of receiver pins at corresponding voltage levels less than the clean voltage during the first phase of the clean mode including coupling the plurality of receiver pins to ground via corresponding transistors of a plurality of diode-connected transistors of the transceiver circuit.

[0016] In an exemplary method, coupling the plurality of receiver pins to the ground supply node may include activating a plurality of transistors coupled between the ground supply node and corresponding receiver pins of the plurality of receiver pins in response to receiving a control bit.

[0017] Yet another example is a communication system, the communication system comprising: a plurality of transceiver circuits coupled to a power supply node; and a controller circuit coupled to the plurality of transceiver circuits in a daisy-chain manner. The controller circuit may be configured to: in response to activation of a cleaning mode, perform a first phase of an initial cleaning operation by adjusting a voltage level of the power supply node; in response to determining that a first predetermined time period has passed since the first phase, reset the plurality of transceiver circuits; perform a second phase of the initial cleaning operation by adjusting the voltage level of the power supply node; in response to determining that a second predetermined time has passed since the second phase, reset the plurality of transceiver circuits; and in response to determining that the second phase has been completed, perform a communication check.

[0018] In an exemplary communication system, to adjust the voltage level of the power supply node, the controller circuit may be configured to set the voltage level of the power supply node to a clean voltage level that is greater than an operable voltage level of the plurality of transceiver circuits for non-clean operation. To reset the plurality of transceiver circuits in response to the determination that the first predetermined time period has passed, the controller circuit may be further configured to return the voltage level of the power supply node to the operable voltage level. To perform the second phase, the controller circuit may be further configured to shift control bits through the plurality of transceiver circuits. The controller circuit may be coupled to the plurality of transceiver circuits using corresponding differential communication buses in a plurality of differential communication buses, and wherein a given transceiver circuit in the plurality of transceiver circuits may be configured to activate a low impedance path between an input pin of the given transceiver circuit and a ground supply node, wherein the input pin is coupled to a corresponding line of a specific differential communication bus in the corresponding differential communication buses. To perform the communication check, the controller circuit may be further configured to confirm that the control bits are received from the last transceiver circuit in the plurality of transceiver circuits. The controller circuit may be further configured to perform a second cleaning operation after the initial cleaning operation in response to determining that the communication check has failed. The controller circuit may be further configured to terminate the cleaning mode in response to determining that a predetermined number of cleaning operations have been performed without a successful communication check.

[0019] In an exemplary communication system, a given transceiver circuit of the plurality of transceiver circuits may be coupled to a branch of light emitting diodes (LEDs). BRIEF DESCRIPTION OF THE DRAWINGS

[0020] To describe in detail example embodiments, reference will now be made to the accompanying drawings, in which:

[0021] Figure 1 is a block diagram of an implementation of a transceiver circuit.

[0022] Figure 2is a block diagram of an implementation of a receiver cleaner circuit.

[0023] Figure 3 is a block diagram of an implementation of a transmitter cleaner circuit.

[0024] Figure 4 is a block diagram of an implementation of a system including multiple transceiver circuits coupled together via a communication bus.

[0025] Figure 5 is a block diagram of an implementation scheme of a light emitting diode control system.

[0026] Figure 6 is a flow chart depicting an embodiment of a method for a transceiver circuit to perform a cleaning operation.

[0027] Figure 7 is a flow chart depicting an embodiment of a method for performing a cleaning operation on transceiver circuitry.

[0028] Many electrical connections in the drawings are shown as directly coupled without intervening devices, but are not explicitly described as such in the following description. However, for electrical connections shown in the drawings without intervening devices, this paragraph should serve as an antecedent basis for the claims for referring to any electrical connection as "directly coupled."

[0029] definition

[0030] Various terms are used to refer to specific system components. Different companies may refer to a component by different names - this document is not intended to distinguish between components that differ in name but have the same function. In the following discussion and in the claims, the terms "include" and "comprising" are used in an open-ended manner, and therefore, these terms should be interpreted to mean "including but not limited to...". In addition, the terms "couple" or "couples" are intended to mean either an indirect connection or a direct connection. Thus, if a first device is coupled to a second device, that connection may be made through a direct connection or through an indirect connection via other devices and connections.

[0031] As used herein, "a," "an," and "the" refer to both singular and plural referents, unless the context clearly indicates otherwise. For example, a "processor" programmed to perform various functions refers to one processor programmed to perform each function, or more than one processors collectively programmed to perform each of the various functions. Consistent with the antecedent basis requirements of the claims, later references to "processors" should not negate the fact that the processor may be more than one processor.

[0032] With respect to an electrical device (whether stand-alone or as part of an integrated circuit), the terms "input" and "output" refer to electrical connections to the electrical device and should not be construed as requiring verbs to operate. For example, a differential amplifier (such as an operational amplifier) ​​may have a first differential input and a second differential input, and these "inputs" define electrical connections to the operational amplifier and should not be construed as requiring signal inputs to the operational amplifier.

[0033] "Asserting" shall mean creating or maintaining a first predetermined state of a Boolean signal. At the discretion of the circuit designer, a Boolean signal may be asserted high or with a higher voltage, and a Boolean signal may be asserted low or with a lower voltage. Similarly, "de-asserting" shall mean creating or maintaining a second predetermined state of a Boolean signal that is opposite to the asserted state.

[0034] "FET" shall mean a field effect transistor, such as a junction gate FET (JFET) or a metal oxide semiconductor field effect transistor (MOSFET).

[0035] "Closing" with respect to an electrically controlled switch (eg, a FET) shall mean turning the electrically controlled switch on. For example, closing a FET used as an electrically controlled switch may mean driving the FET to a fully on state.

[0036] "Off" with respect to an electronically controlled switch (eg, a FET) shall mean rendering the electronically controlled switch non-conductive.

[0037] “Controller” or “controller circuit” shall mean, alone or in combination, an individual circuit component, an application specific integrated circuit (ASIC), a microcontroller with control software, a reduced instruction set computer (RISC) with control software, a digital signal processor (DSP), a processor with control software, a programmable logic device (PLD), a field programmable gate array (FPGA), or a programmable system on a chip (PSOC), that is configured to read inputs and drive outputs in response to those inputs. DETAILED DESCRIPTION

[0038] The following discussion relates to various embodiments of the present invention. Although one or more of these embodiments may be preferred, the disclosed embodiments should not be interpreted or otherwise used to limit the scope of the present disclosure, including the claims. In addition, it should be understood by those skilled in the art that the following description has a wide range of applications, and the discussion of any embodiment is only intended to be an example of that embodiment, and is not intended to indicate that the scope of the present disclosure, including the claims, is limited to that embodiment.

[0039] In some applications, light emitting diodes (LEDs) have replaced traditional light bulbs. For example, in automotive applications, LEDs can be used to implement exterior lighting, which can cover large areas inside or outside the vehicle and can allow animated color schemes to indicate the status of the vehicle.

[0040] In order to realize such a lighting system, a modular LED system can be adopted, in which the primary device is connected to multiple secondary devices in a daisy chain manner. The secondary device can control one or more LED branches. For example, a secondary device can control 4 to 20 LED branches, and up to 128 secondary devices can be included in the daisy chain.

[0041] In many cases, the special requirements needed to integrate a modular LED system into a vehicle can employ multiple connectors to couple together the different segments of the modular LED system. To reduce costs, the connectors are not coated with gold but with cheaper materials. Although the use of cheaper materials reduces costs, cheaper materials increase the risk of oxidation of the connectors over time.

[0042] When an oxide layer forms on the surface of the connector, the electrical signals used by the primary and secondary devices may not be able to propagate from one device to the other, resulting in loss of communication and possible failure between components of the modular LED system. To reduce the risks associated with using less expensive connectors, a cleaning mode can be employed to maintain low resistance on the connector when oxide forms.

[0043] This cleaning mode may be activated periodically and employs a combination of high voltage (e.g., 10 to 15 volts) to break down any oxide on the connector and injecting current (e.g., 10 mA) for a specific period of time to further remove any residual oxide. In many systems, the transmitter side of a particular device in a daisy chain may apply high voltage and high current to a signal line connected to the receiver side of a different device in the daisy chain.

[0044] While this cleaning mode can maintain the operation of the system (i.e., modular LED system), problems may occur when using certain communication bus structures. In a differential communication bus, information in the form of bits or symbols of data is encoded in the voltage difference between two wires or conductors. Oxide accumulation on connectors in series with either signal line may cause communication failures.

[0045] In many low voltage differential signaling ("LVDS") applications, a termination resistor may be employed between two signal lines. In order for the clean mode to be effective, the voltage level of the pin that is open or electrically floating due to oxide buildup needs to be kept low so that the entire clean voltage is applied across the oxide. When only a single signal line is affected by oxide in the connector, the high voltage applied during the clean mode will cause the voltage level of the unaffected signal line to increase. A termination resistor internal to the receiving device couples the two receiver pins together, which allows the high voltage pull-up of the unaffected signal line to connect to the receiver pin of the affected signal line, thereby reducing the voltage level across the oxide and limiting the effectiveness of the clean mode. Additionally, when the connection suffers from high impedance due to oxide, the communication needs to remain functional in order to enable a low impedance path by coupling the receiver pin to ground during the clean mode.

[0046] Embodiments described herein may provide techniques for maintaining a low voltage level on a receiver pin that is electrically floating due to oxide on a connector coupled in series with a signal line of a differential communication bus coupled to the receiver pin during a clean mode. Additionally, embodiments described herein may provide techniques for activating a low impedance path from a transmit side of a particular device to a receiver side of a different device using a differential communication bus to allow a clean current to flow during a clean mode. By maintaining a floating pin at a low voltage and activating a low impedance during a clean mode, the effectiveness of the clean mode may be improved for a communication bus that employs multiple signal lines.

[0047] exist Figure 1 1 is a block diagram of a transceiver circuit. As shown, the transceiver circuit 100 includes a receiver circuit 101, a transmitter circuit 102, and a logic circuit 105. The receiver circuit 101 includes a receive pin 106 and a receiver cleaner circuit 103. The transmitter circuit 102 includes a transmit pin 107 and a transmitter cleaner circuit 104. The receiver circuit 101 and the transmitter circuit 102 are coupled to a power supply node 108. In various embodiments, the voltage of the power supply node 108 may be changed from an operating supply voltage to a cleaning voltage 115 during a cleaning operation. It should be noted that the cleaning voltage 115 is large enough to decompose the oxide layer formed on the connector coupled to the transmit pin 107. For example, in some embodiments, the operating supply voltage may be 5 volts, while the cleaning voltage 115 may be in the range of 10 volts to 15 volts. As used herein, the operating supply voltage is the voltage level of the power supply node 108 for non-cleaning mode operation.

[0048] The receiver circuit 101 is configured to receive data via a receive pin 106 and send the received data 111 to the logic circuit 105 when operating in a non-clean data transmission mode. The receiver cleaner circuit 103 is configured to maintain the receive pin 106 at a corresponding voltage level during the first stage of the clean mode in response to maintaining electrical floating. In various embodiments, the corresponding voltage level is less than the clean voltage 115. For example, the receiver pin 106 can be maintained at a voltage less than 5 volts, and the clean voltage 115 can be in the range of 10 volts to 15 volts. In various embodiments, the receiver cleaner circuit 103 is further configured to couple the receive pin 106 to the ground supply node 110 using the second stage of the clean mode. In various embodiments, the receiver circuit 101 can be configured to receive a clean signal on a communication bus coupled to the receive pin 106 via a low-frequency communication protocol. It should be noted that the receiver pin 106 is high voltage resistant and can be biased at a clean voltage without damaging the circuit inside the receiver circuit 101.

[0049] The transmitter circuit 102 is configured to receive transmit data 112 from the logic circuit 105 and to send the transmit data to other transceiver circuits or controller circuits via the transmit pin 107 when operating in a non-clean data transmit mode. The transmitter cleaner circuit 104 is configured to couple the transmit pin 107 to a clean voltage 115 during a first stage of the clean mode in response to activation of the clean mode. In various embodiments, the transmitter cleaner circuit 104 is further configured to supply a clean current 114 to the transmit pin 107 during a second stage of the clean mode. In some embodiments, the transmitter circuit 104 is further configured to send a clean signal 116 before supplying the clean current 114. In various embodiments, the transmitter circuit 102 may be configured to send (or "shift") a clean signal or control bit on a communication bus coupled to the transmit pin 107 via a low-frequency communication protocol during the clean operation. As described below, the clean signal or control bit may not propagate to another transceiver circuit because the oxide on the connector or contacts has created an open circuit between the transceiver circuits.

[0050] It should be noted that in some embodiments, the transmitter cleaner circuit 104 can be configured to perform the above operations substantially simultaneously with the receiver cleaner circuit 103. In other embodiments, the transmitter cleaner circuit 104 can be configured to perform its operations in response to determining that the receiver cleaner circuit 103 has completed its operations.

[0051] Logic circuit 105 is configured to process received data 111. In some cases, logic circuit 105 is configured to generate control signal 113 based on received data 111. In response to determining that received data 111 is intended for a different recipient, logic circuit 105 may generate transmit data 112 based on received data 111. In various implementations, logic circuit 105 may be implemented using a processor, a controller or microcontroller, a state machine, or any other suitable combination of combinatorial and sequential logic circuits.

[0052] Steering Figure 2 , depicts a block diagram of an embodiment of the receiver cleaner circuit 103. As shown, the receiver cleaner circuit 103 includes transistors 201-204, diodes 205 and 206, and resistors 207 and 208.

[0053] Resistor 207 is coupled between pin Rxp 209 and node 211, and resistor 208 is coupled between pin Rxn 210 and node 212. In various embodiments, pin Rxp 209 and pin Rxn 210 may be included in Figure 1 In various implementations, nodes 211 and 212 may be coupled to corresponding inputs of a differential amplifier circuit or other suitable comparator circuit to generate received data 111 based on a difference between the respective voltage levels of nodes 211 and 212.

[0054] Transistor 201 is coupled between node 211 and ground supply node 110. The control terminal of transistor 201 is also coupled to node 211. In a similar manner, transistor 203 is coupled between node 212 and ground supply node 110, with its control terminal coupled to node 212. With its control terminal coupled to its drain terminal, transistors 201 and 203 are referred to as "diode connected". In various embodiments, transistors 201 and 203 are configured to maintain the voltage levels of nodes 211 and 212 when Rxp 209 and Rxn 210 are floating. In various embodiments, the respective voltage levels of nodes 211 and 212 may be multiples of the gate-to-source voltages associated with transistors 201 and 203. By maintaining the respective voltage levels of nodes 211 and 212 at these values, a voltage difference sufficient to decompose oxides in the connectors coupled to pins Rxp 209 and pin Rxn 210 may be maintained during the first stage of the cleaning mode. For example, if pin Rxp 209 is coupled to an oxidized connector, then when a clean voltage is applied, the transmit side of the connector will be at the clean voltage and pin Rxp 209 will be at a voltage level based on the gate to source voltage of transistor 201 .

[0055] Diode 205 is coupled between pin Rxp 209 and node 213, and diode 206 is coupled between pin Rxn 210 and node 214. Transistor 202 is coupled between node 213 and ground supply node 110, and transistor 204 is coupled between node 214 and ground supply node 110. Control terminals of transistors 202 and 204 are coupled to clean signal 215. In response to activation of clean signal 215, transistors 202 and 204 are configured to couple nodes 213 and 214 to ground supply node 110, respectively. In the case where nodes 213 and 214 are coupled to ground supply node 110, a low impedance path is available between pins Rxp 209 and Rxn 210, thereby providing a path for clean current to ground. In various embodiments, diodes 205 and 206 allow negative input voltages on Rxp 209 and Rxn 210, which may be generated by noise coupling, ground loss, etc.

[0056] In various embodiments, transistors 201-204 may be implemented as n-channel double diffused metal oxide semiconductor ("DMOS") field effect transistors or any other suitable transconductance device. Although transistors 201-204 are depicted as single devices, in other embodiments, any of transistors 201-204 may be implemented using any suitable series and / or parallel combination of transistors.

[0057] In various embodiments, diodes 205 and 206 may be implemented as discrete diodes coupled to pins Rxp 209 and Rxn 210, respectively. In some embodiments, diodes 205 and 206 may be high voltage devices capable of applying a cleaning voltage to their respective anode terminals. In other embodiments, diodes 205 and 206 may be implemented using any suitable PN junction structure available on an integrated circuit including transistors 201-204 and other components of receiver cleaner circuit 103.

[0058] In some embodiments, resistors 207 and 208 may be implemented as discrete resistors coupled to pins Rxp 209 and Rxn 210, respectively. In other embodiments, resistors 207 and 208 may be implemented using polysilicon or any other suitable material available on a semiconductor manufacturing process. Although depicted as a single resistor, in other embodiments, resistors 207 and 208 may be implemented using any suitable series and / or parallel combination of resistors.

[0059] Steering Figure 3 , depicts a block diagram of an embodiment of transmitter cleaner circuit 104. As shown, transmitter cleaner circuit 104 includes transistors 301-303, diodes 306 and 307, and resistors 310-313.

[0060] Resistor 311 is coupled between power supply node 108 and node 319, while resistor 312 is coupled between power supply node 108 and node 320. Transistor 301 is coupled between node 319 and node 321, while transistor 302 is coupled between node 320 and node 322. Respective control terminals of transistors 301 and 302 are coupled to node 317.

[0061] Diode 306 is coupled between node 321 and pin Txn 316, and diode 307 is coupled between node 322 and pin Txp 315. In various embodiments, pin Txp 315 and pin Txn 316 may be included in transmit pin 107. Diode 306 may be configured to prevent current from flowing from pin Txn 316 to power supply node 108 via transistor 301 and resistor 311. In a similar manner, diode 307 may be configured to prevent current from flowing from pin Txp 315 to power supply node 108 via transistor 302 and resistor 312.

[0062] Resistor 310 is coupled between power supply node 108 and node 317. Transistor 303 is coupled between node 317 and node 318 and is controlled by enable signal 326. Resistor 313 is coupled between node 318 and ground supply node 110. In various embodiments, in response to activation of enable signal 326, transistor 303 is configured to couple node 317 to node 318. When node 317 is coupled to node 318, a resistive voltage divider is formed by resistors 310 and 313, thereby generating a voltage level on node 317 sufficient to activate transistors 301 and 302. As the voltage on node 317 decreases, transistors 301 and 302 become conductive, thereby coupling nodes 321 and 322 to power supply node 108 via resistors 311 and 312, respectively. As the voltage levels of nodes 321 and 322 increase, the voltage levels of pins Txp 315 and Txn 316 also increase until they reach a voltage level at or near the clean voltage 115 .

[0063] In response to the deactivation of the enable signal 326, the transistor 303 is configured to decouple the node 317 from the node 318. When the node 317 is decoupled from the node 318, the voltage level of the node 317 increases to a voltage level at or near the clean voltage 115 due to the resistor 310. In response to the increase in the voltage level of the node 317, the transistors 301 and 302 transition to the off state, thereby decoupling the nodes 321 and 322 from the nodes 319 and 320, respectively. The pins Txp 315 and Txn 316 are then free to return to normal operational voltages.

[0064] In various embodiments, transistor 303 may be implemented as an n-channel DMOS field effect transistor or any other suitable power MOSFET, and transistors 301 and 302 may be implemented as p-channel DMOS field effect transistors or any other suitable transconductance devices. Although transistors 301-303 are depicted as a single device, in other embodiments, any of transistors 301-303 may be implemented using any suitable series and / or parallel combination of transistors.

[0065] Resistors 310-313 may be implemented using polysilicon or any other suitable material available on a semiconductor fabrication process.Although depicted as a single resistor, in other embodiments, resistors 310-313 may be implemented using any suitable series and / or parallel combination of resistors.

[0066] In various embodiments, diodes 306 and 307 can be implemented as high voltage devices capable of applying cleaning voltage 115 to their respective anode terminals. In other embodiments, diodes 306 and 307 can be implemented using any suitable PN junction structure available on an integrated circuit including transistors 301-303 and other components of emitter cleaner circuit 104.

[0067] Steering Figure 4 , depicts a block diagram of an embodiment of a system including a plurality of transceiver circuits coupled together via a communication bus. As shown, system 400 includes controller circuit 401 and transceiver circuits 402A-402C. In various embodiments, transceiver circuits 402A-402C may be such as Figure 1 Different examples of transceiver circuit 100 are depicted in FIG.

[0068] Controller circuit 401 is coupled to transceiver circuit 402A via bus 403A, which in turn is coupled to transceiver circuit 402B via bus 403B. Transceiver circuit 402B is coupled to transceiver circuit 402C via bus 403C, and transceiver circuit 402C is coupled to controller circuit 401 via bus 403D. In various embodiments, Figure 4 The arrangement of controller circuit 401 and transceiver circuits 402A-402C depicted in FIG. 4 is referred to as a "daisy chain." Although Figure 4 Only three transceiver circuits are depicted in the daisy chain of FIG. 1 , but in other embodiments, any suitable number of transceiver circuits may be employed. Controller circuit 401 and transceiver circuits 402A-402C are coupled to power supply node 108. In various embodiments, any of transceiver circuits 402A-402C may be coupled to one or more LED branches.

[0069] Bus 403A can be separated by connector 404A, and bus 403B can be separated by connector 404B. In a similar manner, buses 403C and 403D can be separated by connectors 404C and 404D, respectively. Although connectors 404A-404D are depicted as each including two connectors, in other embodiments, multiple connectors in a given one of connectors 404A-404D can correspond to multiple signal lines included in buses 403A-403D. As described above, any connector in connectors 404A-D can form an oxide layer, thereby generating high impedance on the signal line on the corresponding bus in buses 403A-403D. For example, if a specific connector in connector 404A forms an oxide layer, the impedance from control circuit 401 to transceiver circuit 402A along the corresponding signal line of bus 403A may increase to a point where communication between controller circuit 401 and transceiver circuit 402A may be impossible.

[0070] Buses 403A-403D may include any suitable number of signal lines or conductors. In various embodiments, buses 403A-403D may each include two signal lines or conductors, and information (eg, a bit or symbol) may be encoded as the difference between the corresponding voltage levels of the two lines and conductors in the bus.

[0071] The controller circuit 401 may be configured to generate corresponding commands and data for the transceiver circuits 402A-402C. The generated commands and data may be shifted through the transceiver circuits 402A-402C until the last transceiver circuit in the chain receives its corresponding command and data. Alternatively, in various embodiments, the controller circuit 401 may be configured to relay commands and data to different transceiver circuits in the transceiver circuits 402A-402C using bus 403A. In the event that a particular command or data portion is not intended for the transceiver circuit 402A, the particular command or data portion may be relayed to other transceiver circuits along the chain until the particular command or data portion reaches its intended recipient.

[0072] In some embodiments, the system 400 may be used in an environment where oxide may form at the receive pin or transmit pin of any of the transceiver circuits 402A-402C. As described above, a cleaning mode may be activated to break down any oxide buildup on the pin and allow the system to continue operating. In various embodiments, the controller circuit 401 may initiate such a cleaning mode during startup of the system 400 or during shutdown of the system 400. Alternatively or in addition, the controller 401 may initiate the cleaning mode at preset random intervals.

[0073] In response to activating the cleaning mode, the controller circuit 401 is configured to perform a first stage of an initial cleaning operation by adjusting the voltage level of the power supply node 108. In order to adjust the voltage level of the power supply node 108, the controller circuit 401 may be further configured to set the voltage level of the power supply node 108 to a cleaning voltage level determined based on the breakdown voltage of the oxide. In some cases, the cleaning voltage may be greater than the operable voltage level of the transceiver circuits 402A-402C for performing non-cleaning operations. In other embodiments, the operable voltage level may be sufficient to break through the oxide. In this case, the voltage level of the power supply node 108 does not need to be adjusted during the cleaning operation. It should be noted that in some embodiments, the transceiver circuits 402A-402C may include a corresponding boost circuit configured to locally generate a cleaning voltage level.

[0074] In various embodiments, the controller circuit 401 may be further configured to shift the control bit 405 through the transceiver circuits 402A-402C. In some cases, the control bit cannot pass through one of the connectors 404A-404C that has formed an oxide that prevents the control bit 405 from being transmitted. As described above, during the first stage of the initial cleaning operation, each of the transceiver circuits 402A-402C applies a cleaning voltage to its corresponding transmit pin. For example, the transceiver circuit 402A applies a cleaning voltage to its transmit pin coupled to the bus 403C. The higher voltage can break down the oxide, thereby allowing the control bit 405 to shift through the transceiver circuits 402A-402C.

[0075] In response to determining that the first predetermined time period has passed, the controller circuit 401 is configured to reset the transceiver circuits 402A-402C. In various embodiments, to reset the transceiver circuits 402A-402C, the controller circuit 401 is configured to return the voltage level of the power supply node 108 to an operational voltage level. Alternatively, the transceiver circuits 402A-402C may be reset by setting the voltage level of the power supply node 108 to a voltage level lower than an operational voltage, which is a sufficiently low level that causes the sub-circuits within the transceiver circuits 402A-402C to reset. In this case, the voltage level of the power supply node 108 may be ramped up to the operational voltage level to resume non-clean operation.

[0076] After transceiver circuits 402A-402C have been reset, controller circuit 401 is configured to perform a second phase of the initial cleaning operation by adjusting the voltage level of power supply node 108. As in the first phase, to adjust the voltage level of power supply node 108, controller circuit 401 is further configured to set the voltage level of power supply node 108 to a cleaning voltage level.

[0077] To perform the second phase of the initial cleaning operation, the controller circuit 401 is further configured to shift the control bit 405 through the transceiver circuits 402A-402C. The oxide on any of the connectors 404A-404C will be decomposed, thereby allowing the control bit to propagate further through the transceiver circuits 402A-402C. As described above, in response to receiving a corresponding control bit in the control bits 405, the transceiver circuits 402A-402C are configured to activate a low impedance path to a ground supply node in their corresponding input pins. With the input pins of the transceiver circuits coupled to the ground supply node, current may flow from the output of one transceiver circuit to the input of the next transceiver circuit in the chain, thereby further cleaning the connectors 404A-404C.

[0078] The controller circuit 401 may continue the second phase of the initial cleaning operation for a second predetermined time period. In response to determining that the second predetermined time period has passed, the controller circuit 401 is configured to reset the transceiver circuits 402A-402C. As in the first phase, in order to reset the transceiver circuits 402A-402C, the controller circuit 401 may be configured to set the voltage level of the power supply node 108 back to an operable voltage level or a voltage level below the operable voltage sufficient to reset the sub-circuits within the transceiver circuits 402A-402C. In this case, the voltage level of the power supply node 108 may be ramped up to an operable voltage level to resume non-cleaning operation.

[0079] In response to determining that the second phase of the initial cleaning operation has been completed, the controller circuit 401 is configured to perform a communication check. In various embodiments, to perform the communication check, the controller circuit 401 may verify that one or more of the control bits 405 are received from the transceiver circuit 402C. Once it has been verified that one or more of the control bits 405 are received, the controller circuit 401 is configured to determine that the communication check passes. If it is not possible to verify one or more of the control bits 405, the controller circuit 401 may be configured to determine that the communication check fails. It should be noted that for embodiments with more than three transceiver circuits, the controller circuit 401 may be configured to verify that one or more of the control bits 405 are received from the last transceiver circuit in the daisy chain. In other embodiments, as part of the communication check, the controller circuit 401 may be configured to shift predetermined test data instead of the control bits 405 through the transceiver circuits 402A-402C.

[0080] In various embodiments, the controller circuit 401 is configured to perform multiple cleaning operations once the cleaning mode has been activated. For example, the controller circuit 401 may be configured to perform a second cleaning operation after the initial cleaning operation in response to determining that the communication check fails. The maximum number of cleaning operations to be performed when the cleaning mode is effective can be predetermined. In this case, the controller circuit 401 may be further configured to terminate the cleaning mode in response to determining that a predetermined number of cleaning operations have been performed without successful communication checks. Alternatively, the controller circuit 401 may be configured to track the time elapsed from the start of the cleaning mode. In some embodiments, the controller circuit 401 may be further configured to terminate the cleaning mode in response to determining that the time elapsed exceeds a predetermined threshold.

[0081] exist Figure 5 , a block diagram of an embodiment of a light emitting diode control system is depicted in FIG. As shown, light emitting diode system 500 includes controller circuit 501, transceiver circuit 502, light emitting diode branch 503 (denoted as “LED branch 503”), and LED branch 504. It should be noted that in various embodiments, controller circuit 501, transceiver circuit 502, and LED branches 503 and 504 may share a common ground supply node (not shown).

[0082] Controller circuit 501 is coupled to power supply node 108. In addition, controller circuit 501 is coupled to transceiver circuit 502 via bus 506A. In some embodiments, controller circuit 501 is configured to send commands to transceiver circuit 502 via bus 509A. In various embodiments, these commands may include instructions for activating different LEDs in LEDs 505A-505C included in LED branch 503 and LEDs 506A-506C included in LED branch 504. In addition, these commands may include a cleaning signal to activate a cleaning mode in transceiver circuit 502. In various embodiments, bus 509A may be a differential communication bus, in which information is encoded as a difference between corresponding voltage levels of two wires or conductors included in bus 509A. It should be noted that although bus 509A is depicted as including two wires or conductors, in other embodiments, any suitable number of wires or conductors may be employed.

[0083] Transceiver circuit 502 is coupled to power supply node 108 and LED branches 503 and 504. Figure 5In the embodiment of FIG. 5 , the transceiver circuit 502 is depicted as being coupled to two LED branches, but in other embodiments, the transceiver circuit 502 can be coupled to any suitable number of LED branches. The transceiver circuit 502 is further coupled to the controller circuit 501 via bus 509A. Additionally, the transceiver circuit 502 can be coupled to another transceiver circuit via bus 509B. In some cases, the transceiver circuit 502 can be coupled to multiple other transceiver circuits and the controller circuit 501 in a daisy-chain manner.

[0084] In various embodiments, transceiver circuit 502 may be configured to generate control signals 507 and 508 based on commands received from controller circuit 501. Transceiver circuit 502 may be further configured to use bus 509B to relay commands received via bus 509A that are intended for other transceiver circuits. In other embodiments, transceiver circuit 502 may be configured to respond to commands as described above with respect to Figure 1 The cleaning operation is performed by activating the described cleaning mode.

[0085] LED branches 503 and 504 are coupled to power supply node 108. In some embodiments, LED branches 503 and 504 are configured to draw power from power supply node 108. In other embodiments, LED branches 503 and 504 can be configured to draw at least some power from control signals 507 and 508, respectively. LED branch 503 includes LEDs 505A-505C, and LED branch 504 includes LEDs 506A-506C. Although LED branches 503 and 504 are depicted as each including three LEDs, in other embodiments, LED branches 503 and 504 can include any suitable number of LEDs, and the number of LEDs in LED branch 503 can be different from the number of LEDs in LED branch 504. In various embodiments, LED branch 503 is configured to activate one or more of LEDs 505A-505C using control signal 507. In a similar manner, LED branch 504 is configured to activate one or more of LEDs 506A-506C using control signal 508. As used herein, activating an LED refers to applying any suitable combination of voltage and / or current to the LED so that the LED combines electron-hole pairs to generate photons. In some cases, LEDs 505A-505C and LEDs 506A-506C can emit photons corresponding to light of a common wavelength when activated. In other cases, different LEDs in LEDs 505A-505C and 506A-506C can emit photons of different energies corresponding to light of different wavelengths and therefore light of different colors. In some embodiments, any suitable number of LEDs 505A-505C and 506A-506C can be activated at different times based on control signals 507 and 508, respectively.

[0086] Steering Figure 6 , a flow chart depicting an embodiment of a method for a transceiver circuit to perform a cleaning operation is shown. The method, which may be applicable to various transceiver circuits (eg, transceiver circuit 100 ), begins in block 601 .

[0087] The method includes activating a clean mode for a transceiver circuit (block 602). In various embodiments, activating the clean mode includes asserting a clean signal or a dedicated control signal coupled to the transceiver circuit. In various embodiments, the method may include receiving, by the transceiver circuit, the clean signal from the controller circuit via a communication bus coupled between the transceiver circuit and the controller circuit. In other embodiments, the method may include receiving, by the transceiver circuit, the clean signal from a different transceiver circuit via a communication bus coupled between the transceiver circuit and the different transceiver circuit.

[0088] The method also includes maintaining, by the transceiver circuitry, respective voltage levels of the plurality of receiver pins at respective voltage levels less than the clean voltage during the first phase of the clean mode (block 603). In some embodiments, maintaining, by the transceiver circuitry, respective voltage levels of the plurality of receiver pins at respective voltage levels less than the clean voltage during the first phase of the clean mode includes coupling, by the transceiver circuitry, the plurality of receiver pins to ground via respective transistors of the plurality of diode-connected transistors.

[0089] The method also includes coupling, by the transceiver circuit, a plurality of receiver pins to a ground supply node during a second phase of the cleaning mode following the first phase of the cleaning mode (block 604). In some embodiments, the method may also include activating, by the transceiver circuit, the second phase in response to determining that a predetermined time period has elapsed since activating the first phase. In some embodiments, the predetermined time may be selected based on a time required for oxide on the contact to decompose. In various embodiments, coupling the plurality of receiver pins to the ground supply node includes activating a plurality of transistors coupled between the ground supply node and corresponding receiver pins of the plurality of receiver pins. In some embodiments, the method includes activating the plurality of transistors in response to receiving a control signal.

[0090] In various embodiments, the method may further include coupling a plurality of transmit pins included in the transceiver circuit to a clean voltage during a first phase of the clean mode, and supplying corresponding currents to the plurality of transmit pins during a second phase of the clean mode. In some embodiments, the method may further include transmitting a control signal via the plurality of transmit pins to activate the clean mode in different transceiver circuits before coupling the plurality of transmit pins to the clean voltage. In various embodiments, coupling the plurality of transmit pins to the clean voltage includes: activating a plurality of transistors coupled between a high voltage power supply node and corresponding transmit pins of the plurality of transmit pins for a specific time period. In various embodiments, the voltage level of the high voltage power supply node may correspond to the clean voltage.

[0091] It should be noted that in some embodiments, the operations performed on the transmit pins may be performed substantially simultaneously with the operations performed on the receiver pins. However, in some embodiments, the operations performed on the transmit pins may be performed after the operations performed on the receiver pins, or vice versa. The method ends in block 605.

[0092] Steering Figure 7 , a flow chart depicting an embodiment of a method for performing a cleaning operation on a transceiver circuit system is shown. The method, which may be applicable to various systems (eg, system 400 ), begins in block 701 .

[0093] The method includes a first stage of performing, by a controller circuit in response to activating a cleaning mode, an initial cleaning operation by adjusting a voltage level of a power supply node coupled to a plurality of transceiver circuits (block 702). In various embodiments, the plurality of transceiver circuits and the controller circuit are coupled together in a daisy-chain manner. It should be noted that the initial cleaning operation for a given transceiver circuit in the plurality of transceiver circuits may include Figure 6 In some embodiments, adjusting the voltage level of the power supply node includes setting the voltage level of the power supply node to a clean voltage level that is greater than an operable voltage level of the plurality of transceiver circuits for non-clean operation.

[0094] The method also includes resetting, by the controller circuit in response to determining that a first predetermined time has elapsed since the first stage (block 703). In various implementations, resetting the plurality of transceiver circuits includes returning a voltage of a power supply node to an operational voltage level.

[0095] The method also includes performing, by the controller circuit, a second phase of the initial cleaning operation by adjusting the voltage level of the power supply node (block 704). In various embodiments, adjusting the voltage level of the power supply node includes setting the voltage level of the power supply node to a cleaning voltage level. In some embodiments, performing the second phase of the cleaning operation includes shifting control bits through a plurality of transceiver circuits via a differential communication bus by the controller circuit. In other embodiments, a dedicated cleaning control signal separate from the differential communication bus may be employed.

[0096] The method may also include activating, by the given transceiver circuit in response to receiving the at least one control bit, a low impedance path to a ground supply node for at least one input pin of the given transceiver circuit. In various embodiments, activating the low impedance path to the ground supply node may include activating, by the given transceiver circuit, a transistor coupled between the at least one input pin and the ground supply node.

[0097] The method also includes resetting, by the controller circuit in response to determining that a second predetermined time has elapsed since the start of the second phase (block 705), the plurality of transceiver circuits. In various embodiments, resetting the plurality of transceiver circuits includes returning a voltage level of a power supply node to an operational voltage level.

[0098] The method also includes performing, by the controller circuit in response to determining that the second phase has completed (block 706). In some embodiments, performing the communication check may include checking, by the controller circuit, receipt of a control bit from a last transceiver circuit of the plurality of transceiver circuits. Alternatively, performing the communication check may include sending, by the controller circuit, test data through the plurality of transceiver circuits and verifying that the test data is returned from the last transceiver circuit.

[0099] The method may also include, in response to determining that the communication check fails, performing a second cleaning operation after the initial cleaning operation. In some embodiments, the method may also include, by the controller circuit, terminating the cleaning mode in response to determining that a predetermined number of cleaning operations have been performed without a successful communication check. In other embodiments, terminating the cleaning mode may include issuing an error message by the controller circuit. The method ends in block 707.

[0100] The present disclosure includes references to "an embodiment" or "groups of embodiments." As used herein, an embodiment is a different specific implementation of an example of a disclosed concept. References to "an embodiment," "some embodiments," and the like do not necessarily refer to the same embodiment. Many embodiments are possible and contemplated, including those specifically disclosed as well as modifications or substitutions that fall within the spirit or scope of the present disclosure.

[0101] The above disclosure is intended to illustrate the principles and various embodiments of the disclosed concepts. Once the above disclosure is fully understood, many variations and modifications will become apparent to those skilled in the art. The following claims are interpreted as being intended to include all such variations and modifications.

Claims

1. A transceiver device, the transceiver device comprising: Logic circuits; A receiver circuit, the receiver circuit being configured to: receiving data via a plurality of receiver pins; as well as sending the received data to the logic circuit; and a first cleaner circuit, the first cleaner circuit being configured to, in response to activation of a cleaning mode, perform the following operations: maintaining a receiver pin of the plurality of receiver pins at a respective voltage level during a first stage of the cleaning mode, wherein the respective voltage level is less than a cleaning voltage; as well as During a second phase of the cleaning mode, the plurality of receiver pins are coupled to a ground supply node.

2. The transceiver device according to claim 1, further comprising: A transmitter circuit, the transmitter circuit being configured to: receiving transmit data from the logic circuit; as well as transmitting the transmission data via a plurality of transmission pins; and a second cleaner circuit, the second cleaner circuit being configured to, in response to the activation of the cleaning mode: coupling the plurality of transmit pins to the clean voltage during the first phase of the clean mode; as well as During the second phase of the cleaning mode, respective currents are supplied to the plurality of transmit pins. 3 . The transceiver device of claim 1 , wherein the receiver circuit is configured to receive a plurality of control bits, and wherein the transmitter circuit is configured to relay at least a portion of the plurality of control bits.

4. The transceiver device according to claim 1, wherein in order to maintain the receiver pin at the corresponding voltage level, the receiver circuit is further configured to use a plurality of Corresponding ones of the diode-connected transistors maintain the receiver pins at their respective voltage levels.

5. The transceiver device of claim 1 , wherein, to couple the plurality of receiver pins to the ground supply node during the second phase of the cleaning mode, the first cleaner circuit is further configured to activate a plurality of transistors coupled between the ground supply node and corresponding receiver pins of the plurality of receiver pins in response to receiving a control bit.

6. A contact cleaning method, comprising: activating a cleaning mode for the transceiver circuit; maintaining, by the transceiver circuitry, respective voltage levels of a plurality of receiver pins at corresponding voltage levels less than a clean voltage during a first phase of the clean mode; as well as The plurality of receiver pins are coupled to a ground supply node by the transceiver circuit during a second phase of the cleaning mode, wherein the second phase of the cleaning mode is subsequent to the first phase of the cleaning mode.

7. The contact cleaning method according to claim 6, further comprising: coupling, by the transceiver circuit, a plurality of transmit pins to the clean voltage during the first phase of the clean mode; as well as Respective currents are supplied by the transceiver circuit to the plurality of transmit pins during the second phase of the cleaning mode.

8. The contact cleaning method of claim 6, wherein maintaining the respective voltage levels of the plurality of receiver pins at corresponding voltage levels less than the cleaning voltage during the first phase of the cleaning mode comprises: The plurality of receiver pins are coupled to ground by the transceiver circuit via corresponding transistors of a plurality of diode-connected transistors.

9. The contact cleaning method of claim 6, wherein coupling the plurality of receiver pins to the ground supply node comprises: In response to receiving a control bit, a plurality of transistors coupled between the ground supply node and corresponding receiver pins of the plurality of receiver pins are activated.

10. A communication system, comprising: a plurality of transceiver circuits coupled to a power supply node; and a controller circuit coupled to the plurality of transceiver circuits in a daisy-chain manner, wherein the controller circuit is configured to: In response to activation of the cleaning mode, performing a first phase of an initial cleaning operation by adjusting a voltage level of the power supply node; in response to determining that a first predetermined period of time has elapsed since the start of the first phase, resetting the plurality of transceiver circuits; performing a second phase of the initial cleaning operation by adjusting the voltage level of the power supply node; in response to determining that a second predetermined time has elapsed since the start of the second phase, resetting the plurality of transceiver circuits; as well as In response to determining that the second phase has been completed, a communication check is performed.

11. The communication system of claim 10, wherein to adjust the voltage level of the power supply node, the controller circuit is configured to set the voltage level of the power supply node to a clean voltage level that is greater than an operating voltage level of the plurality of transceiver circuits for non-clean operations.

12. The communication system of claim 10, wherein a given transceiver circuit of the plurality of transceiver circuits is coupled to a branch of light emitting diodes (LEDs).

Images