2T1C global shutter pixel structure based on floating gate and working mode

Abstract

The invention discloses a 2T1C global shutter pixel structure based on a floating gate and a working mode, and belongs to the field of image sensors. The method comprises the steps that a global shutter switch tube is arranged above a signal collection area, the proportion of a photoelectric signal collection area is not additionally occupied, and it is guaranteed that the function of a global shutter is added under the condition that the proportion of the photoelectric signal collection area is not lost; the pixel structure provided by the invention is simple, and the shutter efficiency is high; on the premise that the pixel size is reduced and the pixel performance is not sacrificed in a high-resolution application scene, a global shutter function on a small-size pixel unit is realized.

Description

Technical Field

[0001] The present invention relates to the field of image sensors, and in particular to a floating gate-based 2T1C global shutter pixel structure and a working method. Background Art

[0002] Charge-coupled device (CCD) and complementary metal oxide semiconductor (CMOS) are the two main technical routes of current image sensors. Their working principle is to convert light signals into electrical signals, and obtain images by processing and reading out the electrical signals. Compared with CCD, CMOS image sensor (CIS) has more flexible functions, higher frame rate, lower power consumption, lower price and loss during no signal transfer, and currently occupies a larger market share. However, since the realization of CIS pixel unit's photosensitivity, reading, reset and other functions all rely on separate transistors, the increase in the number of transistors will compress the area ratio of the device's photosensitive area, and as the pixel size decreases, the area ratio of the photosensitive area will be even smaller, which will greatly reduce the full well capacity of the pixel, affecting the pixel's peak signal-to-noise ratio, thereby restricting the demand for high-resolution application scenarios.

[0003] In addition, the work of image sensor chips often involves two exposure methods: rolling exposure (Rolling Shutter) and global exposure (Global Shutter). Compared with rolling exposure, global exposure requires a shorter exposure time and is suitable for applications that require high dynamic range and low noise. It can also avoid image deformation and motion blur when exposing high-speed moving objects. Therefore, in surveillance and reconnaissance, industrial inspection, smart vehicles and other fields, when affected by platform vibration or imaging high-speed moving objects, global exposure is usually required to avoid image distortion. Compared with the solution of adding a mechanical shutter to the outside of the detector to achieve a global shutter, the pixel-level global shutter solution has become the main solution for image sensor chips to achieve a global shutter due to its advantages such as high mechanical stability and high global shutter efficiency. Usually the simplest global shutter pixel is a 5T structure, such as Figure 6 As shown in the figure, a field effect transistor (SH) is added to the structure of the standard 4T CIS pixel. It is used to promptly guide the subsequent photoelectric signals entering the PD node after all pixels have completed the transfer of the collected photoelectric signals from the PD node to the FD node to prevent interference signals from entering the FD node. In addition, its FD node also needs to be shielded to ensure the efficiency of the global shutter. Due to the newly added structure, the proportion of the photosensitive area in the pixel of the same size is further compressed. Therefore, in order to ensure sufficient photosensitive area to ensure imaging quality, the pixel size of the image sensor chip with device-level global shutter function is usually larger than 2µm×2µm, and the number of pixels integrated on a single chip is difficult to meet the needs of some high-resolution application scenarios.

[0004] A Chinese patent with publication number CN102938409A discloses a dual-transistor photosensitive detector based on a composite dielectric gate MOSFET and a signal reading method thereof. The detector realizes the photosensitivity and reading functions of the photosensitive detector by using a photosensitive transistor and a reading transistor respectively, and still ensures good imaging quality at a sub-micron pixel size; however, the detector lacks a device-level global shutter structure, which severely restricts its application in scenarios such as capturing high-speed moving objects and imaging on a vibrating platform.

[0005] In general, in application scenarios that require high resolution, the reduction of pixel size becomes an inevitable trend; in application scenarios that require the recognition of high-speed moving objects, such as reconnaissance and vehicle-mounted, global shutter pixels are indispensable. The realization of the global shutter function and the small size of pixels restrict each other, so how to realize the global shutter function on a small size pixel unit without sacrificing pixel performance has become a current research difficulty. Summary of the invention

[0006] The purpose of the present invention is to propose a floating gate-based 2T1C global shutter pixel structure and working mode to address the problems encountered in the current global shutter image sensor pixel size reduction, and to realize the function of a global exposure image sensor through a simplified structure of two transistors (2T) and a capacitor (1C) in the vertical direction.

[0007] The first object of the present invention is to provide a 2T1C global shutter pixel structure based on a floating gate, wherein the global shutter pixel structure specifically includes a floating gate capacitor, a signal collection area, a floating gate transistor, a shallow trench isolation structure, and a global shutter switch tube formed on the same semiconductor substrate; the floating gate capacitor is used for collecting photoelectric signals, and includes a capacitor dielectric layer and a capacitor gate sequentially arranged above the semiconductor substrate, and the semiconductor substrate area below the capacitor dielectric layer is the signal collection area; the floating gate transistor is used for reading out the photoelectric signal, and includes a transistor source, a transistor drain, and a transistor gate sequentially arranged between the transistor source and the transistor drain. The bottom dielectric layer of the transistor, the floating gate of the transistor, the top dielectric layer of the transistor and the top gate of the transistor are located above the conductor substrate; the shallow trench isolation structure is located in the lower substrate range between the floating gate capacitor and the floating gate transistor, separating the area of ​​the substrate close to the upper surface, and is used to prevent the photoelectric signal collected below the floating gate capacitor from being lost through the source or drain of the floating gate transistor; the global shutter switch tube is used to realize the function of the device-level global shutter, and the global shutter switch tube includes a bottom dielectric layer of the switch tube, a switch tube body area, a top dielectric layer of the switch tube, and a switch tube gate, which are located between the floating gate capacitor and the floating gate transistor and are sequentially arranged above the semiconductor substrate.

[0008] One end of the switch tube body region is connected to the capacitor gate, and the other end is connected to the transistor floating gate. All three are in an electrically floating state and are not connected to an external voltage interface; the capacitor gate is not directly connected to the transistor floating gate; the switch tube gate and the transistor top gate are not connected to each other; the switch tube bottom dielectric layer is respectively connected to the capacitor dielectric layer and the transistor bottom dielectric layer, and the switch tube top dielectric layer is connected to the transistor top dielectric layer; the transistor source, transistor drain, transistor top gate, switch tube gate, and semiconductor substrate are respectively connected to different external voltage interfaces.

[0009] Furthermore, the shallow trench isolation structure is located in the substrate surface area below the global shutter switch tube, and the shallow trench isolation structure is filled with an insulating medium.

[0010] Furthermore, the transistor source and drain have the same doping type, which is opposite to the semiconductor substrate doping type; the capacitor gate has the same doping type as the transistor floating gate, which is opposite to the switch body region doping type.

[0011] Furthermore, the bottom dielectric layer of the switch tube is connected to the capacitor dielectric layer and the bottom dielectric layer of the transistor respectively, and the three are an integral structure; the top dielectric layer of the switch tube is connected to the top dielectric layer of the transistor, and the two are an integral structure.

[0012] Furthermore, the semiconductor substrate is composed of single crystal silicon, the transistor floating gate, the switch tube body region, and the capacitor gate material are composed of polycrystalline silicon or single crystal silicon, and the transistor top gate and the switch tube gate material are composed of one of low-resistance polycrystalline silicon, aluminum, tantalum, tungsten, hafnium, titanium or platinum.

[0013] Furthermore, when multiple floating gate-based 2T1C global shutter pixel structures are arranged in an array form, an isolation structure is provided between adjacent pixel structures to reduce crosstalk of photoelectric signals between pixels, and the isolation structure includes an annular front isolation structure and an annular back isolation structure. The annular front isolation structure separates the areas of the substrate close to the upper surface between adjacent floating gate-based 2T1C global shutter pixel structures, and the annular back isolation structure separates the areas of the substrate close to the bottom between adjacent floating gate-based 2T1C global shutter pixel structures, and the top of the annular back isolation structure and the bottom of the annular front isolation structure do not contact each other; and the interior of the isolation structure is filled with an insulating medium or a high-concentration doped semiconductor material of the same doping type as the semiconductor substrate.

[0014] A second object of the present invention is to provide a working method of a 2T1C global shutter pixel structure based on a floating gate, the method comprising the following steps: Step 1: Initial power-on: 0V voltage is applied to the transistor source, transistor drain, transistor top gate, switch gate, and external voltage interface connected to the semiconductor substrate; Step 2: Reset the signal collection area; by adjusting the voltage of the switch tube gate, an inversion layer channel appears on the upper surface of the switch tube body area, the capacitor gate and the transistor floating gate are electrically connected, so that the capacitor gate and the transistor floating gate achieve the same potential; at this time, by applying a voltage difference between the top gate of the transistor and the semiconductor substrate, majority carriers can be accumulated on the lower side of the dielectric gate capacitor, and part of the minority carriers originally located here will recombine with the majority carriers, and the other part will flow away from the transistor source and the transistor drain through diffusion, so as to achieve the reset of the signal collection area; Step 3: Generation and collection of photogenerated charges; maintaining the equipotential state between the capacitor gate and the transistor floating gate, and displacing the majority of carriers in the signal collection area by changing the voltage difference between the top gate of the transistor and the semiconductor substrate, so that the signal collection area forms a depleted photogenerated charge collection well. Under the action of light, photogenerated charges are stimulated in the semiconductor substrate, and the photogenerated charges enter the collection well by diffusion, and are collected on the lower surface of the capacitor dielectric layer under the action of the vertical electric field. The collection of photogenerated charges will change the surface potential on the lower side of the capacitor dielectric layer, thereby changing the distribution of carriers in the capacitor gate and the transistor floating gate, and affecting the potential of the transistor floating gate, thereby realizing the mapping of the collected photogenerated charge signal to the number of carriers in the transistor floating gate; Step 4: Closing of the global shutter; when multiple floating gate-based 2T1C global shutter pixel structures are arranged in an array, "Step 3: Generation and collection of photogenerated charges" of all pixel units are performed simultaneously, by simultaneously changing the voltage of the switch gates in all pixel units, so that the capacitor gates and the transistor floating gates in all pixel units are no longer electrically connected. At this time, the number of carriers and the potential in the transistor floating gate no longer change with the subsequent collection of photogenerated charges, thereby achieving the closure of the global shutter; Step 5: photoelectric signal reading; control the voltage of the switch gate of all floating gate-based 2T1C global shutter pixel structure units in the pixel array, maintain the non-electrical conduction state of the capacitor gate and the transistor floating gate in all pixel units, at this time, the threshold voltage of the floating gate transistor depends on the number of carriers in the floating gate of the transistor, the pixel array is read out row by row, and a voltage difference of 0.1V~1V is applied between the transistor source and the transistor drain of the pixel unit to be read out, and the threshold voltage of the floating gate transistor is quantitatively read out according to the transistor drain current extracted by the subsequent circuit by scanning the voltage of the top gate of the transistor, so as to realize the reading of the photoelectric signal collected by each pixel unit.

[0015] The beneficial effects of the present invention are: The present invention provides a 2T1C global shutter pixel structure based on a floating gate. By arranging the global shutter switch tube above the signal collection area, the duty cycle of the photoelectric signal collection area is not additionally occupied, thereby ensuring that the function of the global shutter is increased without sacrificing the duty cycle of the photoelectric signal collection area; at the same time, a part of the transistor floating gate has the function of storing photoelectric signals; the pixel structure proposed by the present invention is simple, and compared with the prior art, when the global shutter pixel size is less than 5×5µm 2 When the pixel size is reduced to sub-micron size, the duty cycle of the photoelectric signal collection area is usually less than 50%; the pixel structure proposed in the present invention can still ensure a duty cycle of more than 60% of the photoelectric signal collection area. In high-resolution application scenarios, the global shutter function is realized on small-size pixel units without sacrificing pixel performance while reducing the pixel size. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 A circuit schematic diagram of an image sensor based on a floating gate 2T1C global shutter pixel structure proposed in one embodiment of the present invention; Figure 2 A schematic diagram of a three-dimensional structure of an image sensor based on a floating gate 2T1C global shutter pixel structure provided in one embodiment of the present invention; Figure 3 A schematic diagram of a three-dimensional structure of an image sensor based on a floating gate 2T1C global shutter pixel structure along an X-section provided in one embodiment of the present invention; Figure 4 A schematic diagram of a three-dimensional structure of an image sensor based on a floating gate 2T1C global shutter pixel structure along the Y cross section provided in one embodiment of the present invention; Figure 5 A schematic diagram of the working timing of a device based on a floating gate 2T1C global shutter pixel structure provided in one embodiment of the present invention; Figure 6 It is a circuit schematic diagram of a 5T global shutter image sensor in the prior art; Among them, 101-floating gate capacitor; 101a-capacitor dielectric layer; 101b-capacitor gate; 102-signal collection area; 103-floating gate transistor; 103a-transistor source; 103b-transistor drain; 103c-transistor bottom dielectric layer; 103d-transistor floating gate; 103e-transistor top dielectric layer; 103f-transistor top gate; 104-global shutter switch tube; 202a-switch tube bottom dielectric layer; 202b-switch tube body area; 202c-switch tube top dielectric layer; 202d-switch tube gate; 105-semiconductor substrate voltage port; 201-semiconductor substrate; 203-shallow trench isolation structure; 301-annular front isolation structure; 302-annular back isolation structure. DETAILED DESCRIPTION

[0018] To make the content of the present invention more clear and understandable, the content of the present invention is further described below in conjunction with the accompanying drawings of the specification. Of course, the present invention is not limited to this specific embodiment, and general replacements known to those skilled in the art are also covered within the protection scope of the present invention.

[0019] Embodiment 1 The purpose of this embodiment is to provide a 2T1C global shutter pixel structure based on a floating gate, and its circuit schematic diagram is as follows: Figure 1 As shown, it includes a floating gate capacitor 101, a signal collection area 102, a floating gate transistor 103, a global shutter switch tube 104 and a semiconductor substrate voltage port 105; wherein the floating gate capacitor 101 includes a capacitor dielectric layer 101a and a capacitor gate 101b; the floating gate transistor 103 includes a transistor source 103a, a transistor drain 103b, a transistor bottom dielectric layer 103c, a transistor floating gate 103d, a transistor top dielectric layer 103e and a transistor top gate 103f.

[0020] The semiconductor substrate voltage port 105 is connected to the signal collection area 102 and provides a substrate voltage for the floating gate transistor 103. A capacitor dielectric layer 101a is connected in series between the signal collection area 102 and the capacitor gate 101b; a transistor bottom dielectric layer 103c is connected in series between the semiconductor substrate voltage port 105 and the transistor floating gate 103d; a transistor top dielectric layer 103e is connected in series between the transistor floating gate 103d and the transistor top gate 103f; the capacitor gate 101b is connected to one end of the global shutter switch tube 104, and the transistor floating gate 103d is connected to the other end of the global shutter switch tube 104.

[0021] A schematic diagram of a three-dimensional structure of an image sensor based on a floating gate 2T1C global shutter pixel structure provided in this embodiment is shown in FIG. Figure 2 As shown, the pixel structure is formed on the same semiconductor substrate 201, except Figure 1In addition to the structure described in the schematic diagram, the pixel structure of the present invention also includes a shallow trench isolation structure 203, which is filled with insulating material to prevent the photoelectric signal collected in the signal collection area 102 from flowing away from the transistor source 103a and the transistor drain 103b during the collection process. The bottom dielectric layer 202a of the switch tube, the switch tube body area 202b, the top dielectric layer 202c of the switch tube and the switch tube gate 202d are the specific structures of the global shutter switch tube 104. Among them, the bottom dielectric layer 202a of the switch tube is respectively connected to the capacitor dielectric layer 101a and the bottom dielectric layer 103c of the transistor, and the three are an integral structure; the top dielectric layer 202c of the switch tube is connected to the top dielectric layer 103e of the transistor, and the two are an integral structure; one end of the switch tube body area 202b is connected to the capacitor gate 101b, and the other end is connected to the transistor floating gate 103d. The three are electrically floating structures, and the material is polysilicon.

[0022] In this embodiment, the transistor source 103a and the transistor drain 103b are ≥10 19 / cm 3 The semiconductor substrate 201 is 10 15 / cm 3 The P-type doped epi layer has a value of ≥10 17 / cm 3 The switch body region 202b is ≤10 16 / cm 3 A low concentration P-type doped region.

[0023] Figure 3 and Figure 4 Embodiments of the present invention Figure 2 The pixel cross-sectional structure along the X direction and along the Y direction, in addition to the structures mentioned above, also involves the isolation structure between adjacent pixels when the pixel structure of the present invention is arranged in an array form, mainly including an annular front isolation structure 301 and an annular back isolation structure 302, both of which are filled with insulating materials or the same doping type as the semiconductor substrate 201 with a doping concentration of ≥10 18 / cm 3 Highly doped semiconductor materials are used to reduce crosstalk between photoelectric signals collected by different pixels.

[0024] Embodiment 2 The purpose of this embodiment is to provide an image sensor working method based on a floating gate 2T1C global shutter pixel structure. The working method is implemented based on the structure provided in the first embodiment. The timing diagram is as follows: Figure 5As shown; the working mode includes the following five steps: initial pressurization, resetting of the signal collection area, generation and collection of photogenerated charges, closing of the global shutter, and reading of the photoelectric signal. Step 1: Initial voltage application; a voltage of 0V is applied to all voltage ports of the device: transistor source 103a, transistor drain 103b, transistor top gate 103f, switch gate 202d, and semiconductor substrate voltage port 105.

[0025] Step 2: Reset the signal collection area; raise the voltage of the switch gate 202d, generally 2V~3V, so that an inversion layer channel appears on the upper surface of the switch body area 202b, and electrically connect the capacitor gate 101b and the transistor floating gate 103d, so that the two achieve the same potential; reduce the potential on the semiconductor substrate voltage port 105 to -3V~-2V, so as to provide pressurized conditions for the formation of the photogenerated electron collection well in the subsequent step; next, by reducing the potential on the transistor top gate 103f, the potential of the capacitor gate 101b is lower than the potential of the semiconductor substrate voltage port 105, and holes accumulate on the lower side of the capacitor dielectric layer 101a (signal collection area 102), and part of the electrons originally located here recombine with the accumulated holes, and the other part flows away from the transistor source 103a and the transistor drain 103b through diffusion, thereby resetting the signal collection area.

[0026] Step 3: Generation and collection of photogenerated charges; maintain the electrical connection state between the capacitor gate 101b and the transistor floating gate 103d, raise the potential of the transistor top gate 103f to ≥0V, discharge the holes in the signal collection area 102, and form a depleted photogenerated electron collection well in the signal collection area 102. Under the action of external light, photogenerated charge pairs are stimulated in the semiconductor substrate 201, wherein the photogenerated electrons enter the electron collection well by diffusion and are collected on the lower surface of the capacitor dielectric layer 101a under the action of the vertical electric field. As the electrons are collected, the surface potential on the lower side of the capacitor dielectric layer 101a will change accordingly, thereby changing the distribution of carriers in the capacitor gate 101b and the transistor floating gate 103d, and the potential of the transistor floating gate 103d will also become lower accordingly, thereby realizing the mapping of the number of collected photogenerated electrons to the number of carriers in the transistor floating gate 103d.

[0027] Step 4: Closing of the global shutter; when multiple floating gate-based 2T1C global shutter pixel structures of the present invention are arranged in an array, the "third step" of all pixels is performed simultaneously, and the voltage of the switch gate 202d of all pixel units is reduced to ≤-2V, so that the capacitor gate 101b and the transistor floating gate 103d in all pixel units are no longer electrically connected. At this time, the number of charges in the transistor floating gate 103d no longer changes with the subsequent collection of photogenerated charges, and the potential of the transistor floating gate 103d no longer changes with external light, thereby achieving the closing of the global shutter; Step 5: Reading of photoelectric signals; keep the negative voltage state of the gate electrode 202d of all pixel unit switches, at this time, the capacitor gate electrode 101b and the transistor floating gate 103d in each pixel unit maintain a non-electrical conduction state, because the threshold voltage of the floating gate transistor 103 depends on the number of carriers in the transistor floating gate 103d, so its threshold voltage remains unchanged. Then read out the pixel array row by row, that is, raise the potential of the transistor drain electrode 103b of the pixel unit to be read out (0.1V~1V), scan the voltage of the top gate electrode 103f of the transistor of the pixel row to be read out (from 0V to 5V), and read out the threshold voltage of the floating gate transistor 103 quantitatively according to the current of the transistor drain electrode 103b extracted by the subsequent circuit, that is, complete the reading of the photoelectric signals collected by all pixel units.

[0028] In this embodiment, the switch tube body region 202b adopts a thin layer structure with a thickness of several nanometers to tens of nanometers to ensure a smaller volume, which is used to reduce the parasitic light response of the transistor floating gate 103d caused by external light directly irradiating the switch tube body region 202b during the "closing of the global shutter" and "reading of the photoelectric signal" stages, so as to increase the global shutter efficiency.

[0029] The present embodiment provides a solution for realizing a global shutter function on a sub-micron ultra-small pixel. By adding only one global shutter switch tube 104 to the floating gate in the vertical direction, the floating gate not only has the function of transmitting the voltage signal of the signal collection area 102, but also allows a part of the floating gate, that is, the transistor floating gate 103d, to have the function of storing photoelectric signals. Compared with the current conventional solution of adding multiple transistors and storage areas in the horizontal direction to realize the global shutter function, the present invention does not lose the duty cycle of the pixel signal collection area 102. While realizing the global shutter function, it avoids the decline of performance indicators such as the pixel full well capacity, thereby ensuring the imaging quality of sub-micron ultra-small pixels. In addition, since the global shutter switch tube 104 of the present invention is an SOI transistor, the influence of the parasitic photoelectric signal of the semiconductor substrate 201 on the stored signal in the transistor floating gate 103d during the "global shutter closing" stage is effectively shielded, so that only the part of the switch tube body area 202b directly irradiated by external light will introduce parasitic light response. By adopting back-illuminated imaging, setting a metal shading structure, reducing the thickness and area of ​​the switch tube body area 202b, etc., the parasitic light response can be greatly reduced, and the pixel global shutter efficiency can be improved. At present, based on the 10nm switch tube body area thickness, it is possible to achieve a pixel greater than 10 4 High visible light global shutter efficiency (signal collection area quantum efficiency / parasitic light response).

[0030] Although the present invention has been disclosed as above with preferred embodiments, the embodiments are merely examples for the convenience of description and are not intended to limit the present invention. Those skilled in the art may make several changes and modifications without departing from the spirit and scope of the present invention. The scope of protection claimed by the present invention shall be based on the claims.

Claims

1. A 2T1C global shutter pixel structure based on a floating gate, characterized in that: The floating gate-based 2T1C global shutter pixel structure comprises a floating gate capacitor (101), a signal collection region (102), a floating gate transistor (103), a global shutter switch tube (104) and a shallow trench isolation structure (203) formed on the same semiconductor substrate (201); The floating gate capacitor (101), the global shutter switch tube (104) and the floating gate transistor (103) are arranged in sequence on a semiconductor substrate (201); the signal collection area (102) is located below the floating gate capacitor (101) and the global shutter switch tube (104); and the shallow trench isolation structure (203) is also located below the global shutter switch tube (104).

2. The floating gate-based 2T1C global shutter pixel structure according to claim 1, characterized in that: The floating gate capacitor (101) is used for collecting photoelectric signals, and comprises a capacitor dielectric layer (101a) and a capacitor gate (101b) sequentially arranged above the semiconductor substrate (201), and the semiconductor substrate (201) region below the capacitor dielectric layer (101a) is a signal collection region (102); The floating gate transistor (103) is used for reading out a photoelectric signal, and comprises a transistor source (103a), a transistor drain (103b), and a transistor bottom dielectric layer (103c), a transistor floating gate (103d), a transistor top dielectric layer (103e), and a transistor top gate (103f) sequentially arranged above the semiconductor substrate (201); The shallow trench isolation structure (203) is located within the lower substrate between the floating gate capacitor (101) and the floating gate transistor (103), separating the area of ​​the substrate close to the upper surface, and is used to prevent the photoelectric signal collected below the floating gate capacitor (101) from being lost through the floating gate transistor source (103a) or transistor drain (103b); The global shutter switch tube (104) is used to realize the function of a device-level global shutter, and comprises a switch tube bottom dielectric layer (202a), a switch tube body region (202b), a switch tube top dielectric layer (202c), and a switch tube gate (202d) which are sequentially arranged above the semiconductor substrate (201).

3. The floating gate-based 2T1C global shutter pixel structure according to claim 2, characterized in that: One end of the switch tube body region (202b) is connected to the capacitor gate (101b), and the other end is connected to the transistor floating gate (103d), and all three are in an electrically floating state and are not connected to an external voltage interface; the capacitor gate (101b) is not directly connected to the transistor floating gate (103d); the capacitor gate (101b) and the transistor top gate (103f) are not connected to each other; the transistor source (103a), transistor drain (103b), transistor top gate (103f), switch tube gate (202d), and semiconductor substrate (201) are respectively connected to different external voltage interfaces.

4. The floating gate-based 2T1C global shutter pixel structure according to claim 3, characterized in that: The shallow trench isolation structure (203) is located in a substrate surface area below the global shutter switch tube (104), and an insulating medium is filled inside the shallow trench isolation structure (203).

5. The floating gate-based 2T1C global shutter pixel structure according to claim 4, characterized in that: The transistor source (103a) and the transistor drain (103b) have the same doping type, which is opposite to the doping type of the semiconductor substrate (201); the capacitor gate (101b) and the transistor floating gate (103d) have the same doping type, which is opposite to the doping type of the switch body region (202b).

6. The floating gate-based 2T1C global shutter pixel structure according to claim 5, characterized in that: The bottom dielectric layer (202a) of the switch tube is respectively connected to the capacitor dielectric layer (101a) and the bottom dielectric layer (103c) of the transistor, and the three form an integral structure; the top dielectric layer (202c) of the switch tube is connected to the top dielectric layer (103e) of the transistor, and the two form an integral structure.

7. The floating gate-based 2T1C global shutter pixel structure according to claim 6, characterized in that: The semiconductor substrate (201) is made of single crystal silicon, the transistor floating gate (103d), the switch tube body region (202b), and the capacitor gate (101b) are made of polycrystalline silicon or single crystal silicon, and the transistor top gate (103f) and the switch tube gate (202d) are made of one of polycrystalline silicon, aluminum, tantalum, tungsten, hafnium, titanium, or platinum.

8. A 2T1C global shutter pixel structure array based on floating gate, characterized in that: The array is composed of the floating gate-based 2T1C global shutter pixel structure described in any one of claims 1 to 7; an isolation structure is provided between adjacent pixel structures in the array to reduce crosstalk of photoelectric signals between pixels, the isolation structure comprising an annular front isolation structure (301) and an annular back isolation structure (302); the annular front isolation structure (301) separates the areas of the substrate close to the upper surface between adjacent 2T1C global shutter pixel structures based on the floating gate, and the annular back isolation structure (302) separates the areas of the substrate close to the bottom between adjacent 2T1C global shutter pixel structures based on the floating gate, and the top of the annular back isolation structure (302) and the bottom of the annular front isolation structure (301) do not contact each other; and the material composition of the annular front isolation structure (301) and the annular back isolation structure (302) comprises an insulating medium or a semiconductor material of the same doping type as the semiconductor substrate (201).

9. A working mode of a 2T1C global shutter pixel structure based on a floating gate, characterized in that: The working method is implemented based on the floating gate-based 2T1C global shutter pixel structure according to any one of claims 1 to 7 or the floating gate-based 2T1C global shutter pixel structure array according to claim 8; the working method comprises the steps of: Step 1: Initial power-on; 0V voltage is applied to the external voltage interfaces connected to the transistor source (103a), the transistor drain (103b), the transistor top gate (103f), the switch gate (202d), and the semiconductor substrate (201); Step 2: resetting the signal collection area (102); by adjusting the voltage of the switch tube gate (202d), an inversion layer channel appears on the upper surface of the switch tube body area (202b), the capacitor gate (101b) and the transistor floating gate (103d) are electrically connected, so that the capacitor gate (101b) and the transistor floating gate (103d) achieve the same potential; at this time, by applying a voltage difference between the top gate (103f) of the transistor and the semiconductor substrate (201), majority carriers accumulate on the lower side of the capacitor dielectric layer, part of the minority carriers originally located there are recombined with the majority carriers, and the other part flows away from the transistor source (103a) and the transistor drain (103b) through diffusion, thereby resetting the signal collection area (102); Step 3: Generation and collection of photogenerated charges; maintaining an equipotential state between the capacitor gate (101b) and the transistor floating gate (103d), and displacing the majority of carriers in the signal collection area (102) by changing the voltage difference between the transistor top gate (103f) and the semiconductor substrate (201), so that the signal collection area (102) forms a depleted photogenerated charge collection well. Under the action of light, photogenerated charges are stimulated in the semiconductor substrate (201), and the photogenerated charges enter the collection well through diffusion, and are collected on the lower surface of the capacitor dielectric layer (101a) under the action of a vertical electric field. The collection of photogenerated charges changes the surface potential on the lower side of the capacitor dielectric layer (101a), thereby changing the distribution of carriers in the capacitor gate (101b) and the transistor floating gate (103d), and affecting the potential of the transistor floating gate (103d), thereby realizing the mapping of the collected photogenerated charge signal to the number of carriers in the transistor floating gate (103d); Step 4: closing of the global shutter; when a plurality of floating gate-based 2T1C global shutter pixel structures are arranged in an array, "step 3: generation and collection of photogenerated charges" of all pixel units are performed simultaneously, and by simultaneously changing the voltage of the switch gate (202d) in all pixel units, the capacitor gate (101b) and the transistor floating gate (103d) in all pixel units are no longer electrically conductive, and at this time, the number of carriers and the potential in the transistor floating gate (103d) no longer change with the subsequent collection of photogenerated charges, thereby achieving the closing of the global shutter; Step 5: photoelectric signal reading; controlling the voltage of the switch gate (202d) of all the floating gate-based 2T1C global shutter pixel structure units in the pixel array, maintaining the non-electrical conduction state of the capacitor gate (101b) and the transistor floating gate (103d) in all pixel units, at which time the threshold voltage of the floating gate transistor (103) depends on the number of carriers in the transistor floating gate (103d), and the pixel array is read out row by row, and a fixed voltage difference is applied between the transistor source (103a) and the transistor drain (103b) of the pixel unit to be read out, and by scanning the voltage of the top gate (103f) of the transistor, the threshold voltage of the floating gate transistor (103) is quantized and read out according to the current of the transistor drain (103b) extracted by the subsequent circuit, thereby realizing the reading of the photoelectric signal collected by each pixel unit.

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