Multilayer electrode connection structure, on-chip capacitor and multilayer electrode connection method

Abstract

The invention relates to the field of semiconductor devices, and provides a multi-layer electrode connection structure, an on-chip capacitor and a multi-layer electrode connection method, the multi-layer electrode connection structure is applied to the inside of the on-chip capacitor, and the multi-layer electrode connection structure comprises a substrate used for providing an adhesion surface of an electrode layer located at the bottom layer; the electrode layer is provided with an etching groove, and the first area and the second area are used for providing electric conduction; the contours of the adjacent etching grooves in the N electrode layers are not intersected with each other in the stacking direction, and N is a positive integer greater than 2; and the dielectric layers are positioned between the adjacent electrode layers and are used for providing insulating dielectric. The structure is used for reducing the segment difference in the multi-layer electrode so as to ensure the performance of the capacitor.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and in particular to a multi-layer electrode connection structure, an on-chip capacitor and a multi-layer electrode connection method. Background Art

[0002] Silicon-based capacitors are usually built by depositing dielectric materials and electrode materials on a silicon substrate to form a multilayer structure to increase capacitance. As the number of layers increases, it becomes increasingly difficult to connect the electrodes in each layer, especially at the nanoscale.

[0003] In the products currently on the market, after forming a multilayer structure with alternating electrodes and dielectric layers, it is necessary to etch a fixed depth to lead out the positive and negative electrodes respectively to separate the positive and negative electrodes. The process difficulty and cost increase with the number of layers. When the number of layers is large, the position etched to lead out the electrode will collapse, resulting in a step difference. The step difference will not only affect the subsequent deposition of the dielectric layer and the electrode layer, but also introduce additional electric field inhomogeneity between the electrode layers, which may cause the local electric field strength to be too high, thereby increasing the leakage current, reducing the insulation performance of the dielectric layer, and even causing breakdown, affecting the performance of the capacitor. Therefore, there is an urgent need for a multilayer electrode connection structure, an on-chip capacitor, and a multilayer electrode connection method to improve the above problems. Summary of the invention

[0004] The object of the present invention is to provide a multi-layer electrode connection structure, an on-chip capacitor and a multi-layer electrode connection method, which structure is used to reduce the step difference in the multi-layer electrode to ensure the performance of the capacitor.

[0005] In a first aspect, the present invention provides a multilayer electrode connection structure for use inside an on-chip capacitor, comprising: a substrate for providing an attachment surface for an electrode layer located at the bottom layer; an electrode layer provided with etching grooves for providing a conductive first region and a second region; contours of adjacent etching grooves in N electrode layers do not intersect each other in a stacking direction, where N is a positive integer greater than 2; and a dielectric layer located between adjacent electrode layers for providing an insulating dielectric.

[0006] Optionally, the electrode layer is set to be M layers, M is greater than or equal to N; when M is equal to N, the contours of the etched grooves in the N layers of the electrode layer do not intersect each other in the stacking direction.

[0007] Optionally, when M is greater than N, the contours of the etched grooves in the electrode layer within the N layer and the electrode layer outside the N layer intersect.

[0008] Optionally, the electrode layer has a first edge and a second edge opposite to each other, and the etching grooves in two adjacent electrode layers are respectively close to the first edge and the second edge, so that the first regions and the second regions in the adjacent electrode layers overlap alternately.

[0009] Optionally, the substrate is provided with a groove; the width of the groove is greater than the width of the etched groove.

[0010] Optionally, a plurality of the grooves are distributed on the substrate surface in a self-similar patterned array; the shape of the grooves includes at least one of a strip, a rectangle, and a circle.

[0011] In a second aspect, the present invention provides an on-chip capacitor, comprising: the multilayer electrode connection structure described in any one of the first aspects, and: a first conductive sealing end portion, used to connect the first region in each electrode layer; a second conductive sealing end portion, used to connect the second region in each electrode layer; the first conductive sealing end portion and the second conductive sealing end portion are isolated from each other.

[0012] In a third aspect, the present invention provides a multi-layer electrode connection method for forming a multi-layer electrode connection structure as described in any one of the first aspects, comprising: S1, providing a substrate, and forming an electrode layer on its upper surface; S2, performing an etching process on the electrode layer located on the surface so that the electrode layer is divided into a first area and a second area by the etching grooves; S3, forming a dielectric layer on the surface of the electrode layer; forming an electrode layer on the upper surface of the dielectric layer; S4, after repeating S2-S3 several times, executing S2 again; the contours of adjacent etching grooves in N electrode layers do not intersect each other in the stacking direction, and N is a positive integer greater than 2.

[0013] Optionally, S4 further includes: cutting or grinding edges of the stacked electrode layers to expose the first region and the second region of the electrode layers.

[0014] Optionally, the method further includes S5, forming a first conductive sealing end portion for connecting the first region in each electrode layer, and forming a second conductive sealing end portion for connecting the second region in each electrode layer.

[0015] Optionally, the electrode layer and the dielectric layer are respectively formed by at least one of atomic layer deposition and chemical vapor deposition processes; and the first conductive sealing end portion and the second conductive sealing end portion are formed by an electroplating process.

[0016] The beneficial effects of the present invention are as follows: by ensuring that the contours of adjacent etched grooves in the N-layer electrode layer do not intersect each other in the stacking direction, the height difference of the etched grooves set in the multi-layer electrode layers is avoided to accumulate to form a step difference, which can increase the actual effective capacitance area, keep the electric field between the electrode layers uniform, avoid excessive local electric field strength, thereby reducing leakage current, improving the insulation performance of the dielectric layer, avoiding breakdown, and helping to improve the performance of the capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram of a multi-layer electrode connection structure provided by the present invention; Figure 2A schematic diagram of a structure in which a groove is provided on a substrate provided by the present invention; Figure 3 A schematic diagram of a plurality of rectangular grooves provided by the present invention distributed in a rectangular array on a substrate; Figure 4 A schematic diagram of a plurality of strip-shaped grooves linearly arranged on a substrate provided by the present invention; Figure 5 A schematic diagram of the structure of an on-chip capacitor provided by the present invention; Figure 6 A schematic diagram of a process for connecting multi-layer electrodes provided by the present invention; Figure 7 A schematic diagram of a structure in which an odd-numbered first electrode layer is formed on a substrate provided by the present invention; Figure 8 A schematic diagram of a structure in which an odd-numbered first electrode layer etching groove is formed in an odd-numbered first electrode layer provided by the present invention; Fig. 9 A schematic diagram of a structure in which a first dielectric layer is formed on an odd-numbered first electrode layer provided by the present invention; Fig.10 A schematic diagram of a structure in which an odd-numbered second electrode layer is formed on a first dielectric layer provided by the present invention; Fig.11 A schematic diagram of a structure in which an odd-numbered second electrode layer etching groove is formed in an odd-numbered second electrode layer provided by the present invention; Fig.12 A schematic diagram of a structure in which a second dielectric layer is formed on an odd-numbered second electrode layer provided by the present invention.

[0018] Description of reference numerals in the figures: 1. substrate; 5. conductive sealing end; 11. Groove; 21. Odd-numbered first electrode layer; 22. Even-numbered first electrode layer; 31. Odd-numbered second electrode layer; 32. Even-numbered second electrode layer; 41. First dielectric layer; 42. Second dielectric layer; 43. Third dielectric layer; 51. First conductive sealing end; 52. Second conductive sealing end; 201, etching grooves of the first electrode layer of odd-numbered positions; 202, etching grooves of the first electrode layer of even-numbered positions; 211, positive electrode regions of the first electrode layer of odd-numbered positions; 212, negative electrode regions of the first electrode layer of odd-numbered positions; 221, positive electrode regions of the first electrode layer of even-numbered positions; 222, negative electrode regions of the first electrode layer of even-numbered positions; 301, etching grooves of the second electrode layer at odd positions; 302, etching grooves of the second electrode layer at even positions; 311, positive electrode regions of the second electrode layer at odd positions; 312, negative electrode regions of the second electrode layer at odd positions; 321, positive electrode regions of the second electrode layer at even positions; 322, negative electrode regions of the second electrode layer at even positions. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with general skills in the field to which the present invention belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0020] In view of the problems existing in the existing technology, such as Figure 1 As shown, the first embodiment of the present invention provides a multi-layer electrode connection structure, which is applied to the inside of an on-chip capacitor, including: a substrate 1, which is used to provide an attachment surface for an electrode layer located at the bottom layer; an electrode layer provided with etching grooves, which is used to provide a conductive first region and a second region; the contours of adjacent etching grooves in the N-layer electrode layer do not intersect each other in the stacking direction, and N is a positive integer greater than 2; a dielectric layer, which is located between adjacent electrode layers and is used to provide an insulating dielectric. In this embodiment, by making the contours of adjacent etching grooves in the N-layer electrode layer do not intersect each other in the stacking direction, the height difference of the etching grooves set in the multi-layer electrode layers is avoided to accumulate to form a step difference, which can increase the actual effective capacitance area, keep the electric field between the electrode layers uniform, and avoid excessive local electric field strength, thereby reducing leakage current, improving the insulation performance of the dielectric layer, and avoiding breakdown, which is beneficial to improving the performance of the capacitor.

[0021] In some other specific embodiments, the stacking direction of the N-layer electrode layer is along the vertical direction Z, and the extension direction of the substrate 1, the electrode layer and the dielectric layer is along the horizontal plane. The etching groove is configured to gradually penetrate into the electrode layer along the vertical direction Z until it contacts the substrate 1 or the dielectric layer.

[0022] In some other specific embodiments, the substrate 1 is made of silicon, silicon oxide, zirconium oxide, hafnium oxide, germanium, silicon nitride, aluminum oxide or gallium oxide. The electrode layer is set to a conductive material. The dielectric layer is set to an insulating material. The dielectric layer is also used to fill the etched groove of the electrode layer below it, so that the first area and the second area are separated by the insulating material.

[0023] In some embodiments, the electrode layer is configured as M layers, where M is greater than or equal to N; when M is equal to N, the contours of the etched grooves in the N-layer electrode layer do not intersect each other in the stacking direction.

[0024] In some specific embodiments, M=N=4, and an odd-numbered first electrode layer 21 is connected to the attachment surface provided by the substrate 1. A first dielectric layer 41 is connected to the odd-numbered first electrode layer 21. An odd-numbered second electrode layer 31 is connected to the first dielectric layer 41. A second dielectric layer 42 is connected to the odd-numbered second electrode layer 31. An even-numbered first electrode layer 22 is connected to the second dielectric layer 42. A third dielectric layer 43 is connected to the even-numbered first electrode layer 22. The third dielectric layer 43 is connected to the even-numbered second electrode layer 32. In this embodiment, the etched grooves in the N-layer electrode layer are arranged not to intersect each other in the Z direction, thereby avoiding the accumulation of etched groove height differences and fundamentally eliminating the step difference. The actual effective capacitance area of ​​the capacitor is increased, so that the electric field between the electrode layers remains uniform, and the local electric field strength is avoided from being too high, thereby reducing the leakage current, improving the insulation performance of the dielectric layer, and avoiding breakdown, which is beneficial to improving the performance of the capacitor.

[0025] In some examples, the odd-numbered first electrode layer 21 is provided with an odd-numbered first electrode layer etching groove 201 close to the reverse direction of X, and the even-numbered first electrode layer 22 is provided with an even-numbered first electrode layer etching groove 202 close to the reverse direction of X. The odd-numbered first electrode layer etching groove 201 and the even-numbered first electrode layer etching groove 202 are adjacent to each other, and the contours of the two in the Z direction do not intersect each other.

[0026] In other examples, the odd-numbered second electrode layer 31 is provided with an odd-numbered second electrode layer etching groove 301 close to the X direction, and the even-numbered second electrode layer 32 is provided with an even-numbered second electrode layer etching groove 302 close to the X direction. The odd-numbered second electrode layer etching groove 301 and the even-numbered second electrode layer etching groove 302 are adjacent to each other, and the contours of the two in the Z direction do not intersect each other.

[0027] It is worth noting that the micro-displacement fine trench patterning (MDFTP) is used to define the position of the etching grooves of the adjacent electrode layers, which can achieve sub-micron or even nanometer-level positioning accuracy, which is conducive to improving the integration of integrated circuits.

[0028] In some embodiments, when M is greater than N, the contours of the etched grooves in the electrode layer within the N layer and the electrode layer outside the N layer intersect.

[0029] In some specific embodiments, M=20, N=10, 20 electrode layers and 20 dielectric layers are stacked on substrate 1 along the Z direction, and the etched grooves in the electrode layer at the 1st layer intersect with the outlines of the etched grooves in the electrode layer at the 401st layer in the Z direction; the etched grooves in the electrode layer at the 2nd layer intersect with the outlines of the etched grooves in the electrode layer at the 402nd layer in the Z direction; the etched grooves in the electrode layer at the 10th layer intersect with the outlines of the etched grooves in the electrode layer at the 20th layer in the Z direction. This embodiment reuses the etched groove positions after spacing N electrode layers, which can minimize the local accumulation of etched groove height differences, so that the multi-layer electrode connection structure can reach a higher number of layers to meet the design of large-capacity on-chip capacitors. On the other hand, this embodiment can further increase the effective surface area of ​​the electrode by increasing the number of electrode layers to M layers, thereby improving the capacitance density.

[0030] In some embodiments, the electrode layer has a first edge and a second edge opposite to each other, and the etching grooves in two adjacent electrode layers are respectively close to the first edge and the second edge, so that the first regions and the second regions in the adjacent electrode layers overlap alternately.

[0031] In some specific embodiments, the first edge is located in the opposite direction of X, and the second edge is located in the X direction. In some examples, the odd-numbered first electrode layer negative electrode region 212, the odd-numbered second electrode layer positive electrode region 311, the even-numbered first electrode layer negative electrode region 222, and the even-numbered second electrode layer positive electrode region 321 overlap alternately from bottom to top. In other specific embodiments, the first edge is located in the X direction, and the second edge is located in the opposite direction of X. In this embodiment, by making the etching grooves in the two adjacent electrode layers close to the first edge and the second edge, respectively, the space can be better utilized, the effective electrode area can be further increased, and the capacitance density can be improved.

[0032] like Figure 2 As shown, in some embodiments, the substrate 1 is provided with a groove 11; the width of the groove 11 is greater than the width of the etched groove. In some specific embodiments, the groove 11 is formed on the surface of the substrate 1 by an etching process. In some examples, the silicon substrate 1 is etched by a reactive ion etching (RIE) process to form a groove 11 with a depth-to-width ratio ranging from 1:100 to 100:1. The width of the groove 11 ranges from 0.5 to 100 microns. The direction of the width is along the horizontal direction X, and the direction of the depth is along the vertical direction Z.

[0033] In some examples, the aspect ratio of the groove 11 is set to 1:100. The width of the groove 11 is set to 100 micrometers. In other examples, the aspect ratio of the groove 11 is set to 100:1. The width of the groove 11 is set to 0.5 micrometers. In still other examples, the aspect ratio of the groove 11 is set to 1:1. The width of the groove 11 is set to 50.25 micrometers.

[0034] This embodiment can optimize the electrical signal path and reduce signal distortion by controlling the size of the groove 11. In some examples, the cross-section of the groove 11 perpendicular to the Y direction is rectangular. In other examples, the cross-section of the groove 11 perpendicular to the Y direction is trapezoidal. In some other examples, the cross-section of the groove 11 perpendicular to the Y direction is arched. The curved side of the arch can be set as a parabola, an ellipse or a hyperbola. The horizontally set X direction, the horizontally set Y direction and the vertically set Z direction are perpendicular to each other.

[0035] In some embodiments, a plurality of the grooves 11 are distributed on the surface of the substrate 1 in a self-similar patterned array; the shape of the grooves 11 includes at least one of a strip, a rectangle, and a circle.

[0036] like Figure 3 As shown, in some specific embodiments, a single groove 11 is configured as a rectangle, and a plurality of grooves 11 are arranged in a rectangular array, and the outer contour of the rectangular array is similar to that of the single groove 11 in rectangle shape.

[0037] In some other specific embodiments, a single groove 11 is configured in a circular shape, and a plurality of grooves 11 are arranged in a circular array, and the outer contour of the circular array is similar to that of the single groove 11 .

[0038] like Figure 4 As shown, in some specific embodiments, a single groove 11 is configured as a strip, and a plurality of grooves 11 are arranged linearly. In some examples, the extension direction of a single strip groove 11 is along the Y direction, and the linear arrangement direction is along the X direction. In other examples, the extension direction and the linear arrangement direction of a single strip groove 11 are both along the Y direction.

[0039] In this embodiment, the grooves 11 distributed on the surface of the substrate 1 in a self-similar patterned array are provided to make the electric field between the electrode layers uniform and facilitate large-scale design.

[0040] It is worth noting that the etching groove extends to the edge of the electrode layer along the Y direction and the reverse direction of Y. The groove 11 does not need to extend to the edge of the substrate 1.

[0041] like Figure 5As shown, the second embodiment provides an on-chip capacitor, comprising: a multilayer electrode connection structure described in any one of the above embodiments, and: a first conductive sealing end 51, used to connect the first area in each electrode layer; a second conductive sealing end 52, used to connect the second area in each electrode layer; the first conductive sealing end 51 and the second conductive sealing end 52 are isolated from each other.

[0042] In some specific embodiments, the first conductive sealing end portion 51 is used to connect the positive electrode, and the second conductive sealing end portion 52 is used to connect the negative electrode. When there is a potential difference between the positive and negative electrodes, the first region and the second region form an electric field. In other specific embodiments, the first conductive sealing end portion 51 is used to connect the negative electrode, and the second conductive sealing end portion 52 is used to connect the positive electrode. It is worth noting that this embodiment realizes parallel connection of adjacent electrode layers by setting the first conductive sealing end portion 51 and the second conductive sealing end portion 52 isolated from each other, which is conducive to improving the capacity of the capacitor.

[0043] In some examples, the number of electrode layers is an even number, and charges are stored by alternating insulating layers and electrode layers. In other examples, the number of electrode layers is an odd number, and the electrode layer on the top layer is not connected to the first conductive sealing end 51 and the second conductive sealing end 52, which is used to provide shielding. This design can reduce electromagnetic interference between the capacitor and other components, especially in high-frequency applications. The shielding effect of the top electrode layer helps to maintain the stable performance of the capacitor and reduce electromagnetic interference to the outside world.

[0044] The third embodiment provides a multi-layer electrode connection method for forming a multi-layer electrode connection structure described in any one of the above embodiments, including: S1, providing a substrate 1, and forming an electrode layer on its upper surface; S2, performing an etching process on the electrode layer located on the surface so that the electrode layer is divided into a first area and a second area by the etching grooves; S3, forming a dielectric layer on the surface of the electrode layer; forming an electrode layer on the upper surface of the dielectric layer; S4, after repeating S2-S3 several times, executing S2 again; the contours of adjacent etching grooves in N electrode layers do not intersect each other in the stacking direction, and N is a positive integer greater than 2.

[0045] like Figure 7 As shown, in some specific embodiments, S1 further includes: providing a substrate 1 having a groove 11 on its upper surface, wherein the electrode layer uniformly covers the inner wall of the groove 11 and the original substrate surface outside the groove 11. The original substrate surface is connected to the side wall of the groove 11 and protrudes from the bottom wall of the groove 11.

[0046] In some embodiments, the etching groove is disposed on the original substrate surface outside the groove 11. In other embodiments, the etching groove is disposed inside the groove 11, and the etching direction of the etching groove is along the vertical Z direction. In still other embodiments, the etching groove is disposed inside the groove 11, and the etching direction of the etching groove is along the horizontal X direction or the reverse X direction.

[0047] It is worth noting that the electrode layer and the dielectric layer are formed by at least one process of atomic layer deposition (ALD) or chemical vapor deposition (CVD). In this embodiment, by repeatedly executing steps S2 and S3, a new layer is deposited on the basis of the previous electrode and dielectric layers each time, thereby realizing the layer-by-layer accumulation of a multilayer electrode structure. This process demonstrates a high degree of repeatability and control accuracy, and supports large-scale industrial production of complex multilayer structures.

[0048] In the first example, a silicon substrate 1 with a size of 1 cm*1 cm is patterned and etched by reactive ion etching to form a groove 11 with a width of 50 microns and a depth of 40 microns. S1 includes: depositing 20 nanometers of titanium nitride (TiN) as the odd-numbered first electrode layer 21 on the surface of the silicon wafer by atomic layer deposition.

[0049] like Figure 8 As shown, when S2 is executed for the first time, it also includes: etching the odd-numbered first electrode layer 21 at the first edge located in the opposite direction of X to form an odd-numbered first electrode layer etching groove 201, dividing the odd-numbered first electrode layer 21 into an odd-numbered first electrode layer positive electrode region 211 and an odd-numbered first electrode layer negative electrode region 212.

[0050] like Fig. 9 As shown, when S3 is performed for the first time, it also includes: S31, using an atomic layer deposition process to deposit 50nm of zirconium oxide or hafnium oxide on the surface of the odd-numbered first electrode layer 21 as the first dielectric layer 41. Fig.10 As shown, 50 nm of titanium nitride is deposited on the first dielectric layer 41 using an atomic layer deposition process as the odd-numbered second electrode layer 31 .

[0051] like Fig.11 As shown, the second execution of S2 also includes: S41, etching the odd-numbered second electrode layer 31 at the second edge located in the X direction to form an odd-numbered second electrode layer etching groove 301, dividing the odd-numbered second electrode layer 31 into an odd-numbered second electrode layer positive electrode region 311 and an odd-numbered second electrode layer negative electrode region 312.

[0052] like Fig.12As shown, the second execution of S3 also includes: S42, using chemical vapor deposition process to deposit 10nm zirconium oxide or hafnium oxide on the surface of the odd-numbered second electrode layer 31 as the second dielectric layer 42. Using atomic layer deposition process to deposit 20nm titanium nitride on the second dielectric layer 42 as the even-numbered first electrode layer 22.

[0053] The third execution of S2 also includes: S43, etching the even-numbered first electrode layer 22 at the first edge located in the X direction to form an even-numbered first electrode layer etching groove 202, dividing the even-numbered first electrode layer 22 into an even-numbered first electrode layer positive electrode region 221 and an even-numbered first electrode layer negative electrode region 222.

[0054] The third execution of S3 further includes: S44, using an atomic layer deposition process to deposit 50nm of zirconium oxide or hafnium oxide on the surface of the even-numbered first electrode layer 22 as a third dielectric layer 43. Using an atomic layer deposition process to deposit 50nm of titanium nitride on the third dielectric layer 43 as an even-numbered second electrode layer 32.

[0055] The fourth execution of S2 also includes: S45, etching the even-numbered second electrode layer 32 at the second edge located in the X direction to form an even-numbered second electrode layer etching groove 302, dividing the even-numbered second electrode layer 32 into an even-numbered second electrode layer positive electrode region 321 and an even-numbered second electrode layer negative electrode region 322.

[0056] The fourth execution of S3 further includes: S46, depositing 50 nm of zirconium oxide or hafnium oxide as a fourth dielectric layer on the surface of the even-numbered second electrode layer 32 using a chemical vapor deposition process.

[0057] The fourth dielectric layer is used as substrate 1, and the above S1-S46 are repeated 10 times to form the silicon-based multilayer electrode connection structure in the first example. This example uses a combination of atomic layer deposition and chemical vapor deposition to accurately control the thickness and quality of the dielectric layer (such as zirconium oxide, hafnium oxide), ensuring the effective use of high dielectric constant materials, thereby improving the energy density and efficiency of the capacitor. Titanium nitride is selected as the electrode material, thanks to its excellent conductivity and thermal stability. In combination with high dielectric constant materials, it significantly improves the capacitance performance and thermal stability of the device, and adapts to the needs of high-performance electronic devices.

[0058] In the second example, a silicon substrate 1 with a size of 1 cm*1 cm is patterned and etched by reactive ion etching to form a groove 11 with a width of 60 microns and a depth of 80 microns. Atomic layer deposition is used to deposit 200 nanometers of metal tungsten on the surface of the silicon wafer as the odd-numbered first electrode layer 21.

[0059] like Figure 8As shown, when S2 is executed for the first time, it also includes: etching the odd-numbered first electrode layer 21 at the first edge located in the opposite direction of X to form an odd-numbered first electrode layer etching groove 201, dividing the odd-numbered first electrode layer 21 into an odd-numbered first electrode layer positive electrode region 211 and an odd-numbered first electrode layer negative electrode region 212.

[0060] like Fig. 9 As shown, when S3 is performed for the first time, it also includes: S31, using a chemical vapor deposition process to deposit 20nm of silicon oxide on the surface of the odd-numbered first electrode layer 21 as the first dielectric layer 41. Fig.10 As shown, a 300 nm thick metal tungsten is deposited on the first dielectric layer 41 by using a chemical vapor deposition process as the odd-numbered second electrode layer 31 .

[0061] like Fig.11 As shown, the second execution of S2 also includes: S41, etching the odd-numbered second electrode layer 31 at the second edge located in the X direction to form an odd-numbered second electrode layer etching groove 301, dividing the odd-numbered second electrode layer 31 into an odd-numbered second electrode layer positive electrode region 311 and an odd-numbered second electrode layer negative electrode region 312.

[0062] like Fig.12 As shown, the second execution of S3 further includes: S42, using chemical vapor deposition process to deposit 100nm silicon oxide on the surface of the odd-numbered second electrode layer 31 as the second dielectric layer 42. Depositing 200nm of metal tungsten on the second dielectric layer 42 as the even-numbered first electrode layer 22.

[0063] The third execution of S2 also includes: S43, etching the even-numbered first electrode layer 22 at the first edge located in the X direction to form an even-numbered first electrode layer etching groove 202, dividing the even-numbered first electrode layer 22 into an even-numbered first electrode layer positive electrode region 221 and an even-numbered first electrode layer negative electrode region 222.

[0064] The third execution of S3 further includes: S44, using chemical vapor deposition to deposit 20 nm silicon oxide as the third dielectric layer 43 on the surface of the even-numbered first electrode layer 22. Using chemical vapor deposition to deposit 300 nm titanium nitride as the even-numbered second electrode layer 32 on the third dielectric layer 43.

[0065] The fourth execution of S2 also includes: S45, etching the even-numbered second electrode layer 32 at the second edge located in the X direction to form an even-numbered second electrode layer etching groove 302, dividing the even-numbered second electrode layer 32 into an even-numbered second electrode layer positive electrode region 321 and an even-numbered second electrode layer negative electrode region 322.

[0066] The fourth execution of S3 further includes: S46, using a chemical vapor deposition process to deposit 100 nm of zirconium oxide or hafnium oxide as a fourth dielectric layer on the surface of the even-numbered second electrode layer 32.

[0067] The fourth dielectric layer is used as substrate 1, and the above S1-S46 are repeated 15 times to form the silicon-based multilayer electrode connection structure in the second example. Compared with other metals and alloys, metal tungsten has higher conductivity and better corrosion resistance, which not only enhances the conductivity of the electrode, but also may improve the overall stability and service life of the device. The chemical vapor deposition process is used for the first time in S3 to deposit 20nm silicon oxide as the first dielectric layer 41, and the subsequent changes in the thickness of the dielectric layer (for example, 100nm silicon oxide of the second dielectric layer 42) can adjust different dielectric materials and thicknesses to optimize the capacitance characteristics and leakage current, so as to achieve the goal of higher energy density or lower leakage.

[0068] In some embodiments, S4 further includes: cutting or grinding edges of the stacked electrode layers to expose the first region and the second region of the electrode layers.

[0069] In some specific embodiments, the edges of the stacked electrode layers are first cut and polished so that the first region of the electrode layer exposes a flat cross-section at the first edge on the X-opposite side, and the second region of the electrode layer exposes a flat cross-section at the second edge on the X-direction side. This embodiment ensures that the edges of the first region and the second region on the X-opposite side and the X-direction side present a flat cross-section by cutting and subsequently polishing the edges of the stacked electrode layers. This processing method improves the edge neatness of the electrode structure, reduces the risk of electric field concentration or short circuit caused by rough edges, and improves the reliability and electrical performance of the device.

[0070] In some embodiments, the process further includes S5, forming a first conductive sealing end portion 51 for connecting a first region in each electrode layer, and forming a second conductive sealing end portion 52 for connecting a second region in each electrode layer.

[0071] In some specific embodiments, the first conductive sealing end 51 and the second conductive sealing end 52 are formed by electroplating using graphite slurry. In this embodiment, the conductive sealing end 5 formed by the electroplating process using graphite slurry can significantly enhance the conductivity of the electrical connection between the electrode layers, ensure efficient current transmission, and reduce resistance loss, which is particularly critical for improving the overall electrical performance of the capacitor. Graphite material has good conductivity and stability, and the formed sealing end can effectively resist the influence of environmental factors on the electrical connection part, increasing the long-term stability and durability of the device. The conductive sealing end is formed by deposition using an electroplating process, and the thickness and uniformity of the deposited layer can be accurately controlled, which is suitable for mass production, and can simplify the manufacturing process of the conductive sealing end, improve production efficiency and reduce costs.

[0072] Although the embodiments of the present invention are described in detail above, it is obvious to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein may have other embodiments and may be implemented or realized in a variety of ways.

Claims

1. A multi-layer electrode connection structure, applied to an on-chip capacitor, characterized in that: include: A substrate for providing an attachment surface for the electrode layer located at the bottom layer; An electrode layer having an etched groove for providing a conductive first region and a conductive second region; The contours of adjacent etched grooves in the N-layer electrode layer do not intersect each other in the stacking direction, and N is a positive integer greater than 2; The dielectric layer is located between adjacent electrode layers and is used to provide an insulating dielectric.

2. The multi-layer electrode connection structure according to claim 1, characterized in that: The electrode layer is set to be M layers, where M is greater than or equal to N. When M is equal to N, the contours of the etched grooves in the N-layer electrode layer do not intersect each other in the stacking direction.

3. The multi-layer electrode connection structure according to claim 2, characterized in that: When M is greater than N, the contours of the etched grooves in the electrode layer within the N layer intersect with the contours of the etched grooves in the electrode layer outside the N layer.

4. The multi-layer electrode connection structure according to claim 1, characterized in that: The electrode layer has a first edge and a second edge opposite to each other, and the etching grooves in two adjacent electrode layers are respectively close to the first edge and the second edge, so that the first areas and the second areas in the adjacent electrode layers overlap alternately.

5. The multi-layer electrode connection structure according to claim 4, characterized in that: The substrate is provided with a groove; the width of the groove is greater than the width of the etching groove.

6. The multi-layer electrode connection structure according to claim 5, characterized in that: A plurality of the grooves are distributed on the substrate surface in a self-similar patterned array; the shape of the grooves includes at least one of a strip, a rectangle, and a circle.

7. An on-chip capacitor, characterized in that: include: The multilayer electrode connection structure according to any one of claims 1 to 6, and: A first conductive sealing end portion, used to connect the first region in each electrode layer; The second conductive sealing end portion is used to connect the second region in each electrode layer; the first conductive sealing end portion and the second conductive sealing end portion are isolated from each other.

8. A multi-layer electrode connection method for forming a multi-layer electrode connection structure according to any one of claims 1 to 6, characterized in that: include: S1, providing a substrate and forming an electrode layer on the upper surface thereof; S2, performing an etching process on the electrode layer located on the surface, so that the electrode layer is divided into a first area and a second area by the etching grooves; S3, forming a dielectric layer on the surface of the electrode layer; forming an electrode layer on the upper surface of the dielectric layer; S4, after repeating S2-S3 for several times, S2 is executed again; the contours of adjacent etching grooves in the N-layer electrode layer do not intersect each other in the stacking direction, and N is a positive integer greater than 2.

9. The multi-layer electrode connection method according to claim 8, characterized in that: S4 further includes: cutting or grinding edges of the stacked electrode layers to expose the first region and the second region of the electrode layers.

10. The multi-layer electrode connection method according to claim 9, characterized in that: The method further includes S5, forming a first conductive sealing end portion for connecting the first region in each electrode layer, and forming a second conductive sealing end portion for connecting the second region in each electrode layer.

11. The multi-layer electrode connection method according to claim 10, characterized in that: The electrode layer and the dielectric layer are respectively formed by at least one of atomic layer deposition and chemical vapor deposition processes; the first conductive sealing end portion and the second conductive sealing end portion are formed by an electroplating process.

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