A fast recovery diode with modulated carrier distribution and a method of manufacturing the same

Abstract

The application discloses a fast recovery diode capable of modulating carrier distribution and a preparation method thereof, and relates to the technical field of semiconductors. The method comprises the following steps: depositing an epitaxial layer on an N-type substrate, and injecting acceptor-type impurities on the front surface of the epitaxial layer; growing an oxide layer on the surface of the epitaxial layer, and opening a window on the oxide layer; injecting donor-type impurities into the front surface of the epitaxial layer from the window and performing high-temperature diffusion treatment to obtain a first preparation piece; depositing a polysilicon layer on the surface of the first preparation piece, and obtaining a polysilicon field plate through photoetching; opening a source window on the oxide layer, and injecting acceptor-type impurities into the epitaxial layer from the window; injecting heavy metal impurities into the epitaxial layer and performing annealing to obtain a second preparation piece; depositing a metal electrode layer on the front and back surfaces of the second preparation piece; and coating polyimide on both sides of the front metal electrode layer to form a passivation layer. The preparation method can better control the range of the main junction region and the field limiting ring region, reduces the preparation cost, and is beneficial to chip size miniaturization and product stability.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a fast recovery diode with modulated carrier distribution and its fabrication method. Background Technology

[0002] Insulated-gate bipolar transistors (IGBTs) offer advantages such as high switching speed, high input impedance, low control power, and low losses, making them ideal switching devices in the power electronics field. The core technologies of IGBTs involve the design and production of IGBT chips and fast recovery diode chips. The fast recovery diode is often packaged with the IGBT, thus increasing the demands on it.

[0003] Fast recovery diodes can modulate the electric field distribution of power devices by setting a field-limiting ring, enabling the power devices to achieve ideal breakdown voltage levels. Current methods for fabricating field-limiting rings mainly involve coating the area outside the field-limiting ring region with photoresist, photolithographically lithographically processing the field-limiting ring region, then implanting ions and annealing to activate it to form the field-limiting ring. However, the range and dosage of implanted ions are easily affected by the size of the window on the photoresist layer and equipment fluctuations. Furthermore, existing field-limiting ring fabrication requires the addition of highly concentrated doped donor impurities in the terminal region of the substrate for electric field cutoff, thus placing greater demands on the terminal region and hindering chip miniaturization. Summary of the Invention

[0004] The purpose of this invention is to provide a fast recovery diode with modulated carrier distribution and its fabrication method, which can effectively control the range of the main junction region and the field limiting ring region, reduce fabrication costs, and facilitate the miniaturization of chip size and product stability.

[0005] The embodiments of the present invention are implemented as follows:

[0006] In one aspect, the present invention provides a method for fabricating a fast recovery diode with modulated carrier distribution, comprising:

[0007] An epitaxial layer is deposited on an N-type substrate, and acceptor impurities are implanted on the front side of the epitaxial layer. An oxide layer is grown on the surface of the epitaxial layer, and windows are formed in the non-main junction region and field confinement ring region of the N-type substrate corresponding to the oxide layer using photolithography. Donor impurities are implanted into the front side of the epitaxial layer through the windows, and the epitaxial layer is subjected to high-temperature diffusion treatment to ensure uniform diffusion of acceptor and donor impurities, thus obtaining a first fabrication. A polysilicon layer is deposited on the surface of the first fabrication, and a polysilicon field plate is obtained by photolithography. An active region window is formed in the active region of the N-type substrate corresponding to the oxide layer using photolithography, and acceptor impurities are implanted into the epitaxial layer through the active region window to form an ohmic contact region. Heavy metal impurities are implanted into the epitaxial layer and annealed to obtain a second fabrication. A front metal electrode layer is deposited on the front side and a back metal electrode layer is deposited on the back side of the second fabrication, wherein the front metal electrode layer is located at the top of the main junction region of the N-type substrate. Polyimide is coated on both sides of the front metal electrode layer to form a passivation layer, and the passivation layer is deposited on the polysilicon field plate.

[0008] Optionally, an oxide layer is grown on the surface of the epitaxial layer, including: forming a silicon dioxide layer on the surface of the epitaxial layer at a temperature environment below 1100°C.

[0009] Optionally, donor-type impurities are injected into the front side of the epitaxial layer through the window, and the epitaxial layer is subjected to high-temperature diffusion treatment, including: performing high-temperature diffusion treatment on the epitaxial layer at a temperature above 1100°C.

[0010] Optionally, heavy metal impurities are implanted into the epitaxial layer and then annealed, including: the heavy metal impurities being platinum or gold.

[0011] Optionally, depositing a front metal electrode layer on the front side and a back metal electrode layer on the back side of the second fabrication includes: depositing a metal layer on the front side of the second fabrication and removing the portion of the front metal layer other than the main junction region corresponding to the N-type substrate by photolithography.

[0012] Optionally, before depositing a front metal electrode layer on the front side and a back metal electrode layer on the back side of the second fabrication, the method further includes thinning the back side of the N-type substrate to a thickness of 200um-250um.

[0013] Optionally, a front metal electrode layer is deposited on the front side and a back metal electrode layer is deposited on the back side of the second fabrication, including: the front metal electrode layer is a titanium / nickel / silver metal layer deposited sequentially.

[0014] Optionally, the front metal electrode layer is deposited on the front side and the back metal electrode layer is deposited on the back side of the second fabrication, including: the front metal electrode layer is a deposited aluminum mixed metal layer, and the aluminum mixed metal layer is an aluminum-copper layer or an aluminum-silicon-copper layer.

[0015] Optionally, a front metal electrode layer is deposited on the front side and a back metal electrode layer is deposited on the back side of the second fabrication, including: the back metal electrode layer is a titanium / nickel / silver metal layer deposited sequentially.

[0016] In another aspect, the present invention provides a fast recovery diode with modulated carrier distribution, which is prepared by a method for preparing a fast recovery diode with modulated carrier distribution.

[0017] The beneficial effects of the present invention include at least one of the following:

[0018] This application provides a method for fabricating a fast recovery diode with modulated carrier distribution, comprising: depositing an epitaxial layer on an N-type substrate and implanting acceptor impurities on the front side of the epitaxial layer to ensure the dose stability of the acceptor impurities; growing an oxide layer on the surface of the epitaxial layer and creating windows in the non-main junction region and field-limiting ring region of the N-type substrate corresponding to the oxide layer using photolithography; implanting donor impurities into the front side of the epitaxial layer through the windows and performing high-temperature diffusion treatment on the epitaxial layer to ensure uniform diffusion of acceptor and donor impurities, thereby obtaining a first fabrication. This configuration ensures a stable diffusion range of acceptor impurities, thus eliminating the need for a cutoff ring, reducing production costs, and enabling miniaturization of the chip. The process involves: depositing a polycrystalline silicon layer on the surface of a first fabrication piece; obtaining a polycrystalline silicon field plate through photolithography; creating an active region window in the active region of the N-type substrate corresponding to the oxide layer using photolithography; implanting acceptor-type impurities into the epitaxial layer through the active region window to form an ohmic contact region; implanting heavy metal impurities into the epitaxial layer and annealing to obtain a second fabrication piece. The second fabrication piece avoids contamination of the active region and main junction region by impurity ions during the manufacturing process, improving product stability; depositing a front metal electrode layer on the front side and a back metal electrode layer on the back side of the second fabrication piece, wherein the front metal electrode layer is located at the top of the main junction region of the N-type substrate; coating polyimide on both sides of the front metal electrode layer to form a passivation layer, which is then deposited on the polycrystalline silicon field plate. This method for fabricating a fast recovery diode with modulated carrier distribution can effectively control the range of the main junction region and the field-limiting ring region, reduce fabrication costs, and facilitate chip miniaturization and product stability.

[0019] This application also provides a fast recovery diode with modulated carrier distribution, which is prepared by a method for fabricating fast recovery diodes with modulated carrier distribution. The aforementioned fast recovery diode with modulated carrier distribution exhibits good product stability and reliability, which is beneficial for achieving miniaturization of chip size. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 A flowchart illustrating the fabrication process of a fast recovery diode with modulated carrier distribution provided in an embodiment of the present invention;

[0022] Figure 2 One of the structural schematic diagrams of a fast recovery diode with modulated carrier distribution provided in an embodiment of the present invention;

[0023] Figure 3 This is a second schematic diagram of the fast recovery diode with modulated carrier distribution provided in an embodiment of the present invention;

[0024] Figure 4 This is the third schematic diagram of the fast recovery diode with modulated carrier distribution provided in an embodiment of the present invention.

[0025] Icons: 110 - N-type substrate; 111 - Main junction region; 112 - Field confinement ring; 113 - Ohmic contact region; 120 - Epitaxial layer; 130 - Oxide layer; 140 - Polysilicon field plate; 150 - Front metal electrode layer; 160 - Back metal electrode layer; 170 - Passivation layer. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0027] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0028] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0029] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this invention is in use. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention. In addition, the terms "first," "second," "third," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0030] Furthermore, terms such as "horizontal" and "vertical" do not imply that components must be absolutely horizontal or suspended, but rather that they can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal than "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0031] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0032] Please refer to Figure 1 This embodiment provides a method for fabricating a fast recovery diode with modulated carrier distribution, the specific fabrication steps of which are as follows:

[0033] Step S100: Deposit an epitaxial layer 120 on an N-type substrate 110 and implant acceptor-type impurities on the front side of the epitaxial layer 120;

[0034] Specifically, an epitaxial layer 120 can be deposited on an N-type substrate 110 using chemical vapor deposition. The epitaxial layer 120 acts as an isolation and buffer for the substrate, isolating impurities in the N-type substrate 110 and preventing subsequent fabrication processes from affecting the active region, thus ensuring the reliability of the fast recovery diode with modulated carrier distribution. After the epitaxial layer 120 is deposited on the N-type substrate 110, its surface can be cleaned to remove any particulate impurities, organic residues, and metallic impurities that may adhere to it, further improving the fabrication yield of the fast recovery diode with modulated carrier distribution.

[0035] Subsequently, acceptor impurities are implanted into the epitaxial layer 120, preferably boron. Since the entire surface of the epitaxial layer 120 is implanted with acceptor impurities, compared to the prior art method of first performing photolithography on the field limiting ring 112 region and then implanting ions, the dosage of acceptor impurities in this application can be precisely controlled, improving the fabrication yield and reliability of fast recovery diodes with modulated carrier distribution.

[0036] Step S200, as follows Figure 2 As shown, an oxide layer 130 is grown on the surface of the epitaxial layer 120, and windows are opened in the non-main junction region and the field confinement ring 112 region of the N-type substrate 110 corresponding to the oxide layer 130 by photolithography.

[0037] Specifically, an oxide layer 130 can be formed on the surface of the epitaxial layer 120 by methods such as thermal oxidation or chemical vapor deposition. The specific thickness of the oxide layer 130 can be controlled according to specific process requirements. The oxide layer 130 serves to provide electrical insulation, effectively preventing current flow and thus improving device performance and stability. It also provides a suitable working surface for subsequent photolithography processes, improving fabrication efficiency and reliability.

[0038] like Figure 2 As shown, windows are created in the non-main junction region of the oxide layer 130 corresponding to the N-type substrate 110 and the field confinement ring 112 region using photolithography. This facilitates the subsequent implantation of impurities within the windows to form the field confinement ring 112, effectively expanding the space of the electric field distribution and reducing the edge electric field strength, thereby improving the device's breakdown voltage performance. The size, shape, and number of windows can be adjusted according to fabrication requirements, and this application does not impose any limitations in this regard.

[0039] It should be noted that, in one possible embodiment of this application, the oxide layer 130 may be a silicon dioxide layer formed on the surface of the epitaxial layer 120 at a temperature environment below 1100°C.

[0040] Step S300: Inject donor-type impurities into the front side of epitaxial layer 120 through the window, and perform high-temperature diffusion treatment on epitaxial layer 120 to make acceptor-type impurities and donor-type impurities diffuse evenly, so as to obtain the first prepared part.

[0041] Specifically, the window opened in step S200 serves as a channel for impurity injection, ensuring that donor-type impurities are accurately introduced to the locations where electrical properties need to be altered. Preferably, the donor-type impurity is phosphorus.

[0042] When the epitaxial layer 120 is in a high-temperature environment, the atoms gain sufficient energy to achieve the diffusion of donor and acceptor impurities, thus obtaining the first fabricated part. Since the diffusion coefficient of boron is greater than that of phosphorus, under the same conditions, phosphorus can penetrate the impurity region where boron is located, ensuring the stability of the acceptor impurity position and forming a pn junction for voltage withstand; the uniform diffusion of acceptor and donor impurities optimizes the electrical properties of the epitaxial layer 120.

[0043] It should be noted that, in one possible embodiment of this application, step S300 requires high-temperature diffusion treatment of the epitaxial layer 120 at a temperature above 1100°C, so that the injected impurity atoms can be better integrated into the lattice structure of the semiconductor epitaxial layer 120 and thus be activated, while also helping to achieve a more uniform distribution of impurities throughout the epitaxial layer 120.

[0044] Step S400, as follows Figure 3 As shown, a polysilicon layer is deposited on the surface of the first fabrication, and a polysilicon field plate 140 is obtained by photolithography;

[0045] Specifically, a polycrystalline silicon layer can be deposited by chemical vapor deposition. Polycrystalline silicon possesses excellent electrical properties, such as tunable conductivity. Its electrical properties can be altered through doping and other methods, enabling it to effectively conduct or control electric fields. The polycrystalline silicon field plate 140 can extend the surface depletion region laterally to be wider than the bulk region, thereby improving the device's breakdown characteristics. The polycrystalline silicon field plate 140 is disposed in the non-main junction region.

[0046] Step S500, as follows Figure 3 As shown, an active region window is formed in the active region of the N-type substrate 110 corresponding to the oxide layer 130 by photolithography, and acceptor impurities are implanted into the epitaxial layer 120 through the active region window to form an ohmic contact region 113; optionally, the acceptor impurity is boron.

[0047] Step S600: Inject heavy metal impurities into the epitaxial layer 120 and anneal to obtain the second part;

[0048] Specifically, heavy metal impurities can produce unique electrical properties. After being implanted, these heavy metal impurities introduce special energy levels into the semiconductor lattice. These energy levels can act as recombination centers, effectively controlling the lifetime and recombination process of charge carriers. During the formation of the field confinement ring 112, this control over charge carrier recombination helps to adjust the electrical characteristics of the edge region of the epitaxial layer 120.

[0049] During ion implantation, high-speed impurity ions bombard the epitaxial layer 120, causing defects such as lattice atomic displacement and vacancies. Annealing is a heat treatment of the material at a certain temperature, allowing the atoms to gain sufficient energy to rearrange themselves and form field confinement rings 112, such as... Figure 3 As shown. After annealing, the heavy metal impurities are stabilized in the crystal lattice, and their distribution is optimized to some extent due to thermal motion. This optimized impurity distribution helps to form suitable electrical properties in the field-limiting ring 112 region.

[0050] Since ion implantation of the active region and field confinement ring 112 is performed before the implantation of heavy metal impurities, the possibility of impurity ions contaminating the active region and PN junction during the fabrication process can be reduced, thereby improving the stability of the fast recovery diode with modulated carrier distribution.

[0051] It should be noted that, in one specific embodiment of this application, the heavy metal impurity is platinum or gold. Platinum and gold can form effective recombination centers in semiconductor materials. When they are implanted into the epitaxial layer 120, they can capture electron-hole pairs and accelerate the carrier recombination process. During the formation of the field confinement ring 112, the role of these recombination centers is crucial for controlling the carrier lifetime and concentration in the edge region of the epitaxial layer 120. It also helps to adjust the electric field distribution at the edge of the epitaxial layer 120.

[0052] Step S700, as follows Figure 4 As shown, a front metal electrode layer 150 is deposited on the front side and a back metal electrode layer 160 is deposited on the back side of the second fabrication, wherein the front metal electrode layer 150 is located on top of the main junction region 111 of the N-type substrate 110.

[0053] Specifically, the deposition of the front metal electrode layer 150 and the back metal electrode layer 160 is typically achieved using physical vapor deposition or chemical vapor deposition techniques. For example... Figure 4 As shown, the front metal electrode layer 150 is located on top of the main junction region 111 of the N-type substrate. The main junction region 111 is a key part in the semiconductor device that realizes the main electrical functions. Depositing the metal electrode layer at this location can achieve good electrical contact, so as to effectively conduct the current generated in the main junction region 111 or inject charge carriers into the main junction region 111. Optionally, when fabricating the front metal electrode layer 150, a metal layer can be deposited on the front side of the second fabrication first, and the portion of the front metal layer other than the main junction region 111 corresponding to the N-type substrate 110 can be removed by photolithography to obtain the front metal electrode layer 150.

[0054] The back metal electrode layer 160 provides another electrical contact point, which, together with the front metal electrode layer 150, enables a complete electrical path.

[0055] It should be noted that, firstly, before depositing the front metal electrode layer 150 on the front side and the back metal electrode layer 160 on the back side of the second fabrication, the back side of the N-type substrate 110 can be thinned to a thickness of 200µm-250µm. By thinning the back side of the N-type substrate 110, the heat dissipation efficiency and reliability of the fast recovery diode with modulated carrier distribution can be improved.

[0056] Second, in one possible embodiment of this application, the front metal electrode layer 150 is a titanium / nickel / silver metal layer deposited sequentially. The titanium metal layer is deposited first. Titanium has good adhesion and diffusion barrier properties, so it can adhere tightly to the surface of the epitaxial layer 120, providing a stable and solid foundation for the deposition of subsequent metal layers; at the same time, the titanium metal layer can also effectively prevent other metal atoms from diffusing to the bottom layer, ensuring the stability and purity of the entire metal structure.

[0057] Next, a nickel metal layer is deposited. The nickel layer further enhances the bonding between the metal layers on top of the titanium layer and helps improve the overall electrical conductivity and corrosion resistance of the metal structure. The presence of the nickel layer allows the subsequently deposited silver metal layer to better utilize its excellent electrical conductivity.

[0058] Finally, a silver metal layer is deposited. Silver has extremely high conductivity, which provides a low-resistance current conduction path for the fast recovery diode with modulated carrier distribution during operation, ensuring the efficiency and stability of signal transmission, thereby improving the current carrying capacity of the fast recovery diode with modulated carrier distribution.

[0059] In another possible embodiment of this application, the front metal electrode layer 150 is a deposited aluminum mixed metal layer, which is either an aluminum-copper layer or an aluminum-silicon-copper layer. This is because the aluminum mixed metal layer can form good electrical contact with the semiconductor material, ensuring that current can be smoothly transmitted between the metal and the semiconductor without generating large contact resistance.

[0060] Third, in one possible embodiment of this application, the back metal electrode layer 160 may also be a titanium / nickel / silver metal layer deposited sequentially.

[0061] Step S800: Polyimide is coated on both sides of the front metal electrode layer 150 to form a passivation layer 170, and the passivation layer 170 is deposited on the polycrystalline silicon field plate 140.

[0062] Specifically, in order to provide some protection for the polycrystalline silicon field plate 140 and the field confinement ring 112, such as Figure 4As shown, a passivation layer 170 formed of polyimide is deposited on the non-main junction region of the N-type substrate 110. Polyimide has good insulation properties, which can effectively prevent abnormal conduction of charge between different metal layers or other areas of the chip, reduce the risk of leakage current, and ensure the stability of the chip's electrical performance.

[0063] The above-mentioned method for fabricating a fast recovery diode with modulated carrier distribution can effectively control the range of the main junction region 111 and the field limiting ring 112 region, reduce fabrication costs, and facilitate miniaturization of chip size and product stability.

[0064] Another aspect of this application embodiment provides a fast recovery diode with modulated carrier distribution, which is prepared by a method for preparing a fast recovery diode with modulated carrier distribution. The method for preparing the fast recovery diode with modulated carrier distribution has been described in detail above and will not be repeated here. The above-mentioned fast recovery diode with modulated carrier distribution exhibits good product stability and reliability, which is beneficial for achieving miniaturization of chip size.

[0065] The above description is merely an optional embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention can have various modifications and variations. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

[0066] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not describe the various possible combinations separately.

Claims

1. A method of fabricating a fast recovery diode with modulated carrier distribution, characterized in that, The method comprises the following steps: Depositing an epitaxial layer (120) on an N-type substrate (110), and implanting acceptor-type impurities on the front surface of the epitaxial layer (120); Growth of an oxide layer (130) on the surface of the epitaxial layer (120), and setting a window on the oxide layer (130) corresponding to the non-main junction area and field limiting ring (112) of the N-type substrate (110) by a photoetch process; Implanting donor-type impurities on the front surface of the epitaxial layer (120) through the window, and performing high-temperature diffusion treatment on the epitaxial layer (120) to make the acceptor-type impurities and the donor-type impurities uniformly diffuse, thereby obtaining a first preparation; Depositing a polysilicon layer on the surface of the first preparation, and obtaining a polysilicon field plate (140) by photoetching; Setting an active area window on the oxide layer (130) corresponding to the active area of the N-type substrate (110) by a photoetch process, and implanting acceptor-type impurities into the epitaxial layer (120) through the active area window to form an ohmic contact area (113); Implanting heavy metal impurities into the epitaxial layer (120) and annealing, thereby obtaining a second preparation; Depositing a front metal electrode layer (150) on the front surface of the second preparation and depositing a back metal electrode layer (160) on the back surface, wherein the front metal electrode layer (150) is located on the top of the main junction area (111) of the N-type substrate (110); Coating polyimide on both sides of the front metal electrode layer (150) to form a passivation layer (170), and the passivation layer (170) covers the polysilicon field plate (140).

2. The method of manufacturing a carrier distribution modulated fast recovery diode according to claim 1, wherein The growth of the oxide layer (130) on the surface of the epitaxial layer (120) comprises: Growth of a silicon dioxide layer on the surface of the epitaxial layer (120) in a temperature environment below 1100℃.

3. The method of manufacturing a carrier distribution modulated fast recovery diode according to claim 1, wherein The implanting of donor-type impurities on the front surface of the epitaxial layer (120) through the window and the high-temperature diffusion treatment on the epitaxial layer (120) comprise: Performing high-temperature diffusion treatment on the epitaxial layer (120) in a temperature environment above 1100℃.

4. The method of manufacturing a carrier distribution modulated fast recovery diode according to claim 1, wherein The implanting of heavy metal impurities into the epitaxial layer (120) and the annealing comprise: The heavy metal impurities are platinum or gold.

5. The method of manufacturing a carrier distribution modulated fast recovery diode according to claim 1, wherein The depositing of the front metal electrode layer (150) on the front surface of the second preparation and the depositing of the back metal electrode layer (160) on the back surface comprise: Depositing a metal layer on the front surface of the second preparation, and removing the metal layer on the front surface by a photoetch process except for the part corresponding to the main junction area (111) of the N-type substrate (110).

6. The method of fabricating a carrier distribution modulated fast recovery diode according to claim 1, wherein Before the depositing of the front metal electrode layer (150) on the front surface of the second preparation and the depositing of the back metal electrode layer (160) on the back surface, the method further comprises: Thinning the back surface of the N-type substrate (110) to a thickness of 200-250um.

7. The method of manufacturing a carrier distribution modulated fast recovery diode according to claim 1, wherein The depositing of the front metal electrode layer (150) on the front surface of the second preparation and the depositing of the back metal electrode layer (160) on the back surface comprise: The front metal electrode layer (150) is a titanium / nickel / silver metal layer deposited in sequence.

8. The method of manufacturing a carrier distribution modulated fast recovery diode according to claim 1, wherein The front surface of the second preparation piece is deposited with a front surface metal electrode layer (150), and the back surface is deposited with a back surface metal electrode layer (160), comprising: The front surface metal electrode layer (150) is a deposited aluminum mixed metal layer, and the aluminum mixed metal layer is a metal aluminum copper layer or a metal aluminum silicon copper layer.

9. The method of manufacturing a carrier distribution modulated fast recovery diode according to claim 1, wherein The front surface of the second preparation piece is deposited with a front surface metal electrode layer (150), and the back surface is deposited with a back surface metal electrode layer (160), comprising: The back surface metal electrode layer (160) is a titanium / nickel / silver metal layer deposited in sequence.

10. A fast recovery diode with modulated carrier distribution, characterized in that The fast recovery diode with modulated carrier distribution is prepared by the preparation method of any one of claims 1-9.

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