Semiconductor structure and forming method thereof

Abstract

Embodiments include hybrid complementary field effect transistors and unipolar transistors and methods of forming the same. In an embodiment, a semiconductor structure includes: a first semiconductor nanostructure; a second semiconductor nanostructure; a first isolation structure interposed between the first semiconductor nanostructure and the second semiconductor nanostructure; a first source / drain region extending laterally from an end of the first semiconductor nanostructure, the first source / drain region having a first conductivity type; a second source / drain region extending laterally from an end of the second semiconductor nanostructure, the second source / drain region having the first conductivity type, the second source / drain region being vertically aligned with the first source / drain region; and a first gate structure surrounding the first semiconductor nanostructure and the second semiconductor nanostructure. The embodiment of the invention also provides a method for forming the semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor structures and methods of forming the same. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers over a semiconductor substrate, and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of individual electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, additional issues arise that should be addressed. Summary of the invention

[0004] Some embodiments of the present invention provide a method for forming a semiconductor structure, the method comprising: forming a fin extending vertically from a substrate, the fin comprising a lower semiconductor nanostructure, an upper semiconductor nanostructure, and a pseudo semiconductor nanostructure arranged between the lower semiconductor nanostructure and the upper semiconductor nanostructure; etching a first groove and a second groove in the fin through the upper semiconductor nanostructure, the pseudo semiconductor nanostructure, and the lower semiconductor nanostructure, etching in the first groove to form a first sidewall of the upper semiconductor nanostructure and a second sidewall of the lower semiconductor nanostructure in the first groove, etching in the second groove to form a third sidewall of the upper semiconductor nanostructure and a fourth sidewall of the lower semiconductor nanostructure in the second groove; replacing the pseudo semiconductor nanostructure with a first isolation structure; growing a first lower semiconductor structure from the second sidewall and growing a second lower semiconductor structure from the fourth sidewall, the first lower semiconductor structure and the second lower semiconductor structure having a first conductivity type; and growing a first upper semiconductor structure from the first sidewall and growing a second upper semiconductor structure from the third sidewall, the first upper semiconductor structure having a second conductivity type opposite to the first conductivity type, and the second upper semiconductor structure having the first conductivity type.

[0005] Some other embodiments of the present invention provide a method for forming a semiconductor structure, the method comprising: etching a first groove and a second groove in a fin-shaped multilayer semiconductor stack, each of the first groove and the second groove dividing the fin-shaped multilayer semiconductor stack into a plurality of nanostructures; growing a first source / drain region in the first groove from an exposed end of a first nanostructure among the plurality of nanostructures, the first source / drain region having a first conductivity type; growing a second source / drain region in the second groove from an exposed end of a second nanostructure among the plurality of nanostructures, the second source / drain region having the first conductivity type; growing a third source / drain region in the first groove from an exposed end of a third nanostructure among the plurality of nanostructures, the third source / drain region having the first conductivity type, the third source / drain region being disposed directly above the first source / drain region; and growing a fourth source / drain region in the second groove from an exposed end of a fourth nanostructure among the plurality of nanostructures, the fourth source / drain region having a second conductivity type opposite to the first conductivity type, the fourth source / drain region being disposed directly above the second source / drain region.

[0006] Still other embodiments of the present invention provide a semiconductor structure comprising: a first semiconductor nanostructure; a second semiconductor nanostructure; a first isolation structure inserted between the first semiconductor nanostructure and the second semiconductor nanostructure; a first source / drain region extending laterally from an end of the first semiconductor nanostructure, the first source / drain region having a first conductivity type; a second source / drain region extending laterally from an end of the second semiconductor nanostructure, the second source / drain region having the first conductivity type, the second source / drain region being vertically aligned with the first source / drain region; and a first gate structure surrounding the first semiconductor nanostructure and the second semiconductor nanostructure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, aspects of the present disclosure can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1A to Figure 1B An example of a schematic diagram of a complementary field effect transistor (CFET) and a unipolar field effect transistor (UFET) in a three-dimensional view is shown in accordance with some embodiments.

[0009] Figures 2 to 18C is a diagram of an intermediate stage in the fabrication of a CFET and a UFET according to some embodiments.

[0010] Figures 19 to 31C are views of intermediate stages in the fabrication of CFETs and UFETs according to other embodiments.

[0011] Figures 32 to 38C are views of intermediate stages in the fabrication of CFETs and UFETs according to yet other embodiments.

[0012] FIG. 39A to FIG. 54C is a view of a continued intermediate stage in the fabrication of gate structures in CFETs and UFETs according to some embodiments.

[0013] Figures 55 to 59C is a diagram of an intermediate stage in the fabrication of a CFET and a UFET according to some other embodiments. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for implementing the different components of the present application. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an additional component that can be formed between the first component and the second component, so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0015] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0016] According to various embodiments, a stacked FET is formed. The stack includes a lower nanostructure FET and an upper nanostructure FET. A CFET is a stacked FET in which the upper nanostructure FET and the lower nanostructure FET have opposite conductivity. For example, the lower nanostructure FET can be a pFET device, and the upper nanostructure FET can be an nFET device (or vice versa). CFET is useful for certain device types that require complementary operation (such as SRAM), but some transistors that do not need to be in a complementary configuration are usually used. In this case, the upper nanostructure FET or the lower nanostructure FET can be considered as a pseudo FET and can not be used. However, the embodiment does not abandon these FETs, but provides the ability to form a unipolar FET (UFET) next to the CFET device. UFET is a stacked FET in which the upper nanostructure FET and the lower nanostructure FET have the same conductivity type. Therefore, both the upper nanostructure FET and the lower nanostructure FET can be used. Placing the UFET and the CFET next to each other produces a higher chip density, thereby reducing costs and providing better performance.

[0017] Figure 1A to Figure 1B An example of a UFET / CFET schematic is shown according to some embodiments. Figure 1A to Figure 1B It is a three-dimensional view, in which some components of the UFET / CFET are omitted for clarity of illustration. Figure 1A For example, a CFET portion is provided, and Figure 1B For example, a portion of UFET is provided.

[0018] UFET / CFET includes multiple vertically stacked nanostructured FETs (e.g., nanowire FET, nanosheet FET, multi-bridge channel (MBC) FET, nanoribbon FET, gate-all-around (GAA) FET, etc.). For example, CFET (see Figure 1A ) may include a lower nanostructure FET of a first device type (e.g., n-type / p-type) and an upper nanostructure FET of a second device type (e.g., p-type / n-type) opposite to the first device type. Specifically, CFET (see Figure 1A ) may include a lower PMOS transistor and an upper NMOS transistor, or a CFET may include a lower NMOS transistor and an upper PMOS transistor. For example, a UFET (see Figure 1B ) may include a lower nanostructure FET of a first device type (e.g., n-type / p-type) and an upper nanostructure FET also of the first device type (e.g., n-type). Specifically, UFET (see Figure 1B) may include a lower PMOS transistor and an upper PMOS transistor, or the UFET may include a lower NMOS transistor and an upper NMOS transistor. Each nanostructure FET includes a semiconductor nanostructure 66 (including a lower semiconductor nanostructure 66L and an upper semiconductor nanostructure 66U), wherein the semiconductor nanostructure 66 serves as a channel region of the nanostructure FET. The semiconductor nanostructure 66 may be a nanosheet, a nanowire, etc. The lower semiconductor nanostructure 66L is used for the lower nanostructure FET, and the upper semiconductor nanostructure 66U is used for the upper nanostructure FET. The channel isolation material ( Figure 1A to Figure 1B Not explicitly shown, see FIG. 54A to FIG. 54C ) may be used to separate the upper semiconductor nanostructure 66U from the lower semiconductor nanostructure 66L and electrically isolate the upper semiconductor nanostructure 66U from the lower semiconductor nanostructure 66L.

[0019] The gate dielectric 132 is along the top surface, sidewalls, and bottom surface of the semiconductor nanostructure 66. The gate electrode 134 (including the lower gate electrode 134L and the upper gate electrode 134U) is located above the gate dielectric 132 and around the semiconductor nanostructure 66. The gate electrode 134 for the UFET includes the lower gate electrode 134L located in the upper position. The source / drain region 108 (including the lower epitaxial source / drain region 108L and the upper epitaxial source / drain region 108U1 of the CFET, see Figure 1A , and the lower epitaxial source / drain region 108L and the upper epitaxial source / drain region 108U2 of the UFET, see Figure 1B ) are disposed at opposite sides of the gate dielectric 132 and the gate electrode 134. The source / drain region 108 may refer to the source or drain individually or collectively depending on the context. Isolation features may be formed to separate desired source / drain regions of the source / drain region 108 and / or desired gate electrodes of the gate electrode 134. For example, the lower gate electrode 134L may be optionally separated from the upper gate electrode 134U by an isolation layer (not shown separately). Alternatively, the lower gate electrode 134L may be coupled to the upper gate electrode 134U. In addition, the upper epitaxial source / drain region 108U may be separated from the upper gate electrode 134U by one or more dielectric layers ( Figure 1A to Figure 1B Not explicitly shown, see FIG. 54A to FIG. 54C ) is separated from the lower epitaxial source / drain region 108L. The isolation features between the channel region, gate, and source / drain regions allow vertical stacking of transistors, thereby improving device density. Due to the vertical stacking nature of the CFET, this schematic diagram may also be referred to as a stacked transistor or a folded transistor.

[0020] Figure 1A to Figure 1BReference cross sections used in subsequent figures are further illustrated. Cross section AA' is parallel to the longitudinal axis of the semiconductor nanostructure 66 of the CFET and in the direction of current flow, for example, between the source / drain regions 108 of the CFET. Cross section BB' is perpendicular to cross section AA' and along the longitudinal axis of the gate electrode 134 of the CFET. Cross section CC' is parallel to cross section BB' and extends through the source / drain regions 108 of the CFET. For clarity, subsequent figures refer to these reference cross sections.

[0021] Figures 2 to 54C is a diagram of an intermediate stage in fabricating a CFET and forming a metallization pattern for contacts to the CFET, according to some embodiments. Figure 2 , Figure 3 and Figure 4 Is displayed with Figure 1A to Figure 1B Similar 3D views of the 3D view.

[0022] Figure 5 , Fig. 6A , Figure 7 , Figure 8 , Fig. 9 , Fig. 10A , Fig.11 , Fig. 12A , Fig.13 , Fig.14 , Fig.15A , Fig.16A , Fig.17A , Fig.18A , Fig.19 , Fig. 20 , Fig.21 , Fig. 22 , Fig.23 , Fig.24 , Fig.25A , Fig.26 , Fig.27A , Fig.28A , Fig.29A , Fig. 30A , Fig.31A , Fig.32 , Fig.33 , Fig.34 , Fig.35A , Fig.36A , Fig.37A , Fig.38A , Fig.39A , Fig.40 , Fig.41A , Fig.42A , Fig.43A , Fig.44A , Fig.45A , Fig.46A , Fig.47A , Fig.48A , Fig.49A , Fig.50A , Fig.51A, Fig.52A , Fig.53A and Fig.54A Shows that along with Figure 1A to Figure 1B A cross-sectional view of a cross section similar to the reference cross section AA'. Figure 6B , Fig. 10B , Fig. 12B , Fig. 15B , Fig. 16B , Fig. 17B , Fig.18B , Fig.25B , Fig.27B , Fig.28B , Fig.29B , Fig. 30B , Fig.31B , Fig.35B , Fig.36B , Fig.37B , Fig.38B , Fig.39B , Fig.41B , Fig.42B , Fig.43B , Fig.44B , Fig.45B , Fig.46B , Fig.47B , Fig.48B , Fig.49B , Fig.50B , Fig.51B , Fig.52B , Fig.53B and Fig.54B Shows that along with Figure 1A to Figure 1B A cross-sectional view of a cross section similar to the reference cross section BB'. Figure 6C , Fig. 10C , Fig. 12C , Fig. 15C , Fig. 16C , Fig. 17C , Fig. 18C , Fig.25C , Fig.27C , Fig.28C , Fig.29C , Fig. 30C , Fig.31C , Fig.35C , Fig.36C , Fig.37C , Fig.38C , Fig.39C , Fig.41C , Fig.53C and Fig.54C Shows that along with Figure 1A to Figure 1B A cross-sectional view of a cross section similar to the reference cross section CC'.

[0023] exist Figure 2In the embodiment, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., with a p-type or n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a semiconductor material layer formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. An insulator layer is provided on a substrate core, generally on a silicon substrate or a glass substrate. Other substrates, such as multilayer substrates or gradient substrates may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; a compound semiconductor including carbon-doped silicon, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenide phosphide; or a combination thereof. For example, substrate 50 may be a multi-layer substrate including layers of semiconductor material formed on a silicon germanium layer, wherein the silicon germanium layer is provided on a substrate core (typically a silicon substrate or a glass substrate).

[0024] A multilayer stack 52 is formed over the substrate 50. The multilayer stack 52 includes alternating dummy layers 54 (including a first dummy layer 54A and a second dummy layer 54B) and semiconductor layers 56 (including a lower semiconductor layer 56L and an upper semiconductor layer 56U). A subset of the lower semiconductor layer 56L and the first dummy layer 54A is disposed below the second dummy layer 54B. Another subset of the upper semiconductor layer 56U and the first dummy layer 54A is disposed above the second dummy layer 54B. As described in more detail later, the dummy layer 54 will be removed and the semiconductor layer 56 will be patterned to form a channel region of the CFET / UFET. Specifically, the lower semiconductor layer 56L will be patterned to form a channel region of the lower nanostructure FET of the CFET / UFET, and the upper semiconductor layer 56U will be patterned to form a channel region of the upper nanostructure FET of the CFET / UFET.

[0025] The multilayer stack 52 is shown to include a specific number of dummy layers 54 and a specific number of semiconductor layers 56. It should be understood that the multilayer stack 52 may include any number of dummy layers 54 and semiconductor layers 56. Each layer of the multilayer stack 52 may be grown by a process such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), deposited by a process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), etc.

[0026] The first dummy layer 54A is formed of a first semiconductor material, and the second dummy layer 54B is formed of a second semiconductor material. The first semiconductor material and the second semiconductor material can be selected from candidate semiconductor materials of the substrate 50. The semiconductor materials of the first dummy layer 54A and the second dummy layer 54B will be described in more detail later. The first semiconductor material and the second semiconductor material have high etching selectivity to each other. In this way, in subsequent processing, the material of the second dummy layer 54B can be removed at a faster rate than the material of the first dummy layer 54A.

[0027] The semiconductor layer 56 (including the lower semiconductor layer 56L and the upper semiconductor layer 56U) is formed of one or more semiconductor materials. The semiconductor material can be selected from the candidate semiconductor material of the substrate 50. The lower semiconductor layer 56L and the upper semiconductor layer 56U can be formed of the same semiconductor material, or can be formed of different semiconductor materials. In some embodiments, the lower semiconductor layer 56L and the upper semiconductor layer 56U are both formed of semiconductor materials suitable for p-type devices and n-type devices (such as silicon). In some embodiments, the lower semiconductor layer 56L is formed of a semiconductor material suitable for p-type devices (such as germanium or silicon germanium), and the upper semiconductor layer 56U is formed of a semiconductor material suitable for n-type devices (such as silicon or carbon-doped silicon). The semiconductor material of the semiconductor layer 56 will be described in more detail later. The semiconductor material of the semiconductor layer 56 has a high etching selectivity relative to the semiconductor material of the dummy layer 54. In this way, in subsequent processing, the material of the dummy layer 54 can be removed at a faster rate than the material of the semiconductor layer 56.

[0028] Some layers of the multilayer stack 52 may be thicker than other layers of the multilayer stack 52. The thickness of the second dummy layer 54B may be different from (e.g., greater than or less than) the thickness of each first dummy layer 54A. In addition, the thickness of each semiconductor layer 56 may be different from (e.g., greater than or less than) the thickness of each dummy layer 54.

[0029] In some embodiments, the first dummy layer 54A is formed of silicon germanium (Ge percentage between 20% and 30%), the second dummy layer 54B is formed of silicon germanium with a high germanium concentration (Ge percentage between 40% and 60%), and the semiconductor layer 56 is formed of silicon. At this processing step, the silicon of the semiconductor layer 56 can be undoped or lightly doped, with dopants suitable for each layer, such as n-type dopants for the upper semiconductor layer 56U and p-type dopants for the lower semiconductor layer 56L, or vice versa. The n-type dopant can be phosphorus, arsenic, antimony, etc. The p-type dopant can be boron, boron fluoride, indium, etc. Using silicon germanium with a high concentration of germanium as the second dummy layer 54B allows the second dummy layer 54B to have a high etching selectivity relative to the first dummy layer 54A and the semiconductor layer 56. For example, the second dummy layer 54B can be at least partially replaced with an isolation structure. As part of the replacement process, the second dummy layer 54B can be removed with an etchant that is selective to the germanium-rich second dummy layer 54B. Accordingly, the second dummy layer 54B may be removed at a faster rate than the first dummy layer 54A and the semiconductor layer 56 .

[0030] exist Figure 3 In the embodiment of the present invention, semiconductor fins 62 are formed in substrate 50. In addition, nanostructures 64, 66 (including first pseudo nanostructures 64A, second pseudo nanostructures 64B, lower semiconductor nanostructures 66L, middle semiconductor nanostructures 66M, and upper semiconductor nanostructures 66U) are formed in multilayer stack 52. In some embodiments, nanostructures 64, 66 and fins 62 may be formed in multilayer stack 52 and substrate 50, respectively, by etching trenches in multilayer stack 52 and substrate 50. Etching may be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. Etching may be anisotropic. By etching the multilayer stack 52 to form the nanostructures 64, 66, the first pseudo nanostructure 64A may be defined from the first pseudo layer 54A, the second pseudo nanostructure 64B may be defined from the second pseudo layer 54B, the lower semiconductor nanostructure 66L may be defined from some lower semiconductor layers of the lower semiconductor layer 56L, the upper semiconductor nanostructure 66U may be defined from some upper semiconductor layers of the upper semiconductor layer 56U, and the intermediate semiconductor nanostructure 66M may be defined from some lower semiconductor layers 56L and some upper semiconductor layers 56U. The first pseudo nanostructure 64A and the second pseudo nanostructure 64B may also be collectively referred to as pseudo nanostructures 64. The lower semiconductor nanostructure 66L and the upper semiconductor nanostructure 66U may also be collectively referred to as semiconductor nanostructures 66.

[0031] As described in more detail later, individual nanostructures in the nanostructures 64, 66 will be removed to form the channel region of the CFET / UFET. Specifically, the lower semiconductor nanostructure 66L will serve as the channel region of the lower nanostructure FET of the CFET / UFET. In addition, the upper semiconductor nanostructure 66U will serve as the channel region of the upper nanostructure FET of the CFET / UFET.

[0032] The intermediate semiconductor nanostructure 66M is a semiconductor nanostructure 66 directly above / below (e.g., in contact with) the second pseudo nanostructure 64B. Depending on the height of the source / drain regions subsequently formed, the intermediate semiconductor nanostructure 66M may or may not be adjacent to any source / drain regions and may or may not be a functional channel region of the CFET / UFET. The second pseudo nanostructure 64B will subsequently be replaced by an isolation structure. The isolation structure and the intermediate semiconductor nanostructure 66M may define the boundaries of the lower nanostructure FET and the upper nanostructure FET.

[0033] The fins 62 and nanostructures 64, 66 may be patterned by any suitable method. For example, the fins 62 and nanostructures 64, 66 may be patterned using one or more lithography processes, including a double double patterning process or a multiple patterning process. Typically, a double patterning process or a multiple patterning process combines a lithography process with a self-aligned process, thereby allowing the creation of patterns having, for example, a smaller pitch than that obtainable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and the sacrificial layer is patterned using a lithography process. Using a self-aligned process, spacers are formed next to the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins 62 and nanostructures 64, 66. In some embodiments, a mask (or other layer) may remain on the nanostructures 64, 66.

[0034] Although the fin 62 and each of the nanostructures 64, 66 are shown as having a constant width throughout, in other embodiments, the fin 62 and / or the nanostructures 64, 66 may have tapered sidewalls such that the width of each of the fin 62 and / or the nanostructures 64, 66 continuously increases in a direction toward the substrate 50. In such embodiments, each of the nanostructures 64, 66 may have a different width and be trapezoidal in shape.

[0035] In addition, an isolation region 70 is formed above the substrate 50 and between adjacent fins 62. The isolation region 70 may include a liner and a filling material above the liner. Each of the liner and the filling material may include a dielectric material, such as an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), etc., or a combination thereof. The formation of the isolation region 70 may include depositing a dielectric material, and performing a planarization process such as a chemical mechanical polishing (CMP) process, a mechanical polishing process, etc. to remove excess portions of the dielectric material, such as portions located above the nanostructures 64 and 66. The deposition process may include ALD, high density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD), etc., or a combination thereof. In some embodiments, the isolation region 70 includes silicon oxide formed by an FCVD process followed by an annealing process. Then, the dielectric material is recessed to define the isolation region 70. The dielectric material may be recessed so that the upper portions of the fins 62 and the nanostructures 64 and 66 extend higher than the isolation region 70.

[0036] The foregoing process is merely one example of how the fin 62 and nanostructures 64, 66 may be formed. In some embodiments, the fin 62 and / or nanostructures 64, 66 may be formed using a mask and epitaxial growth process. For example, a dielectric layer may be formed above the top surface of the substrate 50, and a trench may be etched through the dielectric layer to expose the underlying substrate 50. The epitaxial structure may be epitaxially grown in the trench, and the dielectric layer may be recessed so that the epitaxial structure protrudes from the dielectric layer to form the fin 62 and / or nanostructures 64, 66. The epitaxial structure may include the alternating semiconductor materials previously described. In some embodiments of epitaxially grown epitaxial structures, the epitaxially grown material may be doped in situ during growth, which may avoid prior and / or subsequent implants, however in situ doping and implant doping may be used together.

[0037] In addition, appropriate wells (not shown separately) may be formed in the semiconductor nanostructure 66. For example, n-type dopant implantation and / or p-type dopant implantation may be performed, or the semiconductor material may be doped in situ during growth. The n-type dopant may be a concentration of 10 17 Atom / cm 3 Up to 10 19 Atom / cm 3 Any n-type dopant among those mentioned above within the range. The p-type dopant may be a concentration of 10 17 Atom / cm 3 Up to 10 19 Atom / cm 3The well in the lower semiconductor nanostructure 66L has a conductivity type opposite to that of the lower source / drain region (which will be formed later to be adjacent to the lower semiconductor nanostructure 66L). The well in the upper semiconductor nanostructure 66U has a conductivity type opposite to that of the upper source / drain region (which will be formed later to be adjacent to the upper semiconductor nanostructure 66U).

[0038] exist Figure 4 In the embodiment of the present invention, a dummy dielectric layer 72 is formed on the fin 62 and / or the nanostructure 64, 66. The dummy dielectric layer 72 may be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and the dummy dielectric layer 72 may be deposited or thermally grown according to an acceptable technique. A dummy gate layer 74 is formed over the dummy dielectric layer 72, and a mask layer 76 is formed over the dummy gate layer 74. The dummy gate layer 74 may be deposited over the dummy dielectric layer 72, and then the dummy gate layer 74 may be planarized, such as by CMP. The mask layer 76 may be deposited over the dummy gate layer 74. The dummy gate layer 74 may be a conductive or non-conductive material, and may be selected from a group including amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, and metal. The dummy gate layer 74 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing selected materials. The dummy gate layer 74 may be formed of other materials having high etching selectivity to insulating materials. The mask layer 76 may include, for example, silicon nitride, silicon oxynitride, etc. In the illustrated embodiment, the dummy dielectric layer 72 covers the isolation region 70 such that the dummy dielectric layer 72 extends between the dummy gate layer 74 and the isolation region 70. In another embodiment, the dummy dielectric layer 72 only covers the fins 62 and / or the nanostructures 64, 66.

[0039] exist Figure 5 In the embodiment of the present invention, the mask layer 76 can be patterned using acceptable photolithography and etching techniques to form a mask 86. The pattern of the mask 86 can then be transferred to the dummy gate layer 74 and the dummy dielectric layer 72 to form a dummy gate 84 and a dummy dielectric 82, respectively. The dummy gate 84 covers the corresponding channel region of the nanostructures 64, 66. The pattern of the mask 86 can be used to physically separate each dummy gate 84 from the adjacent dummy gates 84. The dummy gate 84 can also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of the corresponding semiconductor fin 62. After patterning, the mask 86 can be optionally removed, such as by any acceptable etching technique.

[0040] exist FIG. 6A to FIG. 6CIn the embodiment, gate spacers 90 are formed above the nanostructures 64, 66 and on the exposed sidewalls of the mask 86 (if present), the dummy gate 84, and the dummy dielectric 82. The gate spacers 90 can be formed by conformally forming one or more dielectric materials and then etching the dielectric materials. Acceptable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride oxide, etc., and the acceptable dielectric materials may be formed by deposition processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. Other dielectric materials formed by any acceptable process may be used. Any acceptable etching process (such as dry etching) may be performed to pattern the dielectric material. The etching may be anisotropic. When etching the dielectric material, the dielectric material may have portions remaining on the sidewalls of the dummy gate 84 (thus forming the gate spacers 90). As will be described in more detail later, when etching the dielectric material, the dielectric material may have portions remaining on the sidewalls of the fins 62 and / or nanostructures 64, 66 (thus forming the fin spacers 92, see Figure 6C ).

[0041] In addition, an implantation may be performed to lightly dope source / drain (LDD) regions (not shown separately). The LDD implantation may be performed prior to forming the gate spacer 90. Appropriate types of dopants may be implanted into the nanostructures 64, 66 to a desired depth. The conductivity type of the LDD region may be the same as the conductivity type of the source / drain region that will be subsequently formed adjacent to the semiconductor nanostructure 66. Additionally, the conductivity type of the LDD region in the lower semiconductor nanostructure 66L may be opposite to the conductivity type of the LDD region in the upper semiconductor nanostructure 66U. In some embodiments, the lower semiconductor nanostructure 66L has a p-type LDD region, and the upper semiconductor nanostructure 66U has an n-type LDD region. In some embodiments, the lower semiconductor nanostructure 66L has an n-type LDD region, and the upper semiconductor nanostructure 66U has a p-type LDD region. The n-type dopant may be any of the n-type dopants discussed previously, and the p-type dopant may be any of the p-type dopants discussed previously. The dopant concentration of the lightly doped source / drain region may be between 10 and 100 nm. 17 Atom / cm 3 Up to 10 20 Atom / cm 3 Annealing can be used to repair implant damage and activate implanted dopants. In some embodiments, the growing material of the nanostructures 64, 66 can be doped in situ during growth, which can avoid implantation, however in situ doping and implantation doping can be used together.

[0042] It should be noted that the previous disclosure generally describes the process of forming spacers and LDD regions. Other processes and sequences can be used. For example, fewer or additional spacers can be used, different step sequences can be used, additional spacers can be formed and removed, and the like.

[0043] Source / drain recesses 94 are formed in the fins 62, the nanostructures 64, 66, and the substrate 50. An epitaxial source / drain region will subsequently be formed in the source / drain recesses 94. The source / drain recesses 94 may extend through the nanostructures 64, 66 and into the substrate 50. The fins 62 may be etched so that the bottom surface of the source / drain recesses 94 is disposed above, below, or flush with the top surface of the isolation region 70. In the example shown, the top surface of the isolation region 70 is located above the bottom surface of the source / drain recesses 94. The source / drain recesses 94 may be formed by etching the fins 62, the nanostructures 64, 66, and the substrate 50 using an anisotropic etching process such as RIE, NBE, etc. During the etching process for forming the source / drain recesses 94, the gate spacers 90 and the dummy gates 84 mask portions of the fins 62, the nanostructures 64, 66, and the substrate 50. A single etching process or multiple etching processes may be used to etch each layer of nanostructures 64, 66 and / or fins 62. A timed etching process may be used to stop the etching of source / drain recesses 94 after the source / drain recesses 94 reach a desired depth.

[0044] exist Figure 7 In the embodiment of the present invention, an internal spacer 98 is formed on the sidewalls of the remaining portion of the first pseudo nanostructure 64A. As will be described in more detail later, a source / drain region will be formed in the source / drain recess 94, and the first pseudo nanostructure 64A will be replaced with a corresponding gate structure. The internal spacer 98 serves as an isolation component between the subsequently formed source / drain region and the subsequently formed gate structure. In addition, the internal spacer 98 can be used to prevent damage to the subsequently formed source / drain region by a subsequent etching process (such as an etching process for forming a gate structure). In addition, the second pseudo nanostructure 64B is replaced by an isolation structure 100, which is located between the intermediate semiconductor nanostructures 66M. The isolation structure 100 and the intermediate semiconductor nanostructure 66M will define the boundaries of the lower nanostructure FET and the upper nanostructure FET. The isolation structure 100 can have similar dimensions to the second pseudo nanostructure 64B that they replace.

[0045] As an example of forming an internal spacer 98 and an isolation structure 100, the sidewalls of the first pseudo nanostructure 64A exposed by the source / drain groove 94 can be recessed to form a sidewall groove. In addition, the second pseudo nanostructure 64B is removed to form an opening between the intermediate semiconductor nanostructure 66M, for example, between the lower semiconductor nanostructure 66L (commonly) and the upper semiconductor nanostructure 66U (commonly). The sidewalls of the first pseudo nanostructure 64A can be recessed to form a sidewall groove by any acceptable etching process. The etching is selective to the first pseudo nanostructure 64A (for example, the material of the first pseudo nanostructure 64A is selectively etched at a faster rate than the material of the semiconductor nanostructure 66). The etching can be isotropic. Although the sidewalls of the first pseudo nanostructure 64A are shown as being straight after etching, the sidewalls can be concave or convex. The openings located between the intermediate semiconductor nanostructures 66M can be formed by removing the second pseudo nanostructure 64B by any acceptable etching process. The etching is selective to the second pseudo nanostructure 64B (e.g., selectively etching the material of the second pseudo nanostructure 64B at a faster rate than the material of the semiconductor nanostructure 66). The etching may be isotropic. The pseudo gate 84 may adhere to and support the upper semiconductor nanostructure 66U so that the upper semiconductor nanostructure 66U does not collapse after forming an opening between the intermediate semiconductor nanostructures 66M. The intermediate semiconductor nanostructure 66M is exposed through the opening. In some embodiments, the etching process thins the intermediate semiconductor nanostructure 66M. Accordingly, the thickness of the intermediate semiconductor nanostructure 66M may be different from (e.g., less than) the thickness of the lower semiconductor nanostructure 66L and the thickness of the upper semiconductor nanostructure 66U.

[0046] In some embodiments, the same etching process is used to recess the sidewall of the first pseudo nanostructure 64A and remove the second pseudo nanostructure 64B. For example, the second pseudo nanostructure 64B can be completely removed without completely removing the first pseudo nanostructure 64A, and the first pseudo nanostructure 64A can be recessed without significantly recessing the semiconductor nanostructure 66. The etching process has selectivity between the materials of the first pseudo nanostructure 64A, the second pseudo nanostructure 64B, and the semiconductor nanostructure 66. Specifically, the etching process selectively etches the material of the first pseudo nanostructure 64A at a faster rate than the material of the semiconductor nanostructure 66, and also selectively etches the material of the second pseudo nanostructure 64B at a faster rate than the material of the first pseudo nanostructure 64A. Therefore, the etching rate of the first pseudo nanostructure 64A is less than the etching rate of the second pseudo nanostructure 64B and greater than the etching rate of the semiconductor nanostructure 66.

[0047] Then, an insulating material is conformally formed in the source / drain grooves 94, the sidewall grooves, and the openings between the intermediate semiconductor nanostructures 66M, and then the insulating material is etched. The insulating material can be a carbon-containing dielectric material, such as silicon oxynitride, silicon oxycarbon, silicon oxynitride, etc. Other low dielectric constant (low-k) materials with k values ​​less than about 3.5 can be used. The insulating material can be formed by a deposition process such as ALD, CVD, etc. The etching of the insulating material can be anisotropic. For example, the etching process can be a dry etch such as RIE, NBE, etc. When etching the insulating material, the insulating material has a portion retained in the sidewall grooves (thus forming the internal spacer 98), and has a portion retained in the opening between the intermediate semiconductor nanostructures 66M (thus forming the isolation structure 100).

[0048] Although the outer sidewalls of the inner spacers 98 and the isolation structures 100 are shown aligned with the sidewalls of the semiconductor nanostructures 66, the outer sidewalls of the inner spacers 98 and the isolation structures 100 may extend beyond or be recessed from the sidewalls of the semiconductor nanostructures 66. Thus, the inner spacers 98 and the isolation structures 100 may partially fill, completely fill, or overfill the sidewall recesses and the openings between the intermediate semiconductor nanostructures 66M, respectively. Moreover, although the sidewalls of the inner spacers 98 and the isolation structures 100 are shown as straight, those sidewalls may be concave or convex.

[0049] In addition, a sacrificial dielectric 102 is formed in the lower portion of the source / drain recess 94. The sacrificial dielectric 102 is disposed on the sidewalls of the lower semiconductor nanostructure 66L and some of the internal spacers 98. The sacrificial dielectric 102 may be formed by conformally forming a dielectric material and then recessing the dielectric material. Acceptable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride oxide, combinations thereof, and the like, and acceptable dielectric materials may be formed by deposition processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), and the like. Other dielectric materials formed by any acceptable process may be used. The dielectric material of the sacrificial dielectric 102 has a high etch selectivity relative to the dielectric material of the isolation structure 100. Any acceptable etching process such as dry etching, wet etching, or a combination thereof may be performed to recess the dielectric material. The etching may be isotropic, such as an etch-back process that removes the dielectric material from the upper portion of the source / drain recess 94. When the dielectric material is etched, the dielectric material has portions remaining in the lower portions of the source / drain recesses 94 (thereby forming the sacrificial dielectric 102 ).

[0050] exist Figure 8In the embodiment of the present invention, a dummy spacer 104 is formed above the sacrificial dielectric 102 and in the upper portion of the source / drain recess 94. The dummy spacer 104 is disposed on the sidewalls of the upper semiconductor nanostructure 66U, the intermediate semiconductor nanostructure 66M, the gate spacer 90, the isolation structure 100, and some of the internal spacers 98. The dummy spacer 104 can be formed by conformally forming a dielectric material and then etching the dielectric material. Acceptable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, aluminum oxide, combinations thereof, and the like, and acceptable dielectric materials may be formed by deposition processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), and the like. Other dielectric materials formed by any acceptable process may be used. The dielectric material of the dummy spacer 104 has a high etching selectivity relative to the dielectric material of the sacrificial dielectric 102 and the isolation region 70. In some embodiments, the dummy spacer and / or the sacrificial dielectric 102 each include carbon nitride silicon oxide, and the carbon content in each of the dummy spacer 104 and the sacrificial dielectric 102 can be selected to adjust the etching selectivity of the dummy spacer 104 and / or the sacrificial dielectric 102. In addition, although the dummy spacers 104 are each shown as a single layer having a uniform material composition, the dummy spacer 104 can have a multilayer structure including different layers of different dielectric materials. Any acceptable etching process, such as dry etching, can be performed to pattern the dielectric material. The etching can be anisotropic. The etching is selective to the dummy spacer 104 (for example, the material of the dummy spacer 104 is selectively etched at a faster rate than the material of the sacrificial dielectric 102). When etching the dielectric material, the dielectric material has a portion remaining on the sidewalls of the upper semiconductor nanostructure 66U, the intermediate semiconductor nanostructure 66M, the gate spacer 90, the isolation structure 100, and some internal spacers 98 (thereby forming the dummy spacer 104).

[0051] Figures 9 to 18C A process of forming source / drain regions of a CFET next to source / drain regions of a UFET is shown in accordance with some embodiments. Figures 19 to 31C Another process of forming source / drain regions of a CFET next to source / drain regions of a UFET according to other embodiments is shown. Figures 32 to 38C Another process of forming the source / drain region of the CFET next to the source / drain region of the UFET according to other embodiments is shown. The source / drain region of the CFET is formed in the CFET region 50C, while the source / drain region of the UFET is formed in the UFET region 50U. Although not shown separately, the CFET region 50C can be separated from the UFET region 50U. Any components can be arranged between the CFET region 50C and the UFET region 50U.

[0052] exist Fig. 9, the sacrificial dielectric 102 is removed from the source / drain recess 94. Any acceptable etching process, such as dry etching, wet etching, etc., or a combination thereof, may be performed to remove the sacrificial dielectric 102. The etching may be isotropic. The etching is selective to the sacrificial dielectric 102 (e.g., selectively etching the material of the sacrificial dielectric 102 at a faster rate than the material of the nanostructures 64, 66, the internal spacers 98, and the dummy spacers 104). Removing the sacrificial dielectric 102 exposes the sidewalls of the lower semiconductor nanostructure 66L, while the sidewalls of the upper semiconductor nanostructure 66U are still covered by the dummy spacers 104. In the illustrated embodiment, the dummy spacers 104 also cover the sidewalls of the intermediate semiconductor nanostructures 66M. In other embodiments, depending on the desired height of the subsequently formed source / drain regions, the height of the sacrificial dielectric 102 may be adjusted so that the dummy spacers 104 may expose the sidewalls of one or more of the intermediate semiconductor nanostructures 66M.

[0053] exist FIG. 10A to FIG. 10C , a lower epitaxial source / drain region 108L is formed in a lower portion of the source / drain recess 94. The lower epitaxial source / drain region 108L only partially fills the source / drain recess 94, so that the lower epitaxial source / drain region 108L contacts the lower semiconductor nanostructure 66L and does not contact the upper semiconductor nanostructure 66U. The dummy spacer 104 may mask the intermediate semiconductor nanostructure 66M and / or the upper semiconductor nanostructure 66U, so that the lower epitaxial source / drain region 108L only partially fills the source / drain recess 94 and is not formed on the upper semiconductor nanostructure 66U.

[0054] In some embodiments, the lower epitaxial source / drain regions 108L apply stress in the corresponding channel region of the lower semiconductor nanostructure 66L, thereby improving performance. The lower epitaxial source / drain regions 108L are formed in the source / drain recesses 94 so that each stack of the lower semiconductor nanostructures 66L is disposed between the lower epitaxial source / drain regions 108L of the corresponding adjacent pairs. In some embodiments, the internal spacers 98 are used to separate the lower epitaxial source / drain regions 108L from the first dummy nanostructure 64A by an appropriate lateral distance so that the lower epitaxial source / drain regions 108L do not short circuit with the gate of the resulting device formed subsequently.

[0055] A lower epitaxial source / drain region 108L is epitaxially grown in a lower portion of the source / drain recess 94. The lower epitaxial source / drain region 108L has a conductivity type suitable for the device type of the lower nanostructure FET. In some embodiments, the lower epitaxial source / drain region 108L is an n-type source / drain region. For example, if the lower semiconductor nanostructure 66L is silicon, the lower epitaxial source / drain region 108L may include a material that applies tensile strain to the lower semiconductor nanostructure 66L, such as silicon, carbon-doped silicon, phosphorus-doped silicon, silicon phosphide, silicon arsenide, etc. In some embodiments, the lower epitaxial source / drain region 108L is a p-type source / drain region. For example, if the lower semiconductor nanostructure 66L is silicon germanium, the lower epitaxial source / drain region 108L may include a material that applies compressive strain to the lower semiconductor nanostructure 66L, such as silicon germanium, boron-doped silicon germanium, boron-doped silicon, germanium, germanium tin, etc. The lower epitaxial source / drain regions 108L may have surfaces that are raised from the corresponding upper surfaces of the lower semiconductor nanostructures 66L and may have facets.

[0056] The lower epitaxial source / drain region 108L may be implanted with dopants to form source / drain regions, similar to the process previously discussed for forming lightly doped source / drain regions, followed by annealing. The source / drain region may have a dopant at 10 19 Atom / cm 3 Up to 10 21 Atom / cm 3 The n-type and / or p-type dopants used for the source / drain regions may be any of the dopants discussed previously. In some embodiments, the epitaxial source / drain regions 108L are doped in situ during growth.

[0057] Due to the epitaxial process used to form lower epitaxial source / drain region 108L, the upper surface of lower epitaxial source / drain region 108L has facets that extend laterally outward beyond the sidewalls of nanostructures 64, 66. Fig. 10C As shown, after the epitaxial process is completed, the adjacent lower epitaxial source / drain regions 108L remain separated. In other embodiments, these facets cause adjacent lower epitaxial source / drain regions 108L of the same nanostructure FET to merge (not shown separately). In the illustrated embodiment, fin spacers 92 are formed on the top surface of the isolation region 70, thereby blocking epitaxial growth. In some other embodiments, the fin spacers 92 can cover portions of the sidewalls of the nanostructures 64, 66 and / or semiconductor fins 62, thereby further blocking epitaxial growth. In another embodiment, the spacer etch used to form the gate spacer 90 is adjusted so as not to form the fin spacers 92 so as to allow the lower epitaxial source / drain regions 108L to extend to the surface of the isolation region 70.

[0058] The lower epitaxial source / drain region 108L may include one or more semiconductor material layers. For example, the lower epitaxial source / drain region 108L may include a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer. Any number of semiconductor material layers may be used for the lower epitaxial source / drain region 108L. Each of the first semiconductor material layer, the second semiconductor material layer, and the third semiconductor material layer may be formed of different semiconductor materials and may be doped to different dopant concentrations. In some embodiments, the first semiconductor material layer may have a dopant concentration that is less than the second semiconductor material layer and greater than the third semiconductor material layer. In an embodiment where the lower epitaxial source / drain region 108L includes three semiconductor material layers, the first semiconductor material layer may be grown from the lower semiconductor layer (e.g., the lower semiconductor nanostructure 66L), the second semiconductor material layer may be grown on the first semiconductor material layer, and the third semiconductor material layer may be grown on the second semiconductor material layer.

[0059] exist Fig.11 , the dummy spacer 104 is removed from the source / drain recess 94. Any acceptable etching process, such as dry etching, wet etching, etc., or a combination thereof, may be performed to remove the dummy spacer 104. The etching may be isotropic. The etching is selective to the dummy spacer 104 (e.g., selectively etches the material of the dummy spacer 104 at a faster rate than the material of the lower epitaxial source / drain region 108L and the isolation structure 100). Removing the dummy spacer 104 exposes the sidewalls of the upper semiconductor nanostructure 66U.

[0060] exist FIG. 12A to FIG. 12C In the embodiment of the present invention, a first interlayer dielectric (ILD) 114 is formed over the lower epitaxial source / drain region 108L, the gate spacer 90, the mask 86 (if present) or the dummy gate 84, and the isolation region 70. The first ILD 114 may be formed of a dielectric material that may be deposited by any suitable method, such as CVD, plasma enhanced chemical vapor deposition (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other dielectric materials formed by any acceptable process may be used.

[0061] In some embodiments, a first contact etch stop layer (CESL) 112 is formed between the first ILD 114 and the lower epitaxial source / drain regions 108L, the gate spacer 90, the mask 86 (if present) or the dummy gate 84, and the isolation region 70. The first CESL 112 may be formed of a dielectric material having a high etching selectivity relative to the dielectric material of the first ILD 114, such as silicon nitride, silicon oxide, silicon oxynitride, etc., and the first CESL 112 may be formed by any suitable deposition process such as CVD, ALD, etc.

[0062] exist Fig.13 In the embodiment of the present invention, the first ILD 114 and the first CESL 112 are recessed so that they are removed from the upper portion of the source / drain recess 94. After the recessing, the first ILD 114 only partially fills the source / drain recess 94 so that the sidewalls of the upper semiconductor nanostructure 66U are exposed. An etching process may be used to recess the first ILD 114 and the first CESL 112. The etching exposes the sidewalls of the upper semiconductor nanostructure 66U. In some embodiments, the first ILD 114 is etched using the first CESL 112 as an etch stop layer, and then the first CESL 112 is etched using the first ILD 114 as an etch mask.

[0063] exist Fig.14 In the embodiment of the present invention, a blocking liner 116 is formed over the region of the device where the UFET is to be formed, and the region of the device where the CFET is to be formed remains exposed. The blocking liner 116 can be formed by conformally forming a dielectric material and then etching the dielectric material to remove a portion of the dielectric material in the CFET region 50C. Acceptable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride oxide, aluminum oxide, combinations thereof, and the like, which may be formed by deposition processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), and the like. Other dielectric materials formed by any acceptable process may be used. After depositing the dielectric material of the blocking liner 116, the dielectric material may be patterned by forming a photomask over the UFET region 50U, developing the photomask to expose the dielectric material in the CFET region 50C, and then etching the dielectric material to remove the dielectric material in the CFET region 50C, thereby forming a blocking liner 116 in the UFET region 50U. The photomask may then be removed, for example, by an ashing technique. The blocking liner 116 may have a similar etch selectivity as the dummy spacer 104 discussed above.

[0064] exist FIG. 15A to FIG. 15CIn the embodiment of the present invention, an upper epitaxial source / drain region 108U1 is formed in an upper portion of the source / drain recess 94 in the CFET region 50C. On the other hand, the barrier liner 116 prevents growth from occurring in the UFET region 50U. The upper epitaxial source / drain region 108U1 only partially fills the source / drain recess 94 so that the upper epitaxial source / drain region 108U1 is in contact with the upper semiconductor nanostructure 66U and is not in contact with the lower semiconductor nanostructure 66L. The first ILD 114 can provide isolation between the upper epitaxial source / drain region 108U1 and the lower epitaxial source / drain region 108L.

[0065] In some embodiments, the upper epitaxial source / drain regions 108U1 apply stress in the corresponding channel region of the upper semiconductor nanostructure 66U, thereby improving performance. The upper epitaxial source / drain regions 108U1 are formed in the source / drain recesses 94 so that each stack of the upper semiconductor nanostructure 66U is disposed between the upper epitaxial source / drain regions 108U1 of the corresponding adjacent pairs. In some embodiments, the internal spacers 98 are used to separate the upper epitaxial source / drain regions 108U1 from the first dummy nanostructure 64A by an appropriate lateral distance so that the upper epitaxial source / drain regions 108U1 do not short-circuit with the gate of the resulting device formed subsequently.

[0066] An upper epitaxial source / drain region 108U1 is epitaxially grown in an upper portion of the source / drain recess 94 in the CFET region 50C. For example, the upper epitaxial source / drain region 108U1 may be laterally grown from the exposed sidewalls of the upper semiconductor nanostructure 66U. As the upper epitaxial source / drain region 108U1 grows in the source / drain recess 94, facets may be formed and adjacent growths may merge together to form the upper epitaxial source / drain region 108U1. The upper epitaxial source / drain region 108U1 has a conductivity type suitable for the device type of the upper nanostructure FET. The conductivity type of the upper epitaxial source / drain region 108U1 may be opposite to the conductivity type of the lower epitaxial source / drain region 108L. In other words, the upper epitaxial source / drain region 108U1 may be doped opposite to the lower epitaxial source / drain region 108L. In some embodiments, the upper epitaxial source / drain region 108U1 is an n-type source / drain region. For example, if the upper semiconductor nanostructure 66U is silicon, the upper epitaxial source / drain region 108U1 may include a material that applies tensile strain to the upper semiconductor nanostructure 66U, such as silicon, carbon-doped silicon, phosphorus-doped silicon, silicon phosphide, silicon arsenide, etc. In some embodiments, the upper epitaxial source / drain region 108U1 is a p-type source / drain region. For example, if the upper semiconductor nanostructure 66U is silicon germanium, the upper epitaxial source / drain region 108U1 may include a material that applies compressive strain to the upper semiconductor nanostructure 66U, such as silicon germanium, boron-doped silicon germanium, boron-doped silicon, germanium, germanium tin, etc. The upper epitaxial source / drain region 108U1 may have a surface that protrudes from the corresponding upper surface of the upper semiconductor nanostructure 66U and may have a small facet.

[0067] The upper epitaxial source / drain region 108U1 may be implanted with dopants to form a source / drain region, similar to the process previously discussed for forming a lightly doped source / drain region, followed by an anneal. In some embodiments, the anneal may be performed after depositing the upper epitaxial source / drain region 108U2 discussed below. The source / drain region may have a dopant at 10 19 Atom / cm 3 Up to 10 21 Atom / cm 3 The dopant concentration is within a range of . The n-type and / or p-type dopants used for the source / drain regions can be any of the dopants previously discussed. In some embodiments, the upper epitaxial source / drain regions 108U1 are doped in situ during growth. In the illustrated embodiment, the upper epitaxial source / drain regions 108U1 extend to the surface of the first ILD 114.

[0068] Due to the epitaxial process used to form the upper epitaxial source / drain region 108U1, the upper surface of the upper epitaxial source / drain region 108U1 has facets that extend laterally outward beyond the sidewalls of the nanostructures 64, 66. Fig. 15C As shown, after the epitaxial process is completed, adjacent upper epitaxial source / drain regions 108U1 remain separated. In other embodiments, these facets cause adjacent upper epitaxial source / drain regions 108U1 of the same nanostructure FET to merge (not shown separately), such as merging with adjacent upper epitaxial drain / source regions 108U1 (not shown separately).

[0069] The upper epitaxial source / drain region 108U1 may include one or more semiconductor material layers. For example, the upper epitaxial source / drain region 108U1 may include a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer. Any number of semiconductor material layers may be used for the upper epitaxial source / drain region 108U1. Each of the first semiconductor material layer, the second semiconductor material layer, and the third semiconductor material layer may be formed of a different semiconductor material and may be doped to a different dopant concentration. In some embodiments, the first semiconductor material layer may have a dopant concentration that is less than the second semiconductor material layer and greater than the third semiconductor material layer. In an embodiment where the upper epitaxial source / drain region 108U1 includes three semiconductor material layers, the first semiconductor material layer may be grown above the first ILD 114, the second semiconductor material layer may be grown on the first semiconductor material layer, and the third semiconductor material layer may be grown on the second semiconductor material layer.

[0070] The source / drain recess 94 in the CFET region 50C thus includes the upper epitaxial source / drain region 108U1, the first ILD 114, and the lower epitaxial source / drain region 108L. The first ILD 114 is located between the upper epitaxial source / drain region 108U1 and the lower epitaxial source / drain region 108L. The lower epitaxial source / drain region 108L is used for the lower nanostructure FET of the CFET, and the upper epitaxial source / drain region 108U1 is used for the upper nanostructure FET of the CFET. Therefore, the first ILD 114 acts as an isolation region to prevent short circuits of the lower nanostructure FET and the upper nanostructure FET. The source / drain recess 94 in the UFET region 50U includes the first ILD 114 and the lower epitaxial source / drain region 108L. The upper epitaxial source / drain region 108U2 is described below for the UFET region 50U.

[0071] exist FIG. 16A to FIG. 16CIn the embodiment of the present invention, the blocking liner 116 is removed from the source / drain recess 94 in the UFET region 50U. Any acceptable etching process, such as dry etching, wet etching, etc., or a combination thereof, may be performed to remove the blocking liner 116. The etching may be isotropic. The etching is selective to the blocking liner 116. Removing the blocking liner 116 exposes the sidewalls of the upper semiconductor nanostructure 66U in the UFET region 50U.

[0072] After removing the blocking liner 116, a blocking liner 118 is formed over the upper epitaxial source / drain region 108U1 in the CFET region 50C. The blocking liner 118 prevents additional epitaxial growth of the upper epitaxial source / drain region 108U1 during the deposition of the upper epitaxial source / drain region 108U2 discussed below. The blocking liner 118 can be formed by depositing a dielectric material and then patterning the dielectric material to expose the end of the upper semiconductor nanostructure 66U in the UFET region 50U. The blocking liner 118 can be deposited and patterned using a process and material similar to that of the blocking liner 116.

[0073] exist FIG. 17A to FIG. 17C In the embodiment of the present invention, an upper epitaxial source / drain region 108U2 is formed in an upper portion of the source / drain recess 94 in the UFET region 50U. On the other hand, the barrier liner 118 prevents growth from occurring in the CFET region 50C. The upper epitaxial source / drain region 108U2 only partially fills the source / drain recess 94 so that the upper epitaxial source / drain region 108U2 is in contact with the upper semiconductor nanostructure 66U and is not in contact with the lower semiconductor nanostructure 66L. The first ILD 114 can provide isolation between the upper epitaxial source / drain region 108U2 and the lower epitaxial source / drain region 108L.

[0074] In some embodiments, the upper epitaxial source / drain regions 108U2 apply stress in the corresponding channel regions of the upper semiconductor nanostructure 66U, thereby improving performance. The upper epitaxial source / drain regions 108U2 are formed in the source / drain recesses 94 so that each stack of the upper semiconductor nanostructure 66U is disposed between the upper epitaxial source / drain regions 108U2 of the corresponding adjacent pairs. In some embodiments, the internal spacers 98 are used to separate the upper epitaxial source / drain regions 108U2 from the first dummy nanostructure 64A by an appropriate lateral distance so that the upper epitaxial source / drain regions 108U2 are not short-circuited with the gate of the resulting device formed subsequently.

[0075] An upper epitaxial source / drain region 108U2 is epitaxially grown in an upper portion of the source / drain recess 94 in the UFET region 50U. For example, the upper epitaxial source / drain region 108U2 may be laterally grown from the exposed sidewalls of the upper semiconductor nanostructure 66U. As the upper epitaxial source / drain region 108U2 grows in the source / drain recess 94, a facet may be formed and the adjacent growths may merge together to form the upper epitaxial source / drain region 108U2. The upper epitaxial source / drain region 108U2 has a conductivity type suitable for the device type of the upper nanostructure FET. Because the UFET region 50U provides a unipolar stacked transistor, the conductivity type of the upper epitaxial source / drain region 108U2 is the same as the conductivity type of the lower epitaxial source / drain region 108L. In other words, the upper epitaxial source / drain region 108U2 may be doped with the same conductivity type as the lower epitaxial source / drain region 108L. In some embodiments, the upper epitaxial source / drain region 108U2 is an n-type source / drain region. For example, if the upper semiconductor nanostructure 66U is silicon, the upper epitaxial source / drain region 108U2 may include a material that applies tensile strain to the upper semiconductor nanostructure 66U, such as silicon, carbon-doped silicon, phosphorus-doped silicon, silicon phosphide, silicon arsenide, etc. In some embodiments, the upper epitaxial source / drain region 108U2 is a p-type source / drain region. For example, if the upper semiconductor nanostructure 66U is silicon germanium, the upper epitaxial source / drain region 108U1 may include a material that applies compressive strain to the upper semiconductor nanostructure 66U, such as silicon germanium, boron-doped silicon germanium, boron-doped silicon, germanium, germanium tin, etc. The upper epitaxial source / drain region 108U2 may have a surface that protrudes from the corresponding upper surface of the upper semiconductor nanostructure 66U and may have a small facet.

[0076] The upper epitaxial source / drain region 108U2 may be implanted with dopants to form source / drain regions, similar to the process previously discussed for forming lightly doped source / drain regions, followed by annealing. The source / drain region may have a 19 Atom / cm 3 Up to 10 21 Atom / cm 3 The dopant concentration is within a range of . The n-type and / or p-type dopants used for the source / drain regions can be any of the dopants previously discussed. In some embodiments, the upper epitaxial source / drain regions 108U2 are doped in situ during growth. In the illustrated embodiment, the upper epitaxial source / drain regions 108U2 extend to the surface of the first ILD 114.

[0077] Due to the epitaxial process used to form the upper epitaxial source / drain region 108U2, the upper surface of the upper epitaxial source / drain region 108U2 has facets that extend laterally outward beyond the sidewalls of the nanostructures 64, 66. Fig. 17C As shown, after the epitaxial process is completed, adjacent upper epitaxial source / drain regions 108U2 remain separated. In other embodiments, these facets cause adjacent upper epitaxial source / drain regions 108U2 of the same nanostructure FET to merge (not shown separately), for example, merge with adjacent upper epitaxial drain / source regions 108U2.

[0078] Similar to the upper epitaxial source / drain region 108U1 discussed above, the upper epitaxial source / drain region 108U2 may include one or more semiconductor material layers, which will not be described again herein.

[0079] The source / drain recess 94 in the UFET region 50U thus includes an upper epitaxial source / drain region 108U2, a first ILD 114, and a lower epitaxial source / drain region 108L. The first ILD 114 is located between the upper epitaxial source / drain region 108U2 and the lower epitaxial source / drain region 108L. The lower epitaxial source / drain region 108L is used for the lower nanostructure FET of the UFET, and the upper epitaxial source / drain region 108U2 is used for the upper nanostructure FET of the UFET. Therefore, the first ILD 114 can act as an isolation region to prevent short circuits of the lower nanostructure FET and the upper nanostructure FET. On the other hand, as shown and discussed below, the upper epitaxial source / drain region 108U2 and the lower epitaxial source / drain region 108L can then be electrically coupled together.

[0080] exist 18A to 18C In the embodiment of the present invention, the blocking liner 118 is removed from the source / drain recess 94 in the CFET region 50C. Any acceptable etching process, such as dry etching, wet etching, etc., or a combination thereof, may be performed to remove the blocking liner 118. The etching may be isotropic. The etching is selective to the blocking liner 118. After removing the blocking liner 118, the outer surfaces of the upper epitaxial source / drain region 108U1 and the upper epitaxial source / drain region 108U2 are exposed.

[0081] Figures 9 to 18C One process for forming upper epitaxial source / drain regions 108U2 for UFETs in the UFET region 50U is shown, wherein the upper epitaxial source / drain regions 108U2 are formed in a separate process from the lower epitaxial source / drain regions 108L. Figures 19 to 31CAnother process for forming the upper epitaxial source / drain region 108U2 for the UFET in the UFET region 50U is shown, wherein the lower epitaxial source / drain region 108L is formed in the same process as forming the upper epitaxial source / drain region 108U2. Fig.19 From Figure 8 The structure shown.

[0082] exist Fig.19 , after forming the dummy spacer 104, a sacrificial dielectric 105 is formed over the sacrificial dielectric 102. The sacrificial dielectric 105 is disposed on the sidewalls of the lower portion (adjacent intermediate semiconductor nanostructure 66M) of the dummy spacer 104 and may overlap with some of the internal spacers 98. The sacrificial dielectric 105 may be formed by conformally forming a dielectric material and then recessing the dielectric material. Acceptable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride oxide, combinations thereof, and the like, and acceptable dielectric materials may be formed by deposition processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), and the like. Other dielectric materials formed by any acceptable process may be used. The dielectric material of the sacrificial dielectric 105 has an etching selectivity relative to the dummy spacer 104. The dielectric material of the sacrificial dielectric 105 may be the same material or a different material as the sacrificial dielectric 102. Any acceptable etching process such as dry etching, wet etching, or a combination thereof may be performed to recess the dielectric material. The etching may be isotropic, such as an etch-back process that removes the dielectric material from the upper portion of the source / drain recesses 94. When the dielectric material is etched, the dielectric material has a portion remaining in the lower portion of the source / drain recesses 94 (thereby forming the sacrificial dielectric 105). The portion of the dummy spacer 104 located above the sacrificial dielectric 105 is exposed by recessing the dielectric material of the sacrificial dielectric 105.

[0083] exist Fig. 20In the embodiment of the present invention, a masking structure 105B is formed over the CFET region 50C to protect the dummy spacer 104. In the UFET region 50U, the dummy spacer 104 will be recessed in a subsequent process. The masking structure 105B can be any suitable mask, including a photoresist mask or a multilayer structure, including a photoresist mask and an upper hard mask, such as an inorganic material, such as an oxide or nitride of silicon or aluminum. In some embodiments, the masking structure 105B is a dielectric material having an etching selectivity relative to the dummy spacer 104. The masking structure 105B can be formed, patterned, and developed using a spin coating process to remain only in the CFET region 50C to protect the dummy spacer 104. Therefore, the masking structure 105B is removed from the UFET region 50U. The masking structure 105B can also be formed using other processes, such as by CVD, PVD, ALD, etc., or a combination thereof. Then, portions of the masking structure 105B can be removed from the UFET region 50U by an etching process.

[0084] exist Fig.21 , the exposed portion of the dummy spacer 104 is removed from the source / drain recess 94 in the UFET region 50U, leaving the lower dummy spacer 104A. Any acceptable etching process, such as dry etching, wet etching, etc., or a combination thereof, may be performed to remove the upper portion of the dummy spacer 104. The etching may be isotropic. The etching is selective to the material of the dummy spacer 104 (e.g., selectively etching the material of the dummy spacer 104 at a faster rate than the material of the sacrificial dielectric 105). For example, etching may also remove some of the sacrificial dielectric 105, such as to make the upper surface concave or dished. Removing the upper portion of the dummy spacer 104 in the UFET region 50U exposes the sidewalls of the upper semiconductor nanostructure 66U.

[0085] exist Fig. 22 , the masking structure 105B is removed. The masking structure 105B may be removed by any acceptable technique, such as by an etching process if the masking structure 105B is a dielectric material, or by an ashing process if the masking structure 105B is a photoresist.

[0086] exist Fig.23 , the sacrificial dielectric 105 is removed from the source / drain recess 94. Any acceptable etching process, such as dry etching, wet etching, etc., or a combination thereof, may be performed to remove the sacrificial dielectric 105. The etching may be isotropic. The etching is selective to the sacrificial dielectric 105 (e.g., selectively etches the material of the sacrificial dielectric 105 at a faster rate than the material of the dummy spacer 104). Removing the sacrificial dielectric 105 exposes the lower portion of the dummy spacer 104.

[0087] exist Fig.24, sacrificial dielectric 102 is removed from source / drain recess 94. In some embodiments, the removal of sacrificial dielectric 102 may be the same process as the removal process of sacrificial dielectric 105, while in other embodiments, the removal of sacrificial dielectric 102 may be a different process, such as by using a different etchant. Any acceptable etching process, such as dry etching, wet etching, etc., or a combination thereof, may be performed to remove sacrificial dielectric 102. The etching may be isotropic. The etching is selective to sacrificial dielectric 102 (e.g., selectively etching the material of sacrificial dielectric 102 at a faster rate than the material of nanostructures 64, 66, internal spacers 98, and dummy spacers 104). Removing sacrificial dielectric 102 exposes the sidewalls of lower semiconductor nanostructure 66L, while the sidewalls of upper semiconductor nanostructure 66U and middle semiconductor nanostructure 66M in CFET region 50C are still covered by dummy spacer 104, and the sidewalls of middle semiconductor nanostructure 66M in UFET region 50U are still covered by dummy spacer 104A. In the illustrated embodiment, the dummy spacer 104 also covers the sidewalls of the intermediate semiconductor nanostructures 66M. In other embodiments, depending on the desired height of the subsequently formed source / drain regions, the height of the sacrificial dielectric 102 and / or the sacrificial dielectric 105 can be adjusted so that the dummy spacer 104 can expose the sidewalls of one or more of the intermediate semiconductor nanostructures 66M.

[0088] exist FIG. 25A to FIG. 25C, a lower epitaxial source / drain region 108L is formed in the lower portion of the source / drain recess 94 in both the CFET region 50C and the UFET region 50U, and an upper epitaxial source / drain region 108U2 is simultaneously formed in the upper portion of the source / drain recess 94 in the UFET region 50U. For the intermediate semiconductor nanostructure 66M, the dummy spacer 104 prevents growth from occurring in the CFET region 50C, and the dummy spacer 104A prevents growth from occurring in the UFET region 50U. The lower epitaxial source / drain region 108L and the upper epitaxial source / drain region 108U2 can be grown using the materials and processes discussed above, which will not be repeated here. However, it should be noted that in the CFET region 50C, only the lower semiconductor nanostructures 66L are exposed, so growth will start from these lower semiconductor nanostructures 66L, while in the UFET region 50U, both the lower semiconductor nanostructures 66L and the upper semiconductor nanostructures 66U are exposed, so growth will occur from both the lower semiconductor nanostructures 66L and the upper semiconductor nanostructures 66U. The lower epitaxial source / drain region 108L and the upper epitaxial source / drain region 108U2 may include doping, as discussed above, respectively. Moreover, they may have respective facets and exert compressive or tensile forces on the channel region, as discussed above. Other features and properties of the lower epitaxial source / drain region 108L and the upper epitaxial source / drain region 108U2 also apply.

[0089] exist Fig.26 , remove the dummy spacers 104 and dummy spacers 104A. Any acceptable etching process, such as dry etching, wet etching, etc., or a combination thereof, may be performed to remove the dummy spacers 104 and dummy spacers 104A. The etching may be isotropic. The etching is selective to the dummy spacers 104 and 104A (e.g., selectively etching the material of the dummy spacers 104 and 104A at a faster rate than the material of the semiconductor nanostructures 66 and the internal spacers 98). Removing the dummy spacers 104 and 104A exposes the sidewalls of the upper semiconductor nanostructure 66U in the CFET region 50C.

[0090] exist FIG. 27A to FIG. 27C In the embodiment, a first interlayer dielectric (ILD) 114 is formed over the lower epitaxial source / drain regions 108L, the gate spacers 90, the mask 86 (if present) or the dummy gate 84, and the isolation regions 70. The same method as described above with respect to FIG. 12A to FIG. 12C The first ILD 114 is formed using processes and materials similar to those described above for the first ILD 114. Similarly, the first CESL 112 is formed between the first ILD 114 and the lower epitaxial source / drain regions 108L, the gate spacers 90, the mask 86 (if present) or the dummy gate 84, and the isolation regions 70. The same processes and materials as described above for the first ILD 114 may be used. FIG. 12A to FIG. 12C The first ILD 114 may be formed using processes and materials similar to those described above with respect to the first ILD 114. FIG. 12A to FIG. 12C The first CESL 112 is formed using processes and materials similar to those described above for forming the first CESL 112. However, it should be noted that the first CESL 112 surrounds the sides, top, and bottom of the upper epitaxial source / drain regions 108U2.

[0091] exist FIG. 28A to FIG. 28C In the embodiment of the present invention, the first ILD 114 and the first CESL 112 are recessed so that they are removed from the upper portion of the source / drain recess 94. After the recessing, the first ILD 114 only partially fills the source / drain recess 94 so that the sidewalls of the upper semiconductor nanostructure 66U are exposed in the CFET region 50C. An etching process may be used to recess the first ILD 114 and the first CESL 112. The etching exposes the sidewalls of the upper semiconductor nanostructure 66U. In some embodiments, the first ILD 114 is etched using the first CESL 112 as an etch stop layer, and then the first CESL 112 is etched using the first ILD 114 as an etch mask. It is noteworthy that after the recessing of the first ILD 114 and the first CESL 112, a portion of the first CESL 112 remains disposed below and in contact with the lower surface of the upper epitaxial source / drain region 108U2. The portion is embedded in the upper surface of the first ILD 114 .

[0092] exist FIG. 29A to FIG. 29C In the embodiment, a blocking liner 116 is formed over the UFET region 50U, while exposing the CFET region 50C. Specifically, the blocking liner 116 is formed over the upper epitaxial source / drain region 108U2 to prevent further epitaxial growth during deposition of the upper epitaxial source / drain region 108U1, as described below. FIG. 15A to FIG. 15C The blocking liner 116 may be formed by processes and materials similar to those discussed above. Specifically, after depositing the dielectric material of the blocking liner 116, the dielectric material may be patterned by forming a photomask over the UFET region 50U, developing the photomask to expose the dielectric material in the CFET region 50C, and then etching the dielectric material to remove the dielectric material in the CFET region 50C, thereby forming the blocking liner 116 in the UFET region 50U. The photomask may then be removed, for example, by an ashing technique. The blocking liner 116 may have an etch selectivity similar to that of the dummy spacer 104 discussed above.

[0093] exist FIG. 30A to FIG. 30CIn the CFET region 50C, an upper epitaxial source / drain region 108U1 is formed in the upper portion of the source / drain recess 94 in the CFET region 50C. On the other hand, the blocking liner 116 prevents growth from occurring in the UFET region 50U. The upper epitaxial source / drain region 108U1 only partially fills the source / drain recess 94 so that the upper epitaxial source / drain region 108U1 is in contact with the upper semiconductor nanostructure 66U and is not in contact with the lower semiconductor nanostructure 66L. The first ILD 114 can provide isolation between the upper epitaxial source / drain region 108U1 and the lower epitaxial source / drain region 108L. The upper epitaxial source / drain region 108U1 can be grown using the materials and processes discussed above, which are not repeated here. However, it should be noted that in the CFET region 50C, only the upper semiconductor nanostructures 66U are exposed, so growth will start from these semiconductor nanostructures 66U. As discussed above, the upper epitaxial source / drain regions 108U1 may include doping. Furthermore, they may have respective facets and apply compressive or tensile forces to the channel region, as discussed above. Other features and characteristics of the upper epitaxial source / drain regions 108U1 also apply.

[0094] exist FIG. 31A to FIG. 31C In the embodiment of the present invention, the blocking liner 116 is removed from the source / drain recess 94 in the UFET region 50U. Any acceptable etching process, such as dry etching, wet etching, etc., or a combination thereof, may be performed to remove the blocking liner 116. The etching may be isotropic. The etching is selective to the blocking liner 116. After removing the blocking liner 116, the outer surfaces of the upper epitaxial source / drain region 108U1 and the upper epitaxial source / drain region 108U2 are exposed.

[0095] Figures 32 to 38C Another process of forming upper epitaxial source / drain regions 108U2 for UFETs in UFET region 50U is shown, wherein lower epitaxial source / drain regions 108L are formed in the same process as forming upper epitaxial source / drain regions 108U2. Fig.32 From Figure 8 The structure shown. Figures 32 to 38C The process is similar to that corresponding to Figures 19 to 31C The process is similar to that of FIG. 1 , except that the dummy spacer 104A is not formed. This allows the lower epitaxial source / drain region 108L and the upper epitaxial source / drain region 108U2 to grow from the middle semiconductor nanostructure 66M in the UFET region 50U, thereby forming a larger epitaxial source / drain region in the UFET region 50U. Similar reference numerals are used for similar structures.

[0096] exist Fig.32In the embodiment, a masking structure 105B is formed over the CFET region 50C to protect the dummy spacer 104. The dummy spacer 104 in the UFET region 50U is exposed from the masking structure 105B. Fig. 20 The materials and processes described above are used to form the masking structure 105B.

[0097] exist Fig.33 In the embodiment of the present invention, the dummy spacer 104 in the UFET region 50U is removed, thereby exposing the upper semiconductor nanostructure 66U, the middle semiconductor nanostructure 66M and the lower semiconductor nanostructure 66L. The dummy spacer 104 in the UFET region 50U can be used as described above. Fig.21 Similar processes and materials are discussed for removal.

[0098] exist Fig.34 In the embodiment, the masking structure 105B and the sacrificial dielectric 102 are removed, and the dummy spacer 104 remains in the CFET region 50C. Fig. 22 The masking structure 105B can be removed using similar processes and materials discussed above. Fig.24 Similar processes and materials are discussed to remove the sacrificial dielectric 102 .

[0099] exist FIG. 35A to FIG. 35CIn the embodiment of the present invention, a lower epitaxial source / drain region 108L is formed in the lower portion of the source / drain grooves 94 in both the CFET region 50C and the UFET region 50U, and an upper epitaxial source / drain region 108U2 is simultaneously formed in the upper portion of the source / drain grooves 94 in the UFET region 50U. The dummy spacer 104 prevents growth from occurring in the CFET region 50C. The lower epitaxial source / drain region 108L and the upper epitaxial source / drain region 108U2 can be grown using the materials and processes discussed above, which are not repeated here. However, it should be noted that in the CFET region 50C, as shown, only the lower semiconductor nanostructures 66L are exposed, so growth will start from these semiconductor nanostructures 66L. However, the length of the dummy spacer 104 can be changed so that the intermediate semiconductor nanostructures 66M below the isolation structure 100 can also be exposed. In the UFET region 50U, both the lower semiconductor nanostructure 66L and the upper semiconductor nanostructure 66U are exposed together with the middle semiconductor nanostructure 66M, so growth can occur from each of the upper semiconductor nanostructure 66U, the middle semiconductor nanostructure 66M, and the lower semiconductor nanostructure 66L. The lower epitaxial source / drain region 108L and the upper epitaxial source / drain region 108U2 may include doping, as discussed above, respectively. Moreover, they may have respective facets and exert compressive or tensile forces on the channel region, as discussed above. Other features and properties of the lower epitaxial source / drain region 108L and the upper epitaxial source / drain region 108U2 also apply.

[0100] In addition, as shown, because the intermediate semiconductor nanostructure 66M is used, the lower epitaxial source / drain region 108L in the UFET region 50U can be larger than the lower epitaxial source / drain region 108L in the CFET region 50C. It should be noted that in some embodiments, the lower epitaxial source / drain region 108L in the UFET region 50U can be vertically merged with the upper epitaxial source / drain region 108U2.

[0101] exist FIG. 36A to FIG. 36B In the embodiment, after forming the lower epitaxial source / drain region 108L and the upper epitaxial source / drain region 108U2, the dummy spacers 104 may be removed using a process similar to that described above with respect to the dummy spacers 104 of other embodiments.

[0102] Next, a first ILD 114 is formed and recessed. A first CESL 112 may also be formed and recessed between the first ILD 114 and the lower epitaxial source / drain regions 108L and between the first ILD 114 and side structures such as the inner spacers 98, the isolation structures 100, the semiconductor nanostructures 66, and the gate spacers 90. The first ILD 114 and the first CESL 112 may be formed using the same techniques as described above, for example, with respect to FIG. 27A to FIG. 27C After forming the first ILD 114 and the first CESL 112, the first ILD 114 and the first CESL 112 may be recessed to expose the upper semiconductor nanostructure 66U in the CFET region 50C. FIG. 28A to FIG. 28C Recessing of the first ILD 114 and the first CESL 112 is performed using processes and materials similar to those discussed above.

[0103] Still reference FIG. 36A to FIG. 36C , a blocking liner 116 is formed over the UFET region 50U, while exposing the CFET region 50C. FIG. 29A to FIG. 29C Similar processes and materials as discussed above are used to form the blocking liner 116. It is noteworthy that a portion of the first CESL 112 remains disposed below the upper epitaxial source / drain regions 108U2.

[0104] exist FIG. 37A to FIG. 37CIn the CFET region 50C, an upper epitaxial source / drain region 108U1 is formed in the upper portion of the source / drain recess 94 in the CFET region 50C. On the other hand, the blocking liner 116 prevents growth from occurring in the UFET region 50U. The upper epitaxial source / drain region 108U1 only partially fills the source / drain recess 94 so that the upper epitaxial source / drain region 108U1 is in contact with the upper semiconductor nanostructure 66U and is not in contact with the lower semiconductor nanostructure 66L. The first ILD 114 can provide isolation between the upper epitaxial source / drain region 108U1 and the lower epitaxial source / drain region 108L. The upper epitaxial source / drain region 108U1 can be grown using the materials and processes discussed above, which are not repeated here. However, it should be noted that in the CFET region 50C, only the upper semiconductor nanostructures 66U are exposed, so growth will start from these semiconductor nanostructures 66U. In some embodiments, the first ILD 114 and the first CESL 112 may be optionally further lowered to expose portions of the intermediate semiconductor nanostructure 66M, which will cause growth therefrom and may cause a larger upper epitaxial source / drain region 108U1. As discussed above, the upper epitaxial source / drain region 108U1 may include doping. Moreover, they may have respective facets and apply compressive or tensile forces to the channel region, as discussed above. Other features and characteristics of the upper epitaxial source / drain region 108U1 also apply.

[0105] exist FIG. 38A to FIG. 38C In the embodiment of the present invention, the blocking liner 116 is removed from the source / drain recess 94 in the UFET region 50U. FIG. 31A to FIG. 31C Similar processes and materials as those discussed above are used to remove the barrier liner 116 .

[0106] FIG. 39A to FIG. 54C Shows 18A to 18C , FIG. 31A to FIG. 31C or FIG. 38A to FIG. 38C Continuous process on the structure. FIG. 31A to FIG. 31C The portion of the first CESL 112 below the upper epitaxial source / drain region 108U2 is not specifically shown, however, it can be replaced as appropriate in the illustrated embodiment. FIG. 38A to FIG. 38C The larger upper epitaxial source / drain regions 108U2 are not specifically shown, however, they may be replaced as appropriate in the illustrated embodiment.

[0107] exist FIG. 39A to FIG. 39CIn the embodiment of the present invention, a second ILD 124 is deposited over the upper epitaxial source / drain region 108U, the first ILD 114, the gate spacer 90, and the mask 86 (if present) or the dummy gate 84. The second ILD 124 may be formed of a dielectric material, and the second ILD 124 may be deposited by any suitable method, such as CVD, plasma enhanced chemical vapor deposition (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other dielectric materials formed by any acceptable process may be used.

[0108] In some embodiments, a second CESL 122 is formed between the second ILD 124 and the upper epitaxial source / drain regions 108U, the first ILD 114, the gate spacer 90, and the mask 86 (if present) or the dummy gate 84. The second CESL 122 may be formed of a dielectric material having a high etching selectivity relative to the dielectric material of the second ILD 124, such as silicon nitride, silicon oxide, silicon oxynitride, etc., and the second CESL 122 may be formed by any suitable deposition process such as CVD, ALD, etc.

[0109] exist Fig.40 In the embodiment shown, a removal process is performed to make the top surface of the second ILD 124 flush with the top surface of the gate spacer 90 and the mask 86 (if present) or the dummy gate 84. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. can be used. The planarization process can also remove the mask 86 on the dummy gate 84 and the portion of the gate spacer 90 along the sidewall of the mask 86. After the planarization process, the top surfaces of the second ILD 124, the gate spacer 90, and the mask 86 (if present) or the dummy gate 84 are substantially coplanar (within process variations). Accordingly, the top surface of the mask 86 (if present) or the dummy gate 84 is exposed through the second ILD 124. In the embodiment shown, the mask 86 is retained after the removal process. In other embodiments, the mask 86 is removed so that the top surface of the dummy gate 84 is exposed through the second ILD 124.

[0110] exist FIG. 41A to FIG. 41CIn the embodiment of the present invention, the dummy gate 84 is removed in one or more etching steps so that the groove 126 is formed between the gate spacers 90. The portion of the dummy dielectric 82 located in the groove 126 is also removed. In some embodiments, the dummy gate 84 and the dummy dielectric 82 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the material of the dummy gate 84 at a faster rate than the material of the second ILD 124, the isolation structure 100, the inner spacer 98, and the gate spacer 90. Each groove 126 exposes a portion of the nanostructure 64, 66 that is a channel region in the resulting device, and / or is placed above a portion of the nanostructure 66, 64 that is a channel region in the resulting device. The portion of the nanostructure 64, 66 that is a channel region is disposed between the adjacent pair of lower epitaxial source / drain regions 108L or between the adjacent pair of upper epitaxial source / drain regions 108U. During the removal, when etching the dummy gate 84, the dummy dielectric 82 may be used as an etch stop layer. Then, after removing the dummy gate 84 , the dummy dielectric 82 may be removed.

[0111] The remaining portion of the first pseudo nanostructure 64A is then removed to form an opening 128 in the region between the semiconductor nanostructures 66. The remaining portion of the first pseudo nanostructure 64A may be removed by any acceptable etching process that selectively etches the material of the first pseudo nanostructure 64A at a faster rate than the material of the semiconductor nanostructure 66, the internal spacer 98, and the isolation structure 100. The etching may be isotropic. For example, when the first pseudo nanostructure 64A is formed of silicon germanium, the semiconductor nanostructure 66 is formed of silicon, the internal spacer 98 is formed of silicon oxynitride, and the isolation structure 100 is formed of silicon oxynitride, the etching process may be a wet etch using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc. In some embodiments, a trimming process (not shown separately) is performed to reduce the thickness of the exposed portion of the semiconductor nanostructure 66 and expand the opening 128.

[0112] exist FIG. 42A to FIG. 42B, a gate dielectric layer 130 is conformally formed on the channel region of the semiconductor nanostructure 66 so that it conformally lines the recess 126 and the opening 128. Specifically, the gate dielectric layer 130 is formed on the top surface of the fin 62; on the top surface, sidewalls, and bottom surface of the semiconductor nanostructure 66; and on the sidewalls of the gate spacer 90. The gate dielectric layer 130 wraps around all (e.g., four) sides of the semiconductor nanostructure 66. The gate dielectric layer 130 may also be formed on the top surfaces of the second ILD 124 and the gate spacer 90, and may be formed on the sidewalls of the fin 62 (e.g., in an embodiment where the top surface of the isolation region 70 is below the top surface of the fin 62). The gate dielectric layer 130 may include an oxide such as silicon oxide or a metal oxide, a silicate such as a metal silicate, a combination thereof, a multilayer thereof, and the like. The gate dielectric layer 130 may include a high dielectric constant (high-k) material (having a k value greater than about 7.0), such as a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The formation method of the gate dielectric layer 130 may include molecular beam deposition (MBD), ALD, PECVD, etc. Although a single-layer gate dielectric layer 130 is shown, the gate dielectric layer 130 may include multiple layers, such as an interface layer and an upper high-k dielectric layer.

[0113] exist FIG. 43A to FIG. 43B In the embodiment, a liner layer 135 is conformally deposited over the gate dielectric layer 130 and in the openings 128 between the semiconductor nanostructures 66. The liner layer 135 can be made of any suitable material. In an embodiment, the liner layer 135 can be a titanium nitride layer to provide etching selectivity to other adjacent material layers. Alternative materials such as dielectric materials can be used as long as they have good etching selectivity to the gate dielectric layer 130 and the deposited structures that subsequently contact the liner layer 135. The deposition of the liner layer 135 can be performed by CVD, ALD, etc., or a combination thereof.

[0114] exist FIG. 44A to FIG. 44B In the embodiment of the present invention, a dummy gate electrode 137 is formed on the liner layer 135 and in the lower part of the groove 126. The dummy gate electrode 137 can be formed of any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, etc. or a combination thereof. The dummy gate electrode 137 can be deposited by CVD or other suitable processes. After the liner layer 135 is deposited, a back etching process can be used to recess the dummy gate electrode 137 so that the upper surface of the dummy gate electrode 137 is set adjacent to the isolation structure 100. The liner layer 135 can be used as a protective layer to protect the upper part of the temporary fin during the back etching process. The back etching process can utilize any suitable etching technology, such as wet etching or dry etching. After the back etching process, the exposed portion of the liner layer 135 can be removed by another etching process using an etchant suitable for etching titanium nitride.

[0115] exist FIG. 45A to FIG. 45B In the embodiment, a protective layer 139 may be conformally deposited over the exposed portion of the gate dielectric layer 130 and around the upper semiconductor nanostructure 66U. The protective layer 139 provides a conformal liner to temporarily mask some of the upper semiconductor nanostructures 66U. The protective layer 139 may be made of any suitable material. In an embodiment, the protective layer 139 may be an amorphous silicon layer to provide etching selectivity to other adjacent material layers. Alternative materials such as dielectric materials may be used as long as they have good etching selectivity to the gate dielectric layer 130 and the deposited structure that subsequently contacts the protective layer 139. The deposition of the protective layer 139 may be performed by CVD, ALD, etc., or a combination thereof. After depositing the protective layer 139, an anisotropic etch-back process may be used to recess a portion of the protective layer 139 in the recess 126.

[0116] exist FIG. 46A to FIG. 46B In the embodiment, a photoresist 141 is formed over the upper epitaxial source / drain region 108U1 of the CFET region 50C and over a portion of the dummy gate electrode 137 in the CFET region 50C. The photoresist 141 can be formed, patterned, and developed by a spin coating process or other suitable process to expose the UFET region 50U. After the UFET region 50U is exposed, the exposed protective layer 139 can be removed from the UFET region 50U, for example, by an etch-back process.

[0117] exist FIG. 47A to FIG. 47B In the CFET region 50C, the photoresist 141 can be removed, for example, by a suitable ashing technique. Then, the dummy gate electrode 137 and the liner layer 135 can be removed by a suitable etching technique. In the CFET region 50C, the protective layer 139 remains around the upper semiconductor nanostructure 66U, so that a suitable electrode for the structure can be formed in a subsequent step.

[0118] exist FIG. 48A to FIG. 48B In the gate dielectric layer 130 (see FIG. 47A to FIG. 47B ) and the protective layer 139 to form a lower gate electrode 134L. The lower gate electrode 134L is disposed in the lower portion of the groove 126 and in the opening 128 between the lower semiconductor nanostructures 66L. Moreover, the lower gate electrode 134L matches the conductivity of the UFET region 50U. Accordingly, the lower gate electrode 134L surrounds the upper semiconductor nanostructure 66U in the UFET region 50U, and surrounds the lower semiconductor nanostructure 66L in the CFET region 50C and in the UFET region 50U. Although the lower gate electrode 134L surrounds the protective layer 139, this portion will be removed in a subsequent process.

[0119] The lower gate electrode 134L may be formed of a metal-containing material such as tungsten, titanium, titanium nitride, tantalum, tantalum nitride, tantalum carbide, aluminum, ruthenium, cobalt, combinations thereof, multilayers thereof, etc. Although a single-layer gate electrode is shown, the lower gate electrode 134L may include any number of work function adjustment layers, any number of barrier layers, any number of glue layers, and filling materials.

[0120] The lower gate electrode 134L is formed of a material suitable for the device type of the lower nanostructure FET. For example, the lower gate electrode 134L may include one or more work function adjustment layers formed of work function adjustment metals suitable for the device type of the lower nanostructure FET and UFET. In some embodiments, the lower gate electrode 134L includes an n-type work function adjustment layer, which may be formed of titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum carbide, combinations thereof, and the like. In some embodiments, the lower gate electrode 134L includes a p-type work function adjustment layer, which may be formed of titanium nitride, tantalum nitride, combinations thereof, and the like. Additionally or alternatively, the lower gate electrode 134L may include a dipole-inducing element suitable for the device type of the lower nanostructure FET. Acceptable dipole-inducing elements include lanthanum, aluminum, scandium, ruthenium, zirconium, erbium, magnesium, strontium, and combinations thereof. The lower gate electrode 134L may be formed by conformally depositing one or more gate electrode layers in the recess 126 and in the opening 128.

[0121] Optionally, a removal process is performed to form the gate dielectric 132 and to make the top surface of the gate dielectric 132 flush with the top surfaces of the gate spacer 90, the second ILD 124, and the lower gate electrode 134L. After the removal process, the gate dielectric layer 130 has a portion remaining in the recess 126 and the opening 128 (thereby forming the gate dielectric layer 132). In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. may be utilized. After the planarization process, the top surfaces of the lower gate electrode 134L, the gate dielectric 132, the second ILD 124, and the gate spacer 90 are substantially coplanar (within process variations).

[0122] exist FIG. 49A to FIG. 49B , a photoresist mask 143 is formed over a portion of the lower gate electrode 134L in the UFET region 50U. The photoresist mask 143 may be formed by spin coating, patterning, and development to leave a portion above the lower gate electrode 134L in the UFET region 50U. Next, the gate electrode 134L exposed from the photoresist mask 143 (e.g., located in the CFET region 50C) is recessed. Any acceptable etching process, such as dry etching, wet etching, etc., or a combination thereof, may be performed to recess the gate electrode 134L. The etching may be anisotropic, such as an etch-back process that removes the gate electrode 134L from the upper portion of the recess 126. The upper portion of the CFET region 50C is protected by the protective layer 139 during etching.

[0123] exist FIG. 50A to FIG. 50B In the embodiment of the present invention, the protective layer 139 is removed from the exposed upper portion of the CFET region 50C. The protective layer 139 may be removed using any suitable etching technique, such as the corresponding techniques discussed above.

[0124] exist FIG. 51A to FIG. 51B , an upper gate electrode 134U is formed on the lower gate electrode 134L. The upper gate electrode 134U is disposed in the upper portion of the recess 126 in the CFET region 50C and in the opening 128 between the upper semiconductor nanostructures 66U. Accordingly, the upper gate electrode 134U surrounds the upper semiconductor nanostructure 66U in the CFET region 50C. The upper gate electrode 134U may be formed of a metal-containing material such as tungsten, titanium, titanium nitride, tantalum, tantalum nitride, tantalum carbide, aluminum, ruthenium, cobalt, combinations thereof, multilayers thereof, and the like. Although a single-layer gate electrode is shown, the upper gate electrode 134U may include any number of work function adjustment layers, any number of barrier layers, any number of glue layers, and filling materials.

[0125] The upper gate electrode 134U is formed of a material suitable for the device type of the upper nanostructure FET. For example, the upper gate electrode 134U may include one or more work function adjustment layers formed of a work function adjustment metal suitable for the device type of the upper nanostructure FET. In some embodiments, the upper gate electrode 134U includes an n-type work function adjustment layer, which may be formed of titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum carbide, combinations thereof, and the like. In some embodiments, the upper gate electrode 134U includes a p-type work function adjustment layer, which may be formed of titanium nitride, tantalum nitride, combinations thereof, and the like. The work function adjustment metal of the upper gate electrode 134U may be different from the work function adjustment metal of the lower gate electrode 134L. Additionally or alternatively, the upper gate electrode 134U may include a dipole-inducing element suitable for the device type of the upper nanostructure FET. Acceptable dipole-inducing elements include lanthanum, aluminum, scandium, ruthenium, zirconium, erbium, magnesium, strontium, and combinations thereof. The dipole-inducing element of the upper gate electrode 134U may be different from the dipole-inducing element of the lower gate electrode 134L. The lower gate electrode 134L may be formed by conformally depositing one or more gate electrode layers in the recess 126 and in the opening 128 .

[0126] exist FIG. 52A to FIG. 52B In the embodiment, a removal process is performed to remove an excess portion of the upper gate electrode 134U, which is located above the top surface of the gate spacer 90 and the second ILD 124. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, or the like is utilized.

[0127] Each corresponding pair of the gate dielectric 132 and the gate electrode 134 (including the upper gate electrode 134U and / or the lower gate electrode 134L) may be collectively referred to as a “gate structure”. Each gate structure extends along three sides (e.g., top surface, sidewall, and bottom surface) of the channel region of the semiconductor nanostructure 66. The gate structure may also extend along the sidewall and / or top surface of the fin 62.

[0128] exist FIG. 53A to FIG. 53C In the embodiment of the present invention, source / drain contacts 144 are formed for the source / drain regions 108. The source / drain contacts 144 may be physically and electrically coupled to the upper epitaxial source / drain regions 108U.

[0129] As an example of forming a source / drain contact 144, an opening for the source / drain contact 144 is formed through the second ILD 124 and the second CESL 122. The opening can be formed using acceptable photolithography and etching techniques. In the illustrated embodiment, the opening is formed by a self-aligned contact (SAC) process. A liner (not shown separately) such as a diffusion barrier layer, an adhesion layer, etc. and a conductive material are formed in the opening. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be cobalt, tungsten, copper, copper alloy, silver, gold, aluminum, nickel, etc. A removal process may be performed to remove excess material from the top surface of the gate spacer 90 and the second ILD 124. The remaining liner and conductive material form a source / drain contact 144 in the opening. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. is utilized. After the planarization process, top surfaces of the gate spacers 90 , the second ILD 124 , the upper gate electrode 134U, and the source / drain contacts 144 are substantially coplanar (within process variations).

[0130] Optionally, a metal-semiconductor alloy region 142 is formed at the interface between the upper epitaxial source / drain region 108U and the source / drain contact 144. The metal-semiconductor alloy region 142 may be a silicide region formed of a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), a germanide region formed of a metal germanide (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), a silicon germanide region formed of both a metal silicide and a metal germanide, etc. The metal-semiconductor alloy region 142 may be formed by depositing a metal in an opening for the source / drain contact 144, and then performing a thermal annealing process, before the material of the source / drain contact 144. The metal can be any metal that can react with the semiconductor material (e.g., silicon, silicon germanium, germanium, etc.) of the upper epitaxial source / drain region 108U to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or alloys thereof. The metal can be deposited by a deposition process such as ALD, CVD, PVD, etc. After the thermal annealing process, a cleaning process such as wet cleaning can be performed to remove any residual metal from the opening for the source / drain contact 144 (such as from the surface of the metal-semiconductor alloy region 142). The material of the source / drain contact 144 can then be formed on the metal-semiconductor alloy region 142.

[0131] In the illustrated embodiment, the source / drain contacts 144 are coupled to the upper epitaxial source / drain region 108U. In another embodiment (not separately shown), some of the source / drain contacts 144 are shared source / drain contacts coupled to both the upper epitaxial source / drain region 108U and the lower epitaxial source / drain region 108L. For example, the shared source / drain contact may be formed through the upper epitaxial source / drain region 108U, the first ILD 114, and the first CESL 112 to couple to the lower epitaxial source / drain region 108L. When forming such a shared source / drain contact, an opening for the shared source / drain contact may also be formed through the upper epitaxial source / drain region 108U, the first ILD 114, and the first CESL 112; in addition, the metal-semiconductor alloy region 142 may be formed on the sidewalls of the upper epitaxial source / drain region 108U.

[0132] exist FIG. 54A to FIG. 54CIn the embodiment of the present invention, a third ILD 154 is deposited over the gate spacer 90, the second ILD 124, the upper gate electrode 134U, and the source / drain contact 144. In some embodiments, the third ILD 154 is a flowable film formed by a flowable CVD method, which is subsequently cured. In some embodiments, the third ILD 154 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and the third ILD 154 can be deposited by any suitable method such as CVD, PECVD, etc.

[0133] In some embodiments, an etch stop layer (ESL) 152 is formed between the third ILD 154 and the gate spacer 90, the second ILD 124, the upper gate electrode 134U, and the source / drain contacts 144. The ESL 152 may include a dielectric material having a high etch selectivity relative to the dielectric material of the third ILD 154, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0134] A gate contact 156 and a source / drain via 158 are formed through the third ILD 154 to contact the upper gate electrode 134U and the source / drain contact 144, respectively. The gate contact 156 may be physically and electrically coupled to the upper gate electrode 134U. The source / drain via 158 may be physically and electrically coupled to the source / drain contact 144.

[0135] As an example of forming a gate contact 156 and a source / drain via 158, an opening for a gate contact 156 and a source / drain via 158 is formed through the third ILD 154 and the ESL 152. The opening can be formed using acceptable photolithography and etching techniques. A liner (not shown separately) and a conductive material such as a diffusion barrier layer, an adhesive layer, etc. are formed in the opening. The liner can include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material can be cobalt, tungsten, copper, copper alloy, silver, gold, aluminum, nickel, etc. A planarization process such as CMP can be performed to remove excess material from the top surface of the third ILD 154. The remaining liner and conductive material form a gate contact 156 and a source / drain via 158 in the opening. The gate contact 156 and the source / drain via 158 can be formed in different processes, or the gate contact 156 and the source / drain via 158 can be formed in the same process. Although shown as being formed in the same cross-section, it is understood that each of the gate contact 156 and the source / drain vias 158 may be formed in different cross-sections, which may avoid shorting of the contacts.

[0136] The active devices shown are collectively referred to as a device layer. In some embodiments, contacts to the lower gate electrode 134L and the lower epitaxial source / drain regions 108L can be made through the back side of the device layer (eg, the side opposite the source / drain contacts 144).

[0137] Advantages that can be achieved by embodiments. By utilizing unipolar stacked FETs and complementary stacked FETs in the same device, embodiments can utilize more available area for use by active transistors. For example, in SRAM, the ratio of the number of single N / P transistors to CMOS transistors to SRAM I / Os is about 1:2:(3-4.5). Therefore, by utilizing more stacked transistors as unipolar for single N / P transistors and for SRAM I / Os, space savings of between about 40%-50% can be achieved.

[0138] Figures 55 to 59C is a view of an intermediate stage in the fabrication of a CFET and a UFET according to some other embodiments. In this embodiment, a lower nanostructure FET may be formed first. An upper nanostructure FET may then be formed over the lower nanostructure FET. Fig.55 , Fig.56A , Fig.57A , Fig.58A and Fig.59A Shows that along with Figure 1A to Figure 1B A cross-sectional view of a cross section similar to the reference cross section AA'. Fig.56B , Fig.57B , Fig.58B and Fig.59B Shows that along with Figure 1A to Figure 1B A cross-sectional view of a cross section similar to the reference cross section BB'. Fig.56C , Fig.57C , Fig.58C and Fig.59C Shows that along with Figure 1A to Figure 1B A cross-sectional view of a cross section similar to the reference cross section CC'.

[0139] exist Fig.55 In the embodiment, a first substrate 50A is provided. A first multilayer stack 52A is formed over the first substrate 50A. The first multilayer stack 52A includes a first dummy layer 54A and a lower semiconductor layer 56L. The first substrate 50A and the first multilayer stack 52A may be formed in the same manner as previously described with respect to Figure 2 The method is similar to that described.

[0140] exist FIG. 56A to FIG. 56C, appropriate steps as discussed above are performed to form a lower nanostructure FET. A lower semiconductor nanostructure 66L is patterned from a lower semiconductor layer 56L. A lower epitaxial source / drain region 108L is formed adjacent to the lower semiconductor nanostructure 66L. A lower gate dielectric 132L and a lower gate electrode 134L are formed around the lower semiconductor nanostructure 66L. A first ILD 114 is formed over the lower epitaxial source / drain region 108L.

[0141] exist FIG. 57A to FIG. 57C In the embodiment, a second substrate 50B is provided. A second multilayer stack 52B is formed over the second substrate 50B. The second multilayer stack 52B includes a first dummy layer 54A and an upper semiconductor layer 56U. The second substrate 50B and the second multilayer stack 52B may be formed in the same manner as previously described with respect to Figure 2 The structure is then flipped over and a second multilayer stack 52B is bonded to FIG. 56A to FIG. 56C The structure shown.

[0142] One or more bonding layers 162 may be used to bond the structures to each other. For example, a first bonding layer 162A is formed over the first substrate 50A, and a second bonding layer 162B is formed over the second substrate 50B. In some embodiments, the bonding layer 162 is formed of silicon oxide (e.g., high density plasma (HDP) oxide, etc.) deposited by CVD, ALD, etc. The bonding layer 162 may also include an oxide layer formed using, for example, CVD, ALD, thermal oxidation, etc. Other suitable materials may be used for the bonding layer 162.

[0143] exist FIG. 58A to FIG. 58C In the second multilayer stack 52B, the upper semiconductor nanostructure 66U and the first dummy nanostructure 64A are patterned. The upper semiconductor nanostructure 66U and the first dummy nanostructure 64A may be patterned in the same manner as previously described for Figure 3 The second substrate 50B may be removed before or after patterning. During patterning of the upper semiconductor nanostructures 66U and the first dummy nanostructures 64A, one or more bonding layers 162 may be etched.

[0144] exist Figures 59A to 59C In the embodiment of the present invention, appropriate steps as discussed above are performed to form an upper nanostructure FET. An upper epitaxial source / drain region 108U is formed adjacent to the upper semiconductor nanostructure 66U. An upper gate dielectric 132U and an upper gate electrode 134U are formed around the upper semiconductor nanostructure 66U. A second ILD 124 is formed over the upper epitaxial source / drain region 108U.

[0145] The upper nanostructure FETs for UFET and CFET can be formed in the UFET region 50U and the CFET region 50C, respectively, using appropriate processes in the aforementioned processes. For example, the upper epitaxial source / drain region 108U1 and the upper epitaxial source / drain region 108U2 can be formed using any of the masking and growth steps previously described. Similarly, the lower gate electrode 134L for the upper nanostructure FET can be formed. Subsequently, appropriate steps as previously described can be performed to complete the formation of the device.

[0146] In the foregoing embodiments, the lower nanostructure FETs have the same device type, while the upper nanostructure FETs have different device types. It should be understood that similar techniques as previously described can be used to form nanostructure FETs stacked in a manner opposite to that previously described. As a result, the upper nanostructure FETs can have the same device type, and the lower nanostructure FETs can have different device types.

[0147] In an embodiment, a method includes: forming a fin extending vertically from a substrate, the fin including a lower semiconductor nanostructure, an upper semiconductor nanostructure, and a pseudo semiconductor nanostructure disposed between the lower semiconductor nanostructure and the upper semiconductor nanostructure; etching a first groove and a second groove in the fin through the upper semiconductor nanostructure, the pseudo semiconductor nanostructure, and the lower semiconductor nanostructure, the etching forming a first sidewall of the upper semiconductor nanostructure in the first groove and a second sidewall of the lower semiconductor nanostructure in the first groove, the etching forming a third sidewall of the upper semiconductor nanostructure in the second groove and a fourth sidewall of the lower semiconductor nanostructure in the second groove; replacing the pseudo semiconductor nanostructure with a first isolation structure; growing a first lower semiconductor structure from the second sidewall and a second lower semiconductor structure from the fourth sidewall, the first lower semiconductor structure and the second lower semiconductor structure having a first conductivity type; and growing a first upper semiconductor structure from the first sidewall and a second upper semiconductor structure from the third sidewall, the first upper semiconductor structure having a second conductivity type opposite to the first conductivity type, and the second upper semiconductor structure having the first conductivity type. In some embodiments of the method, growing the first lower semiconductor structure, the second lower semiconductor structure, and the second upper semiconductor structure occurs simultaneously. In some embodiments, the method further includes: forming the first upper semiconductor structure before forming the second upper semiconductor structure. In some embodiments, the method further comprises: blocking the third sidewall while growing the first upper semiconductor structure from the first sidewall. In some embodiments, the method further comprises: blocking the first sidewall while growing the first lower semiconductor structure, and the growth of the second lower semiconductor structure and the second upper semiconductor structure occurs simultaneously. In some embodiments, the method further comprises: removing the dummy gate surrounding the upper semiconductor nanostructure and the lower semiconductor nanostructure; forming a gate dielectric surrounding the upper semiconductor nanostructure and the lower semiconductor nanostructure; forming a protective structure around the upper semiconductor nanostructure; depositing a first gate structure surrounding the lower semiconductor nanostructure and the protective structure; recessing the first gate structure to expose the protective structure; removing the protective structure; and depositing a second gate structure surrounding the upper semiconductor nanostructure. In some embodiments, the method further comprises: masking a portion of the first gate structure before recessing the first gate structure, wherein the recessing of the first gate structure recesses an unmasked portion of the first gate structure; and depositing the second gate structure so that the second gate structure is both vertically above the first gate structure and horizontally adjacent to the first gate structure.

[0148] In an embodiment, a method includes: etching a first groove and a second groove in a fin-shaped multilayer semiconductor stack, each of the first groove and the second groove dividing the fin-shaped multilayer semiconductor stack into a plurality of nanostructures; growing a first source / drain region in the first groove from an exposed end of a first nanostructure in the plurality of nanostructures, the first source / drain region having a first conductivity type; growing a second source / drain region in the second groove from an exposed end of a second nanostructure in the plurality of nanostructures, the second source / drain region having a first conductivity type; growing a third source / drain region in the first groove from an exposed end of a third nanostructure in the plurality of nanostructures, the third source / drain region having a first conductivity type, the third source / drain region being disposed directly above the first source / drain region; and growing a fourth source / drain region in the second groove from an exposed end of a fourth nanostructure in the plurality of nanostructures, the fourth source / drain region having a second conductivity type opposite to the first conductivity type, the fourth source / drain region being disposed directly above the second source / drain region. In some embodiments of the method, growing the first source / drain region and the second source / drain region occurs simultaneously. In some embodiments, the method further comprises: after growing the first source / drain region, forming a first isolation structure above the first source / drain region; after forming the first isolation structure, blocking the third nanostructure and growing the fourth source / drain region; and after growing the fourth source / drain region, blocking the fourth source / drain region and growing the third source / drain region. In some embodiments of the method, growing the first source / drain region, the second source / drain region, and the third source / drain region occurs simultaneously. In some embodiments, the method further comprises: after growing the first source / drain region, forming a first isolation structure over the first source / drain region, the second source / drain region, and the third source / drain region, the first isolation structure comprising a liner layer surrounding the third source / drain region, including the bottom surface of the third source / drain region, the first isolation structure covering the fourth nanostructure; recessing the first isolation structure to expose the end of the fourth nanostructure, with a portion of the liner layer remaining disposed below the third source / drain region; growing the fourth source / drain region; and forming a second isolation structure over the third source / drain region and the fourth source / drain region, with a portion of the liner layer remaining disposed below the third source / drain region. In some embodiments, the method further comprises: removing the dummy gate to expose the intermediate surface of the first nanostructure, the intermediate surface of the second nanostructure, the intermediate surface of the third nanostructure, and the intermediate surface of the fourth nanostructure; and forming a first gate structure surrounding the intermediate surface of the first nanostructure, the intermediate surface of the second nanostructure, the intermediate surface of the third nanostructure, and the intermediate surface of the fourth nanostructure.In some embodiments, the method further includes: before forming the first gate structure, forming a protection structure surrounding the fourth nanostructure; after forming the first gate structure, forming a groove in the first gate structure, the groove exposing the protection structure, and the third nanostructure remains surrounded by the first gate structure; removing the protection structure; and forming a second gate structure surrounding the fourth nanostructure in the groove. In some embodiments of the method, forming the protection structure includes: forming a first liner around the first nanostructure, the second nanostructure, the third nanostructure, and the fourth nanostructure; forming a dummy material around a portion of the first liner located around the first nanostructure and the second nanostructure; removing a portion of the first liner exposed from the dummy material; forming a second liner around the third nanostructure and the fourth nanostructure; masking the second liner surrounding the fourth nanostructure with a mask; removing the second liner from the third nanostructure; removing the mask and the dummy material; and removing a portion of the first liner located around the first nanostructure and the second nanostructure, wherein the protection structure includes the second liner surrounding the fourth nanostructure.

[0149] In an embodiment, a structure includes: a first semiconductor nanostructure; a second semiconductor nanostructure; a first isolation structure inserted between the first semiconductor nanostructure and the second semiconductor nanostructure; a first source / drain region extending laterally from an end of the first semiconductor nanostructure, the first source / drain region having a first conductivity type; a second source / drain region extending laterally from an end of the second semiconductor nanostructure, the second source / drain region having the first conductivity type, the second source / drain region being vertically aligned with the first source / drain region; and a first gate structure surrounding the first semiconductor nanostructure and the second semiconductor nanostructure. In some embodiments, the first gate structure includes a first region surrounding the first semiconductor nanostructure and a second region surrounding the second semiconductor nanostructure, the first region and the second region each including a work function configured for the first conductivity type. In some embodiments, the structure further comprises: a third semiconductor nanostructure; a fourth semiconductor nanostructure; a second isolation structure inserted between the third semiconductor nanostructure and the fourth semiconductor nanostructure; a third source / drain region extending laterally from an end of the third semiconductor nanostructure, the third source / drain region having a first conductivity type; a fourth source / drain region extending laterally from an end of the fourth semiconductor nanostructure, the fourth source / drain region having a second conductivity type opposite to the first conductivity type, the fourth source / drain region being vertically aligned with the third source / drain region; and a second gate structure surrounding the third semiconductor nanostructure and the fourth semiconductor nanostructure, wherein the second gate structure comprises a third region surrounding the third semiconductor nanostructure and a fourth region surrounding the fourth semiconductor nanostructure, the third region comprising a work function configured for the first conductivity type, and the fourth region comprising a work function configured for the second conductivity type. In some embodiments, the structure further comprises: a third semiconductor nanostructure inserted between the first semiconductor nanostructure and the first isolation structure, the third semiconductor nanostructure having the same material composition as the first semiconductor nanostructure; and a second isolation structure inserted between the first source / drain region and the second source / drain region, wherein the end of the third semiconductor nanostructure abuts the second isolation structure. In some embodiments, the structure further includes: a second isolation structure inserted between the second source / drain region and the first source / drain region, the second isolation structure comprising a pad disposed directly below and contacting a bottom surface of the second source / drain region.

[0150] The features of the embodiments are summarized above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor structure, comprising: forming a fin extending vertically from a substrate, the fin comprising a lower semiconductor nanostructure, an upper semiconductor nanostructure, and a dummy semiconductor nanostructure disposed between the lower semiconductor nanostructure and the upper semiconductor nanostructure; Etching a first groove and a second groove in the fin through the upper semiconductor nanostructure, the dummy semiconductor nanostructure, and the lower semiconductor nanostructure, the etching forming a first sidewall of the upper semiconductor nanostructure in the first groove and a second sidewall of the lower semiconductor nanostructure in the first groove, the etching forming a third sidewall of the upper semiconductor nanostructure in the second groove and a fourth sidewall of the lower semiconductor nanostructure in the second groove; replacing the dummy semiconductor nanostructure with a first isolation structure; growing a first lower semiconductor structure from the second sidewall and growing a second lower semiconductor structure from the fourth sidewall, the first lower semiconductor structure and the second lower semiconductor structure having a first conductivity type; as well as A first upper semiconductor structure is grown from the first sidewall and a second upper semiconductor structure is grown from the third sidewall, the first upper semiconductor structure having a second conductivity type opposite to the first conductivity type and the second upper semiconductor structure having the first conductivity type.

2. The method according to claim 1, wherein: Growing the first lower semiconductor structure, the second lower semiconductor structure, and the second upper semiconductor structure occurs simultaneously.

3. The method according to claim 1, further comprising: The first upper semiconductor structure is formed before forming the second upper semiconductor structure.

4. The method according to claim 1, further comprising: The third sidewall is blocked when the first upper semiconductor structure is grown from the first sidewall.

5. The method according to claim 1, further comprising: When the first lower semiconductor structure is grown, the first sidewall is blocked, and the second lower semiconductor structure and the second upper semiconductor structure are grown simultaneously.

6. The method according to claim 1, further comprising: removing the dummy gate surrounding the upper semiconductor nanostructure and the lower semiconductor nanostructure; forming a gate dielectric surrounding the upper semiconductor nanostructure and the lower semiconductor nanostructure; forming a protective structure around the upper semiconductor nanostructure; depositing a first gate structure surrounding the lower semiconductor nanostructure and the protection structure; recessing the first gate structure to expose the protection structure; removing the protective structure; as well as A second gate structure is deposited around the upper semiconductor nanostructure.

7. The method according to claim 6, further comprising: prior to recessing the first gate structure, masking a portion of the first gate structure, wherein the recessing of the first gate structure recesses an unmasked portion of the first gate structure; and The second gate structure is deposited such that the second gate structure is both vertically above the first gate structure and horizontally adjacent to the first gate structure.

8. A method of forming a semiconductor structure, comprising: etching a first groove and a second groove in a fin-shaped multilayer semiconductor stack, each of the first groove and the second groove dividing the fin-shaped multilayer semiconductor stack into a plurality of nanostructures; growing a first source / drain region in the first recess from an exposed end of a first nanostructure of the plurality of nanostructures, the first source / drain region having a first conductivity type; growing a second source / drain region in the second recess from an exposed end of the second nanostructure among the plurality of nanostructures, the second source / drain region having the first conductivity type; Growing a third source / drain region in the first groove from an exposed end of a third nanostructure among the plurality of nanostructures, the third source / drain region having the first conductivity type, and the third source / drain region being disposed directly above the first source / drain region; as well as A fourth source / drain region is grown in the second groove from an exposed end of a fourth nanostructure among the plurality of nanostructures, the fourth source / drain region having a second conductivity type opposite to the first conductivity type, and the fourth source / drain region is disposed directly above the second source / drain region.

9. The method according to claim 8, wherein: Growing the first source / drain region and the second source / drain region occurs simultaneously.

10. A semiconductor structure comprising: The first semiconductor nanostructure; a second semiconductor nanostructure; a first isolation structure inserted between the first semiconductor nanostructure and the second semiconductor nanostructure; a first source / drain region extending laterally from an end of the first semiconductor nanostructure, the first source / drain region having a first conductivity type; a second source / drain region extending laterally from an end of the second semiconductor nanostructure, the second source / drain region having the first conductivity type, the second source / drain region being vertically aligned with the first source / drain region; as well as The first gate structure surrounds the first semiconductor nanostructure and the second semiconductor nanostructure.

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