Method for manufacturing semiconductor device

Abstract

The embodiment of the invention provides a manufacturing method of a semiconductor device. In particular, embodiments of the present disclosure provide a method for incorporating a fill element into a high dielectric constant dielectric layer in a gate structure. This fill element reduces vacancies in the high dielectric constant dielectric layer, thereby improving threshold voltage control and device performance.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device having a high-k dielectric layer. Background Art

[0002] The semiconductor industry has experienced continued rapid growth due to the increasing integration of various electronic components. In large part, the increase in integration comes from the continuous reduction in the size of the smallest component, allowing more components to be integrated into a given chip area. This miniaturization process generally provides benefits by increasing production efficiency and reducing related costs.

[0003] When manufacturing field effect transistors (FETs), as the FET devices continue to shrink, a smaller threshold voltage (Vt) in the gate terminal is required to further speed up the operation of the FET devices. Therefore, it is necessary to solve the above problems. Summary of the invention

[0004] The purpose of the present disclosure is to provide a method for manufacturing a semiconductor device to solve at least one of the above problems.

[0005] The present disclosure provides a method for manufacturing a semiconductor device, comprising: depositing an interface layer on a semiconductor channel region; depositing a high-k dielectric layer on the interface layer; processing the high-k dielectric layer to incorporate a filling element having vacancies into the high-k dielectric layer; and depositing a gate electrode layer on the high-k dielectric layer.

[0006] The present disclosure provides a method for manufacturing a semiconductor device, comprising: depositing an interface layer on a semiconductor channel region; depositing a high-k dielectric layer on the interface layer; depositing a source layer on the high-k dielectric layer, wherein the source layer contains fluorine; performing a solid phase annealing process to drive the fluorine from the source layer into the high-k dielectric layer; removing the source layer; and depositing a gate electrode layer on the high-k dielectric layer.

[0007] The present disclosure provides a method for manufacturing a semiconductor device, comprising: forming a semiconductor device, comprising: a first source / drain region; a second source / drain region; a channel region, disposed between the first source / drain region and the second source / drain region; an interface layer, formed on the channel region; a high dielectric constant dielectric layer, formed on the interface layer, wherein the high dielectric constant dielectric layer includes fluorine with a molecular concentration between approximately 18% and approximately 22%; and a gate electrode layer, disposed above the high dielectric constant dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The following will be described in detail with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale and are only used for illustration. In fact, the size of the components can be arbitrarily enlarged or reduced to clearly show the features of the embodiments of the present invention.

[0009] Figure 1A The present invention is a flowchart of a method for manufacturing a semiconductor substrate according to an embodiment of the present disclosure.

[0010] Figure 1B The present invention is a flow chart of a method for processing a gate dielectric layer according to an embodiment of the present disclosure.

[0011] Figure 2A , Figure 2B , Figure 2C , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Fig. 6A and Figure 6B Various stages of manufacturing a semiconductor device according to an embodiment of the present disclosure are schematically shown.

[0012] Figure 7 and Figure 8 FIG. 4 is a graph showing the performance improvement of a semiconductor device according to an embodiment of the present disclosure.

[0013] The reference numerals are as follows:

[0014] 100: Method

[0015] 102, 104, 106, 108, 110, 112, 114, 116: Operation

[0016] 150, 152, 154, 156, 158, 160, 162, 164: Operation

[0017] 200:Semiconductor devices

[0018] 210A: n-row doped region / n-type well

[0019] 210B: p-type doped region / p-type well

[0020] 212: Sidewall spacer

[0021] 214:Substrate

[0022] 216A:Semiconductor fins

[0023] 216B:Semiconductor fins

[0024] 218: Isolation layer

[0025] 220A: epitaxial source / drain region

[0026] 220B: epitaxial source / drain region

[0027] 221: Interface layer

[0028] 222: First semiconductor layer / semiconductor layer

[0029] 223: Second semiconductor layer / semiconductor layer

[0030] 224: High dielectric constant dielectric layer

[0031] 225: Gate dielectric layer

[0032] 226: Gate electrode layer

[0033] 226A: p-type gate electrode layer

[0034] 226B: n-type gate electrode layer

[0035] 228: Internal spacer

[0036] 234:CESL

[0037] 236:ILD layer

[0038] 250: Sacrificial gate dielectric layer

[0039] 252: Sacrificial gate electrode layer

[0040] 280: First cover layer

[0041] 282: Second cover layer

[0042] 284: Source layer

[0043] 286: Third cover layer / cover layer

[0044] 288: Barrier layer

[0045] AA:Line

[0046] BB:Line

[0047] CC:Line

[0048] Icell: cell current / current data / channel current

[0049] Vmin: minimum driving voltage

[0050] Vt: threshold voltage DETAILED DESCRIPTION

[0051] The following disclosure provides many embodiments or examples for implementing different elements of the subject matter provided. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, if the description mentions that a first element is formed on a second element, it may include an embodiment in which the first and second elements are in direct contact, and it may also include an embodiment in which an additional element is formed between the first and second elements so that they are not in direct contact. In addition, the embodiments of the present invention may repeat reference values ​​and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity, rather than for indicating the relationship between the different embodiments and / or configurations discussed.

[0052] Furthermore, spatially relative terms such as "under," "below," "lower," "above," "upper," and the like may be used to facilitate description of the relationship between one component or feature and another component or feature in the drawings. Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations depicted in the drawings. When the device is turned to a different orientation (rotated 64 degrees or other orientations), the spatially relative adjectives used therein will also be interpreted based on the orientation after the rotation.

[0053] The foregoing broadly summarizes some aspects of the embodiments described in the present disclosure. Although some embodiments described in the present disclosure are described in the context of a nanosheet channel FET, implementations of some aspects of the present disclosure may be used in other processes and / or other devices, such as planar field effect transistors, fin field effect transistors (Fin-FETs), horizontal all-around gate (Horizontal Gate All Around; HGAA) field effect transistors, vertical all-around gate (Vertical Gate All Around; VGAA) field effect transistors, and other suitable devices. A person skilled in the art of the present invention will readily understand other modifications that are expected to be made within the scope of the present disclosure. In addition, although method embodiments may be described in a specific order, various other method embodiments may also be performed in any logical order and may include fewer or more steps than those described in the present disclosure. In the present disclosure, source / drain refers to source and / or drain. Source and drain may be used interchangeably.

[0054] The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns having, for example, a smaller pitch than that obtained using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins.

[0055] Figure 1A is a flow chart of a method for manufacturing a semiconductor substrate 100 according to an embodiment of the present disclosure. Figure 1B The present invention is a flow chart of a method for processing a gate dielectric layer according to an embodiment of the present disclosure. Figure 2A , Figure 2B , Figure 2C , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Fig. 6A , Figure 6B Various stages of fabricating a semiconductor device 200 are schematically illustrated according to the method 100. For additional embodiments of the method, additional operations may be provided before, during, and after the operations / processes of the method 100, and some operations described below may be replaced or deleted.

[0056] The semiconductor device 200 in the following example is a gate-all-around (GAA) device. It should be noted that embodiments of the present disclosure may be applied to other semiconductor devices, such as Fin-FET devices and planar field effect transistor devices.

[0057] In some embodiments, the semiconductor device 200 may be included in a microprocessor, a memory and / or other integrated circuit (IC) devices. In some embodiments, the semiconductor device 200 may be a part of an IC chip, a system on chip (SoC), or a portion thereof, which includes various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), FinFETs, nanosheet FETs, nanowire FETs, other types of multi-gate FETs, metal-oxide FETs (MOSFETs), complementary metal-oxide semiconductors (CMOS) transistors. For clarity, Figure 2A , Figure 2B , Figure 2C The present invention has been simplified to better understand the inventive concepts of the present disclosure. In some embodiments, the semiconductor device 200 may be part of a memory cell array, such as a static random-access memory (SRAM) cell. Additional components may be added to the semiconductor device 200, and some of the components described below may be replaced, modified, or deleted in other embodiments of the semiconductor device 200.

[0058] like Figure 2A , Figure 2B , Figure 2C As shown, the method 100 begins at operation 102 where semiconductor fins 216A, 216B are formed over a substrate 214 . Figure 2A , Figure 2B , Figure 2C is a schematic cross-sectional view of a semiconductor device 200 . Figure 2B , Figure 2C Along Figure 2A Schematic cross-sectional views of the semiconductor device 200 taken along lines “BB” and “CC”. Figure 2A For along Figure 2B FIG. 2 is a schematic cross-sectional view of the semiconductor device 200 taken along line “AA” in FIG.

[0059] A semiconductor substrate 214 is provided to form the semiconductor device 200 thereon. The semiconductor substrate 214 may include a single crystalline semiconductor material, such as, but not limited to, silicon, germanium, silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium arsenic antimonide (GaAsSb), and indium phosphide (InP). Depending on the circuit design, the substrate 214 may include various doping configurations. For example, different doping profiles, such as n-type wells and p-type wells, may be formed in regions of the substrate 214 designed for different device types, such as NFETs and PFETs. In some embodiments, the substrate 214 may be a silicon-on-insulator (SOI) substrate, which includes an insulator structure (not shown) for enhancement.

[0060] The substrate 214 includes a p-type doped region or p-type well 210B and an n-type doped region or n-type well 210A. One or more n-type devices, such as NFETs, will be formed on and / or in the p-type well 210B. One or more p-type devices, such as PFETs, will be formed on and / or in the n-type well 210A.

[0061] A semiconductor stack may be formed over the n-type well 210A and patterned to form semiconductor fins 216A. The semiconductor stack includes alternating semiconductor layers made of different materials to facilitate the formation of nanosheet channels in a multi-gate p-type device, such as a nanosheet channel PFET. A semiconductor stack may be formed over the p-type well 210B and patterned to form semiconductor fins 216B. The semiconductor stack includes alternating semiconductor layers made of different materials to facilitate the formation of nanosheet channels in a multi-gate n-type device, such as a nanosheet channel NFET. In some embodiments, the semiconductor stack includes a first semiconductor layer 222 interposed by a second semiconductor layer 223. The first semiconductor layer 222 and the second semiconductor layer 223 have different compositions and different oxidation rates and / or different etching selectivities. At a later manufacturing stage, a portion of the second semiconductor layer 222 forms a nanosheet channel in a multi-gate device. Depending on the desired number of channels in the semiconductor device to be formed, more or fewer semiconductor layers 222, 223 may be included in the semiconductor stack. In some embodiments, the number of semiconductor layers 222 and 223 is between 1 and 10.

[0062] Semiconductor layer 222 is intended to be a channel of a GAA device. Semiconductor 223 is intended to be a sacrificial layer between channels in a GAA device. In some embodiments, semiconductor layer 223 may include silicon germanium. Semiconductor layer 223 may be a silicon germanium layer, and the silicon germanium layer may include germanium with a molar ratio greater than 25%. For example, semiconductor layer 223 may be a silicon germanium layer, and the silicon germanium layer may include germanium with a molar ratio between 25% and 50%. The semiconductor layer 222 may include silicon, germanium, a compound semiconductor (silicon carbide (SiC), gallium arsenide, gallium phosphide, indium arsenide and / or indium antimonide), an alloy semiconductor (silicon germanium, gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (InGaAs), gallium indium phosphide (GaInP) and / or gallium indium arsenic phosphide (GaInAsP), or a combination thereof. In some embodiments, the semiconductor layer 222 may be a germanium layer. The semiconductor layer 222 may include a p-type dopant, such as boron. The semiconductor layer 222 may include silicon. In some embodiments, the semiconductor layer 222 may include an n-type dopant, such as phosphorus, arsenic, etc.

[0063] The semiconductor layer 222 and the semiconductor layer 223 may be formed by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes. The semiconductor fin 216A and the semiconductor fin 216B are formed from a semiconductor stack and a portion of the n-type well 210A and a portion of the p-type well 210B below the semiconductor stack, respectively. Each of the semiconductor fins 216A and 216B has an active portion formed from the semiconductor stack and a well portion formed in the n-type well 210A and the p-type well 210B, respectively.

[0064] An isolation layer 218 is then formed by filling the trench between the semiconductor fin 216A and the semiconductor fin 216B and then etching back to below the semiconductor stack of the semiconductor fins 216A and 216B. An isolation material is deposited over the substrate 214 to cover at least a portion of the well portion of the semiconductor fins 216A and 216B. The isolation material may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD), or other suitable deposition processes. In some embodiments, the isolation material may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, or a combination thereof. In some embodiments, an isolation material is formed by a suitable deposition process to cover the semiconductor fins 216A and 216B to fill the trench between the semiconductor fins 216A and 216B, and then a suitable anisotropic etching process is used to perform recessed etching to expose the active portions of the semiconductor fins 216A and 216B, thereby forming an isolation layer 218.

[0065] like Figure 2A , Figure 2B , Figure 2C As shown, in operation 104, a sacrificial gate structure and spacers are then formed over the semiconductor fins 216A, 216B. A sacrificial gate dielectric layer 250 is deposited over the exposed surface of the semiconductor device 200. The sacrificial gate dielectric layer 250 may be conformally formed over the semiconductor fins 216A, 216B and over the isolation layer 218. In some embodiments, the sacrificial gate dielectric layer 250 may be deposited by a CVD process, a sub-atmospheric CVD (SACVD) process, a FCVD process, an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, or other suitable process. The sacrificial gate dielectric layer 250 may include one or more film layers of dielectric materials, such as silicon dioxide, silicon nitride, a high-k dielectric material, and / or other suitable dielectric materials.

[0066] A sacrificial gate electrode layer 252 is deposited over the exposed surface of the semiconductor device 200. The sacrificial gate electrode layer 252 may be blanket deposited over the sacrificial gate dielectric layer 250. The sacrificial gate electrode layer 252 includes silicon, such as polysilicon or amorphous silicon. The thickness of the sacrificial gate electrode layer 252 is between about 42 nm and about 200 nm. In some embodiments, the sacrificial gate electrode layer 252 is planarized. The sacrificial gate electrode layer 252 may be deposited using CVD, including low pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), PVD, ALD, or other suitable processes.

[0067] The sacrificial gate structure is formed over the isolation layer 218 and over the exposed portions of the semiconductor fins 216A, 216B. The sacrificial gate structure is formed over the portions of the semiconductor fins 216A, 216B that will become the channel regions. The sacrificial gate electrode layer 252 and the sacrificial gate dielectric layer 250 are patterned to form the sacrificial gate structure.

[0068] Then, sidewall spacers 212 and inner spacers 228 are formed. The sidewall spacers 212 are formed on the sidewalls of the sacrificial gate structure. After the sacrificial gate structure is formed, the sidewall spacers 212 are formed by blanket depositing an insulating material and then performing anisotropic etching to remove the insulating material from the horizontal surface. The thickness of the sidewall spacers 212 may be between about 4 nm and about 7 nm. In some embodiments, the insulating material of the sidewall spacers 212 is based on a silicon nitride-based material, such as silicon nitride, silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride, and combinations thereof. The exposed semiconductor fins 216A, 216B are etched, and inner spacers 228 are formed. Although each operation is described together, the process for the region of the p-type device (i.e., above the n-type well 210A) and the process for the region of the n-type device (i.e., above the p-type well 210B) may be performed separately using a patterned mask and different process recipes.

[0069] The semiconductor fins 216A and 216B not covered by the sacrificial gate structure are etched to expose the well portions of the semiconductor fins 216A and 216B. In some embodiments, suitable dry etching and / or wet etching may be used to remove the semiconductor layer 222 and the semiconductor layer 223 together or separately.

[0070] After the semiconductor fins 216A, 216B are recessed, an inner spacer 228 is formed. To form the inner spacer 228, the semiconductor layer 223 below the sidewall spacer 212 is selectively etched from the semiconductor layer 222 in a horizontal direction or an x-direction to form a spacer cavity. In some embodiments, the semiconductor layer 223 may be selectively etched by using a wet etchant, such as but not limited to ammonium hydroxide, tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or a potassium hydroxide solution. In some embodiments, the etched thickness of the semiconductor layer 223 along the x-direction is in a range between about 2 nm and about 10 nm.

[0071] After forming the spacer cavity, an inner spacer 228 is formed in the spacer cavity by conformally depositing an insulating layer and then partially removing the insulating layer. The insulating layer can be formed by ALD or any other suitable method. A subsequent etching process removes most of the insulating layer except inside the cavity, thereby forming the inner spacer 228. The thickness of the inner spacer 228 along the X direction is between about 4 nm and about 7 nm.

[0072] like Figure 2A , Figure 2B , Figure 2C As shown, epitaxial source / drain regions 220A, 220B are formed in operation 106. As described above, epitaxial source / drain regions 220A for p-type devices and epitaxial source / drain regions 220B for n-type devices are formed using patterned masks and different epitaxial processes.

[0073] For p-type devices (e.g., PFETs), epitaxial source / drain regions 220A for p-type devices may include silicon, silicon germanium, germanium with one or more layers having p-type dopants (e.g., boron). In some embodiments, epitaxial source / drain regions 220A may be silicon germanium boron (SiGeB) materials, wherein boron is the dopant. Epitaxial source / drain regions 220B for n-type devices may include one or more layers of silicon, silicon phosphide, silicon carbide, and silicon carbon phosphide (SiCP). Epitaxial source / drain regions 220B also include n-type dopants, such as phosphorus, arsenic, etc. In some embodiments, epitaxial source / drain regions 220B may be silicon layers including phosphorus dopants.

[0074] like Figure 2A , Figure 2B , Figure 2CAs shown, in operation 108, a contact etch stop layer (CESL) 234 and an interlayer dielectric (ILD) layer 236 are then formed. The CESL 234 is formed on the epitaxial source / drain regions 220A, on the epitaxial source / drain regions 220B, on the sidewall spacers 212, and on the isolation layer 218. In some embodiments, the thickness of the CESL 234 is between about 4 nm and about 7 nm. The CESL 234 may include silicon nitride (Si 3 N 4 ), silicon oxynitride, silicon carbide nitride (SiCN), or any other suitable material, and may be formed by CVD, PVD, or ALD.

[0075] An ILD layer 236 is formed over the CESL 234. Materials for the ILD layer 236 include compounds of silicon, oxygen, carbon, and / or hydrogen, such as silicon oxide, silicon oxycarbide (SiCOH), and silicon oxycarbide (SiOC). Organic materials, such as polymers, may be used for the ILD layer 236. The ILD layer 236 protects the epitaxial source / drain regions 220A, 220B during removal of the sacrificial gate structure. A planarization process may be performed after depositing the ILD layer 236 to expose the sacrificial gate electrode layer 252.

[0076] like Figure 3A , Figure 3B As shown, in operation 110 , the sacrificial gate structure and the semiconductor layer 223 are removed to expose the semiconductor layer 222 . Figure 3A For along Figure 3B Schematic cross-section along line AA. Figure 3B For along Figure 3A Schematic cross-sectional view of line BB in FIG. The sacrificial gate electrode layer 252 and the sacrificial gate dielectric layer 250 may be removed in sequence. The sacrificial gate electrode layer 252 may be removed using plasma dry etching and / or wet etching. When the sacrificial gate electrode layer 252 is polysilicon, a wet etchant such as a TMAH solution may be used to selectively remove the sacrificial gate electrode layer 252 without removing the dielectric material of the ILD layer 236 and the dielectric material of the CESL 234. After removing the sacrificial gate electrode layer 252, the sacrificial gate dielectric layer 250 may be removed using a suitable etching process.

[0077] The semiconductor layer 223 is then removed during the same etching process or a different process. The semiconductor layer 223 may be selectively removed using a wet etchant such as, but not limited to, ammonium hydroxide, TMAH, EDP, or potassium hydroxide solution.

[0078] like Figure 4A , Figure 4BAs shown, in operation 112 , an interface layer 221 and a high-k dielectric layer 224 are formed on the semiconductor layer 223 . Figure 4A For along Figure 4B Schematic cross-section along line AA. Figure 4B For along Figure 4A Schematic cross-section of line BB.

[0079] After removing the semiconductor layer 223, the interface layer 221 is formed on the exposed surface of the channel region, that is, the exposed surface of the semiconductor layer 222. The interface layer 221 may include a dielectric material, such as silicon oxide (SiO 2 ) layer, silicon nitride layer, silicon oxynitride, and mixed silicon-germanium oxide. A chemical oxidation process may be used to form the interface layer 221. Alternatively, the interface layer 221 may be formed by thermal oxidation, ALD, CVD, and / or other suitable methods. In some embodiments, the thickness of the interface layer 221 may be between about 0.2 nm and about 6 nm.

[0080] like Figure 4A , Figure 4B As shown, a high-k dielectric layer 224 is deposited on the interface layer 221 and other exposed surfaces on the semiconductor device 200. In some embodiments, the high-k dielectric layers 224 for n-type devices and for p-type devices may have different compositions and dimensions and are formed separately using patterned mask layers and different deposition recipes.

[0081] The high-k dielectric layer 224 may include one or more layers of dielectric materials, such as silicon oxide, silicon nitride, or high-k dielectric materials, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include hafnium oxide (HfO 2 ), hafnium silicate (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO 2 -Al 2 O 3 ) alloy, other suitable high-k dielectric materials and / or combinations thereof. In some embodiments, the high-k dielectric layer 224 is a high-k material having a k-value greater than about 3.9, for example, a k-value between 4.0 and 30. The high-k dielectric layer 224 may include hafnium oxide, lanthanum oxide, aluminum oxide, yttrium oxide or combinations thereof.

[0082] In some embodiments, the high-k dielectric layer 224 may be continuously blanket deposited using ALD or plasma-enhanced ALD (PEALD). Alternatively, the high-k dielectric layer 224 may be formed by CVD or any other suitable method. In some embodiments, the high-k dielectric layer 224 has a thickness ranging from about 1 nm to about 6 nm.

[0083] like Figure 5A , Figure 5B , Figure 5C , Figure 5D As shown, in operation 114 , the high-k dielectric layer 224 is processed to incorporate a filling element having vacancy in the high-k dielectric layer 224 . Figure 5A , Figure 5B , Figure 5C , Figure 5D FIG. 1 is a schematic partial enlarged cross-sectional view of the high-k dielectric layer 224 during operation 104 .

[0084] The high-k dielectric layer 224 is a work function layer within the gate structure of a subsequently formed transistor (e.g., GAA FET or FinFET). The work function layer partially controls the threshold voltage of the transistor. More specifically, the threshold voltage value of the field effect transistor (e.g., GAA FET or FinFET) depends on the total thickness and type of the work function layer. In some embodiments, the threshold voltage value can be tuned by adjusting the vacancies in the high-k dielectric layer 224.

[0085] P-type field effect transistors and n-type field effect transistors exhibit different absolute threshold voltages, for example, the magnitude of the threshold voltage is independent of polarity. For example, a p-type field effect transistor requires a higher voltage to turn on, for example to allow current to flow between the source and drain terminals of the transistor. The magnitude of the threshold voltage is related to the work function layer, for example, the elements of the film layer, the thickness of the film layer, and the composition. The work function layers used by p-type field effect transistors and n-type field effect transistors may differ in thickness, number and / or composition. Typically, p-type field effect transistors have a higher absolute threshold voltage than n-type field effect transistors.

[0086] Embodiments of the present disclosure provide methods for treating a high-k dielectric layer 224 to improve threshold voltage control. In some embodiments, a solid phase annealing process is performed to drive filler elements into the high-k dielectric layer of a work function layer stack, such as the high-k dielectric layer 224 in the semiconductor device 200. The atoms of the filler element can fill vacancies in the high-k dielectric material, thereby improving the reliability of the work function layer stack. The treatment of the high-k dielectric layer 224 according to the present disclosure has been shown to increase the current through the channel, reduce the threshold voltage, and reduce the metal boundary effect in semiconductor devices (such as SRAM cells).

[0087] The treatment of the high-k dielectric layer 224 may be performed in a process sequence. In some embodiments, a solid phase annealing process may be used to introduce a fill element into the high-k dielectric layer 224. In some embodiments, the fill element is fluorine. A fluorine-containing source layer may be first deposited on the high-k dielectric layer 224. An annealing process is then performed to drive the fill element from the source layer into the high-k dielectric layer 224. In some embodiments, a cap layer may be formed on the source layer before the annealing process.

[0088] In some embodiments, the high-k dielectric layer 224 may be processed according to Figure 1B The process sequence shown is performed. Specifically, the high-k dielectric layer 224 may be annealed twice. The first annealing process is performed to improve the crystal structure of the high-k dielectric layer 224, for example, to reduce the voids in the high-k dielectric layer 224. The second annealing process is performed to drive the fill element into the high-k dielectric layer 224. Alternatively, the first annealing process may be omitted. Figure 1B As shown, operation 114 may be performed using operations 150 to 164. In operations 150 to 156, a first annealing process is performed. In operations 158 to 164, a second annealing process is performed.

[0089] like Figure 5A As shown, in operation 150, a first capping layer 280 is deposited over the high-k dielectric layer 224. The first capping layer 280 may be a nitride layer. The first capping layer 280 may be formed using ALD, CVD, or any suitable method. In some embodiments, the first capping layer 280 includes a titanium nitride layer. In other embodiments, the first capping layer 280 may be a titanium silicon nitride (TiSiN) layer formed by alternately depositing titanium nitride layers and silicon nitride layers.

[0090] In some embodiments, an optional annealing process may be performed after depositing the first capping layer 280. The optional annealing process may be performed at a temperature between about 600° C. and about 900° C. The duration of the flash anneal may be between about 2 seconds and about 120 seconds. The optional annealing process may be performed using a process gas including ammonia, nitrogen, hydrogen, oxygen, and / or the like. Alternatively, the flash annealing process may be omitted.

[0091] like Figure 5A As shown, in operation 152, a second capping layer 282 is deposited over the first capping layer 280. In some embodiments, the second capping layer 282 may include a silicon capping layer. The second capping layer 282 may be deposited using a silicon-containing precursor, which may include silane, disilane, dichlorosilane (DCS), or the like.

[0092] like Figure 5A As shown, in operation 154, an annealing process is performed. This annealing process may be referred to as a post-capping annealing (PCA) process. The PCA process may be performed using furnace annealing, flash annealing, or a similar annealing process. The temperature of the PCA process may be between about 650° C. and about 1100° C. The PCA process may be performed using a process gas, the process gas including ammonia, nitrogen, hydrogen, oxygen, and / or the like. The duration of the annealing may be between about 2 seconds and about 120 seconds. In some embodiments, the duration of the annealing may be between about 5 seconds and about 60 seconds.

[0093] The PCA process may be performed to reduce silicon / oxide interface traps between the channel region (ie, the semiconductor layer 222 and the interface layer 221 ) and / or to improve interfacial mixing between the interface layer 221 and the high-k dielectric layer 224 .

[0094] In some embodiments, the PCA process may be a flash anneal with a higher peak annealing temperature and a shorter annealing time. In some embodiments, the peak annealing temperature is equal to or less than about 1250° C. The duration of the flash anneal is equal to or less than about 40 milliseconds. The flash annealing process may be performed to reduce silicon / oxide interface traps in the interface layer 221 and the high-k dielectric layer 224.

[0095] In some embodiments, the PCA process may be performed at a temperature of about 600° C. to about 900° C. for a duration of about 2 seconds to about 60 seconds to improve intermixing between the interface layer 221 and the high-k dielectric layer 224 .

[0096] like Figure 5B As shown, in operation 156, the second capping layer 282 and the first capping layer 280 are removed to expose the high-k dielectric layer 224. The deposition, annealing, and subsequent removal of the second capping layer 282 and the first capping layer 280 can improve the reliability of the high-k dielectric layer 224 and the thermal stability of the high-k dielectric layer 224. In some embodiments, operations 150, 152, 154, and 156 can be skipped.

[0097] like Figure 5C As shown, in operation 158, a source layer 284 is deposited over the high-k dielectric layer 224. The source layer 284 can be any suitable film layer containing a filling element. In some embodiments, the filling element is fluorine, and the source layer 284 is a fluorine-containing layer. In some embodiments, the source layer 284 is formed using a fluorine-containing precursor (e.g., tungsten hexafluoride (WF 6 The tungsten layer may be deposited using an ALD process using tungsten hexafluoride and a reducing gaseous reactant. The reducing gas may be a hydrogen-containing chemical such as diborane (B 2 H 6 ), disilane (Si 2 H 6 In some embodiments, process conditions, such as the pressure of the tungsten hexafluoride precursor and the reducing agent and the duty cycle, are selected to allow a certain proportion of fluorine to remain in the source layer 284 (i.e., the tungsten layer). In some embodiments, the fluorine concentration in the source layer 284 can be controlled by measuring the byproducts of the ALD of tungsten. In some embodiments, the source layer 284 can be between about 1000 Å thick and about 2000 Å thick. To about In some embodiments, source layer 284 may include fluorine at a molecular concentration ranging from about 20% to about 50%.

[0098] like Figure 5C As shown, in operation 160, a third capping layer 286 is deposited over the source layer 284. The third capping layer 286 may include a nitride layer, such as titanium nitride. The third capping layer 286 may be formed by ALD or CVD. In some embodiments, in some embodiments, the thickness of the third capping layer 286 may be between 1000 and 2000. Approximately to approximately For example, approximately

[0099] like Figure 5CAs shown, in operation 162, a solid phase annealing process is performed to drive the filling elements into the high-k dielectric layer 224. The solid phase annealing process may be performed using furnace annealing, flash annealing, or a similar annealing process. The temperature of the solid phase annealing process may be between about 500° C. and about 700° C. In some embodiments, the solid phase annealing process may be performed at a temperature of about 500° C. The solid phase annealing process may be performed using a process gas, which may include ammonia, nitrogen, hydrogen, oxygen, and / or the like. The duration of the annealing may be between about 2 seconds and about 120 seconds.

[0100] like Figure 5C As shown, the solid phase annealing process drives the atoms of the filling element (i.e., fluorine atoms) from the source layer 284 into the high-k dielectric layer 224. In some embodiments, the solid phase annealing process may result in a more than four-fold increase in the fluorine concentration in the high-k dielectric layer 224. In some embodiments, the high-k dielectric layer 224 may have a molecular concentration of fluorine between about 10% and about 22%, for example, about 18% to 22%.

[0101] The fluorine atoms combine with the vacancies in the high-k dielectric layer 224, thereby reducing the vacancies in the high-k dielectric layer 224. During operation, the vacancies in the high-k dielectric layer 224 may induce the diffusion of metal elements (such as aluminum) used in the work function layer or the metal filling layer. The atoms of the filling element fill the vacancies in the high-k dielectric layer 224, thereby preventing aluminum from diffusing into the high-k dielectric layer 224, thereby improving device performance. For example, when the semiconductor device 200 is an SRAM cell, the increased fluorine atoms in the high-k dielectric layer 224 can reduce the threshold voltage Vt, reduce the metal boundary effect (caused by aluminum diffusion), reduce the minimum drive voltage (Vmin), and increase the cell current (Icell).

[0102] like Figure 5D As shown, in operation 164, the third capping layer 286 and the source layer 284 are removed. The third capping layer 286 and the source layer 284 may be removed using a suitable process, such as an etching process.

[0103] After removing the third capping layer 286 and the source layer 284 , the high-k dielectric layer 224 is exposed for subsequent processes. Figure 5E FIG. 2 is a schematic partial enlarged cross-sectional view of the gate structure after processing the high-k dielectric layer 224 .

[0104] In some embodiments, Figure 5EAs shown, capping layer 286 is deposited over high-k dielectric layer 224. In some embodiments, capping layer 286 may include a lanthanum-based oxide layer, such as LaO x In some embodiments, the cap layer 286 may include other film layers, such as aluminum oxide (Al 2 O 3 ) layer, silicon oxide (SiO 2 ) layer, yttrium oxide (Y 2 O 3 ), a titanium nitride layer, a titanium silicon nitride layer, a combination thereof, or other suitable capping layers. The capping layer 286 may be formed using PVD, CVD, ALD, and / or other suitable methods.

[0105] In some embodiments, Figure 5E As shown, barrier layer 288 is disposed over capping layer 286. Barrier layer 288 may include metal nitride. For example, barrier layer 288 may include tantalum nitride, titanium nitride, niobium nitride, or a combination thereof. Various other materials are also possible. Barrier layer 288 may be formed by ALD, PVD, CVD, or other suitable methods. Barrier layer 288 may protect capping layer 286 from various etching processes during patterning of a work function metal layer for threshold voltage tuning. For example, a p-type work function metal may be deposited simultaneously over a p-type device region and over an n-type device region, and then the portion located in the n-type region may be replaced with an n-type work function metal. Alternatively, an n-type work function metal may be deposited simultaneously over a p-type device region and over an n-type device region, and then the portion located in the p-type region may be replaced with a p-type work function metal. During these processes, barrier layer 288 protects capping layer 286 from being etched during the patterning / metal removal process.

[0106] The high-k dielectric layer 224, the cap layer 286, and the barrier layer 288 may be collectively referred to as a gate dielectric layer 225. Depending on the design of the semiconductor device 200, more or less film layers may be deposited on the high-k dielectric layer 224 to form the gate dielectric layer 225.

[0107] Reference Figure 1A ,like Fig. 6A , Figure 6B As shown, after the processing sequence of operation 114 , operation 116 is performed to deposit a gate electrode layer 226 or a work function metal layer over the gate dielectric layer 225 . Fig. 6A For along Figure 6B Schematic cross-section along line AA. Figure 6B For along Fig. 6AAs discussed above, the gate electrode layer 226 may include different materials for n-type devices and for p-type devices, and the gate electrode layer 226 may be sequentially deposited using a patterning scheme.

[0108] In some embodiments, the p-type gate electrode layer 226A may be deposited simultaneously on the p-type device region and the n-type device region, and then the n-type gate electrode layer 226B may be used to replace the portion in the n-type region, or vice versa.

[0109] The p-type gate electrode layer 226A may include a metal having a sufficiently large effective work function, selected from but not limited to the group consisting of titanium nitride, tantalum nitride, ruthenium, molybdenum, tungsten, platinum, or a combination thereof. The p-type gate electrode layer 226A may include one or more material film layers. The p-type gate electrode layer 226A may be deposited by CVD, PVD, ALD, and / or other suitable processes.

[0110] The n-type gate electrode layer 226B may include one or more layers of conductive materials. Specifically, the n-type gate electrode layer 226B includes a metal having a sufficiently low effective work function, selected from but not limited to the group consisting of titanium, aluminum, zirconium, tantalum, niobium, titanium aluminum (TiAl), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), titanium silicon nitride (TiSiN), titanium aluminum carbide (TiAlC), or a combination thereof. The n-type gate electrode layer 226B may be deposited by PVD, CVD, ALD, and / or other suitable processes. In some embodiments, the n-type gate electrode layer 226B includes aluminum.

[0111] In some embodiments, a metal filling layer may be deposited over the gate electrode layer 226. The metal filling layer is formed of tungsten or cobalt and may be formed by a suitable method, such as ALD, CVD or other methods. After the metal filling layer is formed, a planarization process may be performed to remove excess portions of the deposition.

[0112] As discussed above, by incorporating fluorine with vacancies in the high-k dielectric layer in the gate structure, embodiments of the present disclosure achieve improved threshold voltage control, particularly for n-type FETs containing aluminum in the work function metal layer. Embodiments of the present disclosure are particularly beneficial for SRAM cells. Figure 7 as well as Figure 8 Contains graphs showing the improvement of SRAM cells.

[0113] Figure 7The channel current data Icell corresponding to various threshold voltages Vt of the n-type FET in the SRAM cell is included. The current data Icell of the SRAM cell of the existing (state-of-art) SRAM is represented by squares. The current data Icell of the SRAM cell according to the present disclosure is represented by diamonds. Figure 7 As shown, the SRAM cell according to the present disclosure (ie, a high-k dielectric layer having a fluorine concentration between about 18% and about 22%) exhibits a 10% increase in the channel current Icell.

[0114] Figure 8 The minimum driving voltage Vmin of the 256M SRAM cell corresponding to different NP voltage differences is included. The current data Icell of the SRAM cell of the existing SRAM is represented by squares. The current data Icell of the SRAM cell according to the present disclosure is represented by diamonds. Figure 8 As shown, the SRAM cell according to the present disclosure (ie, a high-k dielectric layer having a fluorine concentration between about 18% and about 22%) exhibits a 10% reduction in the minimum drive voltage.

[0115] Various embodiments or examples described in the present disclosure provide multiple advantages over the prior art. Using the solid phase annealing process according to the present disclosure, vacancies in the high-k dielectric layer are reduced, thereby preventing aluminum from diffusing into the high-k dielectric layer and improving device performance. Specifically, the embodiments of the present disclosure can reduce the threshold voltage Vt, reduce the metal boundary effect, reduce the minimum drive voltage, and increase the cell current.

[0116] It should be understood that not all advantages are necessarily discussed herein, that all embodiments or examples do not require a particular advantage, and that other embodiments or examples may provide different advantages.

[0117] Some embodiments of the present disclosure provide a method for manufacturing a semiconductor device, comprising: depositing an interface layer on a semiconductor channel region; depositing a high-k dielectric layer on the interface layer; processing the high-k dielectric layer to incorporate a filling element having vacancies into the high-k dielectric layer; and depositing a gate electrode layer on the high-k dielectric layer. In some embodiments, the step of processing the high-k dielectric layer comprises: depositing a source layer on the high-k dielectric layer, wherein the source layer contains a filling element; depositing a cap layer on the source layer, performing an annealing process to incorporate the filling element into the high-k dielectric layer; and removing the cap layer and the source layer. In some embodiments, the filling element is fluorine. In some embodiments, the step of depositing the source layer comprises using a fluorine-containing precursor to deposit a tungsten layer. In some embodiments, the fluorine-containing precursor is tungsten hexafluoride. In some embodiments, the cap layer comprises titanium nitride. In some embodiments, the thickness of the source layer is between about To about In some embodiments, the annealing process is performed at a temperature between about 500°C and about 700°C.

[0118] Some embodiments of the present disclosure provide a method for manufacturing a semiconductor device, comprising: depositing an interface layer on a semiconductor channel region; depositing a high-k dielectric layer on the interface layer; depositing a source layer on the high-k dielectric layer, wherein the source layer contains fluorine; performing a solid phase annealing process to drive fluorine from the source layer into the high-k dielectric layer; removing the source layer; and depositing a gate electrode layer on the high-k dielectric layer. In some embodiments, the method for manufacturing a semiconductor device further comprises: before the step of performing the solid phase annealing process, depositing a first cap layer on the source layer; and removing the first cap layer. In some embodiments, the first cap layer comprises titanium nitride. In some embodiments, the method for manufacturing a semiconductor device further comprises: before the step of depositing the source layer, depositing a titanium nitride layer on the high-k dielectric layer; depositing a silicon layer on the titanium nitride layer; and removing the silicon layer and the titanium nitride layer to expose the high-k dielectric layer. In some embodiments, the step of depositing the source layer comprises depositing a tungsten layer using tungsten hexafluoride. In some embodiments, the solid phase annealing process is performed at a temperature between about 500°C and about 700°C.

[0119] The above summarizes the components of several embodiments so that those skilled in the art can more easily understand the concepts of the present disclosure. Those skilled in the art should understand that they can design or modify other processes and structures based on the disclosure to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also understand that such equivalent processes and structures do not deviate from the spirit and scope of the present disclosure, and they can make various changes, substitutions and replacements without violating the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, comprising: Depositing an interface layer on a semiconductor channel region; Depositing a high dielectric constant dielectric layer on the interface layer; Treating the high-k dielectric layer to dope a filling element having vacancies in the high-k dielectric layer; and A gate electrode layer is deposited on the high-k dielectric layer.

2. The method for manufacturing a semiconductor device as claimed in claim 1, wherein the step of processing the high-k dielectric layer comprises: Depositing a source layer on the high-k dielectric layer, wherein the source layer contains the filling element; depositing a cap layer over the source layer, Performing an annealing process to incorporate the filling element into the high-k dielectric layer; and The cap layer and the source layer are removed.

3. The method for manufacturing a semiconductor device as claimed in claim 2, wherein the filling element is fluorine. 4 . The method for manufacturing a semiconductor device as claimed in claim 3 , wherein the step of depositing the source layer comprises depositing a tungsten layer using a fluorine-containing precursor.

5. A method for manufacturing a semiconductor device, comprising: Depositing an interface layer on a semiconductor channel region; Depositing a high dielectric constant dielectric layer on the interface layer; Depositing a source layer on the high-k dielectric layer, wherein the source layer contains fluorine; performing a solid phase annealing process to drive fluorine from the source layer into the high-k dielectric layer; Remove the source layer; and A gate electrode layer is deposited on the high-k dielectric layer.

6. The method for manufacturing a semiconductor device according to claim 5, further comprising: Before the step of performing the solid phase annealing process, depositing a first cap layer on the source layer; and The first cover layer is removed. 7 . The method for manufacturing a semiconductor device as claimed in claim 5 , wherein the solid phase annealing process is performed at a temperature ranging from 500° C. to 700° C.

8. A method for manufacturing a semiconductor device, comprising: A semiconductor device is formed, comprising: a first source / drain region; a second source / drain region; a channel region disposed between the first source / drain region and the second source / drain region; an interface layer formed on the channel region; a high-k dielectric layer formed on the interface layer, wherein the high-k dielectric layer includes fluorine with a molecular concentration ranging from 18% to 22%; and A gate electrode layer is disposed above the high-k dielectric layer. 9 . The method for manufacturing a semiconductor device as claimed in claim 8 , wherein the gate electrode layer comprises aluminum. 10 . The method for manufacturing a semiconductor device as claimed in claim 8 , wherein the channel region comprises two or more nanosheet channels.

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