An oxide semiconductor thin film transistor and a method for manufacturing the same

Abstract

The application discloses a preparation method of an oxide semiconductor thin film transistor, which comprises the following steps: selecting a substrate, cleaning the substrate, and sequentially forming a back gate electrode, a back gate dielectric, a channel material, a source electrode and a drain electrode on the selected substrate from bottom to top to prepare the oxide semiconductor thin film transistor, wherein the deposition of the back gate dielectric and the channel material adopts an atomic layer deposition process; and the oxide semiconductor thin film transistor is subjected to ozone pulse treatment for a predetermined time. The application can solve the abnormal problem of the switching state of the oxide semiconductor thin film transistor caused by too high carriers, accurately control the threshold voltage of the oxide semiconductor thin film transistor, improve the problem of the rising of the contact resistance caused by the high-temperature long-time heat annealing process, and thus improve the performance of the oxide semiconductor thin film transistor.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, and particularly relates to an oxide semiconductor thin film transistor and its fabrication method. Background Technology

[0002] Thin-film transistors (TFTs) are a special type of transistor characterized by the deposition of semiconductor and other materials onto a substrate using thin-layer technology. TFTs are primarily used in active-matrix liquid crystal displays (AMLCDs) and are a core component of modern display technology. The development of TFT technology has progressed through several stages, including amorphous silicon TFTs, low-temperature polycrystalline silicon TFTs, and oxide semiconductor TFTs. Among these, oxide semiconductor TFTs have gained widespread application in active-matrix displays, 3D monolithic integration of embedded memory, sensors, and in-memory computing due to their advantages such as low-temperature fabrication processes, high mobility, and extremely low leakage current.

[0003] Existing oxide semiconductor thin-film transistors (OSBMTs) typically exhibit an amorphous structure during fabrication, resulting in numerous defects in their bulk and surface, such as oxygen vacancies. When hydrogen impurities act as donor impurities, they provide a large number of electrons, causing abnormal switching states in OSBMTs. Consequently, OSBMTs operate in depletion mode, meaning that even when the gate voltage is zero, source-drain currents still exist. This results in high power consumption during OSBMT operation, limiting their application in CMOS and 3D monolithic integration scenarios.

[0004] To meet the application requirements of oxide semiconductor thin-film transistors (OSTs) in various electronic circuits, it is necessary to regulate the threshold voltage of OSTs. In particular, to achieve enhancement-mode operation, the threshold voltage needs to be shifted positively. Common methods for regulating the threshold voltage of OSTs include changing the thickness of the channel material, using metals with different work functions as gate electrodes, and altering the channel carrier concentration. Annealing is a commonly used method to change the carrier concentration of the oxide channel material because it can suppress the formation of oxygen vacancies in OSTs, thereby solving the problem of excessively high carrier concentration in the device.

[0005] However, traditional thermal annealing methods, with annealing times measured in hours or minutes, hinder the development of efficient fabrication. Furthermore, because thermal annealing involves uniform heating of the device, it can cause redistribution of impurities in the semiconductor material, and even induce the diffusion of impurity elements from the gate dielectric or substrate into the channel material, thus affecting device performance. In addition, insufficient vacuum in the thermal annealing equipment makes the chamber atmosphere susceptible to atmospheric contamination, introducing unexpected impurities during the annealing process. Most importantly, traditional thermal annealing presents a trade-off between performance and threshold voltage. This is because the typically long annealing time can passivate oxygen vacancy defects in the source-drain contact region, increasing contact resistance and reducing the device's saturation output current, thus impacting performance. Therefore, a new threshold voltage control method suitable for oxide semiconductor thin-film transistors needs to be explored.

[0006] This invention designs an oxide semiconductor thin-film transistor and its fabrication method, which can solve the problem of abnormal switching state of oxide semiconductor thin-film transistors caused by excessive charge carriers, accurately control the threshold voltage of oxide semiconductor thin-film transistors, and improve the problem of increased contact resistance caused by high temperature and long-term thermal annealing process, thereby improving the performance of oxide semiconductor thin-film transistors. Summary of the Invention

[0007] To address the shortcomings and improvement needs of existing technologies, this invention provides an oxide semiconductor thin-film transistor and its fabrication method. It can solve the problem of abnormal switching state of oxide semiconductor thin-film transistors caused by excessive charge carriers, accurately control the threshold voltage of oxide semiconductor thin-film transistors, and improve the problem of increased contact resistance caused by high-temperature long-term thermal annealing process, thereby improving the performance of oxide semiconductor thin-film transistors.

[0008] To address the aforementioned technical problems, this invention provides a method for fabricating an oxide semiconductor thin-film transistor, the method comprising the following steps:

[0009] Step S11: Select a substrate, clean the substrate, and sequentially form a back gate electrode, a back gate dielectric, a channel material, a source electrode, and a drain electrode on the selected substrate from bottom to top to fabricate the oxide semiconductor thin-film transistor, wherein the deposition of the back gate dielectric and the channel material is performed using an atomic layer deposition process; and

[0010] Step S12: Perform ozone pulse treatment on the oxide semiconductor thin film transistor for a predetermined time.

[0011] Optionally, the substrate includes a thin film and a base, wherein the thin film is silicon dioxide, aluminum oxide, hafnium oxide or beryllium oxide, and the base is silicon-based, silicon carbide or sapphire.

[0012] The specific steps of S11 include:

[0013] Step S21: Clean the substrate with deionized water and dry it with nitrogen gas, wherein the substrate thickness is 250-400 μm;

[0014] Step S22: A marking layer is prepared on the substrate by spin coating photoresist, baking photoresist, photolithography, development, evaporation deposition of metal, and lift-off process as a marker for alignment of the layout layer;

[0015] Step S23: The back gate electrode is prepared by spin coating photoresist, baking photoresist, photolithography, development, evaporation deposition of metal, and lift-off process, wherein the thickness of the back gate electrode is 10-40 nm.

[0016] Step S24: Deposit the back gate dielectric using an atomic layer deposition process, wherein the thickness of the back gate dielectric is 3-20 nm;

[0017] Step S25: Deposit the channel material using an atomic layer deposition process, wherein the thickness of the channel material is 2-4 nm;

[0018] Step S26 involves isolating the active region through spin-coating photoresist, baking, photolithography, and development processes, wherein the active region is etched using a diluted hydrochloric acid solution after development; and

[0019] Step S27: The source and drain are prepared by spin coating photoresist, baking photoresist, photolithography, development, evaporation deposition of metal, and lift-off process, wherein the thickness of the source and drain is 30-100nm.

[0020] Optionally, the channel material is indium oxide, zinc oxide, tin oxide, gallium oxide, indium zinc oxide, indium gallium oxide, indium tin oxide, zinc tin oxide, zinc gallium oxide, indium gallium zinc oxide, gallium tin zinc oxide, indium aluminum zinc oxide, indium magnesium zinc oxide, indium silicon zinc oxide, indium titanium zinc oxide, indium germanium zinc oxide, or indium molybdenum zinc oxide.

[0021] Optionally, the back gate electrode, the source electrode, and the drain electrode metal are one or a combination of two of nickel, titanium, ruthenium, rhodium, palladium, silver, osmium, iridium, platinum, gold, titanium, aluminum, chromium, germanium, molybdenum, tungsten, copper, cobalt, or iron.

[0022] Optionally, the precursor for depositing the back gate medium is tetra(ethylmethylamine) hafnium (TEMAHf) and ozone.

[0023] Optionally, the precursor for depositing the channel material is trimethylindium and water molecules.

[0024] In step S12, the ozone pulse treatment time is 0-100 seconds, and the ozone pulse treatment temperature is 50-300 degrees Celsius.

[0025] The present invention also provides an oxide semiconductor thin film transistor, which is prepared by the above-described preparation method.

[0026] The oxide semiconductor thin-film transistor and its fabrication method provided by this invention can solve the problem of abnormal switching state of oxide semiconductor thin-film transistors caused by excessive charge carriers, and can also precisely control the threshold voltage of oxide semiconductor thin-film transistors, thereby improving the performance of oxide semiconductor thin-film transistors. Furthermore, it avoids the problems of longer processing time and higher temperature requirements under traditional thermal annealing processes, greatly improving the performance of metal oxide semiconductor thin-film transistors. Attached Figure Description

[0027] Figures 1a-1e This is a schematic diagram of the process steps for fabricating oxide semiconductor thin-film transistors according to an embodiment of the present invention;

[0028] Figure 2 A flowchart illustrating a method for fabricating an oxide semiconductor thin-film transistor according to an embodiment of the present invention;

[0029] Figure 3 A flowchart illustrating a method for fabricating an oxide semiconductor thin-film transistor according to an embodiment of the present invention is shown. Figure 2 Detailed step diagram for step S11;

[0030] Figure 4 This is a schematic diagram illustrating the relationship between the gate voltage and source / drain current of an oxide semiconductor thin-film transistor according to an embodiment of the present invention; and

[0031] Figure 5 This is a comparison chart of the gate voltage and source-drain current relationship of an oxide semiconductor thin film transistor according to an embodiment of the present invention with the gate voltage and source-drain current relationship of an oxide semiconductor thin film transistor processed by conventional thermal annealing. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0033] This invention provides a method for fabricating oxide semiconductor thin-film transistors. Figures 1a-1e A schematic diagram illustrating the process steps for fabricating an oxide semiconductor thin-film transistor according to an embodiment of the present invention is shown. Figure 1aAs shown, a substrate 1 is provided, wherein the substrate 1 includes a thin film 11 and a base 12, wherein the thin film 11 includes, but is not limited to, dielectric materials such as silicon dioxide, aluminum oxide, hafnium oxide, and beryllium oxide, and the base 12 includes, but is not limited to, silicon-based, silicon carbide, and sapphire, wherein the thickness of the substrate 1 is 250-400 μm. In one embodiment, the thin film 11 is selected as a silicon dioxide layer with a thickness of 10-100 nm, and the base 12 is selected as a silicon-based layer.

[0034] like Figure 1b As shown, a back gate electrode 2 is fabricated on the surface of substrate 1. Specifically, the back gate electrode 2 is fabricated using processes including spin-coating photoresist, photoresist baking, photolithography, development, evaporation deposition, and lift-off. The metals evaporated and deposited include, but are not limited to, one or a combination of two of nickel, titanium, ruthenium, rhodium, palladium, silver, osmium, iridium, platinum, gold, titanium, aluminum, chromium, germanium, molybdenum, tungsten, copper, cobalt, or iron. The deposition thickness can be, but is not limited to, 10-40 nm. Preferably, in this invention, the metals evaporated and deposited when fabricating the back gate electrode 2 are 3 nm of nickel and 15 nm of platinum.

[0035] like Figure 1c As shown, a back gate dielectric 3 is deposited on the substrate 1 and the back gate electrode 2. The back gate dielectric 3 includes, but is not limited to, materials such as hafnium dioxide, and the thickness of the back gate dielectric includes, but is not limited to, 3-20 nm. Specifically, the back gate dielectric 3 is, but is not limited to, fabricated using atomic layer deposition (ALD) technology. In one embodiment, hafnium dioxide is deposited as the back gate dielectric 3 using an atomic layer deposition apparatus, with tetra(ethylmethylamine)hafnium (TEMAHf) and ozone (O3) as precursors. The reaction temperature is set to 150-280 degrees Celsius. This reaction temperature is merely an example of the present invention and should not be construed as a limitation of the present invention.

[0036] Figure 1d As shown, channel material 4 is deposited on the back gate dielectric 3. Channel material 4 includes, but is not limited to, indium oxide, zinc oxide, tin oxide, gallium oxide, indium zinc oxide, indium gallium oxide, indium tin oxide, zinc tin oxide, zinc gallium oxide, indium gallium zinc oxide, gallium tin zinc oxide, indium aluminum zinc oxide, indium magnesium zinc oxide, indium silicon zinc oxide, indium titanium zinc oxide, indium germanium zinc oxide, indium molybdenum zinc oxide, etc. The thickness of channel material 4 includes, but is not limited to, 2-4 nm. Specifically, channel material 4 is, but is not limited to, fabricated using atomic layer deposition (ALD) technology. In one embodiment, indium oxide is deposited as channel material 4 using an ALD apparatus, with trimethylindium (TMIn) and water molecules (H2O) as precursors. The reaction temperature is set to 200-225 degrees Celsius. This reaction temperature is merely an example of the present invention and should not be considered a limitation thereof.

[0037] Figure 1eAs shown, source electrode 5 and drain electrode 6 are fabricated on channel material 4. The source and drain metal layers include, but are not limited to, nickel, titanium, ruthenium, rhodium, palladium, silver, osmium, iridium, platinum, gold, titanium, aluminum, chromium, germanium, molybdenum, tungsten, copper, cobalt, or iron. Specifically, they are fabricated using processes such as spin-coating photoresist, photoresist baking, photolithography, development, evaporation deposition, and lift-off. In particular, the source and drain metal layers can be deposited by evaporation, and the deposition thickness can be, but is not limited to, 30-100 nm. Preferably, in one embodiment of the present invention, the evaporated and deposited metals are 15 nm nickel and 25 nm gold.

[0038] like Figure 2 The diagram shown is a flowchart of a method for fabricating an oxide semiconductor thin-film transistor according to an embodiment of the present invention. The method illustrates a fabrication process for an oxide semiconductor thin-film transistor, specifically including the following steps:

[0039] Step S11: Select a substrate, clean the substrate, and form a back gate electrode, a back gate dielectric, a channel material, a source electrode, and a drain electrode sequentially from bottom to top on the selected substrate to prepare an oxide semiconductor thin film transistor. The deposition of the back gate dielectric and the channel material is carried out using an atomic layer deposition process.

[0040] Step S12: The oxide semiconductor thin-film transistor undergoes ozone pulse treatment for a predetermined time. Specifically, in step S11, the selected substrate can be a silicon wafer or a glass substrate, etc.; the back gate electrode, source electrode, and drain electrode are fabricated using processes such as spin-coating photoresist, baking, photolithography, development, evaporation deposition, and lift-off; the back gate dielectric and channel material are deposited using atomic layer deposition (ALD) or other techniques; before fabricating the back gate electrode, a marking layer is prepared using processes such as spin-coating photoresist, baking, photolithography, development, evaporation deposition, and lift-off to prepare markers for alignment of different layout layers on the substrate; and before fabricating the source and drain electrodes, active region isolation is achieved using processes such as spin-coating photoresist, baking, photolithography, and development. In step S12, the fabricated oxide semiconductor thin-film transistor is placed in the atomic layer deposition chamber, and the device undergoes ozone pulse treatment. Specifically, the temperature of the ozone pulse treatment includes, but is not limited to, 50-300 degrees Celsius. The ozone pulse is designed as a rectangular pulse, the rectangular pulse time includes, but is not limited to, 0-100 seconds, and the interval between rectangular pulses is 5-20 seconds. Finally, the device is rinsed with 10-40 ozone pulses. The rectangular pulse time, the interval between rectangular pulses, and the number of ozone pulses are not limited to these.

[0041] In one embodiment, a silicide substrate is first selected, such as one composed of silicon and silicon dioxide. Metal is then deposited on the silicide substrate using processes such as spin-coating photoresist, baking photoresist, photolithography, development, evaporation deposition, and lift-off to serve as the back gate electrode. Next, hafnium dioxide is deposited as the back gate dielectric and oxide as the channel material using atomic layer deposition equipment. Then, metal is deposited as the source and drain electrodes using processes such as spin-coating photoresist, baking photoresist, photolithography, development, evaporation deposition, and lift-off.

[0042] Figure 3 A flowchart illustrating a method for fabricating an oxide semiconductor thin-film transistor according to an embodiment of the present invention is shown. Figure 2 The detailed steps of step S11 are shown in the diagram, which includes:

[0043] Step S21: Clean the substrate with deionized water and dry it with nitrogen gas. The substrate thickness is 250-400 μm. In one embodiment, the deionized water is prepared by mixing deionized water and ammonia in a 5:1 ratio. 150 ml of deionized water and 30 ml of ammonia are poured into a beaker, heated to 70°C on a hot plate, and then 30 ml of hydrogen peroxide is added. The solution is heated to 110°C. After the solution bubbles, the silicon wafer is immersed in the solution and heated for 10 minutes. The wafer is then removed, cleaned with deionized water, and dried with a nitrogen gun. Those skilled in the art should understand that the quantities of solutions, heating temperatures, and times described in this embodiment are for illustrative purposes only and should not be construed as limiting the invention.

[0044] Step S22 involves spin-coating photoresist onto the substrate, followed by baking, photolithography, development, metal deposition by evaporation, and a lift-off process to prepare a marker layer as a marker for alignment with the layout layer. In one embodiment, firstly, polymethyl methacrylate (PMMA A4) electron beam photoresist is dropped onto the cleaned substrate, covering two-thirds of the substrate surface. The photoresist is then spin-coated using a spin coater at 3000 rpm for 60 seconds. Next, the photoresist is baked on a hot plate at 180 degrees Celsius for 90 seconds. Then, electron beam lithography is used to expose the marker layer as a layout. A developer solution with a mass ratio of methyl isobutyl ketone (MIBK) to isopropanol (IPA) of 1:3 is selected. The substrate is immersed in the developer solution for 50 seconds, removed, and cleaned with IPA for 30 seconds, followed by further cleaning. The substrate is dried using a nitrogen gun. During metal deposition, an electron beam evaporation device is used. The deposited metals include, but are not limited to, one or a combination of two of the following: nickel, titanium, ruthenium, rhodium, palladium, silver, osmium, iridium, platinum, gold, titanium, aluminum, chromium, germanium, molybdenum, tungsten, copper, cobalt, or iron. For example, depositing 20nm nickel and 40nm gold. During stripping, the substrate is immersed in an acetone solution at 50°C for 30 minutes, then rinsed with a syringe to remove the photoresist and metal from the unexposed areas. After stripping, the substrate is cleaned with IPA and then dried using a nitrogen gun. Those skilled in the art should understand that the amount of solution, heating temperature, time, and thickness of deposited metal in this embodiment are for illustrative purposes only and should not be construed as limiting the invention.

[0045] Step S23 involves fabricating a back gate electrode through spin-coating photoresist, photoresist baking, photolithography, development, metal evaporation deposition, and lift-off processes. The thickness of the back gate electrode is 10-40 nm. Specifically, the back gate electrode layout design used in the photolithography step involves evaporating and depositing metals including, but not limited to, one or a combination of two of the following: nickel, titanium, ruthenium, rhodium, palladium, silver, osmium, iridium, platinum, gold, titanium, aluminum, chromium, germanium, molybdenum, tungsten, copper, cobalt, or iron. For example, depositing 3 nm of nickel and 15 nm of platinum.

[0046] Step S24: Deposit the back gate dielectric using atomic layer deposition (ALD), wherein the thickness of the back gate dielectric is 3-20 nm. Specifically, an oxide is grown as the back gate dielectric using an ALD apparatus. In one embodiment, the back gate dielectric is hafnium dioxide, and the precursors are tetra(ethylmethylamine)hafnium (TEMAHf) and ozone (O3), with the reaction temperature set to 150-280 degrees Celsius.

[0047] Step S25 involves depositing a channel material using atomic layer deposition (ALD), wherein the thickness of the channel material is 2-4 nm. Specifically, an oxide is grown as the channel material using an ALD apparatus. The channel material includes, but is not limited to, indium oxide, zinc oxide, tin oxide, gallium oxide, indium zinc oxide, indium gallium oxide, indium tin oxide, zinc tin oxide, zinc gallium oxide, indium gallium zinc oxide, gallium tin zinc oxide, indium aluminum zinc oxide, indium magnesium zinc oxide, indium silicon zinc oxide, indium titanium zinc oxide, indium germanium zinc oxide, and indium molybdenum zinc oxide. In one embodiment, indium oxide is deposited as the channel material, with trimethylindium (TMIn) and water molecules (H₂O) as precursors, and the reaction temperature is set to 200-225 degrees Celsius.

[0048] Step S26 involves isolating the active region through spin-coating photoresist, baking the photoresist, photolithography, and development. After development, a diluted hydrochloric acid solution is used to etch and isolate the active region. In one embodiment, a hydrochloric acid solution with a pH of 1 is first prepared, and the developed substrate is immersed face down in the hydrochloric acid solution for 6 minutes. After immersion, the substrate is removed, rinsed with deionized water for about 1 minute, and then dried with a nitrogen gun. Next, after etching, the substrate is immersed in an N-methylpyrrolidone (NMP) solution at 120 degrees Celsius for 2 hours to remove undeveloped photoresist, then cleaned with isopropanol, and finally dried with a nitrogen gun. The pattern used in the photolithography step is a pattern layer for isolating the active region. Those skilled in the art should understand that the solutions, heating temperatures, and times listed in this embodiment are for illustrative purposes only and should not be construed as limiting the invention.

[0049] Step S27 involves fabricating the source and drain electrodes through spin-coating photoresist, photoresist baking, photolithography, development, metal evaporation deposition, and lift-off processes. The thickness of the source and drain electrodes is 30-100 nm. The metals used for evaporation deposition of the source and drain electrodes include, but are not limited to, one or a combination of two of nickel, titanium, ruthenium, rhodium, palladium, silver, osmium, iridium, platinum, gold, titanium, aluminum, chromium, germanium, molybdenum, tungsten, copper, cobalt, or iron. For example, depositing 15 nm of nickel and 25 nm of gold. The photolithography uses a layout design of the source and drain contact layers.

[0050] Specifically, the photoresist mentioned in the above-mentioned fabrication process includes traditional photoresist and electron beam photoresist; photolithography includes traditional photolithography and electron beam photolithography; evaporation deposition includes thermal evaporation deposition and electron beam evaporation deposition.

[0051] Figure 4 This is a schematic diagram illustrating the relationship between the gate voltage and source / drain current of an oxide semiconductor thin-film transistor according to an embodiment of the present invention. Figure 4The figure shows a comparison of the gate voltage and source-drain current of the oxide semiconductor thin-film transistor (OSBMT) after undergoing 10, 20, 30, and 40 cycles of ozone pulse treatment, respectively. The OSBMT undergoing 10 cycles of ozone pulse treatment did not show good switching characteristics; when the gate voltage was 0V, the OSBMT was in the on-state, indicating an excessively high carrier concentration in the channel material. As the number of ozone pulses increased, the switching characteristics of the OSBMT gradually improved, and the threshold voltage gradually shifted positively. This indicates that the ozone pulse treatment effectively controlled the oxygen vacancy defect concentration in the channel material, thereby controlling the carrier concentration range and achieving the switching characteristics of the OSBMT. After 40 cycles of ozone pulse treatment, the device exhibited good switching characteristics, and the on-state current only decreased slightly compared to other conditions. This reflects a decrease in the carrier concentration of the OSBMT, indicating that the ozone pulse treatment had a relatively small impact on the on-state current. The ozone pulse treatment achieved a better balance between the performance and threshold voltage of the OSBMT.

[0052] Figure 5 This is a comparison graph showing the gate voltage and source-drain current relationship of an oxide semiconductor thin-film transistor according to an embodiment of the present invention with that of an oxide semiconductor thin-film transistor processed by conventional thermal annealing. Figure 5 As shown, traditional thermal annealing can also improve the switching characteristics of oxide semiconductor thin-film transistors, achieving a positive shift in threshold voltage. Compared with the oxide semiconductor thin-film transistor of the present invention, after 40 ozone pulse cycles and 10 minutes of traditional thermal annealing, the transfer curve shows a similar threshold voltage, indicating that both treatments achieve similar passivation effects. However, comparing the time, ozone pulse treatment is more efficient. In the embodiments disclosed in this invention, the total effective time of ozone pulse treatment is 100s, while the total effective time of traditional thermal annealing is 600s. Furthermore, the temperature of ozone pulse treatment is lower, ranging from 50-300 degrees Celsius, preferably 200-225 degrees Celsius, while the thermal annealing temperature is 300-500 degrees Celsius. Taking the indium oxide metal oxide used in this invention as an example, the preferred thermal annealing temperature is 400 degrees Celsius. Finally, the long thermal annealing time also passivates the area beneath the source-drain contact, increasing contact resistance. This means that achieving the switching characteristics of oxide semiconductor thin-film transistors inevitably sacrifices some device performance. Furthermore, some applications require oxide semiconductor thin-film transistors with a more positive threshold voltage, necessitating even longer annealing times and resulting in greater performance degradation. Compared to traditional thermal annealing, ozone pulse treatment's efficiency helps resolve the trade-off between high performance and threshold voltage, allowing passivation of the channel material before significantly impacting the contact area.

[0053] The oxide semiconductor thin-film transistor and its fabrication method provided by this invention can solve the problem of abnormal switching state of oxide semiconductor thin-film transistors caused by excessive charge carriers, and can also precisely control the threshold voltage of oxide semiconductor thin-film transistors, thereby improving the performance of oxide semiconductor thin-film transistors. Furthermore, it avoids the problems of longer processing time and higher temperature requirements under traditional thermal annealing processes, greatly improving the performance of metal oxide semiconductor thin-film transistors.

[0054] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for fabricating an oxide semiconductor thin-film transistor, characterized in that, include: Step S11: Select a substrate, clean the substrate, and form the back gate electrode, back gate dielectric, channel material, source electrode and drain electrode sequentially from bottom to top on the selected substrate to prepare the oxide semiconductor thin film transistor, wherein the deposition of the back gate dielectric and the channel material is performed by atomic layer deposition process; as well as Step S12: The oxide semiconductor thin film transistor is subjected to ozone pulse treatment for a predetermined time, wherein the metal of the source and the drain blocks ozone and active oxygen atoms, the ozone pulse treatment passivates the non-metal-covered channel region, and the ozone pulse treatment controls the carrier concentration range by adjusting the oxygen vacancy defect concentration in the channel material to achieve the switching characteristics of the oxide semiconductor thin film transistor.

2. The method for fabricating an oxide semiconductor thin-film transistor according to claim 1, characterized in that, The substrate includes a thin film and a base, wherein the thin film is silicon dioxide, aluminum oxide, hafnium oxide or beryllium oxide, and the base is silicon-based, silicon carbide or sapphire.

3. The method for fabricating an oxide semiconductor thin-film transistor according to claim 1, characterized in that, Step S11 specifically includes: Step S21: Clean the substrate with deionized water and dry it with nitrogen gas, wherein the substrate thickness is 250-400 μm; Step S22: A marking layer is prepared on the substrate by spin coating photoresist, baking photoresist, photolithography, development, evaporation deposition of metal, and lift-off process as a marker for alignment of the layout layer; Step S23: The back gate electrode is prepared by spin coating photoresist, baking photoresist, photolithography, development, evaporation deposition of metal, and lift-off process, wherein the thickness of the back gate electrode is 10-40 nm. Step S24: Deposit the back gate dielectric using an atomic layer deposition process, wherein the thickness of the back gate dielectric is 3-20 nm; Step S25: Deposit the channel material using an atomic layer deposition process, wherein the thickness of the channel material is 2-4 nm; Step S26 involves isolating the active region through spin-coating photoresist, baking, photolithography, and development processes. After development, the active region is etched using a diluted hydrochloric acid solution. Step S27: The source and drain are prepared by spin coating photoresist, baking photoresist, photolithography, development, evaporation deposition of metal, and lift-off process, wherein the thickness of the source and drain is 30-100nm.

4. The method for fabricating an oxide semiconductor thin-film transistor according to claim 3, characterized in that, The channel material is indium oxide, zinc oxide, tin oxide, gallium oxide, indium zinc oxide, indium gallium oxide, indium tin oxide, zinc tin oxide, zinc gallium oxide, indium gallium zinc oxide, gallium tin zinc oxide, indium aluminum zinc oxide, indium magnesium zinc oxide, indium silicon zinc oxide, indium titanium zinc oxide, indium germanium zinc oxide, and indium molybdenum zinc oxide.

5. The method for fabricating an oxide semiconductor thin-film transistor according to claim 3, characterized in that, in, The back gate electrode, the source electrode, and the drain electrode metal are one or a combination of two of the following: nickel, titanium, ruthenium, rhodium, palladium, silver, osmium, iridium, platinum, gold, titanium, aluminum, chromium, germanium, molybdenum, tungsten, copper, cobalt, or iron.

6. The method for fabricating an oxide semiconductor thin-film transistor according to claim 3, characterized in that, in, The precursors for depositing the back gate medium are tetra(ethylmethylamine) hafnium (TEMAHf) and ozone.

7. The method for fabricating an oxide semiconductor thin-film transistor according to claim 4, characterized in that, in, The precursor for depositing the channel material is trimethylindium and water molecules.

8. The method for fabricating an oxide semiconductor thin-film transistor according to claim 1, characterized in that, In step S12, the ozone pulse treatment lasts for 0-100 seconds.

9. The method for fabricating an oxide semiconductor thin-film transistor according to claim 8, characterized in that, In step S12, the temperature of the ozone pulse treatment is 50-300 degrees Celsius.

10. An oxide semiconductor thin-film transistor, characterized in that, It is prepared by the method for preparing oxide semiconductor thin film transistors as described in claim 1.

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