Semiconductor radio frequency device and method of fabricating a gate thereof

Abstract

The application discloses a semiconductor radio frequency device and a preparation method of a gate thereof. The preparation method of the gate of the semiconductor radio frequency device comprises the following steps: forming a support layer on an epitaxial structure, and forming a gate cap metal layer on the support layer; forming a gate root metal layer with uniform thickness and continuity on the surface of the epitaxial structure and / or the support layer and the gate cap metal layer; etching the gate root metal layer, and at least the gate root metal layer covering the sidewall of the gate cap metal layer or covering the sidewall of the gate cap metal layer / the sidewall of the support layer is reserved and serves as a gate root, and the gate root cooperates with the gate cap metal layer to form a gate. The gate length is defined by depositing a gate metal film / etching a gate metal film, and experimental results show that the gate length of 30nm-300nm can be stably prepared by the scheme of the application.

Description

TECHNICAL FIELD

[0001] The application particularly relates to a semiconductor radio frequency device and a preparation method of a gate thereof, and belongs to the technical field of micro-nano. BACKGROUND

[0002] The main research direction of the current GaN HEMT is how to improve the working frequency of the device. The gate length of the device is one of the most critical factors affecting the frequency performance of the device. In the process of pursuing higher frequency performance, the gate length of the mainstream GaN HEMT device has been successfully reduced to below 100 nm. The extremely short gate line width poses extremely strict challenges to the manufacturing process of the device.

[0003] In the manufacturing process of the GaN HEMT radio frequency device, the preparation of the nanometer gate generally relies on an electron beam lithography machine to perform nanometer line lithography. In order to improve the performance of the device, most devices adopt a T-shaped gate, the gate cap is about 300 nm to 800 nm, and the gate root is generally below 150 nm or even below 100 nm. The long gate cap is used to reduce the gate resistance, and the short gate root is used to improve the transconductance. Therefore, the requirements for lithography are very strict. The process flow of the T-shaped gate is to first coat two or three layers of photoresist on the GaN / AlGaN heterojunction, then define the pattern by electron beam lithography, and finally deposit metal and then peel off to prepare the T-shaped gate. The similar preparation scheme of the extremely short gate of the GaN HEMT radio frequency device also includes a self-aligned gate end technology, a photoresist thermal reflow process, etc.

[0004] The existing electron beam lithography process flow is shown in Figure 1 However, the current electron beam lithography still has some disadvantages, as shown in Figure 2 On the one hand, the electron beam lithography machine will encounter problems such as charge accumulation and overlay deviation when preparing lines less than 100 nm, as shown in the figure. These problems are related to many factors such as electron beam photoresist, ultraviolet lithography prepared electron beam lithography marks, mark recognition, electron beam lithography dose, wafer conductivity, etc. Moreover, the wafer in-die consistency is also difficult to guarantee. In actual production, a large amount of manpower and material resources are needed for parameter verification. On the other hand, due to the process principle characteristics of the electron beam lithography, its processing efficiency is very low. The electron beam needs to "write" out each line on the wafer one by one, which requires a lot of time compared with the ultraviolet lithography technology and other batch processing technologies. It often takes 5-6 hours to complete the entire electron beam lithography preparation of a 2-inch wafer.

[0005] Based on the disadvantages of electron beam lithography, some researchers in the industry have also developed many self-alignment technologies, such as: self-alignment gate end process, photoresist hot reflow process, twice ultraviolet lithography overlay definition gate length and the like. The alignment gate end process realizes the preparation of the radio frequency device without electron beam lithography, but the gate length is defined by wet etching, which is difficult to accurately control in the actual application, and the gate length prepared in the literature is 210 nm. The photoresist hot reflow process is relatively simple and can also achieve a smaller gate size, but whether the gate length can be prepared below 100 nm remains to be discussed. In addition, through the photoresist hot reflow method, on the one hand, the accuracy is difficult to control, and on the other hand, the cross section of the photoresist after hot reflow is an irregular curve, and the gate root height of the device is difficult to control, which will increase the parasitic capacitance of the device. The scheme of twice ultraviolet lithography overlay definition gate length completely depends on the overlay alignment capability of the lithography machine, and the error is large.

[0006] In summary, in the process of preparing GaN HEMT nanometer gate, the current mainly relies on electron beam lithography technology. Although it can realize extremely short gate size, it also has many problems. For example, the charge accumulation effect will cause the line width of the lithography to be difficult to control; the overlay deviation problem will affect the gate alignment accuracy; the mechanical strength and processing efficiency of the gate are also the problems that need to be overcome in the preparation process. These problems make it difficult for GaN HEMT prepared by relying on electron beam lithography to realize mass processing, and the yield is limited. And for the current international environment, the introduction, repair and maintenance of electron beam lithography machine will also be limited. In order to solve the dependence of GaN HEMT nanometer gate on electron beam lithography, some researchers try to develop self-alignment process. Although this method can avoid the dependence on electron beam lithography technology, the prepared gate length is limited, and the consistency of the gate length is difficult to control. Therefore, how to get rid of the dependence of nanometer gate preparation on electron beam lithography machine and provide an effective scheme that can avoid using electron beam lithography technology and prepare extremely short gate is still one of the problems to be solved in the industry. SUMMARY

[0007] The main purpose of the present application is to provide a semiconductor radio frequency device and a preparation method of the gate thereof, so as to solve the dependence of nanometer gate preparation on electron beam lithography machine and the problems of gate alignment and process efficiency, thereby overcoming the deficiencies in the prior art.

[0008] In order to achieve the above-mentioned purpose of the application, the technical scheme adopted by the present application comprises:

[0009] The first aspect of the embodiment of the present application provides a preparation method of a gate of a semiconductor radio frequency device, which comprises:

[0010] forming a support layer on the epitaxial structure, and forming a gate cap metal layer on the support layer;

[0011] A gate root metal layer with uniform thickness and continuity is formed on the surface of the epitaxial structure and / or the support layer and the gate cap metal layer;

[0012] The gate root metal layer is etched, and at least the gate root metal layer covering the gate cap sidewall or covering the gate cap sidewall / the support layer sidewall is reserved and serves as a gate root, the gate cap metal layer serves as a gate cap, and the gate root and the gate cap electrically cooperate to form a gate.

[0013] The second aspect of the embodiment of the present application provides a semiconductor radio frequency device, and the gate of the semiconductor radio frequency device is obtained by the preparation method of the gate of the semiconductor radio frequency device.

[0014] Compared with the prior art, the advantages of the present application include:

[0015] The preparation method of the semiconductor radio frequency device provided by the embodiment of the present application has low requirements on equipment, and the embodiment of the present application prepares an extremely short gate through deposition-etching, and the present application can completely not need electron beam lithography technology, and domestic equipment can meet the production demand.

[0016] The preparation method of the semiconductor radio frequency device provided by the embodiment of the present application has high efficiency, the electron beam lithography used in the prior art has low efficiency and great process difficulty, the present application defines a gate cap metal layer pattern through i-line lithography, and defines a gate root through deposition-etching, and the present application has higher efficiency and can be mass-produced. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 is a manufacturing flowchart of a single gate root T-shaped gate in the prior art;

[0018] Figure 2 is a diagram of unstable factors of an electron beam lithography process in the prior art;

[0019] Figure 3 is a manufacturing flowchart of a semiconductor radio frequency device provided in the embodiment of the present application;

[0020] Figure 4 is a coverage effect diagram of a side wall W layer after inserting a Ni layer in the embodiment of the present application. DETAILED DESCRIPTION

[0021] In view of the deficiencies in the prior art, the present application has been proposed by the present inventor after long-term research and a large number of practices. The technical solution, the implementation process and principles thereof will be further explained as follows.

[0022] The first aspect of the embodiment of the present application provides a preparation method of a gate of a semiconductor radio frequency device, which comprises:

[0023] forming a support layer on the epitaxial structure, and forming a gate cap metal layer on the support layer;

[0024] forming a gate root metal layer with uniform thickness and continuity on the surface of the epitaxial structure and / or the support layer, the gate cap metal layer;

[0025] etching the gate root metal layer, and at least retaining the gate root metal layer covering the gate cap sidewall or covering the gate cap sidewall / the support layer sidewall as a gate root, the gate cap metal layer as a gate cap, and the gate root and the gate cap electrically cooperating to form a gate electrode.

[0026] Further, the method for preparing the gate electrode of the semiconductor radio frequency device comprises:

[0027] forming a support layer on the epitaxial structure, the support layer comprising a first support part, a second support part and a third support part arranged in sequence, the first support part, the second support part and the third support part of the support layer covering a first region, a second region and a third region of the epitaxial structure respectively, one of the source region and the drain region being located in the first region, and the other being located in the third region;

[0028] forming a gate cap metal layer on the second support part of the support layer;

[0029] etching to remove the third support part to expose the third region of the epitaxial structure;

[0030] forming a gate root metal layer with continuity and uniform thickness on the surface of the first support part of the support layer, the gate cap metal layer and the third region of the epitaxial structure, and then removing the gate root metal layer except for the gate root metal layer remaining on the second sidewall of the gate cap metal layer and the third sidewall of the second support part, the gate root metal layer remaining on the second sidewall of the gate cap metal layer and the third sidewall of the second support part as a gate root, wherein the first sidewall and the second sidewall of the gate cap metal layer are oppositely arranged, the first sidewall being a sidewall close to the first support part of the support layer, and the third sidewall of the second support part being located on the same side as the second sidewall.

[0031] Further, the method for preparing the gate electrode of the semiconductor radio frequency device comprises:

[0032] forming a second mask on the first support part of the support layer and a part of the gate cap metal layer close to the first support part;

[0033] using the second mask and the gate cap metal layer as a mask together to etch and remove the third support part to expose the third region of the epitaxial structure;

[0034] The second mask is removed, and a continuous and uniform-thickness gate root metal layer is formed on the first supporting part of the supporting layer, the gate cap metal layer, and the surface of the third region of the epitaxial structure;

[0035] An anisotropic etching process is used to etch the gate root metal layer, so as to synchronously remove the gate root metal layer distributed on the first sidewall and the second sidewall of the gate cap metal layer and the third sidewall of the second supporting part.

[0036] Further, the second sidewall of the gate cap metal layer and the third sidewall of the second supporting part are vertical, and the second sidewall and the third sidewall are located in the same vertical plane.

[0037] In a more specific embodiment, the method for manufacturing the gate of the semiconductor radio frequency device specifically comprises:

[0038] A Ti / Au / Cr / Ni metal layer is formed on the second supporting part of the supporting layer as a gate cap metal layer;

[0039] The third supporting part is etched to expose the third region of the epitaxial structure;

[0040] A uniform-thickness and continuous Ni layer and a first W layer are sequentially formed on the first supporting part of the supporting layer, the gate cap metal layer, and the surface of the third region of the epitaxial structure, so as to form a Ni / W metal layer;

[0041] The Ni / W metal layer on the surface of the gate cap metal layer and the Ni layer and the Cr layer on the surface layer of the gate cap metal layer are removed;

[0042] A uniform-thickness and continuous second W layer is further formed on the surface of the remaining Ni / W metal layer and the remaining gate cap metal layer, and the second W layer is laminated with the remaining Ni / W metal layer to form the gate root metal layer;

[0043] Preferably, the Ni layer and the first W layer in the Ni / W metal layer are formed by physical vapor deposition, and the second W layer is formed by chemical vapor deposition;

[0044] Further, the method for removing the Ni / W metal layer on the surface of the gate cap metal layer and the Ni layer and the Cr layer on the surface layer of the gate cap metal layer specifically comprises: etching the Cr layer in the gate cap metal layer, and the Ni layer covering the Cr layer in the gate cap metal layer, the Ni / W metal layer covering the gate cap metal layer, and the Au layer of the gate cap metal layer are separated and removed.

[0045] Further, the thickness of the second W layer is greater than the thickness of the first W layer.

[0046] Further, the method for removing the gate root metal layer distributed outside the first sidewall and the second sidewall of the gate cap metal layer and the third sidewall of the second support part specifically comprises:

[0047] First, the anisotropic etching process is used to synchronously remove the second W layer and the first W layer distributed outside the first sidewall and the second sidewall of the gate cap metal layer and the third sidewall of the second support part, and then the Ni layer distributed outside the first sidewall and the second sidewall of the gate cap metal layer and the third sidewall of the second support part is etched.

[0048] Compared with the previous proposal of forming the gate metal by using only a single magnetron sputtering, the present application can provide better sidewall shape covering effect, higher gate metal work function, lower gate input resistance, and the Ni metal in the gate root metal layer can be used as an etching stop layer when etching W, thereby avoiding damage to the device in the over-etching W process.

[0049] Further, the method for preparing the gate of the semiconductor radio frequency device specifically comprises: forming a patterned first mask on the support layer, and then forming a gate cap metal layer in a region not covered by the first mask.

[0050] Further, the material of the support layer comprises at least one of inorganic non-metallic materials and organic materials, but is not limited thereto.

[0051] The second aspect of the embodiment of the present application provides a semiconductor radio frequency device, and the gate of the semiconductor radio frequency device is obtained by the method for preparing the gate of the semiconductor radio frequency device.

[0052] Further, the semiconductor radio frequency device comprises:

[0053] An epitaxial structure and a source electrode, a drain electrode and a gate electrode matched with the epitaxial structure, the gate electrode being arranged between the source electrode and the drain electrode, and the source electrode and the drain electrode being electrically connected through a carrier channel in the epitaxial structure;

[0054] Further, the epitaxial structure is further provided with a support layer, the support layer being arranged at least in a gate region, and a drain region of the epitaxial structure being completely exposed, the gate electrode comprising a gate root and a gate cap, the gate cap being arranged on the support layer, the gate cap having a second sidewall, a second support part of the support layer having a third sidewall, the second sidewall and the third sidewall being located in a same vertical plane, and the gate root being continuously arranged on the second sidewall of the gate cap and the third sidewall of the second support part.

[0055] Further, the epitaxial structure comprises a GaN-based heterojunction or a GaAs-based heterojunction, etc.

[0056] The technical solutions, implementation processes and principles will be further explained in combination with the drawings and specific implementation cases. Unless specifically stated, the semiconductor epitaxy, photolithography, etching, metal deposition, device isolation and other processes and their equipment used in the embodiments of the present application can be known in the art, and the photoresist, epitaxial structure material, electrode material and the like used can also be known in the art.

[0057] Embodiment 1

[0058] Please refer to Figure 3 A method for manufacturing a semiconductor radio frequency device, comprising the following steps:

[0059] (a) manufacturing an epitaxial structure comprising an AlGaN / GaN heterojunction, of course, the epitaxial structure can also comprise a cap layer, a buffer and the like and its structure, and the specific structure of the epitaxial structure can be known in the art, which is not specifically described here.

[0060] (b) isolating the devices of the epitaxial structure, specifically, the device isolation can be achieved by ion implantation to form an isolation region or etching to form an isolation trench, and the device isolation of the epitaxial structure is a conventional process known in the art, which is not specifically limited here.

[0061] (c) manufacturing a source and a drain in the source region and the drain region of the epitaxial structure, and electrically connecting the source and the drain with the two-dimensional electron gas in the epitaxial structure; of course, an ohmic contact layer can also be formed in the source region and the drain region of the epitaxial structure first, and then the source and the drain are manufactured on the ohmic contact layer, the ohmic contact layer can be a heavily doped GaN layer, and of course, the ohmic contact layer can also be manufactured by ion implantation and the like, it can be understood that the formation of the ohmic contact layer to realize the ohmic contact between the source, the drain and the epitaxial structure is a conventional process known in the art, which is not specifically limited here.

[0062] (d) depositing a layer of SiO2 as a support layer on the surface of the epitaxial structure, the thickness and other parameters of the support layer are not the key technology of the present application, and are not specifically limited here, and the support layer is defined to comprise a first support part, a second support part and a third support part arranged in sequence along the lateral direction of the support layer.

[0063] (e) forming a patterned first mask on the support layer by photoresist (PR) to define the position and pattern of the gate cap metal layer; specifically, the first mask covers the first support part and the third support part of the support layer.

[0064] (f) depositing a Ti / Au / Cr / Ni metal stack as a gate cap metal layer on the second support part of the support layer surface not covered by the first mask (which can be understood as a gate region), the thickness of each layer is not specifically limited here, and the bottom layer of the Ti / Au / Cr / Ni metal stack is a Ti layer.

[0065] (g) stripping off the first mask to form a patterned gate cap metal layer; the way of stripping off the first mask can adopt a way known in the art, which is not specifically limited here.

[0066] (h) photoetching and covering photoresist (PR) on the surface of the first support part of the support layer and the part of the gate cap metal layer close to the first sidewall thereof to form a second mask, the other part of the gate cap metal layer close to the second sidewall thereof and the third support part of the support layer close to the second sidewall of the gate cap metal layer are exposed, wherein the first sidewall and the second sidewall are arranged back to back, and one of the first sidewall and the second sidewall faces the source electrode, and the other one faces the drain electrode.

[0067] It should be noted that, in order to solve the problem of poor step coverage of the W metal layer prepared by magnetron sputtering (PVD), the present application uses chemical vapor deposition (CVD) to prepare the gate root material W, and CVD preparation of W is in a high-temperature environment, so photoresist cannot be used as a photoetching mask, and other inorganic material masks will become more difficult to remove after being subjected to high temperature (such as SiO2), and the problem of removing the inorganic material mask removal corrosion medicine also needs to be considered, the present application only exposes one side wall of the support layer close to the second sidewall of the gate cap metal layer, and the other side of the support layer serves as a mask for depositing W, after depositing the W material, only the gate root metal layer on one side of the second sidewall of the gate cap metal layer is in contact with the barrier layer to form an effective gate.

[0068] (i) etching away the third support part of the support layer close to the second sidewall of the gate cap metal layer with the second mask and the gate cap metal layer as masks, the area of the epitaxial structure surface close to the second sidewall of the gate cap metal layer is exposed, and the third sidewall of the second support part of the remaining support layer is located on the same side as the second sidewall of the gate cap metal layer and in the same vertical plane.

[0069] (j) removing the second mask, and sequentially depositing a Ni layer and a first W layer on the surface of the structure formed in step (i) by using a magnetron sputtering process to form a Ni / W metal stack, which can ensure covering the top and sidewall of the gate cap metal layer.

[0070] (k) removing the Cr layer in the gate cap metal layer by a wet etching process, the Ni layer covering the Cr layer in the gate cap metal layer, the Ni / W metal stack covering the gate cap metal layer and the Au layer in the gate cap metal layer are removed, thereby avoiding the problem of splitting between the gate root and the gate cap when etching the residual Ni layer in step (n).

[0071] (l) forming a second W layer with uniform thickness and continuity on the surface of the structure formed in step (k) by a chemical vapor deposition process, the second W layer and the residual Ni / W metal stack form the gate root metal layer, as shown in Figure 4 The thickness of the second W layer is greater than the thickness of the first W layer, and the thickness of the second W layer is 120 nm.

[0072] The CVD process is used to form the second W layer, the step coverage of the W layer formed by the CVD process is better, the aspect ratio (ratio of side wall gate length to film thickness) of the W layer obtained by the PVD process is about 0.37, the aspect ratio of the W layer prepared by the CVD process is about 0.8-0.9, and the shape is basically preserved. The resistivity of the W layer formed by the CVD process is lower, which is beneficial to the improvement of the device. The resistivity of the W layer prepared by the PVD process is about 120 μΩ·cm; while the resistivity of the W layer prepared by the CVD process is about 18 μΩ·cm. The W layer is formed by two processes, which is beneficial to the addition of the Ni etching stop layer. The work function of Ni is higher, which is 5.15 while the work function of W is 4.5. The gate of the HEMT device prepared by the AlGaN / GaN heterojunction is usually Ni / Au, Pt / Au, etc., and the contact layer is Ni, Pt, etc. high work function metal. After inserting the Ni layer under the W layer, the Ni layer can be used as the etching stop layer for etching the W layer, which prevents the plasma damage to the barrier layer during etching the W layer. After etching the W layer, the surface Ni layer can be removed by wet etching, and the Ni under the gate root is retained. Therefore, inserting the Ni layer under the W layer can greatly improve the performance of the device.

[0073] (m) simultaneously etching the gate root metal layer by anisotropic etching process, stopping at the bottom Ni layer of the gate root metal layer, and removing the W layer (including the first W layer and the second W layer) on the surface of the gate root metal layer except the third side wall of the gate cap metal layer first side wall, the second side wall, the second support part, and the Au layer on the surface of the gate cap metal layer is exposed.

[0074] (n) removing the Ni layer remaining on the surface of the first support part of the support layer and the drain region of the epitaxial structure by a wet etching process, the gate root metal layer remaining on the second side wall of the gate cap metal layer and the third side wall of the second support part of the support layer as the gate root, and the pre-reserved Au layer as the gate cap, thereby forming the gate.

[0075] It should be noted that the preparation method further comprises processing the residual W and the support layer covering the source after etching the gate root metal layer, and preparing a lead wire, etc.

[0076] The W layer prepared by the CVD process can achieve better profile coverage effect (in the case of the same thickness of the deposited thin film, the side wall is thicker), in the case of the same etching condition, a thinner W can achieve the same effect as the prior art, and the resistivity of the W gate root is lower, and after adding the Ni etching stop layer, the gate length can be reduced by increasing the over-etching time. The semiconductor radio frequency device preparation method provided by the embodiment of the application has low equipment requirements, the extremely short gate is prepared by deposition-etching, and the application can completely not need electron beam lithography technology, and domestic equipment can meet the production requirements.

[0077] The semiconductor radio frequency device preparation method provided by the embodiment of the application has high efficiency, the electron beam lithography used in the prior art has low efficiency and high process difficulty, the application defines the gate cap metal layer pattern through i-line lithography, and defines the gate root through deposition-etching, and the efficiency is higher, and batch production can be performed.

[0078] In view of the problem of difficult preparation of the nanometer gate of the AlGaN / GaN HEMT radio frequency device, the application provides a more stable scheme to realize the preparation of the nanometer gate. For the traditional single-gate radio frequency device, the application defines the gate length by depositing a gate metal thin film / etching a gate metal thin film, and experimental results show that the gate length of 30nm-300nm can be stably prepared by the scheme of the application.

[0079] It should be understood that the above embodiments are only for illustrating the technical concept and characteristics of the application, and the purpose is to enable those skilled in the art to understand the content of the application and implement it, and cannot limit the protection scope of the application. Any equivalent changes or modifications made according to the spirit and principle of the application should be covered within the protection scope of the application.

Claims

1. A method of fabricating a gate of a semiconductor radio frequency device, characterized by, The application comprises the following steps: forming a support layer on the epitaxial structure, the support layer comprising a first support part, a second support part and a third support part arranged in sequence, the first support part, the second support part and the third support part of the support layer covering the first region, the second region and the third region of the epitaxial structure respectively, one of the source region and the drain region being located in the first region and the other being located in the third region; forming a gate cap metal layer on the second support part of the support layer; etching the third support part to expose the third region of the epitaxial structure; forming a continuous and uniform-thickness gate root metal layer on the surface of the first support part of the support layer, the gate cap metal layer and the third region of the epitaxial structure, and then removing the gate root metal layer except for the first sidewall and the second sidewall of the gate cap metal layer and the third sidewall of the second support part, so that the gate root metal layer remaining on the second sidewall of the gate cap metal layer and the third sidewall of the second support part serves as a gate root, the gate cap metal layer serves as a gate cap, and the gate root and the gate cap electrically cooperate to form a gate electrode, wherein the first sidewall and the second sidewall of the gate cap metal layer are oppositely arranged, the first sidewall is the sidewall close to the first support part of the support layer, and the third sidewall is located on the same side as the second sidewall.

2. The method of claim 1, wherein the method further comprises: Specifically, the application comprises the following steps: forming a second mask on the first support part of the support layer and a part of the gate cap metal layer close to the first support part; using the second mask and the gate cap metal layer as a mask, etching the third support part to expose the third region of the epitaxial structure; removing the second mask and forming a continuous and uniform-thickness gate root metal layer on the surface of the first support part of the support layer, the gate cap metal layer and the third region of the epitaxial structure; using an anisotropic etching process to etch the gate root metal layer to synchronously remove the gate root metal layer except for the first sidewall and the second sidewall of the gate cap metal layer and the third sidewall of the support layer.

3. A method of fabricating a gate of a semiconductor radio frequency device according to claim 1 or 2, characterised in that: The second sidewall of the gate cap metal layer and the third sidewall of the second support part are both vertical, and the second sidewall and the third sidewall are located in the same vertical plane.

4. The method of claim 1 or 2, wherein Specifically, the application comprises the following steps: forming a Ti / Au / Cr / Ni metal stack as a gate cap metal layer on the second support part of the support layer; etching the third support part to expose the third region of the epitaxial structure; forming a uniform-thickness and continuous Ni layer and a first W layer in sequence on the surface of the first support part of the support layer, the gate cap metal layer and the third region of the epitaxial structure, thereby forming a Ni / W metal stack; removing the Ni / W metal stack on the surface of the gate cap metal layer and the Ni layer and the Cr layer on the surface layer of the gate cap metal layer; forming a uniform-thickness and continuous second W layer on the surface of the remaining Ni / W metal stack and the remaining gate cap metal layer, and the second W layer and the remaining Ni / W metal stack form the gate root metal layer.

5. The method of claim 4, wherein: The Ni layer and the first W layer in the Ni / W metal stack are formed by physical vapor deposition, and the second W layer is formed by chemical vapor deposition.

6. The method of claim 4, wherein: The method for removing the Ni / W metal stack on the surface of the gate cap metal layer and the Ni layer and the Cr layer on the surface of the gate cap metal layer specifically comprises: etching to remove the Cr layer in the gate cap metal layer, and the Ni layer covering the Cr layer in the gate cap metal layer and the Ni / W metal stack covering the gate cap metal layer are separated from the Au layer of the gate cap metal layer and removed.

7. The method of claim 4, wherein: The thickness of the second W layer is greater than the thickness of the first W layer.

8. The method of claim 4, wherein the gate of the semiconductor radio frequency device is formed by: The method for removing the gate root metal layer distributed outside the first sidewall and the second sidewall of the gate cap metal layer and the third sidewall of the second support part specifically comprises: The method for removing the gate root metal layer distributed outside the first sidewall and the second sidewall of the gate cap metal layer and the third sidewall of the second support part specifically comprises:

9. The method of claim 1, wherein the gate of the semiconductor radio frequency device is formed by: The method specifically comprises: The method specifically comprises:

10. The method of claim 1, wherein: The method specifically comprises:

11. A semiconductor radio frequency device, characterized by: The material of the support layer comprises at least one of inorganic non-metallic material and organic material.

12. The semiconductor radio frequency device of claim 11, wherein, The gate of the semiconductor radio frequency device is obtained by the method for preparing the gate of the semiconductor radio frequency device according to any one of claims 1-10. The method specifically comprises: An epitaxial structure and a source, a drain and a gate matched with the epitaxial structure, the gate being arranged between the source and the drain, the source and the drain being electrically connected through a carrier channel in the epitaxial structure; The epitaxial structure further comprises a support layer arranged on the epitaxial structure, the support layer being arranged at least in a gate region, a drain region of the epitaxial structure being completely exposed, the gate comprising a gate root and a gate cap, the gate cap being arranged on the support layer, the gate cap having a second sidewall, the second support part having a third sidewall, the second sidewall and the third sidewall being located in the same vertical plane, and the gate root being continuously arranged on the second sidewall of the gate cap and the third sidewall of the second support part.

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