Method for manufacturing semiconductor power device
By using the sacrificial oxide layer removal process and the CMP process plus dry etching process in the manufacturing process of semiconductor power devices, the problem of cracks at the bottom of the gate conductive material layer is solved, and the stability and performance of the device are improved.
Patent Information
- Application Number
- CN202411904144.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-23
- Publication Date
- 2025-04-04
AI Technical Summary
During the manufacturing process, existing semiconductor power devices are prone to cracks at the bottom of the gate conductive material layer, resulting in a large reverse gate source and drain current, a large threshold voltage range, and serious channel leakage, which affects device stability.
In the process of manufacturing semiconductor power devices, the growth and removal process of the sacrificial oxide layer is used to eliminate the sharp corners of the dielectric layer at the bottom of the gate conductive material layer to form an arc structure, and the first process is performed using a CMP process plus a dry etching process after the gate conductive material layer is grown to improve the consistency of the gate conductive material layer.
By eliminating sharp angles and improving the consistency of the gate conductive material layer, the reverse gate source and drain current of the device is reduced, the uniformity of the threshold voltage and the uniformity of the gate resistance are improved, thereby enhancing the stability and performance of the device.
Smart Images
Figure CN119767718A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a method for manufacturing a semiconductor integrated circuit, and in particular to a method for manufacturing a semiconductor power device. Background Art
[0002] Split shielded gate (SGT) power field effect transistors have extremely low specific on-resistance and are therefore widely used in energy conversion systems. With the rise of AI, electronic devices have increasingly higher requirements for chip performance and power consumption, and the corresponding performance requirements for power MOS devices are also gradually increasing. Higher power density, lower on-resistance and faster switching speed are the ultimate goals of power MOS device researchers. Therefore, the size of a single cell of the device is developing in a smaller and smaller direction, and with it comes a linear increase in process manufacturing complexity. Copying the previous generation of process flow production can easily lead to device tape-out failures. The cracks at the bottom of the polysilicon gate (gate poly) lead to a large reverse gate-source leakage current (IGSSR), and the gate poly etching stability is poor, resulting in a large range of device threshold voltage (VTH). In addition, for low VTH positions, channel leakage is serious, causing the breakdown voltage to drop, and the device stability drops sharply.
[0003] like Figure 1 FIG. 1 is a schematic diagram of a cross-sectional structure of a half unit cell of an existing shielded gate MOSFET; taking an N-type device as an example, the existing shielded gate MOSFET includes:
[0004] An N-type doped drift region 2 is formed on the surface of a semiconductor substrate 1 .
[0005] A gate trench 101 is formed in a selected area of the drift region 2 .
[0006] A shielding dielectric layer 3 and a shielding gate conductive material layer 4 are formed in the bottom region of the gate trench 101 .
[0007] The material of the shielding dielectric layer 3 is usually silicon dioxide.
[0008] The material of the shielding gate conductive material layer 4 is usually polysilicon.
[0009] A gate conductive material layer bottom dielectric layer 102a is formed on the top surface of the shielding gate conductive material layer 4. The material of the gate conductive material layer bottom dielectric layer 102 includes silicon dioxide. In the existing method, the gate conductive material layer bottom dielectric layer 102a is formed by first filling the gate trench 101 on the top of the shielding gate conductive material layer 4 and then etching back. Figure 1It can be seen that the top surface of the dielectric layer 102a at the bottom of the gate conductive material layer has a flat surface caused by back etching and forms a sharp angle with the side of the gate trench 101, namely the dotted circle 103, and the angle is prone to crack defects.
[0010] A gate dielectric layer 5 is formed on the side of the gate structure 101. Usually, the material of the gate dielectric layer 5 includes silicon dioxide.
[0011] The gate trench 101 at the top of the shielding gate conductive material layer 4 is filled with a gate conductive material layer 6a. Generally, the material of the gate conductive material layer 6 is polysilicon. In the existing method, the steps of forming the gate conductive material layer 6a are: firstly, the gate conductive material layer is grown to completely fill the gate trench 101 at the top of the shielding gate conductive material layer 4 and extend to the surface outside the gate trench 101; then, the gate conductive material layer is etched by a dry etching process. Figure 1 As shown in the gate conductive material layer 6 a , it can be seen that the dry etching process causes the top surface 104 of the gate conductive material layer 6 a to have a curved structure, ie, poor uniformity.
[0012] A P-type doped well region 7 is formed in the surface region of the drift region 2 , and the gate conductive material layer 6 passes through the well region 7 .
[0013] The surface of the well region 7 covered by the side of the gate conductive material layer 6 is used to form a conductive channel. Since the top surface 104 of the gate conductive material layer 6a has poor position uniformity, the control ability of the gate conductive material layer 6a in different regions over the conductive channel will also be different, and the channel length will be different, which will make the uniformity of the threshold voltage of the device worse, causing the device VTH range to be large, and then increase the probability of channel leakage, affect BV, and affect the stability of the device. At the same time, the top surface 104 of the gate conductive material layer 6a has poor position uniformity, and the uniformity of the parasitic resistance brought by the gate conductive material layer 6a will also be poor.
[0014] An N-type heavily doped source region 8 is formed in the surface region of the well region 7 , and the source region 8 is self-aligned with the side surface of the corresponding gate trench 101 .
[0015] A contact hole 11 is formed on the top of the source region 8 through the interlayer film 9 and connected to the source electrode composed of the front metal layer 13. The contact hole 11 on the top of the source region 8 also passes through the source region 8 and forms a P-type heavily doped body contact region 10 at the bottom.
[0016] A drain region formed by thinning the N+ doped semiconductor substrate 1 is formed on the back side of the drift region 2 .
[0017] A back metal layer 12 is formed on the back side of the drain region and a drain electrode composed of the back metal layer 12 is formed. Summary of the invention
[0018] The technical problem to be solved by the present invention is to provide a method for manufacturing a semiconductor power device, which can reduce the IGSSR of the device and improve the consistency of the gate conductive material layer, thereby improving the consistency of the threshold voltage and gate resistance of the device.
[0019] In order to solve the above technical problems, the present invention provides a method for manufacturing a semiconductor power device, comprising the following steps:
[0020] A drift region doped with a first conductivity type is formed on the surface of the semiconductor substrate.
[0021] A gate trench is formed in a selected area of the drift region.
[0022] A dielectric layer is grown at the bottom of the gate conductive material layer to completely fill the gate trench.
[0023] The dielectric layer at the bottom of the gate conductive material layer is first etched back to lower the top surface of the dielectric layer at the bottom of the gate conductive material layer to a set position. The first etch back causes a sharp angle to be formed at the intersection of the top surface of the dielectric layer at the bottom of the gate conductive material layer and the side of the gate trench.
[0024] The sacrificial oxide layer is grown and removed to eliminate the sharp corners and form an arc structure at the intersection of the top surface of the dielectric layer at the bottom of the gate conductive material layer and the side of the gate trench.
[0025] A gate dielectric layer is formed on the side of the gate trench.
[0026] A gate conductive material layer is grown, wherein the gate conductive material layer completely fills the gate trench and extends to a surface outside the gate trench.
[0027] The gate conductive material layer is first treated by a CMP process plus a dry etching process to remove the gate conductive material layer outside the gate trench and lower the top surface of the gate conductive material layer in the gate trench area to a set value, and the effect of the CMP process on uniformly thinning the gate conductive material layer is utilized to reduce the influence of the etching deviation of the dry etching process on the consistency of the top surface position of the gate conductive material layer after the first treatment, so as to improve the consistency of the gate conductive material layer.
[0028] A further improvement is that before growing the dielectric layer at the bottom of the gate conductive material layer, the method further comprises:
[0029] A shielding dielectric layer and a shielding gate conductive material layer are formed in the bottom area of the gate trench.
[0030] A further improvement is that the steps of forming a shielding dielectric layer and a shielding gate conductive material layer in the bottom region of the gate trench include:
[0031] The shielding dielectric layer is grown to a desired thickness, and the shielding dielectric layer is located on the inner surface of the gate trench and extends to the surface outside the gate trench.
[0032] The shielding gate conductive material layer is grown to completely fill the gate trench and extend out of the gate trench.
[0033] The shielding gate conductive material layer outside the gate trench is removed and the top surface of the shielding gate conductive material layer in the gate trench area is lowered to a set value.
[0034] The shielding gate conductive material layer outside the gate trench is removed and the top surface of the shielding gate conductive material layer in the gate trench area is lowered to a set value.
[0035] A further improvement is that the shielding dielectric layer and the dielectric layer at the bottom of the gate conductive material layer are made of the same material.
[0036] After the bottom dielectric layer of the gate conductive material layer grows, the shielding dielectric layer remaining on the top surface of the shielding gate conductive material layer is merged into the bottom dielectric layer of the gate conductive material layer as a component of the bottom dielectric layer of the gate conductive material layer.
[0037] A further improvement is that the material of the dielectric layer at the bottom of the gate conductive material layer includes silicon dioxide.
[0038] A further improvement is that the material of the gate conductive material layer includes polysilicon; and the material of the gate dielectric layer includes silicon dioxide.
[0039] The gate dielectric layer is formed by a dry oxidation process.
[0040] A further improvement is that the material of the shielding gate conductive material layer includes polysilicon; and the material of the shielding dielectric layer includes silicon dioxide.
[0041] The shielding dielectric layer is formed by a dry oxidation process or a wet oxidation process.
[0042] A further improvement is that the growth process of the sacrificial oxide layer adopts a dry oxidation process.
[0043] A further improvement is that the method further comprises the following steps:
[0044] A well region doped with a second conductivity type is formed in a surface region of the drift region, and the gate conductive material layer passes through the well region.
[0045] A source region heavily doped with the first conductivity type is formed in the surface area of the well region, and the source region is self-aligned with the side surface of the corresponding gate trench.
[0046] An interlayer film, a contact hole and a front metal layer are formed, and the front metal layer is patterned to form a source electrode and a gate electrode.
[0047] The well region and the source region are both connected to the source electrode through a contact hole at the top of the source region.
[0048] The gate conductive material layer is connected to the gate through a corresponding contact hole on the top.
[0049] A further improvement is that the semiconductor power device is a power MOSFET, and also includes the following back side processes:
[0050] The semiconductor substrate is thinned, and then a drain region heavily doped with the first conductivity type is formed on the back side of the drift region; the semiconductor substrate is heavily doped with the first conductivity type, and the drain region is composed of the thinned semiconductor substrate; or, the drain region is composed of a back ion implantation region formed by back ion implantation of the thinned semiconductor substrate heavily doped with the second conductivity type.
[0051] A back metal layer is formed on the back side of the drain region and a drain electrode is formed of the back metal layer.
[0052] A further improvement is that the steps of forming the contact hole include:
[0053] A contact hole opening is formed by etching through the interlayer film.
[0054] The contact hole is formed by filling metal in the contact hole opening.
[0055] After the contact hole opening is formed and before the metal filling, the method further comprises:
[0056] Ions of the second conductive type heavy doping are implanted to form a body contact region at the bottom of the contact hole opening in a self-aligned manner, and the well region contacts the contact hole corresponding to the top through the body contact region.
[0057] A further improvement is that the material of the front metal layer includes aluminum.
[0058] The material of the back metal layer includes aluminum.
[0059] A further improvement is that the drift region is formed by epitaxial growth.
[0060] A further improvement is that the material of the semiconductor substrate includes silicon, silicon carbide and gallium nitride.
[0061] A further improvement is that the semiconductor power device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the semiconductor power device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.
[0062] The present invention makes a special arrangement for the process flow of manufacturing semiconductor power devices, mainly after the first back-etching of the dielectric layer at the bottom of the gate conductive material layer, a sacrificial oxide layer growth and removal process is performed to eliminate the sharp corner at the intersection of the top surface of the dielectric layer at the bottom of the gate conductive material layer and the side of the gate groove brought by the first back-etching and form an arc structure. After the gate conductive material layer is formed, the sharp corner at the bottom corner of the gate conductive material layer can be eliminated and the bottom corner of the gate conductive material layer can be made into an arc structure, so that the defect of cracks caused by the sharp corners can be eliminated and the increase of IGSSR caused by the cracks can be eliminated. Therefore, the present invention can reduce the IGSSR of the device and prevent the IGSSR from being too large.
[0063] In addition, the present invention also uses a CMP process plus a dry etching process to perform a first treatment on the gate conductive material layer after the gate conductive material layer grows. Compared with the existing method of using a dry etching process alone to lower the top surface of the gate conductive material layer in the gate groove, the present invention adds a CMP process before the dry etching process. Since the CMP process has better uniformity in thinning the gate conductive material layer, after the gate conductive material layer is thinned by the CMP process, the thickness of the gate conductive material layer processed by the dry etching process is reduced. Therefore, the etching thickness of the dry etching process will become smaller, and the etching deviation will also become smaller. In this way, the consistency of the top surface position of the gate conductive material layer after the first treatment will be better maintained, which meets the process requirements. Therefore, the present invention can improve the consistency of the gate conductive material layer.
[0064] Since the surface of the well region covered by the side of the gate conductive material layer is used to form a conductive channel, after the consistency of the gate conductive material layer is improved, the consistency of the gate conductive material layer's control over the conductive channel is also improved, and the consistency of the device's threshold voltage can be improved; after the consistency of the threshold voltage is improved, it can prevent the defects of low threshold voltage and increased channel leakage caused by the low threshold voltage, and prevent the defect of decreased breakdown voltage caused by this, thereby improving the stability of device performance.
[0065] Improving the consistency of the gate conductive material layer can also improve the consistency of the gate resistance, and can also have a certain optimization effect on the switching speed and oscillation consistency of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0066] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:
[0067] Figure 1It is a schematic diagram of the cross-sectional structure of half of the original cell of the existing shielded gate MOSFET;
[0068] Figure 2 is a flow chart of a method for manufacturing a semiconductor power device according to an embodiment of the present invention;
[0069] Figure 3A-3M is a schematic diagram of a device cross-sectional structure in each step of a method for manufacturing a semiconductor power device according to an embodiment of the present invention;
[0070] Figure 4A is a schematic diagram of a device cross-sectional structure corresponding to when step S106 is directly performed without performing step S105 in the method for manufacturing a semiconductor power device according to an embodiment of the present invention;
[0071] Figure 4B is a schematic diagram of a device cross-sectional structure corresponding to when the existing method is used to replace step S108 in the method for manufacturing a semiconductor power device according to an embodiment of the present invention;
[0072] Figure 5 It is an IGSSR box diagram of a shielded gate MOSFET formed by a method for manufacturing a semiconductor power device according to an embodiment of the present invention and an existing shielded gate MOSFET;
[0073] Figure 6 It is a threshold voltage box diagram of a shielded gate MOSFET formed by the method for manufacturing a semiconductor power device according to an embodiment of the present invention and a conventional shielded gate MOSFET. DETAILED DESCRIPTION
[0074] like Figure 2 FIG. 1 is a flow chart of a method for manufacturing a semiconductor power device according to an embodiment of the present invention; FIG. 3A to FIG. 3M , which is a schematic diagram of a device cross-sectional structure in each step of a method for manufacturing a semiconductor power device according to an embodiment of the present invention; the method for manufacturing a semiconductor power device according to an embodiment of the present invention comprises the following steps:
[0075] Step S101: Figure 3A As shown, a drift region 2 doped with a first conductivity type is formed on the surface of a semiconductor substrate 1 .
[0076] In the embodiment of the present invention, the drift region 2 is formed by epitaxial growth.
[0077] In the embodiment of the present invention, the material of the semiconductor substrate 1 is silicon. In other embodiments, the material of the semiconductor substrate 1 can also be silicon carbide or gallium nitride.
[0078] Step S102: Figure 3B As shown, a gate trench 101 is formed in a selected area of the drift region 2 .
[0079] In the embodiment of the present invention, before subsequently growing the dielectric layer 102 at the bottom of the gate conductive material layer, the method further includes:
[0080] like Figure 3D As shown, a shielding dielectric layer 3 and a shielding gate conductive material layer 4 are formed in the bottom area of the gate trench 101. In this way, the semiconductor power device is a shielded gate semiconductor power device. In other embodiments, the shielding dielectric layer 3 and the shielding gate conductive material layer 4 can also be omitted, and the semiconductor power device is a common trench gate semiconductor power device.
[0081] The steps of forming the shielding dielectric layer 3 and the shielding gate conductive material layer 4 in the bottom area of the gate trench 101 include:
[0082] like Figure 3C As shown, a shielding dielectric layer 3 having a required thickness is grown, and the shielding dielectric layer 3 is located on the inner surface of the gate trench 101 and extends to the surface outside the gate trench 101 .
[0083] In some embodiments, the material of the shielding dielectric layer 3 includes silicon dioxide. The shielding dielectric layer 3 is formed by a dry oxidation process or a wet oxidation process.
[0084] like Figure 3C As shown, the shielding gate conductive material layer 4 is grown to completely fill the gate trench 101 and extend outside the gate trench 101 .
[0085] In some embodiments, the material of the shield gate conductive material layer 4 includes polysilicon.
[0086] like Figure 3D As shown, the shielding gate conductive material layer 4 outside the gate trench 101 is removed and the top surface of the shielding gate conductive material layer 4 in the gate trench 101 region is lowered to a set value.
[0087] like Figure 3D As shown, the shielding gate conductive material layer 4 outside the gate trench 101 is removed and the top surface of the shielding gate conductive material layer 4 in the gate trench 101 region is lowered to a set value.
[0088] Step S103: Figure 3D As shown, a dielectric layer 102 a is grown at the bottom of the gate conductive material layer to completely fill the gate trench 101 .
[0089] In the embodiment of the present invention, the shielding dielectric layer 3 and the dielectric layer 102a at the bottom of the gate conductive material layer are made of the same material.
[0090] After the gate conductive material layer bottom dielectric layer 102a is grown, the shielding dielectric layer 3 remaining on the top surface of the shielding gate conductive material layer 4 is merged into the gate conductive material layer bottom dielectric layer 102a as a component of the gate conductive material layer bottom dielectric layer 102a.
[0091] In some embodiments, the material of the dielectric layer 102 at the bottom of the gate conductive material layer includes silicon dioxide.
[0092] Step S104: Figure 3D As shown, the first back-etching is performed on the bottom dielectric layer 102a of the gate conductive material layer to lower the top surface of the bottom dielectric layer 102a of the gate conductive material layer to a set position. The first back-etching makes the top surface of the bottom dielectric layer 102a of the gate conductive material layer and the side of the gate trench 101 have a sharp corner at the intersection. Figure 3D In the figure, after the first etching back is completed, the bottom dielectric layer of the gate conductive material layer with a sharp corner is marked with a mark 102a alone.
[0093] Step S105: Figure 3E As shown, the growth of the sacrificial oxide layer 201 is performed.
[0094] like Figure 3F As shown, the sacrificial oxide layer 201 is then removed. After removing the sacrificial oxide layer 201, the sharp corners can be eliminated and a circular arc structure can be formed at the intersection of the top surface of the dielectric layer 102 at the bottom of the gate conductive material layer and the side of the gate trench 101. Figure 3F In the figure, the bottom dielectric layer of the gate conductive material layer after the surface is rounded is marked with a mark 102 alone.
[0095] In the embodiment of the present invention, the growth process of the sacrificial oxide layer 201 adopts a dry oxidation process.
[0096] Step S106: Figure 3G As shown, a gate dielectric layer 5 is formed on the side of the gate trench 101 . Figure 3G In FIG. 5 , the top surface of the bottom dielectric layer 102 of the gate conductive material layer located at the bottom of the gate dielectric layer 5 is also marked with a dotted line.
[0097] In some embodiments, the material of the gate dielectric layer 5 includes silicon dioxide.
[0098] The gate dielectric layer 5 is formed by a dry oxidation process.
[0099] In the existing method, before forming the gate dielectric layer 5, a sacrificial oxide layer 201 is used to round the corners of the top surface of the dielectric layer 102a at the bottom of the gate conductive material layer. Figure 4A, is a schematic diagram of the device cross-sectional structure corresponding to when step S106 is performed directly without performing step S105 in the method for manufacturing a semiconductor power device according to an embodiment of the present invention; it can be seen that the corners indicated by the dotted circle 103 have sharp corners, which are prone to crack defects, and the crack defects formed therein are prone to increase the IGSSR.
[0100] Step S107: Figure 3H As shown, a gate conductive material layer 202 is grown, and the gate conductive material layer 202 completely fills the gate trench 101 and extends to the surface outside the gate trench 101 . Figure 3H In the figure, the gate conductive material layer 202 formed by growth is marked with a label 202 alone.
[0101] In some embodiments, the material of the gate conductive material layer 6 includes polysilicon.
[0102] Step S108: Fig. 3I As shown, the gate conductive material layer 6 is first treated by a CMP process plus a dry etching process to remove the gate conductive material layer 6 outside the gate groove 101 and to lower the top surface of the gate conductive material layer 6 in the gate groove 101 area to a set value, and the effect of the CMP process on uniformly thinning the gate conductive material layer 6 is used to reduce the influence of the etching deviation of the dry etching process on the consistency of the top surface position of the gate conductive material layer 6 after the first treatment, so as to improve the consistency of the gate conductive material layer 6.
[0103] That is, in the embodiment of the present invention, the first treatment is implemented using a CMP+dry etch process. In the existing method, the first treatment is completely implemented using a dry etching process. Since the dry etching process has a large etching deviation, when the dry etching process is used to implement the first treatment, the thickness of the gate conductive material layer 202 that needs to be etched by the dry etching process increases, and the etching deviation also increases. In the embodiment of the present invention, since a CMP process is added before the dry etching process, the CMP process can reduce and control the thickness of the gate conductive material layer 202 processed by the dry etching process, thereby reducing the etching deviation of the dry etching process and controlling the etching deviation well, thereby improving the consistency of the top surface position of the gate conductive material layer 6. Figure 4BAs shown, it is a schematic diagram of the device cross-sectional structure corresponding to when the existing method is used to replace step S108 in the manufacturing method of the semiconductor power device of the embodiment of the present invention; the existing method completely adopts the dry etching process to implement the first treatment, and the gate conductive material layer is represented by the mark 6a alone. It can be seen that the top surface flatness of the gate conductive material layer 6a is not good, that is, the etching is very easy to produce deviations, resulting in poor consistency of the top surface position of the gate conductive material layer 6, which leads to different lengths of subsequent channels, resulting in a large VTH range of the device, and then leading to an increase in the probability of channel leakage, affecting BV and affecting device stability.
[0104] In the embodiment of the present invention, the following steps are also included:
[0105] like Figure 3J As shown, a well region 7 doped with the second conductivity type is formed in the surface region of the drift region 2 , and a gate conductive material layer 6 passes through the well region 7 .
[0106] like Figure 3J As shown, a source region 8 heavily doped with the first conductivity type is formed in the surface region of the well region 7 , and the source region 8 and the side surface of the corresponding gate trench 101 are self-aligned.
[0107] like Figure 3K As shown, an interlayer film 9 is formed. In some embodiments, the interlayer film 9 is formed by depositing silicon dioxide.
[0108] The contact hole 11 is formed. The steps of forming the contact hole 11 include:
[0109] like Figure 3L As shown, a contact hole opening is formed through the interlayer film 9 by etching.
[0110] The contact hole opening is filled with metal to form a contact hole 11 .
[0111] After the contact hole opening is formed and before the metal filling, it also includes:
[0112] Ion implantation of heavily doped second conductivity type is performed to form a body contact region 10 at the bottom of the contact hole opening in a self-aligned manner, and the well region 7 is in contact with the corresponding contact hole 11 at the top through the body contact region 10 .
[0113] like Figure 3M As shown, a front metal layer 13 is formed, and the front metal layer 13 is patterned to form a source and a gate. In some embodiments, the filling metal of the contact hole 11 is composed of the front metal layer 13.
[0114] Both the well region 7 and the source region 8 are connected to the source electrode through a contact hole 11 at the top of the source region 8 .
[0115] The gate conductive material layer 6 is connected to the gate through a corresponding contact hole 11 at the top.
[0116] In the embodiment of the present invention, the semiconductor power device is a power MOSFET, and further includes the following back side processes:
[0117] The semiconductor substrate 1 is thinned, and then a drain region heavily doped with the first conductivity type is formed on the back side of the drift region 2. The semiconductor substrate 1 is heavily doped with the first conductivity type, and the drain region is composed of the thinned semiconductor substrate 1. In other embodiments, the drain region is composed of a back ion implantation region formed by performing back ion implantation of heavily doped with the second conductivity type on the thinned semiconductor substrate 1.
[0118] like Figure 3M As shown, a back metal layer 12 is formed on the back side of the drain region and a drain electrode composed of the back metal layer 12 is formed.
[0119] The material of the front metal layer 13 includes aluminum.
[0120] The material of the back metal layer 12 includes aluminum.
[0121] In the embodiment of the present invention, the semiconductor power device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the semiconductor power device can also be a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.
[0122] The embodiment of the present invention makes special arrangements for the process flow of manufacturing semiconductor power devices, mainly performing a growth and removal process of the sacrificial oxide layer 201 after the first back-etching of the dielectric layer 102 at the bottom of the gate conductive material layer, so as to eliminate the sharp corner at the intersection of the top surface of the dielectric layer 102 at the bottom of the gate conductive material layer and the side of the gate trench 101 brought by the first back-etching and form an arc structure. After the gate conductive material layer 6 is formed, the sharp corner at the bottom corner of the gate conductive material layer 6 can be eliminated and the bottom corner of the gate conductive material layer 6 can be made into an arc structure, so that the defect of cracks caused by sharp corners can be eliminated and the increase of IGSSR caused by cracks can be eliminated. Therefore, the embodiment of the present invention can reduce the IGSSR of the device and prevent the IGSSR from being too large.
[0123] In addition, the embodiment of the present invention also uses a CMP process plus a dry etching process to perform a first treatment on the gate conductive material layer 6 after the gate conductive material layer 6 grows. Compared with the existing method of using a dry etching process alone to lower the top surface of the gate conductive material layer 6 in the gate groove 101, the embodiment of the present invention adds a CMP process before the dry etching process. Since the CMP process has better uniformity in thinning the gate conductive material layer 6, after the gate conductive material layer 6 is thinned by the CMP process, the thickness of the gate conductive material layer 6 treated by the dry etching process is reduced. Therefore, the etching thickness of the dry etching process will become smaller, and the etching deviation will also become smaller. In this way, the consistency of the top surface position of the gate conductive material layer 6 after the first treatment will be better maintained, which meets the process requirements. Therefore, the embodiment of the present invention can improve the consistency of the gate conductive material layer 6.
[0124] Since the surface of the well region 7 covered by the side of the gate conductive material layer 6 is used to form a conductive channel, after the consistency of the gate conductive material layer 6 is improved, the consistency of the gate conductive material layer 6's control over the conductive channel is also improved, and the consistency of the threshold voltage of the device can be improved; after the consistency of the threshold voltage is improved, the defects of low threshold voltage and increased channel leakage caused by the low threshold voltage can be prevented, as well as the defect of decreased breakdown voltage caused by this can be prevented, thereby improving the stability of device performance.
[0125] Improving the consistency of the gate conductive material layer 6 can also improve the consistency of the gate resistance, and can also optimize the switching speed and oscillation consistency of the device to a certain extent.
[0126] like Figure 5 , which is an IGSSR box diagram of a shielded gate MOSFET formed by a method for manufacturing a semiconductor power device according to an embodiment of the present invention and a conventional shielded gate MOSFET; Figure 5 In the figure, the ordinate is IGSSR, and the abscissa includes two sets of data, the data in the dashed box 301 is the data of the existing shielded gate MOSFET, i.e., the traditional structure, and the data in the dashed box 302 is the data of the shielded gate MOSFET, i.e., the new structure, formed by the manufacturing method of the semiconductor power device according to the embodiment of the present invention. It can be seen that the IGSSR of the new structure is significantly lower than that of the traditional structure.
[0127] like Figure 6 , which is an IGSSR box diagram of a shielded gate MOSFET formed by a method for manufacturing a semiconductor power device according to an embodiment of the present invention and a conventional shielded gate MOSFET; Figure 5In the figure, the vertical axis is the threshold voltage, i.e., VTH, and the horizontal axis includes two sets of data. The data in the dashed box 303 is the data of the existing shielded gate MOSFET, i.e., the traditional structure, and the data in the dashed box 304 is the data of the shielded gate MOSFET, i.e., the new structure, formed by the manufacturing method of the semiconductor power device according to the embodiment of the present invention. It can be seen that the VTH range of the new structure is significantly better than that of the traditional structure.
[0128] In the embodiment of the present invention, a sacrificial oxidation (SAC) process is added before the growth of the gate oxide, i.e., the gate dielectric layer 5, so that the bottom corner of the gate poly is smoother, the crack at the bottom of the gate poly is effectively solved, and the IGSSR of the device is effectively improved. In addition, the method of chemical mechanical polishing (CMP) plus dry etching (dry etch) is used to replace the existing traditional one-step dry etching method to generate gate poly, so that the overall size consistency of the gate poly is more uniform, and the channel at the bottom of the source region formed after the subsequent source injection is better, and the VTH consistency is better. At the same time, a more uniform gate poly can obtain a more consistent gate resistance (Rg), which also has a certain optimization effect on the switching speed and oscillation consistency of the device.
[0129] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.
Claims
1. A method for manufacturing a semiconductor power device, characterized in that: The steps include: forming a drift region doped with a first conductivity type on a surface of a semiconductor substrate; forming a gate trench in a selected area of the drift region; Growing a dielectric layer at the bottom of the gate conductive material layer to completely fill the gate trench; Performing a first back-etching on the dielectric layer at the bottom of the gate conductive material layer so that the top surface of the dielectric layer at the bottom of the gate conductive material layer is lowered to a set position, wherein the first back-etching causes a sharp angle to be formed at the intersection of the top surface of the dielectric layer at the bottom of the gate conductive material layer and the side of the gate trench; Performing a sacrificial oxide layer growth and removal process to eliminate the sharp corners and form an arc structure at the intersection of the top surface of the dielectric layer at the bottom of the gate conductive material layer and the side of the gate trench; forming a gate dielectric layer on a side of the gate trench; growing a gate conductive material layer, wherein the gate conductive material layer completely fills the gate trench and extends to a surface outside the gate trench; The gate conductive material layer is first treated by a CMP process plus a dry etching process to remove the gate conductive material layer outside the gate trench and lower the top surface of the gate conductive material layer in the gate trench area to a set value, and the effect of the CMP process on uniformly thinning the gate conductive material layer is utilized to reduce the influence of the etching deviation of the dry etching process on the consistency of the top surface position of the gate conductive material layer after the first treatment, so as to improve the consistency of the gate conductive material layer.
2. The method for manufacturing a semiconductor power device according to claim 1, wherein: Before growing the dielectric layer at the bottom of the gate conductive material layer, the method further comprises: A shielding dielectric layer and a shielding gate conductive material layer are formed in the bottom area of the gate trench.
3. The method for manufacturing a semiconductor power device according to claim 2, wherein: The steps of forming a shielding dielectric layer and a shielding gate conductive material layer in the bottom area of the gate trench include: Growing the shielding dielectric layer of required thickness, wherein the shielding dielectric layer is located on the inner surface of the gate trench and extends to the surface outside the gate trench; Growing the shielding gate conductive material layer to completely fill the gate trench and extend it outside the gate trench; Removing the shielding gate conductive material layer outside the gate trench and lowering the top surface of the shielding gate conductive material layer in the gate trench area to a set value; The shielding gate conductive material layer outside the gate trench is removed and the top surface of the shielding gate conductive material layer in the gate trench area is lowered to a set value.
4. The method for manufacturing a semiconductor power device according to claim 3, wherein: The shielding dielectric layer and the dielectric layer at the bottom of the gate conductive material layer are made of the same material; After the bottom dielectric layer of the gate conductive material layer grows, the shielding dielectric layer remaining on the top surface of the shielding gate conductive material layer is merged into the bottom dielectric layer of the gate conductive material layer as a component of the bottom dielectric layer of the gate conductive material layer.
5. The method for manufacturing a semiconductor power device according to claim 1, wherein: The material of the dielectric layer at the bottom of the gate conductive material layer includes silicon dioxide.
6. The method for manufacturing a semiconductor power device according to claim 1, wherein: The material of the gate conductive material layer includes polysilicon; the material of the gate dielectric layer includes silicon dioxide; The gate dielectric layer is formed by a dry oxidation process.
7. The method for manufacturing a semiconductor power device according to claim 2, wherein: The material of the shielding grid conductive material layer includes polysilicon; the material of the shielding dielectric layer includes silicon dioxide; The shielding dielectric layer is formed by a dry oxidation process or a wet oxidation process.
8. The method for manufacturing a semiconductor power device according to claim 1, wherein: The growth process of the sacrificial oxide layer adopts a dry oxidation process.
9. The method for manufacturing a semiconductor power device according to claim 1, wherein: The following steps are also included: forming a well region doped with a second conductivity type in a surface region of the drift region, wherein the gate conductive material layer passes through the well region; forming a heavily doped source region of the first conductivity type in a surface region of the well region, wherein the source region is self-aligned with a side surface of the corresponding gate trench; forming an interlayer film, a contact hole and a front metal layer, and patterning the front metal layer to form a source electrode and a gate electrode; The well region and the source region are both connected to the source electrode through a contact hole at the top of the source region; The gate conductive material layer is connected to the gate through a corresponding contact hole on the top.
10. The method for manufacturing a semiconductor power device according to claim 9, wherein: The semiconductor power device is a power MOSFET, which also includes the following back-side processes: The semiconductor substrate is thinned, and then a drain region heavily doped with a first conductivity type is formed on the back side of the drift region; the semiconductor substrate is heavily doped with the first conductivity type, and the drain region is composed of the thinned semiconductor substrate; or, the drain region is composed of a back ion implantation region formed by back ion implantation of the thinned semiconductor substrate heavily doped with a second conductivity type; A back metal layer is formed on the back side of the drain region and a drain electrode is formed of the back metal layer.
11. The method for manufacturing a semiconductor power device according to claim 9, wherein: The steps of forming the contact hole include: Etching to form a contact hole opening through the interlayer film; Filling metal in the contact hole opening to form the contact hole; After the contact hole opening is formed and before the metal filling, the method further comprises: Ions of the second conductive type heavy doping are implanted to form a body contact region at the bottom of the contact hole opening in a self-aligned manner, and the well region contacts the contact hole corresponding to the top through the body contact region.
12. The method for manufacturing a semiconductor power device according to claim 10, wherein: The material of the front metal layer includes aluminum; The material of the back metal layer includes aluminum.
13. The method for manufacturing a semiconductor power device according to claim 1, wherein: The drift region is formed by epitaxial growth.
14. The method for manufacturing a semiconductor power device according to claim 1, wherein: The material of the semiconductor substrate includes silicon, silicon carbide and gallium nitride.
15. The method for manufacturing a semiconductor power device according to any one of claims 1 to 14, characterized in that: The semiconductor power device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the semiconductor power device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.