A method for fabricating a field-effect transistor

Abstract

This invention provides a method for fabricating a field-effect transistor (FET), relating to the field of semiconductor electronic device technology. The invention uses an epitaxially grown SrTiO3 thin film as the gate dielectric layer, which has the advantage of low roughness. Furthermore, PPC is used as a support layer to achieve the transfer of the SrTiO3 thin film, which greatly reduces the introduction of residues during the fabrication process, resulting in a clean and smooth SrTiO3 film surface. After depositing a two-dimensional layered semiconductor material as the channel material, the interface between the SrTiO3 thin film and the two-dimensional material is effectively optimized, forming a quasi-van der Waals contact. This yields a high-quality gate dielectric and channel material interface, significantly improving device performance. Example results show that the FET fabricated by this invention exhibits a 10-1 8 High on / off ratio, ultra-low subthreshold swing of 69.2mV / dec, and up to 230cm 2 The mobility of a field-effect transistor is 1 / (V·s).

Description

Technical Field

[0001] This invention relates to the field of semiconductor electronic device technology, and in particular to a method for fabricating a field-effect transistor. Background Technology

[0002] Field-effect transistors (FETs) are the cornerstone of modern electronics, driving technological advancements in various electronic devices. However, with the semiconductor industry's relentless pursuit of device miniaturization, traditional silicon-based FETs have encountered significant challenges, such as short-channel effects, increased power consumption, and heat dissipation. Two-dimensional (2D) semiconductors with layered structures and atomic thicknesses can effectively address the challenges of device miniaturization when used as channel materials for FETs. However, the overall performance of FETs depends not only on the quality of the 2D material but also on the characteristics of the gate dielectric layer.

[0003] Because two-dimensional (2D) materials lack dangling bonds, directly growing gate dielectric layers (such as SrTiO3) on 2D materials is extremely difficult. The interface quality between the 2D material and the gate dielectric has a significant impact on the overall performance of the device. To optimize the interface quality, researchers have made various attempts, such as surface modification of the 2D material, introduction of seed layers, and layer-by-layer oxidation of the 2D material to fabricate devices. However, these methods all have certain drawbacks. For example, surface modification of 2D materials may introduce defects or damage the material surface; only a very small number of 2D materials can be oxidized to form oxides suitable for use as gate dielectric layers. How to further optimize the interface quality between the 2D material and the gate dielectric to improve the overall performance of field-effect transistor devices remains a technical challenge that needs to be solved. Summary of the Invention

[0004] In view of this, the purpose of this invention is to provide a method for fabricating field-effect transistors. This invention achieves effective optimization of the interface between the SrTiO3 gate dielectric layer and the two-dimensional material, resulting in the fabrication of high-performance field-effect transistors.

[0005] To achieve the above-mentioned objectives, the present invention provides the following technical solution:

[0006] This invention provides a method for fabricating a field-effect transistor, comprising the following steps:

[0007] A Sr4Al2O7 sacrificial layer and a SrTiO3 thin film layer are epitaxially grown sequentially on the surface of a single-crystal SrTiO3 substrate. A polypropylene carbonate support layer is then spin-coated onto the surface of the SrTiO3 thin film layer to obtain a SrTiO3 substrate / Sr4Al2O7 / SrTiO3 / PPC composite layer structure.

[0008] The SrTiO3 substrate / Sr4Al2O7 / SrTiO3 / PPC composite layer structure was immersed in water to dissolve the Sr4Al2O7 sacrificial layer, thus obtaining the SrTiO3 / PPC composite layer structure.

[0009] The SrTiO3 / PPC composite layer structure is transferred to an insulating substrate with a gate metal electrode, so that the SrTiO3 thin film layer in the SrTiO3 / PPC composite layer structure covers the gate metal electrode. Then, the polypropylene carbonate support layer is etched to obtain the insulating substrate / gate metal electrode / SrTiO3 composite structure.

[0010] A two-dimensional layered semiconductor material layer is deposited on the surface of the SrTiO3 thin film layer of the insulating substrate / gate metal electrode / SrTiO3 composite structure, and a source metal electrode and a drain metal electrode are deposited on the surface of the two-dimensional layered semiconductor material layer to obtain the field-effect transistor.

[0011] Preferably, the thickness of the Sr4Al2O7 sacrificial layer is 8–15 nm, and the thickness of the SrTiO3 thin film layer is 20–28 nm.

[0012] Preferably, the gate metal electrode comprises a stacked titanium electrode and a gold electrode, wherein the thickness of the titanium electrode is 5-8 nm and the thickness of the gold electrode is 15-20 nm, and the titanium electrode is in contact with an insulating substrate.

[0013] Preferably, the insulating substrate is a silicon substrate with a surface covered with silicon dioxide, and the thickness of the silicon dioxide is 285 nm.

[0014] Preferably, the etching reagent used in the etching is an organic solvent.

[0015] Preferably, the two-dimensional layered semiconductor material in the two-dimensional layered semiconductor material layer is a transition metal chalcogenide.

[0016] Preferably, the transition metal chalcogenide includes MoS2.

[0017] Preferably, the thickness of the two-dimensional layered semiconductor material layer is 1.4 to 3.5 nm.

[0018] Preferably, the source metal electrode and the drain metal electrode each comprise a stacked chromium electrode and a gold electrode, the thickness of the chromium electrode being 15–20 nm and the thickness of the gold electrode being 45–55 nm, and the chromium electrode being in contact with a two-dimensional layered semiconductor material layer.

[0019] Preferably, the channel width between the source metal electrode and the drain metal is 4–6 μm.

[0020] This invention provides a method for fabricating a field-effect transistor. The method uses an epitaxially grown SrTiO3 thin film as the gate dielectric layer, which has the advantage of low roughness. Furthermore, it utilizes polypropylene carbonate (PPC) as a support layer to achieve the transfer of the SrTiO3 thin film, which greatly reduces the introduction of residues during the fabrication process. This results in a clean and smooth surface of the self-supporting SrTiO3 thin film. After depositing a two-dimensional layered semiconductor material as the channel material, the interface between the SrTiO3 thin film and the two-dimensional material is effectively optimized. The SrTiO3 thin film and the two-dimensional material form a quasi-van der Waals contact, resulting in a high-quality gate dielectric and channel material interface, significantly improving device performance.

[0021] The results of the examples show that the present invention successfully fabricated a high-performance field-effect transistor, wherein the surface roughness of the self-supporting SrTiO3 film reached 269.27 pm, and the field-effect transistor had a surface roughness of 10 ppm. 8 High on / off ratio, ultra-low subthreshold swing of 69.2mV / dec, and up to 230cm 2 The mobility of a field-effect transistor is 1 / (V·s). Attached Figure Description

[0022] Figure 1 This is a schematic diagram illustrating the peeling and transfer of the self-supporting SrTiO3 film in this invention. Figure 1 (a) is a schematic diagram of the film structure before peeling, (b) is a schematic diagram of the film peeling, and (c) is a schematic diagram of the film structure after it has been transferred to the target substrate.

[0023] Figure 2 This is a schematic diagram of the field-effect transistor structure of the present invention;

[0024] Figures 1-2 In the diagram, 1-PPC support layer, 2-SrTiO3 thin film layer, 3-Sr4Al2O7 sacrificial layer, 4-single crystal SrTiO3 substrate, 5-gate metal electrode, 6-target substrate (insulating substrate), 7-source metal electrode, 8-drain metal electrode, 9-two-dimensional layered semiconductor material layer;

[0025] Figure 3 These are morphology images of the SrTiO3 film surface in Example 1 and the comparative example, characterized using atomic force microscopy. Figure 3 (a) corresponds to the proportions, and (b) corresponds to Example 1;

[0026] Figure 4 The transfer characteristic curves of the field-effect transistors prepared in Example 1 and the comparative example are shown. Figure 4 (a) corresponds to the proportion, and (b) corresponds to Example 1. Detailed Implementation

[0027] This invention provides a method for fabricating a field-effect transistor, comprising the following steps:

[0028] A Sr4Al2O7 sacrificial layer and a SrTiO3 thin film layer are epitaxially grown sequentially on the surface of a single-crystal SrTiO3 substrate. A polypropylene carbonate support layer is then spin-coated onto the surface of the SrTiO3 thin film layer to obtain a SrTiO3 substrate / Sr4Al2O7 / SrTiO3 / PPC composite layer structure.

[0029] The SrTiO3 substrate / Sr4Al2O7 / SrTiO3 / PPC composite layer structure was immersed in water to dissolve the Sr4Al2O7 sacrificial layer, thus obtaining the SrTiO3 / PPC composite layer structure.

[0030] The SrTiO3 / PPC composite layer structure is transferred to an insulating substrate with a gate metal electrode, so that the SrTiO3 thin film layer in the SrTiO3 / PPC composite layer structure covers the gate metal electrode. Then, the polypropylene carbonate support layer is etched to obtain the insulating substrate / gate metal electrode / SrTiO3 composite structure.

[0031] A two-dimensional layered semiconductor material layer is deposited on the surface of the SrTiO3 thin film layer of the insulating substrate / gate metal electrode / SrTiO3 composite structure, and a source metal electrode and a drain metal electrode are deposited on the surface of the two-dimensional layered semiconductor material layer to obtain the field-effect transistor.

[0032] In this invention, unless otherwise specified, all raw materials / components used in the preparation are commercially available products well known to those skilled in the art.

[0033] In this invention, a Sr4Al2O7 sacrificial layer and a SrTiO3 thin film layer are epitaxially grown sequentially on the surface of a single-crystal SrTiO3 substrate, and a polypropylene carbonate support layer is spin-coated on the surface of the SrTiO3 thin film layer to obtain a SrTiO3 substrate / Sr4Al2O7 / SrTiO3 / PPC composite layer structure.

[0034] In this invention, the single-crystal SrTiO3 substrate is preferably (001) oriented. A (001) oriented single-crystal SrTiO3 substrate is beneficial for epitaxial growth and ensures the quality of the SrTiO3 film growth. In this invention, the thickness of the Sr4Al2O7 sacrificial layer is preferably 8–15 nm, and can be 8, 10, or 15 nm; the thickness of the SrTiO3 film layer is preferably 20–28 nm, and can be 20, 21, 22, 23, 24, 25, 26, 27, or 28 nm. This invention controls the thickness of the SrTiO3 film layer within the above range based on a comprehensive consideration of film peeling integrity and film performance. SrTiO3 has high-k properties and can be used as an insulating layer. In this invention, the Sr4Al2O7 sacrificial layer is a water-soluble sacrificial layer grown epitaxially. The lattice constant of Sr4Al2O7 is adjustable within a certain range and has a certain degree of "flexibility". Therefore, it can better grow SrTiO3 material and reduce the stress introduced by lattice mismatch during the growth process. This allows the high-quality SrTiO3 film grown epitaxially to be completely peeled off from the substrate required for growth, making it compatible with the fabrication process of two-dimensional material electronic devices. The epitaxially grown crystalline oxide Sr4Al2O7 has the advantage of low roughness.

[0035] In this invention, the method for epitaxially growing the Sr4Al2O7 sacrificial layer and the SrTiO3 thin film layer is preferably pulsed laser deposition. This invention does not have any special requirements for the process parameters of the pulsed laser deposition method. Process parameters well known in the art can be used to obtain the Sr4Al2O7 sacrificial layer and the SrTiO3 thin film layer that meet the thickness requirements.

[0036] This invention does not have specific requirements regarding the thickness of the polypropylene carbonate (PPC) support layer. Specifically, the polypropylene carbonate is dissolved in a solvent, then spin-coated onto the surface of an SrTiO3 thin film, and dried to obtain the polypropylene carbonate support layer. This invention does not have specific requirements for the polypropylene carbonate used; commercially available products well-known in the art can be used. Using polypropylene carbonate as the support layer in this invention results in low adsorption of SrTiO3 material, significantly reducing the impact of support layer residues and achieving a surface roughness of less than 1 nm for the SrTiO3 thin film. Utilizing PPC as the support layer material in this invention effectively improves the contact interface between the SrTiO3 thin film and the two-dimensional material, achieving quasi-van der Waals contact and significantly improving device performance.

[0037] In this invention, the SrTiO3 substrate / Sr4Al2O7 / SrTiO3 / PPC composite layer structure is as follows: Figure 1 As shown in (a), from top to bottom are PPC support layer, SrTiO3 thin film layer, Sr4Al2O7 sacrificial layer, and single crystal SrTiO3 substrate.

[0038] After obtaining the SrTiO3 substrate / Sr4Al2O7 / SrTiO3 / PPC composite layer structure, the present invention immerses the SrTiO3 substrate / Sr4Al2O7 / SrTiO3 / PPC composite layer structure in water to dissolve the Sr4Al2O7 sacrificial layer, thereby obtaining the SrTiO3 / PPC composite layer structure.

[0039] In this invention, the water is preferably ultrapure water. Through water dissolution, the Sr4Al2O7 sacrificial layer is completely etched, and the SrTiO3 thin film layer separates from the SrTiO3 substrate, resulting in an SrTiO3 thin film with a PPC support layer, i.e., the SrTiO3 / PPC composite layer structure. Figure 1 As shown in (b).

[0040] After obtaining the SrTiO3 / PPC composite layer structure, the present invention transfers the SrTiO3 / PPC composite layer structure onto an insulating substrate with a gate metal electrode, so that the SrTiO3 thin film layer in the SrTiO3 / PPC composite layer structure covers the gate metal electrode, and then the polypropylene carbonate support layer is etched to obtain the insulating substrate / gate metal electrode / SrTiO3 composite structure.

[0041] In this invention, the insulating substrate is preferably a silicon substrate with a surface covered with silicon dioxide, and the thickness of the silicon dioxide is preferably 285 nm. In this invention, the gate metal electrode (i.e., the metal bottom electrode) preferably comprises stacked titanium and gold electrodes, the thickness of the titanium electrode is preferably 5-8 nm, and the thickness of the gold electrode is preferably 15-20 nm. The titanium electrode is in contact with the insulating substrate, specifically with the silicon dioxide surface of the insulating substrate. In this invention, the preferred method for preparing the insulating substrate with the gate metal electrode is: exposing the electrode pattern using ultraviolet photolithography; preparing the titanium and gold electrodes on the silicon dioxide surface of the insulating substrate using a dual-ion-beam evaporation process; and peeling off the excess metal film to obtain the gate metal electrode. This invention does not have special requirements for the process parameters of the dual-ion-beam evaporation process; process parameters well known in the art can be used to obtain titanium and gold electrodes that meet the thickness requirements.

[0042] In this invention, the preferred method for transfer is as follows: the SrTiO3 / PPC composite layer structure is floated on water, and the SrTiO3 / PPC composite layer structure is retrieved using an insulating substrate with a gate metal electrode. The SrTiO3 / PPC composite layer structure is tightly bonded to the insulating substrate with the gate metal electrode, and the SrTiO3 thin film layer covers the gate metal electrode. In this invention, the structure after transfer is as follows: Figure 1 As shown in (c).

[0043] In this invention, the etching reagent used is preferably an organic solvent, and the organic solvent is preferably acetone. Preferably, the sample obtained after the transfer is completely dried before etching. Through etching, the polypropylene carbonate support layer is removed.

[0044] After obtaining the insulating substrate / gate metal electrode / SrTiO3 composite structure, the present invention deposits a two-dimensional layered semiconductor material layer on the surface of the SrTiO3 thin film layer of the insulating substrate / gate metal electrode / SrTiO3 composite structure, and deposits a source metal electrode and a drain metal electrode on the surface of the two-dimensional layered semiconductor material layer to obtain the field-effect transistor.

[0045] In this invention, the two-dimensional layered semiconductor material in the two-dimensional layered semiconductor material layer is preferably a transition metal chalcogenide, and the transition metal chalcogenide preferably includes MoS2; the thickness of the two-dimensional layered semiconductor material layer is preferably 1.4 to 3.5 nm, and can be 1.4, 2.1, 2.8, or 3.5 nm. In this invention, the two-dimensional layered semiconductor material serves as the channel material of the field-effect transistor, and the epitaxially grown self-supporting SrTiO3 thin film serves as the gate dielectric layer.

[0046] This invention preferably employs a mechanical exfoliation and point-to-point transfer method to transfer two-dimensional layered semiconductor materials onto the surface of a SrTiO3 thin film. Specifically, the preferred operation involves mechanically exfoliating the two-dimensional layered semiconductor material using adhesive tape to form two-dimensional layered semiconductor nanosheets, and then transferring the two-dimensional layered semiconductor nanosheets onto the surface of the SrTiO3 thin film. This invention does not impose any particular requirements on the transfer method; any transfer method well-known to those skilled in the art can be used.

[0047] In this invention, the source metal electrode and the drain metal electrode preferably comprise stacked chromium electrodes and gold electrodes, respectively. The thickness of the chromium electrode is preferably 15-20 nm, and the thickness of the gold electrode is preferably 45-55 nm. The chromium electrode is in contact with a two-dimensional layered semiconductor material layer. The source metal electrode and the drain metal electrode may also be respectively bonded to an SrTiO3 thin film layer. In this invention, the channel width between the source metal electrode and the drain metal electrode is preferably 4-6 μm, and can be 4, 5, or 6 μm.

[0048] In this invention, the preferred deposition method for the source metal electrode and the drain metal electrode is as follows: the source metal electrode and the drain metal electrode are patterned using electron beam lithography; a chromium electrode and a gold electrode are prepared using thermal evaporation technology; and excess metal film is removed using a stripping method to obtain the source metal electrode and the drain metal electrode, respectively.

[0049] In this invention, the structure of the field-effect transistor is as follows: Figure 2As shown, the field-effect transistor consists of, from bottom to top, an insulating substrate, a gate metal electrode, a self-supporting SrTiO3 thin film, a two-dimensional layered semiconductor material layer, and source and drain metal electrodes (i.e., source metal electrode and drain metal electrode).

[0050] This invention uses the crystalline oxide SrTiO3 as the gate dielectric layer material for field-effect transistors and a two-dimensional layered semiconductor material as the channel material. Crystalline oxides require growth on specific substrates, and strong covalent bonds form between the film and the substrate, preventing the film from detaching from the substrate. Therefore, large-area crystalline oxides are difficult to integrate into existing two-dimensional material device fabrication processes. This invention achieves the transfer of large-area, high-quality oxide films by growing a sacrificial layer, freeing them from substrate constraints and preventing crack formation during the peeling process. Furthermore, the self-supporting oxide films obtained in this way also possess good flexibility and can be used to fabricate flexible devices. This invention utilizes PPC material as a support layer, greatly reducing the introduction of residues during fabrication, resulting in a clean and smooth surface of the self-supporting SrTiO3 film and a high-quality gate dielectric and channel material interface. This invention combines the advantages of high-k materials, two-dimensional materials, and epitaxial growth, and uses PPC material as a support layer. The resulting epitaxial material, namely crystal oxide (SrTiO3), has the advantage of low roughness and can form quasi-van der Waals contacts with the two-dimensional material, resulting in a high-quality interface and significantly improving device performance. This provides a new design idea for electronic devices using crystal oxide as the gate dielectric.

[0051] To further illustrate the present invention, the fabrication method of the field-effect transistor provided by the present invention will be described in detail below with reference to examples, but these should not be construed as limiting the scope of protection of the present invention.

[0052] Example 1

[0053] The fabrication steps of a field-effect transistor are as follows:

[0054] (1) Material growth

[0055] A Sr4Al2O7 sacrificial layer (10 nm thick) and a SrTiO3 thin film layer (23 nm thick) were grown on a single-crystal SrTiO3 substrate ((001) orientation) using a pulsed laser deposition system.

[0056] (2) Substrate selection

[0057] A silicon substrate with 285nm silicon dioxide on its surface was selected as the target substrate.

[0058] (3) Fabrication of gate metal electrode

[0059] The electrode pattern was exposed using ultraviolet lithography; a 5nm titanium electrode and a 15nm gold electrode were prepared on the silicon dioxide surface of the substrate by dual ion beam evaporation; and the excess metal film was removed by a lift-off method (leaving only the ultraviolet lithographic pattern) to obtain the gate metal electrode.

[0060] (4) Transfer dielectric layer material

[0061] A PPC (polypropylene carbonate) support layer (structure as shown) was spin-coated onto a sample with a grown Sr4Al2O7 sacrificial layer and SrTiO3 thin film. Figure 1 (as shown in (a)); Immerse the sample in water to completely dissolve the sacrificial layer (as shown in (a)). Figure 1 (as shown in Figure (b)); the SrTiO3 film with the PPC support layer floats on the water surface, and the SrTiO3 film with the PPC support layer is retrieved using a target substrate with a gate metal electrode (as shown in Figure (b)). Figure 1 As shown in (c), a SrTiO3 thin film is used to cover the gate metal electrode; the PPC support layer is removed with acetone.

[0062] (5) Preparation and transfer of transition metal chalcogenide MoS2 nanosheets

[0063] MoS2 nanosheets were formed by mechanically exfoliating the transition metal chalcogenide MoS2 material with adhesive tape, and then transferred to the self-supporting SrTiO3 film in step (4). The thickness of the MoS2 nanosheets was 2.8 nm.

[0064] (6) Fabrication of source metal electrode and drain metal electrode

[0065] The source and drain metal electrodes were patterned using electron beam lithography; the metal electrodes were then fabricated using thermal evaporation, with a chromium electrode thickness of 15 nm and a gold electrode thickness of 45 nm; excess metal film was removed using a lift-off method to obtain the source and drain metal electrodes, with a channel width of 5 μm, ultimately yielding a field-effect transistor, as shown in the diagram. Figure 2 As shown.

[0066] Thin film surface morphology characterization: The structure prepared in step (4) was placed on the sample stage of an atomic force microscope, and the morphology of the SrTiO3 thin film on the metal electrode was characterized in tapping mode to obtain the sample surface roughness. The results are as follows: Figure 3 As shown in (b), the surface roughness of the SrTiO3 film is 269.27 pm.

[0067] Electrical performance testing:

[0068] The fabricated field-effect transistor device was placed in a probe station. The source and drain electrodes of the sample were connected to the two ends of an ammeter, respectively, and the gate electrode was connected to the source electrode. The transfer characteristic curves of the device under different bias voltages were measured, and the results are shown below. Figure 4 As shown in (b), the device has an on / off ratio of 10. 8 The lowest subthreshold swing reached 69.2 mV / dec, and the field-effect transistor mobility was 230 cm⁻¹. 2 / (V·s), exhibiting excellent electrical performance.

[0069] Comparative Example

[0070] The spin-coated PPC support layer in step (4) of Example 1 was replaced with a spin-coated PMMA (polymethyl methacrylate) support layer, and the rest was the same as in Example 1, to obtain a field-effect transistor.

[0071] Thin film surface morphology characterization: The structure prepared in step (4) of the comparative example was placed on the sample stage of an atomic force microscope. The morphology of the SrTiO3 thin film on the metal electrode was characterized in tapping mode to obtain the sample surface roughness. The results are as follows: Figure 3 As shown in (a), the surface roughness of the SrTiO3 film is 2009 pm. The field-effect transistor device prepared in the comparative example was subjected to electrical performance testing using the same method as in Example 1. The test results are shown below. Figure 4 As shown in Figure (a), the switching ratio of the device in Comparative Example 1 is 10. 6 The subthreshold swing reaches a minimum of 202 mV / dec, and the field-effect transistor mobility is 20 cm⁻¹. 2 / (V·s).

[0072] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method of fabricating a field effect transistor, characterized by, The method comprises the following steps: sequentially epitaxially growing a Sr4Al2O7 sacrificial layer and a SrTiO3 thin film layer on a surface of a single-crystal SrTiO3 substrate, spin-coating a polypropylene carbonate support layer on a surface of the SrTiO3 thin film layer, and obtaining a SrTiO3 substrate / Sr4Al2O7 / SrTiO3 / PPC composite layer structure; immersing the SrTiO3 substrate / Sr4Al2O7 / SrTiO3 / PPC composite layer structure in water to dissolve the Sr4Al2O7 sacrificial layer, and obtaining a SrTiO3 / PPC composite layer structure; transferring the SrTiO3 / PPC composite layer structure to an insulating substrate with a gate metal electrode, so that the SrTiO3 thin film layer in the SrTiO3 / PPC composite layer structure covers the gate metal electrode, and then etching the polypropylene carbonate support layer, and obtaining an insulating substrate / gate metal electrode / SrTiO3 composite structure; depositing a two-dimensional layered semiconductor material layer on a surface of the SrTiO3 thin film layer of the insulating substrate / gate metal electrode / SrTiO3 composite structure, and depositing a source metal electrode and a drain metal electrode on a surface of the two-dimensional layered semiconductor material layer, and obtaining the field effect transistor.

2. The production method according to claim 1, characterized by, The thickness of the Sr4Al2O7 sacrificial layer is 8-15 nm, and the thickness of the SrTiO3 thin film layer is 20-28 nm.

3. The preparation method according to claim 1, characterized in that, The gate metal electrode comprises a titanium electrode and a gold electrode which are stacked, the thickness of the titanium electrode is 5-8 nm, and the thickness of the gold electrode is 15-20 nm, and the titanium electrode is in contact with the insulating substrate.

4. The production method according to claim 1 or 3, characterized by, The insulating substrate is a silicon substrate with a surface covered by silicon dioxide, and the thickness of the silicon dioxide is 285 nm.

5. The preparation method according to claim 1, characterized in that, The etching reagent used in the etching is an organic solvent.

6. The method of claim 1, wherein, The two-dimensional layered semiconductor material in the two-dimensional layered semiconductor material layer is a transition metal chalcogenide compound.

7. The production method according to claim 6, wherein The transition metal chalcogenide compound comprises MoS2.

8. The production method according to claim 1, 6 or 7, characterized by, The thickness of the two-dimensional layered semiconductor material layer is 1.4-3.5 nm.

9. The method of claim 1, wherein, The source metal electrode and the drain metal electrode each comprise a chromium electrode and a gold electrode which are stacked, the thickness of the chromium electrode is 15-20 nm, the thickness of the gold electrode is 45-55 nm, and the chromium electrode is in contact with the two-dimensional layered semiconductor material layer.

10. The production method according to claim 1 or 9, characterized by, The channel width between the source metal electrode and the drain metal electrode is 4-6 μm.

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