Transistor device

Abstract

Disclosed is a transistor device comprising: a transistor cell (10); and a source electrode (41), in which each transistor cell (10) comprises: a source region (11) of a first doping type; a body region (12) of a second doping type complementary to the first doping type and adjoining the source region (11); a gate electrode (21) adjacent to the body region (12), dielectrically insulated from the body region (12) by a gate dielectric (22), and arranged in a gate trench (120) extending from the first surface (101) of the semiconductor body (100) into the semiconductor body (100); a body contact region (17) adjoining the body region (12) and electrically connected to the source electrode (41), where a distance (d4) between the body contact region (17) and the gate dielectric (22) is less than 300 nanometers. According to the embodiment of the invention, the robustness of the transistor device can be improved.

Description

Technical Field

[0001] The present disclosure generally relates to a transistor device, and more particularly to a super junction transistor device. Background Art

[0002] The super junction transistor device may include a plurality of transistor units, each transistor unit including a gate electrode, a source region, a body region adjacent to the gate electrode and insulated from the gate electrode dielectric by a gate dielectric, and a drift region adjacent to the body region. In the on state (conductive state) of the transistor device, there is a conductive channel in the body region along the gate dielectric. In the off state, the conductive channel is interrupted. The source region, the adjacent body region, and the drift region form a parasitic bipolar transistor, wherein the body region forms the base of the parasitic transistor.

[0003] During operation of the transistor device, operating situations may occur in which charge carriers are injected into the body region, which may cause the parasitic bipolar transistor to turn on, so that the transistor device is in the on-state in an uncontrolled manner at least for a certain period of time. This is highly undesirable. Summary of the invention

[0004] One example relates to a transistor device. The transistor device includes a transistor cell and a source electrode. Each of the transistor cells includes a source region of a first doping type, a body region of a second doping type complementary to the first doping type and adjacent to the source region, and a gate electrode adjacent to the body region, wherein the gate electrode is insulated from the body region dielectric by a gate dielectric and is arranged in a gate trench extending from a first surface of a semiconductor body into the semiconductor body. In addition, each transistor cell includes a body contact region adjacent to the body region and electrically connected to the source electrode. The distance between the body contact region and the gate dielectric is less than 300 nanometers.

[0005] Another example relates to a transistor device. The transistor device includes a transistor cell and a source electrode. Each of the transistor cells includes a source region of a first doping type, a body region of a second doping type complementary to the first doping type and adjacent to the source region, and a gate electrode adjacent to the body region, the gate electrode being insulated from the body region dielectric by a gate dielectric, and arranged in a gate trench extending from a first surface of a semiconductor body into the semiconductor body. In addition, each transistor cell includes a body contact region adjacent to the body region and electrically connected to the source electrode. The body contact region is connected to the source electrode through a conductive via, and the conductive via extends from the source electrode through the insulating layer and a portion of the semiconductor body to the body contact region. The distance between the conductive via and the gate dielectric is less than 350 nanometers. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The examples are explained below with reference to the accompanying drawings. The accompanying drawings are used to illustrate certain principles so that only aspects necessary for understanding these principles are shown. The accompanying drawings are not drawn to scale. In the accompanying drawings, the same reference numerals represent the same features.

[0007] Figure 1 schematically illustrates a vertical cross-sectional view of a portion of a transistor device including a plurality of transistor cells;

[0008] Figure 2 and Figure 3 Shows Figure 1 Horizontal cross-sectional views of the transistor device shown in different horizontal cross-sections;

[0009] Figures 4 to 7 shows a detailed view of a transistor cell according to various examples;

[0010] FIG. 8A to FIG. 8C One example of a method for forming contact regions and contact vias of a transistor cell is shown;

[0011] 9A to 9C Another example of a method for forming contact regions and contact vias of a transistor cell is shown;

[0012] FIG. 10A to FIG. 10C Yet another example of a method for forming contact regions and contact vias of a transistor cell is shown; and

[0013] FIG. 11A to FIG. 11B A top view of a transistor device according to various examples is shown. DETAILED DESCRIPTION

[0014] In the following detailed description, reference is made to the accompanying drawings. The accompanying drawings constitute a part of the specification and, for illustrative purposes, show examples of how the invention may be used and implemented. It should be understood that the features of the various embodiments described herein may be combined with each other unless otherwise specifically noted.

[0015] Figure 1 Schematically shows a portion of a transistor device including a plurality of transistor cells 10. More specifically, Figure 1 A vertical cross-sectional view of a portion of a semiconductor body 100 of a transistor device in which the transistor cell 10 is integrated is shown.

[0016] The semiconductor body 100 includes a single-crystalline semiconductor material, for example, silicon (Si) or silicon carbide (SiC).

[0017] refer to Figure 1Each transistor cell 10 includes a source region 11 of a first doping type, a body region 12 of a second doping type complementary to the first doping type, and a gate electrode 21. The gate electrode 21 is adjacent to the body region 12, dielectrically insulated from the body region 12 by a gate dielectric 22, and is arranged in a gate trench 120 extending from a first surface 101 of the semiconductor body 100 into the semiconductor body 100. Figure 1 , the source regions 11 and body regions 12 of two adjacent transistor units can be arranged in the mesa region between adjacent gate trenches 120. In this example, the body regions 12 of two adjacent transistor units 10 can be formed by a continuous second doping type doped region. In addition, the gate electrodes 21 of two (other) adjacent transistor units can be formed by a continuous electrode arranged in one gate trench 120.

[0018] The gate electrode 21 includes a conductive material. Examples of the conductive material include doped polysilicon or a metal such as tungsten (W), titanium (Ti), copper (Cu), or aluminum (Al). For example, the gate dielectric 22 includes an oxide. According to one example, the oxide is silicon oxide (SiO2).

[0019] The transistor device further comprises a source electrode 41 electrically connected to the source region 11 and the body region 12 of the transistor cell 10. Figure 1 1 and 2 , only schematically illustrate the connection between the source electrode 41 and the source region 11 and the body region 12. A detailed example for connecting the source electrode 41 to the source region 11 and the body region 12 is further explained below. The source electrode includes a conductive material, such as aluminum (Al), copper (Cu), or aluminum-copper alloy (AlCu).

[0020] The source electrode 41 is separated from the semiconductor body 100 by an insulating layer 5. The insulating layer 5 includes an electrically insulating material such as oxide or nitride.

[0021] refer to Figure 1 , the transistor device further includes a drain region 13 of a first doping type, a drift region 14 of the first doping type, a compensation region 15 of a second doping type, and a buffer region 16. The buffer region 16 is of the first doping type and is arranged between the drain region 13 and the drift region 14 and the compensation region 15. According to an example, the buffer region 16 has a lower doping concentration than the drain region 13, and has a higher doping concentration than the drift region 14 and the compensation region 15.

[0022] according to Figure 1 The transistor device including the drift region 14 of the first doping type and the compensation region 15 of the second doping type is a super junction transistor device.

[0023] As further explained below, the transistor device can be operated in an on state or an off state. In the on state, the conductive channel in the body region 12 follows the gate dielectric between the source region 11 and the drift region 14. To this end, each drift region 14 adjoins the gate dielectric 22 and the body region 12 of at least one transistor cell 10. Each compensation region 15 adjoins at least one drift region 14 and is connected to the source electrode 41 ... Figure 1 In the example shown, each compensation region 15 adjoins the body region 12 of at least one transistor cell and is connected to the source electrode 41 via the corresponding body region 12 .

[0024] according to Figure 1 The transistor device is a vertical transistor device. In the present example, the drain region 13 is spaced apart from the source region 11 and the body region 12 of the transistor unit 10 in a vertical direction z of the semiconductor body 100. The vertical direction z is substantially perpendicular to the first surface 101. According to an example, the drain region 13 adjoins a second surface 102 of the semiconductor body 100 opposite to the first surface 101.

[0025] The drain region 13 forms or is connected to a drain node D of the transistor device. The source electrode 41 forms or is connected to a source node S of the transistor device. Furthermore, the gate electrode 21 is connected to a gate node (not shown) of the transistor device.

[0026] refer to Figure 1 , the gate trenches with the gate electrode 21 are spaced apart from each other in a first lateral direction x of the semiconductor body 100. The first lateral direction x is perpendicular to the vertical direction z. According to an example, the gate electrode 21 is implemented as a strip electrode (elongated strip electrode). In this example, the gate electrode 21 is elongated in a second lateral direction y perpendicular to the first lateral direction x.

[0027] exist Figure 2 An example of a long strip gate electrode 21 is shown in FIG. Figure 2 A portion of the semiconductor body 100 is shown in a first horizontal section AA through a gate trench 120 with a gate electrode 21 and a gate dielectric 22 .

[0028] refer to Figure 1 , the drift regions 14 are spaced apart from one another in the first lateral direction x, and the compensation region 15 is arranged between two adjacent drift regions 14 .

[0029] Figure 3 A portion of the semiconductor body 100 is shown in a second horizontal section BB through the drift region 14 and the compensation region 15. Figure 3In the example shown in , the drift region 14 and the compensation region 15 are elongated regions having a longitudinal direction corresponding to the second lateral direction y. In this example, the drift region 14 and the compensation region 15 are substantially parallel to the gate trench 120. However, this is only an example.

[0030] According to another example (not shown), the longitudinal directions of the drift region 14 and the compensation region 15 are both perpendicular to the longitudinal direction of the gate trench 120. In this example, the drift regions 14 are spaced apart from each other in the first lateral direction x and are elongated in the second lateral direction y.

[0031] The transistor device can be operated in a conventional manner by applying a driving voltage (gate-source voltage) between the gate electrode 21 and the source electrode 41. The transistor device is in an on-state (conductive state) when the driving voltage generates a conductive channel in the body region 12 along the gate dielectric 22 between the source region 11 and the drift region 14. When the conductive channel is interrupted, the transistor device is in an off-state (blocking state).

[0032] The transistor device may be implemented as an N-type transistor device or a P-type transistor device. For example, when the driving voltage is higher than a predefined positive threshold voltage, the N-type transistor device is in an on state, and when the driving voltage is lower than the threshold voltage, the N-type transistor device is in an off state.

[0033] In an N-type transistor device, the doped region of the first doping type is an N-type region, and the doped region of the second doping type is a P-type region. In a P-type transistor device, the doped region of the first doping type is a P-type region, and the doped region of the second doping type is an N-type region.

[0034] The source region 11, the body region 12, the drift region 14, the compensation region 15, the buffer region 16 and the drain region 13 may also be referred to as active device regions. For example, in an N-type transistor device, the doping concentration of the active device region is selected from the following ranges:

[0035] Source region 11: 5E19 cm -3 –5E20 cm -3

[0036] Body zone 12: 3E19 cm -3 –3E20 cm -3

[0037] Drain region 13: 5E18 cm -3 –5E20 cm -3

[0038] Drift zone 14: 7E15 cm -3 –7E16 cm -3

[0039] Compensation zone 15: 7E15 cm -3 –7E16 cm -3

[0040] Buffer 16: 5E15 cm -3 –5E16 cm -3

[0041] Body contact area 17: 1E20 cm -3 –1E21 cm -3

[0042] The transistor device can be operated in a forward operation mode or a reverse operation mode. When a voltage that reversely biases the PN junction between the drift region 14 and the body region 12 is applied between the drain node D and the source node S, the transistor device is in the forward operation mode. For example, when a positive voltage is applied between the drain node D and the source node S, the N-type transistor device is in the forward operation mode, and when a negative voltage is applied between the drain node D and the source node S, the N-type transistor device is in the reverse operation mode.

[0043] When the transistor device is in the on state and forward mode of operation, the first type charge carriers flow from the drain source region 11 to the drain region 13 via the conductive channel along the gate dielectric 22, the drift region 14 and the buffer region 16. For example, in an N-type transistor device, the first type charge carriers are electrons.

[0044] When the transistor device is in the off state and the forward operation mode, the conductive channel along the gate dielectric 22 is interrupted, and the PN junction between the body region 12 and the drift region 14 is reverse biased. In this operation mode, as long as the voltage applied between the drain node D and the source node S is lower than the voltage blocking capability of the transistor device, the flow of charge carriers between the source region 11 and the drain region 13 is interrupted. When the voltage applied between the drain node D and the source node S is higher than the voltage blocking capability, avalanche breakdown may occur, causing an avalanche current to flow between the source region 11 and the drain region 13. The operation mode of the transistor device with the flow of the avalanche current is referred to as the avalanche mode hereinafter.

[0045] In the reverse operation mode, the PN junction between the drift region 14 and the body region 12 is forward biased, so that the transistor device is turned on, regardless of whether a conductive channel is generated along the gate dielectric 22 by applying a suitable driving voltage. For example, when a positive voltage is applied between the source node S and the drain node D, the N-type transistor device is in the reverse operation mode.

[0046] When the transistor device is in the on-state (so that there is a conductive channel along the gate dielectric 22) and in the reverse mode of operation, the current flowing between the source region 12 and the drain region 13 is substantially a unipolar current. A unipolar current is a current that substantially only includes majority charge carriers, which are charge carriers of the first type.

[0047] When the transistor device is in the off state (so that the conductive channel along the gate dielectric 22 is interrupted), the current flowing between the source region 12 and the drain region 13 is a bipolar current. The bipolar current includes a first type of charge carrier and a second type of charge carrier. In an N-type transistor device, the first type of charge carrier is an electron and the second type of charge carrier is a hole. The operating mode of the transistor device with bipolar current flowing is referred to as the diode mode hereinafter. The second type of charge carrier is a minority charge carrier in the transistor device.

[0048] In each transistor cell 10, the source region 11, the body region 12 and the drift region 14 adjacent to the body region 12 form a parasitic bipolar transistor. In particular, when the transistor device is in avalanche mode or when the transistor device is in diode mode, second type charge carriers may be injected into the body region 12. These charge carriers may cause the parasitic bipolar transistor to turn on. This is highly undesirable because it will cause the transistor device to turn on in an uncontrolled manner.

[0049] Figures 4 to 7 Different examples are shown for implementing transistor devices in a manner that significantly reduces the risk of turning on a parasitic bipolar transistor. Figures 4 to 7 Each of the figures shows a vertical cross-sectional view of a portion of a semiconductor body 100 including two adjacent transistor cells 10. More specifically, Figures 4 to 7 Each of them shows a mesa region between two adjacent gate trenches 120 , portions of adjacent gate trenches 120 having gate electrodes 21 and gate trenches 22 , and portions of the drift region 14 and compensation region 15 adjoining the body regions 12 of two transistor cells 10 .

[0050] refer to Figures 4 to 7 , each transistor cell 10 includes a body contact region 17 of the second doping type, which is electrically connected to the source electrode 41 through a conductive via 42. The body contact region 17 is adjacent to the body region 12, so that the body region 12 is electrically connected to the source electrode 41 via the body contact region 17 and the conductive via 42. The doping concentration of the body contact region 17 is higher than the doping concentration of the body region 12 and is sufficient to achieve contact between the conductive via 42 and the body contact region 17.

[0051] The conductive via 42 includes a conductive material such as tungsten (W) or titanium (Ti).

[0052] The via 42 is also connected to the source region 11 of the corresponding transistor cell 10 , so that the source region 11 is connected to the source electrode 41 through the conductive via 42 .

[0053] In each transistor cell 10, the body contact region 17 is used not only to connect the body region 12 to the via 42 and the source electrode 41, but also to collect the second type charge carriers that may be injected into the body region 12 to prevent those second type charge carriers from turning on the parasitic bipolar transistor. In order to achieve a high efficiency of the body contact region 17 in collecting minority charge carriers, the body contact region 17 is arranged close to the corresponding gate dielectric 22. This includes a distance d4 between the body contact region 17 and the corresponding gate dielectric 22 (see Figure 4 and Figure 5 ) is less than 300 nanometers.

[0054] According to an example, a distance d4 between the body contact region 17 and the corresponding gate dielectric 22 is greater than 150 nanometers.

[0055] Placing the body contact region 17 close to the gate dielectric 22 prevents minority charge carriers from moving along the gate dielectric 22 to the source region 11. Minority charge carriers moving along the gate dielectric 22 to the source region 11 may cause a voltage drop that may cause the parasitic bipolar transistor to turn on. Therefore, collecting these minority charge carriers by the body contact region 17 may help prevent the parasitic bipolar transistor from turning on.

[0056] refer to Figures 4 to 7 , the body contact region 17 may be spaced apart from the source region 11 in the vertical direction z. However, this is only an example. According to another example (not shown), the body contact region 17 of one transistor cell 10 adjoins the body region 12 and the source region 11 of the corresponding transistor cell 10 .

[0057] according to Figure 4 In an example shown, two transistor cells 10 have their body regions 11 and source regions 12 arranged in a common mesa region between two adjacent gate trenches 120, wherein each transistor cell 10 includes a body contact region 17 and a corresponding via 42, wherein the two body contact regions 17 and the via 42 are spaced apart from each other in a first lateral direction x.

[0058] according to Figure 5 In another example shown, two transistor cells 10 have their body regions 11 and source regions 12 arranged in a common mesa region between two adjacent gate trenches 120 , and the two transistor cells 10 share a body contact region 17 and a corresponding via 42 .

[0059] refer to Figures 4 to 7, the source regions 11 of two adjacent transistor units 10 sharing the mesa region are spaced apart from each other in the first lateral direction x. Figure 4 In the example shown, in which each transistor cell 10 has its own body contact region 17 and corresponding via 42, each source region 11 can be implemented so as not to extend beyond the via 42 in a direction away from the corresponding gate dielectric 22, so that the source region 11 is arranged only between the gate dielectric 22 and the via 42 in the first lateral direction x.

[0060] The source region 11 may be formed before forming the gate via 42. Due to the size of the source region 11 in the first lateral direction x and the inevitable deviation in the positioning of the via 42 relative to the source region 11, the source region may be subdivided by the corresponding via 42 into the desired source region 11 arranged between the gate dielectric 22 and the via 42 and a remaining portion 11' separated from the source region 11 by the via 42. This optional remaining portion 11' is preferably Figure 6 and Figure 7 Shown by dotted lines.

[0061] Each remaining portion 11 ′ forms a parasitic bipolar transistor together with the body region 12 and the drift region 14. In order to ensure that the parasitic bipolar transistor formed by the remaining portion 11 ′, the body region 12 and the drift region 14 does not negatively affect the operation of the transistor device, at least one additional body contact region 18 may be arranged in the mesa region between two adjacent body contact regions 17, wherein the additional body contact region 18 is connected to the source electrode 41 through a corresponding conductive via 43.

[0062] like Figure 6 As shown, the further body contact region 18 may be spaced apart from the body contact region 17 in the first lateral direction x. According to an example, the distance between the further body contact region 18 and the body contact region 17 is less than 300 nm, in particular less than 200 nm or less than 100 nm.

[0063] according to Figure 7 In another example shown, the further body contact region 18 adjoins the body contact region 17. In this example, the via 42, the body contact region 17 and the further body contact region 18 form a closed shield around the remaining part 11'.

[0064] FIG. 8A to FIG. 8C shows the method for forming the Figure 4 , Figure 6 and Figure 7 An example of a method of arranging the body contact area 17 and the conductive via 42 of the structure.

[0065] exist FIG. 8A to FIG. 8CIn the example shown, after forming the gate electrode 21 and the gate dielectric 22 in the gate trench 120, forming the source region 11 and the body region 12 in the mesa region, and forming the insulating layer 5 over the gate electrode 21 and the first surface 101 of the semiconductor body 100, the body contact region 17 and the via 42 are formed. Fig. 8A The method includes forming contact trenches 420 extending through the insulating layer 5 into the mesa region having the source region 11 and the body region 12. The contact trenches 420 are formed such that each contact trench 420 abuts the source region 11 of the corresponding transistor cell 10 and extends in the vertical direction into the body region 12. Forming the contact trenches 420 may include a conventional etching process using an etching mask (not shown) formed on top of the insulating layer 5.

[0066] refer to Figure 8B The method further includes implanting second type dopant atoms into the body region 12 through the bottom of the contact trench 420 to form an implant region 17'. Based on the implant region 17', the body contact region 17 is formed in an annealing process. The annealing process may occur directly after the implantation and before the formation of the via 42, or may occur after the formation of the via 42.

[0067] It should be noted that forming the source region 11 and the body region 12 may also include an implantation process for implanting dopant atoms into the semiconductor body and a subsequent annealing process. The same annealing process may be used to form the source region 11 and the body region 12 as well as the body contact region 17. According to another example, different annealing processes are used to form the source region 11 and the body region 12 on one side and to form the body contact region 17 on the other side.

[0068] refer to Figure 8C The method further includes forming a via 42 in the contact trench 420. Forming the via 42 may include completely filling the contact trench with a conductive material. Alternatively, forming the via 42 includes lining the bottom and sidewalls of the contact trench 420 with a conductive material.

[0069] The optional additional body contact region 18 and the corresponding via 43 may be formed by the same process sequence as the formation of the body contact region 17 and the corresponding via 42. FIG. 8A to FIG. 8C The formation of an optional additional body contact region 18 and a corresponding via 43 is shown in dashed lines in FIG. Fig. 8A ) together to form another contact opening 430, implant second type dopant atoms into the other contact opening 430 to form another implantation region 18′, form another body contact region 18 based on the other implantation region 18′ using an annealing process, and form another via 43 in the other contact opening 430.

[0070] 9A to 9C Shown is the method for forming Figure 5 An example of a method of arranging a structure of the type shown in FIG. 1 , in which two adjacent transistor cells 10 share a body contact region 17 and a corresponding via 42 . 9A to 9C The method is based on FIG. 8A to FIG. 8C method, and according to FIG. 8A to FIG. 8C The method differs in that only one contact opening 420 is formed (see Fig.9A ), dopant atoms are implanted into a contact opening 420 to form an implantation region 17' (see Fig. 9B ), forming only one body contact region 17 in each mesa region based on the implantation region 17 ′, and forming a via 42 in the contact opening 420 .

[0071] exist FIG. 8A to FIG. 8C and 9A to 9C In each of the examples shown in , in the implantation process for forming the implantation region 17', the implantation energy is selected so that the dopant atoms are implanted in a region close to the bottom of the contact opening 420, so that the resulting body contact region 17 abuts the bottom and is connected to the via 42 formed in the contact opening 420. According to one example, the implantation energy is selected from 10 keV to 50 keV. According to one example, the implantation dose is selected from 5E14 cm -2 To 5E15cm -2 between.

[0072] According to an example, the implantation dose is selected such that the minimum doping concentration of the body contact region 17 is at least 10 times the doping concentration of the body region 12 .

[0073] Furthermore, the thickness of the insulation layer 5 is adapted to the implantation energy, so that dopant atoms are not implanted through the insulation layer 5 into the semiconductor body 100 .

[0074] Referring to the above, forming the body contact region 17 based on the implanted region 17' includes an annealing process. According to one example, the temperature and duration of the annealing process are selected so that the implanted dopant atoms are electrically activated. As can be seen from the accompanying drawings, the body contact region 17 can extend from the via 42 to the gate dielectric 22 to a certain extent. This may be due to diffusion in the annealing process, but it may also be due to scattering errors (straggling) in the implantation process. A dedicated annealing process can be used to activate the dopant atoms included in the body contact region 17. According to another example, an annealing process for activating dopant atoms in the source region 11 and the body region 12 is used, for example, to activate the dopant atoms included in the body contact region 17.

[0075] Referring to the above, the body contact region 17 is spaced apart from the gate dielectric 22 by less than 300 nm. For example, the contact opening (contact trench) 420 is formed to be spaced apart from the gate dielectric 22 by less than 350 nm or less than 300 nm.

[0076] According to an example, the vertical dimension of the contact opening 420 in the semiconductor body 100 is between 400nm and 600nm. The vertical dimension is the dimension of the contact opening 420 in the vertical direction z. That is, in this example, the contact opening 420 extends through the insulating layer 5 and extends from the first surface 101 to between 400nm and 600nm in the semiconductor body 100. For example, the vertical dimension of the source region 11 is between 100nm and 200nm. Therefore, the body contact region 17 formed by implanting dopant atoms into the bottom of the contact opening 420 can be spaced apart from the source region 11.

[0077] The depth of the gate trench 120, i.e., the dimension of the gate trench 120 in the vertical direction z, is, for example, between 2 micrometers and 4 micrometers. The width of the gate trench 120, i.e., the dimension of the gate trench 120 in the first lateral direction x, is, for example, between 700 nm and 1.3 micrometers (1300 nm). For example, the spacing w2 (see FIG. 1 ) as the center-to-center distance between two adjacent gate trenches Figures 4 to 7 ) is between 3 microns and 5 microns. The lateral dimension w1 of the mesa region is given by the spacing w2 minus the gate trench width.

[0078] FIG. 10A to FIG. 10C Another example of a method for forming a common body contact region 17 and corresponding via 42 is shown.

[0079] refer to FIG. 10A to FIG. 10B The method comprises forming an implantation region 17' by implanting second type dopant atoms into the body region 12 via the first surface 101. The dopant atoms are implanted using an implantation mask 301 comprising openings, wherein the openings define those regions into which the dopant atoms are to be implanted. The source region 11 and the body region 12 may be formed before or after the implantation of dopant atoms to form the implantation region 17'. The implantation process is performed before forming the insulating layer 5 on top of the first surface 101 of the semiconductor body 100.

[0080] refer to Fig. 10B The method further comprises forming an insulating layer 5 and forming a contact opening 420 in the insulating layer 5 and in a portion of the semiconductor body 100. The contact opening (contact trench) 420 is formed such that it extends through the insulating layer 5 and a portion of the semiconductor body 100 into the implantation region 17' or body contact region 17.

[0081] As explained above, forming the body contact region 17 based on the implant region 17' includes an annealing process. The annealing process may be performed before or after forming the contact opening 420. Therefore, the contact opening 420 is formed to extend into the implant region 17' or into the body contact region 17.

[0082] refer to Fig. 10C The method further includes forming a contact via 42 in the contact opening 420. Fig. 10C In the example shown, the source region 11 extends in a lateral direction to the contact via 42. However, this is only an example. According to another example (not shown), the transistor device includes connecting the source region 11 to the source electrode 41 ( Fig. 10C Additional contact vias are not shown.

[0083] In each of the examples explained above, after forming the contact via 42 and optionally the further contact via 43 , the source electrode 41 is formed on top of the insulating layer 5 .

[0084] Referring to the above, the body contact region 17 increases the robustness of the transistor device, in particular the robustness of the transistor device in avalanche mode or diode mode. The buffer region 16 also contributes to the robustness of the transistor device in these operating modes. Referring to the above, the buffer region 16 is arranged between the drift region 14 and the drain region 13, and has a lower doping concentration than the drift region 14 and the drain region 13. The buffer region 16 contributes to the on-resistance of the transistor device, which is the resistance between the drain node D and the source node S in the on state. Basically, the greater the thickness of the buffer region 16, the higher the on-resistance.

[0085] In the transistor device explained above, it includes a body contact region 17 close to the gate dielectric 22. In order to deactivate the parasitic bipolar transistor, the thickness of the buffer region 16 may be reduced compared to a conventional super junction transistor device.

[0086] The thickness d2 of the buffer zone 16 (see Figure 1 ) is a dimension of the buffer zone 16 in the vertical direction z of the semiconductor body 100. According to an example, a thickness d2 of the buffer zone 16 is less than 25% or even 20% of a distance d1 between the buffer zone 16 and the first surface 101 .

[0087] According to an example, the thickness d2 and the doping concentration of the buffer region 16 are adapted to each other such that the portion of the total on-resistance of the transistor device caused by the resistance of the buffer region 16 is between 10% and 20% of the total on-resistance.

[0088] The distance between the buffer region 16 and the first surface 101 is mainly given by the vertical dimension d3 of the drift region 14 and the compensation region 15. The doping of the drift region 14 and the compensation region 15 and the vertical dimension d3 of the drift region 14 and the compensation region 15 mainly define the voltage blocking capability of the transistor device. The vertical dimension of the body region 12 is much lower than the vertical dimension of the drift region 14 and the compensation region 15, and is less than 3% or even 2% of the vertical dimension d3 of the drift region 14 and the compensation region 15.

[0089] According to an example, the distance d1 between the buffer zone 16 and the first surface 101 is between 35 micrometers and 50 micrometers.

[0090] According to an example, the voltage blocking capability of the transistor device is 600 V. In this example, the distance between the buffer region 16 and the first surface 101 is between 38 μm and 42 μm, and the thickness d3 of the buffer region 16 is, for example, between 6 μm and 10 μm.

[0091] According to another example, the voltage blocking capability of the transistor device is 650 V. In this example, the distance between the buffer region 16 and the first surface 101 is between 42 micrometers and 44 micrometers, and the thickness d3 of the buffer region 16 is, for example, between 8 micrometers and 11 micrometers.

[0092] In both examples, the vertical dimension of the body region 12 is, for example, between 800 nanometers (nm) and 1.8 micrometers.

[0093] FIG. 11A to FIG. 11B Schematically shows a top view of an entire transistor device according to two different examples. More specifically, FIG. 11A to FIG. 11B The source electrode 41 and the first surface 101 (in the semiconductor body 100) are shown. FIG. 11A to FIG. 11B A top view of additional features above (not visible in FIG. 2 ).

[0094] refer to FIG. 11A to FIG. 11B , each transistor device includes a gate runner 44 and a gate pad 45 connected to the gate runner 44. The gate runner 44 surrounds the source electrode 41 in the horizontal direction. The gate pad 45 and the gate runner 44 are spaced apart from the source electrode 41. The gate pad 45, the gate runner 44 and the source electrode 41 may include the same material and may be formed by the same process. The gate pad 45 may be adjacent to the gate runner 41 (as shown). According to another example (not shown), the gate pad 45 is spaced apart from the gate runner 44, and a resistor (gate resistor) is formed between the gate runner 44 and the gate pad 45.

[0095] The transistor unit 10 is Fig.11A and Fig. 11B For illustration purposes only, FIG. 11A to FIG. 11B 4. The positions of two gate trenches 120 among the plurality of gate trenches 120 relative to the source electrode 41 and the gate runner 44 are shown in bold lines. As explained above, in each of these gate trenches 120, a corresponding electrode forming a gate electrode of at least one transistor cell 10 is arranged. The gate electrode 21 in each of these trenches is electrically connected to the gate runner 44 at at least one of the two opposite longitudinal ends of the corresponding gate electrode 21. The longitudinal ends of the gate electrode 21 are the ends of the gate electrode 21 in the second lateral direction y. The gate electrode 21 is connected to the gate runner 44 in a conventional manner, for example using a conductive via. However, such a connection is not particularly convenient. FIG. 11A to FIG. 11B Not shown in FIG.

[0096] The gate pad 45 forms a gate node of the transistor device, such that a driving voltage for turning on or switching the transistor cell 10 may be applied between the gate pad 45 and the source electrode 41 , which may also be referred to as a source pad.

[0097] exist Fig.11A In the example shown, the gate pad 45 is arranged substantially in the middle between two opposite side walls of the semiconductor body 100. Fig. 11B In the example of , the gate pad 45 is arranged at a position close to the corner formed by two adjacent side walls of the semiconductor body 100. In each of these examples, the transistor device may include two types of gate electrodes 21, namely a first type gate electrode and a second type gate electrode. The first type gate electrode 21 has a first longitudinal end and an opposite second longitudinal end both connected to the gate runner 44. The second type gate electrode has only one longitudinal end connected to the gate runner 44.

[0098] The semiconductor body 100 may include an inner region and an edge region. The inner region may also be referred to as an active region, includes the transistor unit 10, and is substantially a region of the semiconductor body 100 arranged below the source electrode 41. The edge region is arranged between the inner region and the sidewall of the semiconductor body 100. According to an example, the gate runner 44 and the gate pad 45 are arranged above the edge region of the semiconductor body 100.

Claims

1. A transistor device, comprising: Transistor unit (10); as well as a source electrode (41), Wherein, each transistor unit (10) comprises: A source region (11) of a first doping type; A body region (12) of a second doping type complementary to the first doping type and adjacent to the source region (11); A gate electrode (21) adjacent to the body region (12), which is dielectrically insulated from the body region (12) by a gate dielectric (22) and is arranged in a gate trench (120) extending from a first surface (101) of the semiconductor body (100) into the semiconductor body (100); A body contact region (17) is adjacent to the body region (12) and electrically connected to the source electrode (41), wherein a distance (d4) between the body contact region (17) and the gate dielectric (22) is less than 300 nanometers.

2. The transistor device according to claim 1, wherein: The distance (d4) between the body contact region (17) and the gate dielectric is greater than 150 nanometers.

3. The transistor device according to claim 1 or 2, wherein: The transistor device further comprises: An insulating layer (5) is arranged between the source electrode (41) and the first surface (101) of the semiconductor body (100).

4. The transistor device according to claim 3, wherein: The body contact region (17) is connected to the source electrode (41) through a conductive via (42), which extends from the source electrode (41) through the insulating layer (5) and a portion of the semiconductor body (100) to the body contact region (17).

5. The transistor device according to claim 4, wherein: The distance between the conductive via (42) and the gate dielectric (22) is less than 350 nanometers.

6. The transistor device according to claim 5, wherein: The source region (11) and the body region (12) of two adjacent transistor units (10) are arranged in the mesa region between adjacent gate trenches (120), and Each of two adjacent transistor cells (10) comprises a corresponding body contact region (17) and a corresponding conductive via (42).

7. The transistor device according to claim 5, wherein: The source region (11) and the body region (12) of two adjacent transistor units (10) are arranged in the mesa region between adjacent gate trenches (120), and Two adjacent transistor units (10) include a common body contact region (17) and a common conductive via (42) connected between the body contact region (17) and a source electrode (41).

8. The transistor device according to claim 6, wherein: The transistor device further comprises: A further body contact region (18) is arranged between the body contact regions (17) of adjacent transistor cells (10) and is connected to the source electrode (41) through a further conductive via (43).

9. The transistor device according to claim 8, wherein: The further body contact region (18) is spaced apart from the body contact region (17) of the adjacent transistor unit (10).

10. The transistor device according to claim 8, wherein: The further body contact regions (18) are respectively adjacent to the body contact regions (17) of adjacent transistor cells (10).

11. A transistor device according to any one of the preceding claims, wherein: The doping concentration of the body contact region (17) is at least 10 times the doping concentration of the body region (12).

12. A transistor device according to any one of the preceding claims, wherein: The transistor device further comprises: A drift region (14) of a first doping type and a compensation region (15) of a second doping type; A drain region (13) of a first doping type; and a buffer region (16) of a first doping type, arranged between the drain region (13) and the drift region (14) and the compensation region (15), Each drift region (14) is adjacent to a body region (12) of at least one transistor unit (10), and Each compensation region (15) is connected to a source electrode (41) and is adjacent to at least one drift region (14).

13. The transistor device according to claim 12, wherein: Each compensation region (15) adjoins a body region (12) of at least one transistor cell (10).

14. The transistor device according to claim 12 or 13, wherein: A dimension (d6) of the buffer region (16) in a vertical direction (z) of the semiconductor body (100) is less than 25% or less than 20% of a distance between the buffer region (16) and the first surface (101).

15. The transistor device according to claim 14, wherein: The distance between the buffer zone (16) and the first surface (101) is selected from 35 micrometers to 50 micrometers.

16. A transistor device comprising: Transistor unit (10); as well as a source electrode (41), Wherein, each transistor unit (10) comprises: A source region (11) of a first doping type; A body region (12) of a second doping type complementary to the first doping type and adjacent to the source region (11); A gate electrode (21) adjacent to the body region (12), which is dielectrically insulated from the body region (12) by a gate dielectric (22) and is arranged in a gate trench (120) extending from a first surface (101) of the semiconductor body (100) into the semiconductor body (100); a body contact region (17) adjacent to the body region (12) and electrically connected to the source electrode (41), The body contact region (17) is connected to the source electrode (41) through a conductive via (42). The conductive via (42) extends from the source electrode (41) through the insulating layer (5) and a portion of the semiconductor body (100) to the body contact region (17), The distance between the conductive via (42) and the gate dielectric (22) is less than 350 nanometers.

17. The transistor device according to claim 16, wherein: The distance between the conductive via (42) and the gate dielectric (22) is less than 300 nanometers.

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