Semiconductor structure and its fabrication method

Abstract

This application provides a semiconductor structure and a method for fabricating the same. The semiconductor structure includes: a substrate; an epitaxial layer located on one side surface of the substrate; a first implantation region and a second implantation region stacked in the epitaxial layer in a direction away from the substrate; a third implantation region and a fourth implantation region, wherein the third implantation region is located within the first implantation region, and the fourth implantation region is located within the first implantation region and at the periphery of the third implantation region; a first dielectric layer located on the side of the epitaxial layer away from the substrate; a first contact hole and two first trenches, both penetrating the first dielectric layer and the second implantation region, and respectively contacting the third and fourth implantation regions, wherein the two first trenches are located at least on both sides of the first contact hole; a second dielectric layer located on the bottom surface of the two first trenches; and a metal layer located on the surface of the first dielectric layer away from the epitaxial layer and on the partial surfaces of the second implantation regions on both sides of the first trenches away from the substrate, wherein the metal layer also fills the two first trenches and the first contact hole.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor structure and a manufacturing method thereof. BACKGROUND

[0002] Trench gate MOSFET devices are widely used in the field of motor drive and the like. When the device is off, the body PN junction breakdown of the device plays a role in freewheeling, and the breakdown current will be collected by the source contact hole. Taking NMOSFET as an example, the breakdown current flows from the P- region to the N+ region of the MOSFET device, and when the potential difference between the P- region and the N+ region reaches the PN junction turn-on voltage, the parasitic triode in the device is turned on, resulting in avalanche breakdown failure of the device. SUMMARY

[0003] The main purpose of the present application is to provide a semiconductor structure and a manufacturing method thereof, so as to at least solve the problem that the avalanche capability improvement scheme of the semiconductor device in the prior art will affect the threshold voltage and on-resistance of the device, thereby affecting the performance of the device.

[0004] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a semiconductor structure is provided, comprising: a substrate; an epitaxial layer located on one side surface of the substrate; a first implantation region and a second implantation region, which are stacked in the epitaxial layer away from the substrate, and the surface of the second implantation region away from the substrate is part of the surface of the epitaxial layer; a third implantation region and a fourth implantation region, the third implantation region is located in the first implantation region, the fourth implantation region is located in the first implantation region and is located at the outer periphery of the third implantation region, the ion concentration of the fourth implantation region is greater than that of the first implantation region and less than that of the third implantation region, the first implantation region, the third implantation region and the fourth implantation region have a first doping type, and the epitaxial layer and the second implantation region have a second doping type; a first dielectric layer located on the side of the epitaxial layer away from the substrate; a first contact hole and two first trenches, both penetrating the first dielectric layer and the second implantation region, the first contact hole being in contact with the third implantation region, and the two first trenches being in contact with the third implantation region and the fourth implantation region respectively, the two first trenches being located on both sides of the first contact hole, and the sidewalls of the two first trenches away from the first contact hole making part of the surface of the second implantation region away from the substrate exposed; a second dielectric layer located on the bottom surface of the two first trenches; a metal layer located on the surface of the first dielectric layer away from the epitaxial layer and on part of the surface of the second implantation region away from the substrate on both sides of the first trench, and the metal layer also fills in the two first trenches and the first contact hole.

[0005] Optionally, the semiconductor structure further includes: a second trench located in the epitaxial layer, the second trench having a greater depth than the first trench, the first trench and the first contact hole being located on one side of the second trench; a shielding gate located in the second trench; a first oxide layer located between a portion of the sidewall of the second trench near the substrate and the shielding gate, and between the bottom surface of the second trench and the shielding gate; a second oxide layer located on the surface of the shielding gate away from the substrate and on a portion of the sidewall of the shielding gate; a third oxide layer located between the epitaxial layer and the first dielectric layer and on a portion of the sidewall of the second trench away from the substrate; and a control gate located between the second oxide layer and the third oxide layer on the sidewall of the second trench, the first dielectric layer covering the surface of the control gate away from the substrate, the surface of the third oxide layer away from the epitaxial layer, and the surface of the second oxide layer away from the substrate.

[0006] Optionally, the depth of the second trench is greater than 3 μm, the thickness of the first oxide layer is greater than 4000 angstroms, and the thickness of the third oxide layer is 500 to 1000 angstroms.

[0007] Optionally, the distance from the surface of the second dielectric layer away from the substrate to the substrate is less than or equal to the distance from the surface of the second injection region near the substrate to the substrate.

[0008] Optionally, the width of the first groove is less than 0.16 μm, the distance between the two first grooves is 0.2 to 0.32 μm, the distance between the first contact hole and the first groove is greater than 0.06 μm, and the width of the first contact hole is less than 0.2 μm.

[0009] According to another aspect of this application, a method for fabricating the semiconductor structure described above is provided, comprising: providing a substrate, the substrate including a substrate, an epitaxial layer, a first implantation region, a second implantation region, a first initial dielectric layer, and a first contact hole, the epitaxial layer being located on one side surface of the substrate, the first implantation region and the second implantation region being stacked in the epitaxial layer in a direction away from the substrate, the surface of the second implantation region away from the substrate being a portion of the surface of the epitaxial layer, the epitaxial layer having two spaced third trenches, the two third trenches extending from the second implantation region into the first implantation region, the first initial dielectric layer being located in the two third trenches and on the surface of the epitaxial layer away from the substrate, the first contact hole being located in the first initial dielectric layer, the second implantation region, and the first implantation region and between the two third trenches, the first implantation region having a first doping type, and the epitaxial layer and the second implantation region having a second doping type; and performing ion implantation of the first doping type on the substrate. Then, the first initial dielectric layer on the sidewall of the first contact hole is removed, and the width of the first contact hole is enlarged to obtain a second contact hole. The orthogonal projections of the two sidewalls of the second contact hole in the epitaxial layer are respectively located between the two sidewalls of the two third trenches. The substrate with the second contact hole is subjected to ion implantation of the first doping type to form a third implantation region and a fourth implantation region located in the first implantation region. The fourth implantation region is located in the first implantation region and is located on the periphery of the third implantation region. Then, at least the first initial dielectric layer on the sidewall of the second contact hole is removed to obtain a third contact hole. The third contact hole exposes the second implantation region on the side of each third trench away from the second contact hole. The remaining first initial dielectric layer on the side of the epitaxial layer away from the substrate forms a first dielectric layer. The first initial dielectric layer in the third trench forms a second dielectric layer. A metal layer is formed in the third contact hole and on the surface of the first dielectric layer away from the epitaxial layer.

[0010] Optionally, removing at least the first initial dielectric layer on the sidewall of the second contact hole includes: etching the first initial dielectric layer using a wet etching method to remove the first initial dielectric layer on the sidewall of the second contact hole and a portion of the first initial dielectric layer in the third trench, such that the etched orthographic projection is located outside the two third trenches respectively, and such that a first distance is less than or equal to a second distance, the first distance being the distance from the surface of the etched first initial dielectric layer in the third trench away from the substrate to the substrate, and the second distance being the distance from the surface of the second injection region near the substrate to the substrate.

[0011] Optionally, a substrate is provided, comprising: providing a substrate and an initial epitaxial layer located on one side surface of the substrate, the initial epitaxial layer having a second trench, the depth of the second trench being greater than the depth of the third trench; forming a first oxide layer, a second oxide layer, a shielding gate, and a control gate in the second trench; and forming a third initial oxide layer on the surface of the initial epitaxial layer away from the substrate and on a portion of the sidewalls of the second trench away from the substrate, wherein the shielding gate is located in the second trench, the first oxide layer is located between the portion of the sidewalls of the second trench near the substrate and the shielding gate, and between the bottom surface of the second trench and the shielding gate, the second oxide layer is located on the surface of the shielding gate away from the substrate and on the exposed side surface of the shielding gate, and the control gate is located between the second oxide layer and the third initial oxide layer on the sidewalls of the second trench; and ion implanting is performed on the structure having the third initial oxide layer to form a first implantation region and a second implantation region in the initial epitaxial layer. The first implantation region and the second implantation region respectively contact the third initial oxide layer on the sidewall of the second trench; a portion of the initial epitaxial layer and a portion of the third initial oxide layer are removed to form two third trenches that penetrate the third initial oxide layer and the second implantation region and extend into the first implantation region. The two third trenches are located on one side of the second trench, and the remaining third initial oxide layer forms a third intermediate oxide layer; a second initial dielectric layer is formed in the two third trenches, on the surface of the third intermediate oxide layer away from the substrate, and on the surface of the control gate away from the substrate; a portion of the second initial dielectric layer, a portion of the third intermediate oxide layer, and a portion of the initial epitaxial layer are removed to form a first contact hole located in the second initial dielectric layer, the third intermediate oxide layer, the second implantation region, and the first implantation region. The remaining third intermediate oxide layer and the remaining second initial dielectric layer form the first initial dielectric layer, and the remaining initial epitaxial layer forms the epitaxial layer.

[0012] Optionally, forming a first oxide layer, a second oxide layer, a shielding gate, and a control gate in the second trench, and forming a third initial oxide layer on the surface of the initial epitaxial layer away from the substrate and on a portion of the sidewalls of the second trench away from the substrate, includes: forming a first initial oxide layer on the bottom surface and sidewalls of the second trench and on the surface of the initial epitaxial layer away from the substrate, and forming the shielding gate in the remaining second trench; removing a portion of the first initial oxide layer, such that the surface of the initial epitaxial layer away from the substrate and a portion of the sidewalls of the second trench are exposed, and the remaining first initial oxide layer forms the first oxide layer; forming a second oxide layer on the exposed surface of the shielding gate, and forming the third initial oxide layer on the exposed sidewalls of the second trench and on the surface of the initial epitaxial layer away from the substrate; and forming the control gate between the second oxide layer and the third initial oxide layer on the sidewalls of the second trench.

[0013] Optionally, removing a portion of the first initial oxide layer to expose the surface of the initial epitaxial layer away from the substrate and a portion of the sidewalls of the second trench includes: removing the first initial oxide layer using a wet etching method to expose the surface of the initial epitaxial layer away from the substrate, and exposing the sidewalls of the second trench to a depth greater than 0.8 μm.

[0014] Optionally, a substrate is provided, comprising: a substrate and an initial epitaxial layer located on one side surface of the substrate, the initial epitaxial layer having a second trench and two third trenches, the second trench having a greater depth than the third trenches, and the two third trenches located on one side of the second trenches; forming a first oxide layer, a second oxide layer, a shielding gate, and a control gate in the second trenches; and forming a third intermediate oxide layer on the surface of the initial epitaxial layer away from the substrate, on a portion of the sidewalls of the second trenches away from the substrate, and in the two third trenches, wherein the shielding gate is located in the second trenches, the first oxide layer is located between a portion of the sidewalls of the second trenches near the substrate and the shielding gate, and between the bottom surface of the second trench and the shielding gate, the second oxide layer is located on the surface of the shielding gate away from the substrate and on the exposed side surface of the shielding gate, and the control gate is located in the second oxide layer. Between the third intermediate oxide layer on the sidewall of the second trench and the structure in which the third intermediate oxide layer is formed; ion implantation is performed on the structure to form the first implantation region and the second implantation region in the initial epitaxial layer, the first implantation region and the second implantation region respectively contacting the third intermediate oxide layer on the sidewall of the second trench; a second initial dielectric layer is formed on the exposed surface of the second oxide layer, the exposed surface of the control gate and the surface of the third intermediate oxide layer away from the substrate; a portion of the second initial dielectric layer, a portion of the third intermediate oxide layer and a portion of the initial epitaxial layer are removed to form the first contact hole located in the second initial dielectric layer, the third intermediate oxide layer, the second implantation region and the first implantation region, the remaining third intermediate oxide layer and the remaining second initial dielectric layer form the first initial dielectric layer, and the remaining initial epitaxial layer forms the epitaxial layer.

[0015] Optionally, a first oxide layer, a second oxide layer, a shielding gate, and a control gate are formed in the second trench, and a third intermediate oxide layer is formed on the surface of the initial epitaxial layer away from the substrate, on a portion of the sidewalls of the second trench away from the substrate, and in the two third trenches. This includes: forming a first initial oxide layer on the bottom surface and sidewalls of the second trench, on the surface of the initial epitaxial layer away from the substrate, and in the two third trenches, and forming a shielding gate in the remaining second trenches; removing a portion of the first initial oxide layer, such that a portion of the surface of the initial epitaxial layer away from the substrate and a portion of the sidewalls of the second trench are exposed, leaving the remaining... The first initial oxide layer located in the second trench forms the first oxide layer, and the remaining first initial oxide layer located on the surface of the initial epitaxial layer on both sides of the third trench forms a pre-oxide layer; the second oxide layer is formed on the exposed surface of the shielding gate, and a third target oxide layer is formed on the exposed sidewall of the second trench and on the surface of the initial epitaxial layer away from the substrate, and the third target oxide layer and the pre-oxide layer are planarized to obtain the third intermediate oxide layer; the control gate is formed between the second oxide layer and the third intermediate oxide layer on the sidewall of the second trench.

[0016] By applying the technical solution of this application, first trenches are provided on both sides of the first contact hole, and the highly doped third implantation region is confined between the two first trenches, thus avoiding the impact of ion implantation on the threshold voltage and on-resistance of the device during the formation of the implantation region. Furthermore, this application forms a fourth implantation region and a third implantation region with sequentially increasing ion concentration in the first implantation region, which can effectively reduce the resistance of the region where the first implantation region is located and improve the avalanche resistance of the semiconductor structure. Therefore, the semiconductor structure of this application effectively improves the avalanche resistance of the device while reducing the impact on the threshold voltage and on-resistance of the device. Attached Figure Description

[0017] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0018] Figure 1 A schematic flowchart of a method for fabricating a semiconductor structure according to an embodiment of this application is shown;

[0019] Figures 2 to 16 A schematic diagram of the semiconductor structure fabrication method provided in the embodiments of this application after each process step is shown.

[0020] The above figures include the following reference numerals:

[0021] 10. Epitaxial layer; 11. First implantation region; 12. Second implantation region; 13. First initial dielectric layer; 14. First contact hole; 15. First trench; 16. Second contact hole; 17. Third implantation region; 18. Fourth implantation region; 19. Third contact hole; 20. Dielectric layer; 21. Metal layer; 22. Initial epitaxial layer; 23. Second trench; 24. First oxide layer; 25. Second oxide layer; 26. Shielding gate; 27. Control gate; 28. Third oxide layer; 29. ​​Second dielectric layer; 30. Third intermediate oxide layer; 31. Second initial dielectric layer; 32. First initial oxide layer; 34. Preparatory oxide layer; 35. Passivation layer; 36. Third trench; 37. Third initial oxide layer. Detailed Implementation

[0022] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0023] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0024] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0025] As described in the background section, existing technologies for improving the avalanche capability of semiconductor devices can affect the device's threshold voltage and on-resistance, thereby impacting device performance.

[0026] The inventors' analysis revealed that there are currently two main solutions for improving the avalanche capability of semiconductor devices, each with its own unavoidable drawbacks:

[0027] 1) Increasing the doping concentration of the low-doped well region below the contact hole reduces the resistance of the low-doped well region, thereby suppressing the conduction of parasitic transistors in the device. However, the doping concentration of the low-doped well region (i.e., the first implantation region) is often determined by the design, and the range of change is limited. If the change is too large, it can easily lead to the threshold voltage not meeting the standard, or even affect the device's withstand voltage and on-resistance.

[0028] 2) Adding an ion implantation at the contact hole reduces the resistance of the low-doped well region near the contact hole. However, if the contact hole size is small, the improvement in avalanche capability is not significant, while if the contact hole is too large, it can easily affect the doping of the channel region; at the same time, if the interlayer overlay misalignment is large, it will seriously affect the threshold voltage and on-resistance of the device.

[0029] To address the above-mentioned technical problems, embodiments of this application provide a semiconductor structure and a method for fabricating the same.

[0030] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0031] This application provides a semiconductor structure, such as Figure 11 As shown, the above semiconductor structure includes:

[0032] Substrate (not shown in the figure);

[0033] Epitaxial layer 10 is located on one side surface of the substrate;

[0034] The first implantation region 11 and the second implantation region 12 are stacked in the epitaxial layer 10 in a direction away from the substrate, and the surface of the second implantation region 12 away from the substrate is a part of the surface of the epitaxial layer 10.

[0035] The third implantation region 17 and the fourth implantation region 18 are located in the first implantation region 11, and the fourth implantation region 18 is located in the first implantation region 11 and on the periphery of the third implantation region 17. The ion concentration of the fourth implantation region 18 is greater than that of the first implantation region 11 and less than that of the third implantation region 17. The first implantation region 11, the third implantation region 17 and the fourth implantation region 18 have a first doping type, and the epitaxial layer 10 and the second implantation region 12 have a second doping type.

[0036] The first dielectric layer 20 is located on the side of the epitaxial layer 10 away from the substrate;

[0037] The first contact hole 14 and the two first trenches 15 both penetrate the first dielectric layer 20 and the second injection region 12. The first contact hole 14 contacts the third injection region 17. The two first trenches 15 respectively contact the third injection region 17 and the fourth injection region 18. The two first trenches 15 are located on both sides of the first contact hole 14. The two first trenches 15 are far away from the sidewall of the first contact hole 14, so that the surface of the second injection region 12 away from the substrate is exposed.

[0038] Specifically, the third injection zone 17 is located between the two first trenches 15.

[0039] The second dielectric layer 29 is located on the bottom surface of the two aforementioned first trenches 15;

[0040] The metal layer 21 is located on the surface of the first dielectric layer 20 away from the epitaxial layer 10 and on the surface of the second injection region 12 away from the substrate on both sides of the first trench 15. The metal layer 21 also fills the two first trenches 15 and the first contact hole 14.

[0041] Specifically, the metal layer 21 is in contact with the second dielectric layer 29 on the bottom surface of the first trench 15. The metal layer 21 continuously covers the sidewall of the second injection region 12, the portion of the second injection region 12 away from the substrate, and the sidewall of the first dielectric layer 20.

[0042] In the aforementioned semiconductor structure, a substrate, an epitaxial layer, a first dielectric layer, and a metal layer are stacked. A second implantation region is formed in the epitaxial layer, which is adjacent to the first dielectric layer. On the surface of the second implantation region in the epitaxial layer near the substrate, a first implantation region, a fourth implantation region, and a third implantation region are formed with sequentially increasing ion concentrations. A first contact hole penetrates the first dielectric layer and the second implantation region and contacts the third implantation region. Two first trenches are located on both sides of the first contact hole, penetrating the first dielectric layer and the second implantation region, and each trench contacts the third and fourth implantation regions, respectively. A second dielectric layer is located on the bottom surface of the two first trenches. The metal layer fills the first contact hole and the two first contact holes, and covers part of the surface of the second implantation region on both sides of the first contact hole. This application provides first trenches on both sides of the first contact hole, and the highly doped third implantation region is confined between the two first trenches, thus avoiding the impact of ion implantation on the threshold voltage and on-resistance of the device during the formation of the implantation region. Furthermore, this application forms a fourth implantation region and a third implantation region with sequentially increasing ion concentration in the first implantation region, which can effectively reduce the resistance of the region where the first implantation region is located and improve the avalanche resistance of the semiconductor structure. Therefore, the semiconductor structure of this application effectively improves the avalanche resistance of the device while reducing the impact on the threshold voltage and on-resistance of the device.

[0043] Specifically, in the above semiconductor structure, the first contact hole 14 and the two first trenches 15 on the bottom surface where the second dielectric layer 29 is formed are used to form the first implantation region 11, the fourth implantation region 18 and the third implantation region 17 with gradually varying ion concentrations in the epitaxial layer 10.

[0044] In one alternative, such as Figure 11 As shown, the above semiconductor structure also includes:

[0045] The second trench is located in the epitaxial layer 10. The depth of the second trench is greater than the depth of the first trench 15. The first trench 15 and the first contact hole 14 are located on one side of the second trench.

[0046] The shielding grid 26 is located in the aforementioned second trench;

[0047] The first oxide layer 24 is located between the second trench near the substrate and the shielding gate 26, and between the bottom surface of the second trench and the shielding gate.

[0048] The second oxide layer 25 is located on the surface of the shielding gate 26 away from the substrate and on a portion of the side surface of the shielding gate 26;

[0049] The third oxide layer 28 is located between the epitaxial layer 10 and the first dielectric layer 20 and on the sidewall of the second trench away from the substrate.

[0050] The control gate 27 is located between the second oxide layer 25 and the third oxide layer 28 on the sidewall of the second trench. The first dielectric layer 20 covers the surface of the control gate 27 away from the substrate, the surface of the third oxide layer 28 away from the epitaxial layer 10, and the surface of the second oxide layer 25 away from the substrate.

[0051] In the above embodiments, a trench shielding gate structure is formed on at least one side of the first contact hole and the two first trenches. This structure can reduce the on-resistance of the device and improve the device performance.

[0052] Specifically, the first oxide layer 24 serves as a ReSurF (ReSurF, Reduce Surface Field) oxide layer, the second oxide layer 25 serves as a shielding gate oxide layer, and the third oxide layer 28 serves as a gate oxide layer. The shielded gate MOSFET utilizes the ReSurF oxide layer and incorporates bulk trench polysilicon. Through oxide layer isolation, a lateral electric field is introduced via charge coupling to the epitaxial silicon, thereby reducing the surface electric field strength of the oxide layer.

[0053] In practical applications, there can be multiple trench shielding grid structures in the epitaxial layer 10.

[0054] In this application, such as Figure 11 As shown, the distance D1 from the surface of the second dielectric layer 29 away from the substrate to the substrate is less than or equal to the distance D2 from the surface of the second implantation region 12 near the substrate to the substrate. That is, the surface of the second dielectric layer 29 away from the substrate can be flush with the surface of the second implantation region 12 near the substrate. In this case, no breakdown current will flow out from the metal layer 21 on the second dielectric layer 29, further improving the device's avalanche resistance. Alternatively, the surface of the second dielectric layer 29 away from the substrate can be lower than the surface of the second implantation region 12 near the substrate. Although some breakdown current will flow out from the metal layer 21 on the second dielectric layer 29, the larger aperture size formed by the first contact hole 14 and the first trench 15 results in a shorter path for the breakdown current. Furthermore, the increasing ion concentrations in the first implantation region 11, the fourth implantation region 18, and the third implantation region 17 further reduce the on-resistance of the region where the first implantation region 11 is located. Therefore, the breakdown voltage is still relatively low in this case, and the device's avalanche resistance is still somewhat improved.

[0055] In some exemplary embodiments, the depth of the second trench is greater than 3 μm, the thickness of the first oxide layer is greater than 4000 angstroms, and the thickness of the third oxide layer is 500 to 1000 angstroms.

[0056] In some embodiments, the width of the first trench is less than 0.16 μm, the distance between two first trenches is 0.2–0.32 μm, the distance between the first contact hole and the first trench is greater than 0.06 μm, and the width of the first contact hole is less than 0.2 μm. By setting the width of the first trench to be small, the distance between the two first trenches to be large, and controlling the distance between the first contact hole and the first trench, sufficient space can be provided for the formation of the first contact hole, thus reducing the difficulty of forming the first contact hole.

[0057] like Figure 11 As shown, the semiconductor structure further includes a passivation layer 35 located on the surface of the metal layer 21 away from the first dielectric layer 20.

[0058] Specifically, the aforementioned structure in the semiconductor structure constitutes a cell. The semiconductor structure may include multiple cells, and the shape of the cell may be strip-shaped, square, circular, hexagonal, figure-eight shaped, or other polygonal shapes. When the cell is strip-shaped, both first trenches are strip-shaped, located on opposite sides of the first contact hole, and are not connected. When the cell is circular, the two first trenches are connected, forming a ring around the outer periphery of the first contact hole. When the cell is polygonal, the two first trenches are connected, forming a polygonal ring around the outer periphery of the first contact hole.

[0059] The semiconductor structure described above in this application can be a MOSFET structure, specifically a trench MOSFET structure, such as a shielded gate MOSFET structure.

[0060] The method for fabricating the semiconductor structure described in this application improves the avalanche resistance of trench gate MOSFETs. Taking shielded gate MOSFETs as an example, a double trench isolation contact hole method is adopted. By fixing the P+ injection region, limiting the breakdown current to low resistance, and performing two P+ injections, the resistance of the P- injection region is effectively reduced while maintaining the electrical stability of the device, thereby improving the avalanche resistance of the device. At the same time, the on-resistance of the device can also be reduced to a certain extent.

[0061] Embodiments of this application also provide a method for fabricating the above-described semiconductor structure.

[0062] Figure 1 This is a flowchart of a method for fabricating a semiconductor structure according to an embodiment of this application. Figures 2 to 11 The illustration shows a schematic diagram of the structure obtained after each process step in a method for fabricating a semiconductor structure according to this application. Figures 12 to 16 as well as Figures 8 to 11 An exemplary schematic diagram of the structure obtained after each process step of another semiconductor structure fabrication method according to this application is shown. Figures 1 to 16 As shown, the method includes the following steps:

[0063] Step S201: Provide a substrate, such as Figure 8As shown, the substrate includes a substrate (not shown), an epitaxial layer 10, a first implantation region 11, a second implantation region 12, a first initial dielectric layer 13, and a first contact hole 14. The epitaxial layer 10 is located on one side surface of the substrate. The first implantation region 11 and the second implantation region 12 are stacked in the epitaxial layer 10 in a direction away from the substrate. The surface of the second implantation region 12 away from the substrate is part of the surface of the epitaxial layer 10. The epitaxial layer 10 has two spaced third trenches 36. The two third trenches 36 extend from the second implantation region into the first implantation region. The first initial dielectric layer 13 is located in the two third trenches 36 and on the surface of the epitaxial layer 10 away from the substrate. The first contact hole 14 is located in the first initial dielectric layer 13, the second implantation region 12, and the first implantation region 11 and is located between the two third trenches 36. The first implantation region 11 has a first doping type, and the epitaxial layer 10 and the second implantation region 12 have a second doping type.

[0064] Step S202: As Figure 8 and Figure 9 As shown, the substrate is subjected to ion implantation of the first doping type, and then the first initial dielectric layer 13 on the sidewall of the first contact hole 14 is removed to enlarge the width of the first contact hole 14 to obtain the second contact hole 16. The orthographic projection of the two sidewalls of the second contact hole 16 in the epitaxial layer 10 is located between the two sidewalls of the two third trenches 36, respectively.

[0065] Specifically, the width of the first contact hole 14 is the width of the first contact hole 14 in a first direction, which is perpendicular to the stacking direction of the substrate and the epitaxial layer 10. Due to the obstruction of the first initial dielectric layer 13, the ion implantation process only implants ions in the first implantation region 11 below the first contact hole 14. Taking the two third trenches 36 located on the left and right sides of the first contact hole 14 as an example, the orthographic projection corresponding to the left side wall of the second contact hole 16 is located between the two side walls of the third trench 36 on the left side of the second contact hole 16, and the orthographic projection corresponding to the right side wall of the second contact hole 16 is located between the two side walls of the third trench 36 on the right side of the second contact hole 16. That is, the width of the second contact hole 16 is less than the maximum spacing between the side walls of the two third trenches 36 and greater than the minimum spacing between the side walls of the two third trenches 36.

[0066] Step S203: As Figure 9As shown, ion implantation of the substrate having the second contact hole 16 is performed on the substrate to form a first doping type, thereby forming a third implantation region 17 and a fourth implantation region 18 located in the first implantation region 11. The fourth implantation region 18 is located in the first implantation region 11 and is located on the outer periphery of the third implantation region 17. Figure 10 As shown, at least the first initial dielectric layer 13 on the sidewall of the second contact hole 16 is removed to obtain the third contact hole 19. The third contact hole 19 exposes the second injection region 12 on the side of each third trench 36 away from the second contact hole 16. The remaining first initial dielectric layer 13 on the side of the epitaxial layer 10 away from the substrate forms the first dielectric layer 20, and the first initial dielectric layer 13 in the third trench 36 forms the second dielectric layer 29, and as shown... Figure 11 As shown, a metal layer 21 is formed in the third contact hole 19 and on the surface of the first dielectric layer 20 away from the epitaxial layer 10.

[0067] Specifically, since the width of the second contact hole 16 is greater than that of the first contact hole 14, ion implantation of the substrate through the second contact hole 16 not only yields a third implantation region 17 with a high ion concentration, but also forms a fourth implantation region 18 around the third implantation region 17. The fourth implantation region 18 surrounds the third implantation region 17, and its ion concentration is lower than that of the third implantation region 17 but higher than that of the first implantation region 11. The two third trenches 36 are located in the orthographic projection of the third contact hole 19 into the epitaxial layer 10, meaning that the width of the third contact hole 19 is greater than the maximum sidewall spacing between the two third trenches 36. The third contact hole 19 includes the first contact hole 14 and a first trench 15 located on both sides of the first contact hole 14 and penetrating the first dielectric layer 20, the second injection region 12 to the third injection region 17 and the fourth injection region 18. That is, the width of the first trench 15 is the same as that of the third trench 36, and the depth of the first trench 15 is greater than the depth of the third trench 36. The remaining first initial dielectric layer 13 located between the epitaxial layer 10 and the first dielectric layer 20 forms the third oxide layer 28.

[0068] In the above embodiments, a substrate is first provided, in which a substrate, an epitaxial layer, and a first initial dielectric layer are stacked sequentially. A first implantation region and a second implantation region are located in the epitaxial layer in a direction away from the substrate. Two spaced third trenches extend from the second implantation region into the first implantation region. The first initial dielectric layer fills the third trenches. A first contact hole is located between the two third trenches and extends from the first initial dielectric layer, through the second implantation region, into the first implantation region. Then, ion implantation is performed on the substrate, followed by the removal of a portion of the first initial dielectric layer to increase the size of the first contact hole, resulting in a second contact hole. Then, ion implantation is performed on the substrate with the second contact hole to form a third implantation region and a fourth implantation region surrounding the third implantation region. Finally, at least a portion of the first initial dielectric layer is removed to increase the size of the second contact hole, so that the second implantation region on the side of the two third trenches away from the second contact hole is partially exposed, resulting in a third contact hole. A metal layer is formed on the exposed surfaces of the third contact hole and the substrate. This application first sets up third trenches on both sides of the first contact hole before performing ion implantation. This confines the highly doped ion implantation region between the two third trenches, avoiding the impact of ion implantation on the threshold voltage and on-resistance of the device. Furthermore, through two ion implantations before and after hole expansion, a fourth implantation region and a third implantation region with successively increasing ion concentration are formed in the first implantation region. This effectively reduces the resistance of the region where the first implantation region is located and improves the avalanche resistance of the semiconductor structure. Therefore, this application effectively improves the avalanche resistance of the device while reducing the impact on the threshold voltage and on-resistance of the device.

[0069] In the above-described scheme of this application, by enlarging the second contact hole, the size and area of ​​the final third contact hole in the second injection region are increased, which reduces the on-resistance of the second injection region to a certain extent.

[0070] In one alternative, at least the first initial dielectric layer on the sidewall of the second contact hole is removed, including: as follows Figure 9 and Figure 10 As shown, the first initial dielectric layer 13 is etched using a wet etching method to remove the first initial dielectric layer 13 on the sidewall of the second contact hole 16 and a portion of the first initial dielectric layer 13 in the third trench, such that the etched orthographic projections are located outside the two third trenches 36, and the first distance D1 is less than or equal to the second distance D2. The first distance D1 is the distance from the surface of the etched first initial dielectric layer 13 (i.e., the second dielectric layer 29) in the third trench away from the substrate to the substrate, and the second distance D2 is the distance from the surface of the second injection region 12 near the substrate to the substrate.

[0071] In the above embodiments, during the process of enlarging the size of the second contact hole, a portion of the first initial dielectric layer in the third trench is removed, making the upper surface of the second dielectric layer flush with the lower surface of the second implantation region, or making the upper surface of the second dielectric layer lower than the lower surface of the second implantation region. When the upper surface of the second dielectric layer is flush with the lower surface of the second implantation region, no breakdown current flows out from the metal layer on the second dielectric layer, which can further improve the device's avalanche resistance. When the upper surface of the second dielectric layer is lower than the lower surface of the second implantation region, although some breakdown current will flow out from the metal layer on the second dielectric layer, the path of the breakdown current is shortened compared to before the hole enlargement because the size of the second contact hole is enlarged. At the same time, the ion implantation before the second contact hole enlargement further reduces the on-resistance of the region where the first implantation region is located. Therefore, the breakdown voltage is still relatively low in this case, and the device's avalanche resistance is still improved to a certain extent. In addition, by enlarging the size of the second contact hole, the second implantation regions on both sides of the second contact hole are exposed, further increasing the contact area between the metal layer and the second implantation region, thereby further reducing the device's on-resistance.

[0072] In some exemplary embodiments, such as Figures 2 to 8 As shown, a substrate is provided, including: Figure 2As shown, a substrate and an initial epitaxial layer 22 located on one side surface of the substrate are provided. The initial epitaxial layer 22 has a second trench 23, the depth of which is greater than the depth of the third trench. A first oxide layer 24, a second oxide layer 25, a shielding gate 26, and a control gate 27 are formed in the second trench 23. A third initial oxide layer 37 is formed on the surface of the initial epitaxial layer 22 away from the substrate and on the sidewalls of the second trench 23 away from the substrate. The shielding gate 26 is located in the second trench 23, and the first oxide layer 24 is located in the third trench 25. Between the second trench 23 and the shielding gate 26 near the substrate sidewall, and between the bottom surface of the second trench 23 and the shielding gate 26, the second oxide layer 25 is located on the surface of the shielding gate 26 away from the substrate and on the exposed side of the shielding gate 26. The control gate is located between the second oxide layer 25 and the third initial oxide layer 37 on the sidewall of the second trench 23. Ion implantation is performed on the structure in which the third initial oxide layer 37 is formed to form the first implantation region 11 and the second implantation region 12 in the initial epitaxial layer 22. 1. The second implantation region 12 and the second implantation region 12 respectively contact the third initial oxide layer 37 on the sidewall of the second trench 23; a portion of the initial epitaxial layer 22 and a portion of the third initial oxide layer 37 are removed to form two third trenches 36 that penetrate the third initial oxide layer 37 and the second implantation region 12 and extend into the first implantation region 11. The two third trenches 36 are located on one side of the second trench 23, and the remaining third initial oxide layer 37 forms a third intermediate oxide layer 30; in the two third trenches 36, the third intermediate oxide layer 30 is located away from the surface of the substrate. A second initial dielectric layer 31 is formed on the surface of the control gate 27 away from the substrate; a portion of the second initial dielectric layer 31, a portion of the third intermediate oxide layer 30, and a portion of the initial epitaxial layer 22 are removed to form the first contact hole 14 located in the second initial dielectric layer 31, the third intermediate oxide layer 30, the second implantation region 12, and the first implantation region 11; the remaining third intermediate oxide layer 30 and the remaining second initial dielectric layer 31 form the first initial dielectric layer 13; and the remaining initial epitaxial layer 22 forms the epitaxial layer 10.

[0073] In the above embodiment, a trench shielding gate structure is first formed in the epitaxial layer, followed by ion implantation to obtain a first implantation region and a second implantation region. Then, two third trenches are formed on one side of the shielding gate structure. Finally, the contact hole is etched and positioned using the two third trenches, thereby forming a first contact hole between the two third trenches. The two shallow third trenches on both sides of the first contact hole can limit the breakdown current to the low-resistance region at the bottom of the two third trenches, further improving the device's avalanche resistance. Furthermore, the two third trenches provide a window for increasing the implantation dose in the regions where the third and fourth implantation regions are located, which can further reduce the resistance in the region where the first implantation region is located, further improving the device's avalanche resistance. At the same time, since the implantation regions obtained through the first and second contact holes are confined between the two third trenches, the second dielectric layer in the aforementioned third trenches can prevent excessively high ion implantation concentrations, further avoiding the impact of registration deviations or excessively concentrated ion implantation on the device's threshold voltage and on-resistance.

[0074] In addition, the etching and ion implantation processes in the above embodiments have a large process window and are relatively easy to perform.

[0075] It should be noted that the two aforementioned third trenches also serve as auxiliary structures for the ion implantation process after the formation of the second contact hole. Controlling the depth of the two third trenches controls the depth of the ion implantation process after the formation of the second contact hole. Simultaneously, the second dielectric layer within the third trenches prevents excessively high ion implantation concentrations during the ion implantation process. This ion implantation process also results in a larger implantation area in the third implantation region, further reducing the on-resistance of the first implantation region and ensuring stronger avalanche resistance of the device. The two third trenches contain a second dielectric layer of a certain thickness; therefore, even with high-dose ion implantation, only a small portion of ions will be implanted into the first implantation region at the bottom of the third trench. This further reduces the resistance of the first implantation region, improving the device's avalanche resistance, and also prevents high-dose ion implantation from affecting channel doping and thus the device's threshold voltage and on-resistance.

[0076] Specifically, the first oxide layer is a ReSurF oxide layer, the second oxide layer is a shielding gate oxide layer, and the third oxide layer is a gate oxide layer. The shielded gate MOSFET utilizes the ReSurF oxide layer and incorporates bulk trench polysilicon. Through oxide layer isolation, a lateral electric field is introduced via charge coupling to the epitaxial silicon, thereby reducing the surface electric field strength of the oxide layer.

[0077] Furthermore, such as Figures 2 to 5As shown, a first oxide layer, a second oxide layer, a shielding gate, and a control gate are formed in the second trench, and a third initial oxide layer is formed on the surface of the initial epitaxial layer away from the substrate and on the sidewalls of the second trench away from the substrate. This includes forming a first initial oxide layer 32 on the bottom surface and sidewalls of the second trench 23 and on the surface of the initial epitaxial layer 22 away from the substrate, and forming the shielding gate 26 in the remaining portion of the second trench 23; as... Figure 3 and Figure 4 As shown, a portion of the first initial oxide layer 32 is removed, exposing the surface of the initial epitaxial layer 22 away from the substrate and a portion of the sidewalls of the second trench 23. The remaining first initial oxide layer 32 forms the first oxide layer 24. The second oxide layer 25 is formed on the exposed surface of the shielding gate 26, and the third initial oxide layer 37 is formed on the exposed sidewalls of the second trench 23 and the surface of the initial epitaxial layer 22 away from the substrate. The control gate 27 is formed between the second oxide layer 25 and the third initial oxide layer 37 on the sidewalls of the second trench 23. Through the above embodiment, forming a trench shielding gate structure in the epitaxial layer can reduce the on-resistance of the device and improve device performance.

[0078] In some embodiments, such as Figure 11 As shown, there can be multiple trench shielding grid structures in the epitaxial layer.

[0079] For example, removing a portion of the first initial oxide layer, exposing the surface of the initial epitaxial layer away from the substrate and a portion of the sidewalls of the second trench, includes: removing the first initial oxide layer using a wet etching method, exposing the surface of the initial epitaxial layer away from the substrate, and exposing the sidewalls of the second trench to a depth greater than 0.8 μm. This ensures that the exposure depth of the shielding gate is greater than 0.8 μm, providing sufficient space for the subsequent growth of the second oxide layer.

[0080] Optionally, removing a portion of the first initial oxide layer to expose the surface of the initial epitaxial layer away from the substrate and a portion of the sidewalls of the second trench includes: removing the first initial oxide layer using a wet etching method to expose the surface of the initial epitaxial layer away from the substrate, and exposing the sidewalls of the second trench to a depth greater than 0.8 μm.

[0081] In this application, the material of the epitaxial layer is silicon. The first initial oxide layer can be formed on the bottom surface, sidewalls, and surface of the initial epitaxial layer away from the substrate of the second trench by thermal oxidation. The thickness of the first initial oxide layer can be greater than 4000 angstroms. The materials of the shielding gate and the control gate can be polysilicon, respectively. The process of forming the shielding gate in the remaining second trench can be as follows: first, deposit polysilicon material on the exposed surface of the first initial oxide layer to fill the remaining second trench; then, etch the polysilicon material back to the designed depth, generally until it is flush with the surface of the initial epitaxial layer, to obtain the shielding gate. The second oxide layer and the third initial oxide layer can be formed by thermal oxidation. The thickness of the third initial oxide layer is generally 500-1000 angstroms. Then, deposit polysilicon material on the exposed surface of the third initial oxide layer and the exposed surface of the second oxide layer; then, etch the polysilicon material back until it is flush with the surface of the initial epitaxial layer, to obtain the control gate.

[0082] Part of the initial epitaxial layer and part of the third initial oxide layer are removed to form two third trenches that penetrate the third initial oxide layer and the second implantation region and extend into the first implantation region. Specifically, this includes photolithographic etching of two third trenches with the mask forming the second trench. The size of the third trenches should be as small as possible, preferably less than 0.16 μm, to leave enough space for subsequent etching of the first contact hole and reduce the difficulty of subsequent alignment of the first contact hole. The spacing between the two third trenches can be selected from 0.2 μm to 0.32 μm.

[0083] The thickness of the second initial dielectric layer is generally greater than 0.8 μm. Therefore, during the formation of the second initial dielectric layer, the two third trenches mentioned above will be filled. After the dielectric layer reflow treatment, the surface step difference of the second initial dielectric layer away from the epitaxial layer will become lower and tend to be flat.

[0084] The aforementioned first contact hole can be obtained through photolithography etching. The distance between the opening of the first contact hole and the two third trenches (hereinafter referred to as trench A and trench B) on the epitaxial layer surface is preferably greater than 0.06 μm. The size of the first contact hole is preferably less than 0.2 μm. Even if the first contact hole is offset into trench A or trench B, the subsequent third implantation region will be fixed between trench A and trench B, without affecting the doping concentration of the channel region, further reducing the influence of ions on the device's threshold voltage and other electrical properties. By restricting the area of ​​the third implantation region, the first implantation region can increase the ion implantation dose to a certain extent without considering the influence of ion implantation, thereby reducing the resistance of the region where the first implantation region is located, further suppressing the conduction of parasitic transistors, and improving the device's avalanche resistance.

[0085] In other exemplary embodiments, such asFigures 12 to 16 as well as Figure 8 As shown, a substrate is provided, including: Figure 12 As shown, a substrate and an initial epitaxial layer 22 located on one side surface of the substrate are provided. The initial epitaxial layer 22 has a second trench 23 and two third trenches 36. The depth of the second trench 23 is greater than the depth of the third trenches 36, and the two third trenches 36 are located on one side of the second trench 23. A first oxide layer 24, a second oxide layer 25, a shielding gate 26, and a control gate 27 are formed in the second trench 23. A third intermediate oxide layer 30 is formed on the surface of the initial epitaxial layer 22 away from the substrate, on the sidewalls of the second trench 23 away from the substrate, and in the two third trenches 36, resulting in the following: Figure 15 The structure shown includes a shielding gate 26 located in the second trench 23; a first oxide layer 24 located between the sidewall of the second trench 23 near the substrate and the shielding gate 26, and between the bottom surface of the second trench 23 and the shielding gate 26; a second oxide layer 25 located on the surface of the shielding gate 26 away from the substrate and on the exposed side of the shielding gate 26; and a control gate 27 located between the second oxide layer 25 and the third intermediate oxide layer 30 on the sidewall of the second trench 23. Ion implantation is performed on the structure in which the third intermediate oxide layer 30 is formed to form the first implantation region 11 and the second implantation region 12 in the initial epitaxial layer 22. The first implantation region 11 and the second implantation region 12 are respectively connected to the upper... The third intermediate oxide layer 30 on the sidewall of the second trench 23 contacts the second intermediate oxide layer 25; a second initial dielectric layer 31 is formed on the exposed surface of the second oxide layer 25, the exposed surface of the control gate 27, and the surface of the third intermediate oxide layer 30 away from the substrate; a portion of the second initial dielectric layer 31, a portion of the third intermediate oxide layer 30, and a portion of the initial epitaxial layer 22 are removed to form the first contact hole 14 located in the second initial dielectric layer 31, the third intermediate oxide layer 30, the second implantation region 12, and the first implantation region 11; the remaining third intermediate oxide layer 30 and the remaining second initial dielectric layer 31 form the first initial dielectric layer 13; the remaining initial epitaxial layer 22 forms the epitaxial layer 10, resulting in the following... Figure 8 The structure shown.

[0086] In the above embodiment, two third trenches are first formed in the initial epitaxial layer, followed by the formation of a trench shielding gate structure. Ion implantation is then performed to obtain a first implantation region and a second implantation region. Finally, the first contact hole is etched and positioned using the two third trenches, thereby forming a first contact hole between the two third trenches. The two shallower third trenches on both sides of the first contact hole can limit the breakdown current to the low-resistivity region at the bottom of the two third trenches, further improving the device's avalanche resistance. Furthermore, the two third trenches provide a window for increasing the implantation dose in the regions where the third and fourth implantation regions are located, which can further reduce the resistance in the region where the first implantation region is located, further improving the device's avalanche resistance. At the same time, since the implantation regions obtained through the first and second contact holes are confined between the two third trenches, the second dielectric layer within the third trenches can prevent excessively high ion implantation concentrations, further avoiding the impact of registration errors or excessively concentrated ion implantation on the device's threshold voltage and on-resistance.

[0087] In addition, the above embodiments have lower difficulty in photolithographic alignment and lower process cost.

[0088] In the application of the substrate, the initial epitaxial layer located on one side surface of the substrate can be obtained by dry etching. During the dry etching process, since the etching depth of the third trench is less than that of the second trench, the mask of the third trench can be omitted based on this characteristic, thus avoiding the alignment problem between the third trench and the second trench. However, the specific depth of the third trench will vary with the fluctuation of the photolithography size, and experiments are needed to select the optimal conditions.

[0089] Specifically, the first oxide layer is a ReSurF oxide layer, the second oxide layer is a shielding gate oxide layer, and the third oxide layer is a gate oxide layer. The shielded gate MOSFET utilizes the ReSurF oxide layer and incorporates bulk trench polysilicon. Through oxide layer isolation, a lateral electric field is introduced via charge coupling to the epitaxial silicon, thereby reducing the surface electric field strength of the oxide layer.

[0090] Further, a first oxide layer, a second oxide layer, a shielding gate, and a control gate are formed in the second trench, and a third intermediate oxide layer is formed on the surface of the initial epitaxial layer away from the substrate, on the partial sidewalls of the second trench away from the substrate, and in the two third trenches, including: Figure 12 and Figure 13As shown, a first initial oxide layer 32 is formed on the bottom surface and sidewalls of the second trench 23, the surface of the initial epitaxial layer 22 away from the substrate, and in the two third trenches 36, and a shielding gate 26 is formed in the remaining second trenches 23; a portion of the first initial oxide layer 32 is removed, exposing the portion of the surface of the initial epitaxial layer 22 away from the substrate and the portion of the sidewalls of the second trenches 23, and the remaining first initial oxide layer 32 in the second trenches 23 forms the first oxide layer 24, and the remaining first initial oxide layer 32 in the third trenches 36 and the third trenches 36 form the first oxide layer 24. A preliminary oxide layer 34 is formed on the surface of the initial epitaxial layer 22 on both sides of the first initial oxide layer 32; a second oxide layer 25 is formed on the exposed surface of the shielding gate 26; and a third target oxide layer is formed on the exposed sidewall of the second trench 23 and on the surface of the initial epitaxial layer 22 away from the substrate. The third target oxide layer and the preliminary oxide layer 34 are planarized to obtain the third intermediate oxide layer 30. A control gate 27 is formed between the second oxide layer 25 and the third intermediate oxide layer 30 on the sidewall of the second trench 23, resulting in... Figure 15 The structure shown is illustrated. Through the above embodiments, forming a trench shielding gate structure in the epitaxial layer can reduce the on-resistance of the device and improve its performance.

[0091] In some embodiments, there may be multiple trench shielding gate structures in the epitaxial layer.

[0092] For example, removing a portion of the first initial oxide layer, exposing the surface of the initial epitaxial layer away from the substrate and a portion of the sidewalls of the second trench, includes: removing the first initial oxide layer using a wet etching method, exposing the surface of the initial epitaxial layer away from the substrate, and exposing the sidewalls of the second trench to a depth greater than 0.8 μm. This ensures that the exposure depth of the shielding gate is greater than 0.8 μm, providing sufficient space for the subsequent growth of the second oxide layer. Furthermore, photolithography using a mask can prevent the removal of the first initial oxide layer in the third trench, which could affect the implantation depth of subsequent ion implantation through the contact holes and cause electrical failure of the device.

[0093] Specifically, a photoresist layer can be coated and photolithography performed on the first initial oxide layer 32 located in the third trench 36 and on both sides of the third trench 36, so that the surface of the initial epitaxial layer 22 away from the substrate is exposed, and the sidewall exposure depth of the second trench is greater than 0.8 μm.

[0094] In this application, the material of the epitaxial layer is silicon. The first initial oxide layer can be formed on the bottom surface, sidewalls, surface of the initial epitaxial layer away from the substrate, and in the third trench via thermal oxidation. The thickness of the first initial oxide layer can be greater than 4000 angstroms. The materials of the shielding gate and the control gate can be polysilicon, respectively. The process of forming the shielding gate in the remaining second trench can be as follows: first, deposit polysilicon material on the exposed surface of the first initial oxide layer to fill the remaining second trench; then, etch the polysilicon material back to the designed depth, generally until it is flush with the surface of the initial epitaxial layer, to obtain the shielding gate. The second oxide layer and the third target oxide layer can be formed by thermal oxidation. The thickness of the third intermediate oxide layer obtained after chemical mechanical polishing is generally 500-1000 angstroms. Then, deposit polysilicon material on the exposed surface of the third intermediate oxide layer and the exposed surface of the second oxide layer, and then etch the polysilicon material back to the surface of the initial epitaxial layer, to obtain the control gate.

[0095] In the above embodiments, if a mask is omitted during the formation of the third trench, and the chemical mechanical polishing step is omitted, then there is only a thin oxide layer in the third trench before the formation of the first and second injection regions. The thickness of the remaining oxide layer in the third trench is approximately equal to the thickness of the third intermediate oxide layer, which is 500 to 1000 angstroms. In this case, an oxide material is deposited first to fill the third trench, and then chemical mechanical polishing or wet etching is performed to the designed thickness before the first and second injection regions are formed. This avoids the thin oxide layer in the third trench affecting the injection depth of the first and second injection regions. Then, a second initial dielectric layer is deposited.

[0096] The aforementioned first contact hole can be obtained through photolithography etching. The distance between the opening of the first contact hole and the two third trenches (hereinafter referred to as trench A and trench B) on the epitaxial layer surface is preferably greater than 0.06 μm. The size of the first contact hole is preferably less than 0.2 μm. Even if the first contact hole is offset into trench A or trench B, the subsequent third implantation region will be fixed between trench A and trench B, without affecting the doping concentration of the channel region, further reducing the influence of ions on the device's threshold voltage and other electrical properties. By restricting the area of ​​the third implantation region, the first implantation region can increase the ion implantation dose to a certain extent without considering the influence of ion implantation, thereby reducing the resistance of the region where the first well region is located, further suppressing the conduction of parasitic transistors, and improving the device's avalanche resistance.

[0097] In step S202 above, ion implantation is performed first, followed by etching a portion of the first initial dielectric layer to enlarge the size of the first contact hole. Simultaneously, it is ensured that the sidewall of the second contact hole does not extend beyond the sidewall of trench A and trench B near the second trench, the purpose being to prevent ion implantation from affecting the second implantation region. Next, ion implantation is performed in step S203 above. Since trench A and trench B contain a certain thickness of the first initial dielectric layer, some ions are still implanted into the first implantation region below trench A and trench B. Although the dose is small, it still helps to reduce the resistance of the area where the first implantation region is located. Next, the first initial dielectric layer is etched using wet etching. Due to the isotropic nature of wet etching, the size of the second contact hole increases. At the same time, the first initial dielectric layer in trench A and trench B is also etched. By controlling the first initial dielectric layer in trench A and trench B to prevent complete etching, the upper surface of the second dielectric layer is not higher than the lower surface of the second injection area, and preferably flush. This ensures that the area through which the conduction current passes in the second injection area is not reduced. Meanwhile, because the size of the contact hole in the second injection area increases and there is also metal contact on the upper surface of the second injection area, the path distance of the conduction current flowing through the second injection area is shortened, which reduces the on-resistance to a certain extent.

[0098] Optionally, the width of the third groove is less than 0.16 μm, the distance between the two third grooves is 0.2 to 0.32 μm, the distance between the first contact hole and the third groove is greater than 0.06 μm, and the width of the first contact hole is less than 0.2 μm.

[0099] Optionally, the depth of the second trench is greater than 3 μm, the thickness of the first oxide layer is greater than 4000 angstroms, and the thickness of the third oxide layer is 500 to 1000 angstroms.

[0100] In some optional embodiments of this application, such as Figure 11 As shown, after forming a metal layer in the third contact hole and on the surface of the dielectric layer away from the epitaxial layer, the method further includes forming a passivation layer 35 on the surface of the metal layer 21 away from the dielectric layer 20.

[0101] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0102] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a substrate; an epitaxial layer on one side surface of the substrate; a first implantation region and a second implantation region stacked in the epitaxial layer away from the substrate, the second implantation region being part of the surface of the epitaxial layer away from the substrate; a third implantation region in the first implantation region and a fourth implantation region in the first implantation region and outside the third implantation region, the fourth implantation region having an ion concentration greater than that of the first implantation region and less than that of the third implantation region, the first, third and fourth implantation regions having a first doping type, and the epitaxial layer and the second implantation region having a second doping type; a first dielectric layer on the side of the epitaxial layer away from the substrate; a first contact hole and two first trenches, all penetrating the first dielectric layer and the second implantation region, the first contact hole contacting the third implantation region, the two first trenches each contacting the third implantation region and the fourth implantation region, the two first trenches being on both sides of the first contact hole, and the two first trenches being away from the side walls of the first contact hole so that part of the surface of the second implantation region away from the substrate is exposed; a second dielectric layer on the bottom surface of the two first trenches; a metal layer on the surface of the first dielectric layer away from the epitaxial layer and on part of the surface of the second implantation region away from the substrate on both sides of the first trenches, the metal layer also filling the two first trenches and the first contact hole.

2. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises: a second trench in the epitaxial layer, the second trench having a greater depth than the first trenches, the first trenches and the first contact hole being on one side of the second trench; a shield gate in the second trench; a first oxide layer between part of the side wall of the second trench close to the substrate and the shield gate and between the bottom surface of the second trench and the shield gate; a second oxide layer on the surface of the shield gate away from the substrate and on part of the side surface of the shield gate; a third oxide layer between the epitaxial layer and the first dielectric layer and on part of the side wall of the second trench away from the substrate; a control gate between the second oxide layer and the third oxide layer on the side wall of the second trench, the first dielectric layer covering the surface of the control gate away from the substrate, the surface of the third oxide layer away from the epitaxial layer, and the surface of the second oxide layer away from the substrate.

3. The semiconductor structure of claim 2, wherein, The depth of the second trench is greater than 3 μm, the thickness of the first oxide layer is greater than 4000 angstroms, and the thickness of the third oxide layer is 500-1000 angstroms.

4. The semiconductor structure of claim 1, wherein, The distance from the surface of the second dielectric layer away from the substrate to the substrate is less than or equal to the distance from the surface of the second implantation region close to the substrate to the substrate.

5. The semiconductor structure of any one of claims 1 to 4, wherein, The width of the first trench is less than 0.16 μm, the distance between the two first trenches is 0.2-0.32 μm, the distance between the first contact hole and the first trench is greater than 0.06 μm, and the width of the first contact hole is less than 0.2 μm.

6. A method of producing the semiconductor structure according to any one of claims 1 to 5, characterized in that Comprise: A substrate is provided, which comprises a substrate, an epitaxial layer on one side surface of the substrate, a first implantation region and a second implantation region stacked in the epitaxial layer in a direction away from the substrate, a part of the surface of the epitaxial layer away from the substrate being the second implantation region, the epitaxial layer having two third trenches spaced apart, the two third trenches extending from the second implantation region into the first implantation region, a first initial dielectric layer being located in the two third trenches and on the surface of the epitaxial layer away from the substrate, and a first contact hole being located in the first initial dielectric layer, the second implantation region and the first implantation region and between the two third trenches, the first implantation region having a first doping type, and the epitaxial layer and the second implantation region having a second doping type; The substrate is subjected to ion implantation of the first doping type, and the first initial dielectric layer on the sidewall of the first contact hole is removed to enlarge the width of the first contact hole to obtain a second contact hole, the orthogonal projection of the two sidewalls of the second contact hole in the epitaxial layer being located between the two sidewalls of the two third trenches, respectively; The substrate formed with the second contact hole is subjected to ion implantation of the first doping type to form a third implantation region and a fourth implantation region in the first implantation region, the fourth implantation region being located in the first implantation region and outside the third implantation region, and the first initial dielectric layer on the sidewall of the second contact hole is removed to obtain a third contact hole, the third contact hole allowing a part of the second implantation region away from one side of the second contact hole to be exposed, the remaining first initial dielectric layer on the surface of the epitaxial layer away from the substrate forming a first dielectric layer, the first initial dielectric layer in the third trench forming a second dielectric layer, and a metal layer being formed in the third contact hole and on the surface of the first dielectric layer away from the epitaxial layer.

7. The method of claim 6, wherein, The first initial dielectric layer on the sidewall of the second contact hole is removed, comprising: The first initial dielectric layer is etched by a wet etching method to remove the first initial dielectric layer on the sidewall of the second contact hole and a part of the first initial dielectric layer in the third trench, so that the orthogonal projection after etching is located outside the two third trenches, respectively, and so that the first distance is less than or equal to the second distance, the first distance being the distance from the surface of the epitaxial layer away from the substrate to the substrate in the third trench after etching, and the second distance being the distance from the surface of the second implantation region close to the substrate to the substrate.

8. The method of claim 6, wherein, A substrate is provided, comprising: A substrate and an initial epitaxial layer on a side surface of the substrate are provided, the initial epitaxial layer having a second trench, a groove depth of the second trench being greater than a groove depth of the third trench; A first oxide layer, a second oxide layer, a shield gate and a control gate are formed in the second trench, and a third initial oxide layer is formed on a surface of the initial epitaxial layer away from the substrate and on a part of a sidewall of the second trench away from the substrate, wherein the shield gate is located in the second trench, the first oxide layer is located between a part of the sidewall of the second trench close to the substrate and the shield gate and between a bottom surface of the second trench and the shield gate, the second oxide layer is located on a surface of the shield gate away from the substrate and on an exposed surface of the shield gate, and the control gate is located between the second oxide layer and the third initial oxide layer on the sidewall of the second trench; Ion implantation is performed on the structure formed with the third initial oxide layer to form the first implantation region and the second implantation region in the initial epitaxial layer, the first implantation region and the second implantation region being in contact with the third initial oxide layer on the sidewall of the second trench, respectively; Part of the initial epitaxial layer and part of the third initial oxide layer are removed to form two third trenches extending through the third initial oxide layer and the second implantation region and into the first implantation region, the two third trenches being located on one side of the second trench, and the remaining third initial oxide layer forming a third intermediate oxide layer; A second initial dielectric layer is formed in the two third trenches, on a surface of the third intermediate oxide layer away from the substrate and on a surface of the control gate away from the substrate; Part of the second initial dielectric layer, part of the third intermediate oxide layer and part of the initial epitaxial layer are removed to form the first contact hole in the second initial dielectric layer, the third intermediate oxide layer, the second implantation region and the first implantation region, the remaining third intermediate oxide layer and the remaining second initial dielectric layer forming the first initial dielectric layer, and the remaining initial epitaxial layer forming the epitaxial layer.

9. The method of claim 8, wherein, Forming a first oxide layer, a second oxide layer, a shield gate and a control gate in the second trench, and forming a third initial oxide layer on a surface of the initial epitaxial layer away from the substrate and on a part of a sidewall of the second trench away from the substrate, comprises: Forming a first initial oxide layer on a bottom surface, a sidewall of the second trench and a surface of the initial epitaxial layer away from the substrate, and forming the shield gate in the remaining second trench; Removing part of the first initial oxide layer so that a surface of the initial epitaxial layer away from the substrate and a part of the sidewall of the second trench are exposed, and the remaining first initial oxide layer forms the first oxide layer; Forming the second oxide layer on an exposed surface of the shield gate, and forming the third initial oxide layer on an exposed sidewall of the second trench and a surface of the initial epitaxial layer away from the substrate; The control gate is formed between the second oxide layer and the third initial oxide layer on the side wall of the second trench.

10. The method of claim 9, wherein, The first initial oxide layer is removed partially, so that the initial epitaxial layer is exposed away from the surface of the substrate and part of the side wall of the second trench, comprising: The first initial oxide layer is removed by wet etching, so that the initial epitaxial layer is exposed away from the surface of the substrate, and the exposed depth of the side wall of the second trench is greater than 0.8 μm.

11. The method of claim 6, wherein, A substrate is provided, comprising: A substrate and an initial epitaxial layer on one side surface of the substrate are provided, the initial epitaxial layer has a second trench and two third trenches, the trench depth of the second trench is greater than that of the third trench, and the two third trenches are located on one side of the second trench; A first oxide layer, a second oxide layer, a shield gate and a control gate are formed in the second trench, and a third intermediate oxide layer is formed on the surface of the initial epitaxial layer away from the substrate, part of the side wall of the second trench away from the substrate, and in the two third trenches, wherein the shield gate is located in the second trench, the first oxide layer is located between part of the side wall of the second trench close to the substrate and the shield gate, and between the bottom surface of the second trench and the shield gate, the second oxide layer is located on the surface of the shield gate away from the substrate and the exposed side surface of the shield gate, and the control gate is located between the second oxide layer and the third intermediate oxide layer on the side wall of the second trench. Ion implantation is performed on the structure formed with the third intermediate oxide layer to form the first implantation region and the second implantation region in the initial epitaxial layer, and the first implantation region and the second implantation region are in contact with the third intermediate oxide layer on the side wall of the second trench, respectively. A second initial dielectric layer is formed on the exposed surface of the second oxide layer, the exposed surface of the control gate, and the surface of the third intermediate oxide layer away from the substrate. Part of the second initial dielectric layer, part of the third intermediate oxide layer, and part of the initial epitaxial layer are removed to form the first contact hole in the second initial dielectric layer, the third intermediate oxide layer, the second implantation region, and the first implantation region, the remaining third intermediate oxide layer and the remaining second initial dielectric layer form the first initial dielectric layer, and the remaining initial epitaxial layer forms the epitaxial layer.

12. The method of claim 11, wherein, A first oxide layer, a second oxide layer, a shield gate and a control gate are formed in the second trench, and a third intermediate oxide layer is formed on the surface of the initial epitaxial layer away from the substrate, part of the side wall of the second trench away from the substrate, and in the two third trenches, comprising: A first initial oxide layer is formed on the bottom surface, the side wall of the second trench, the surface of the initial epitaxial layer away from the substrate, and the two third trenches, and a shield gate is formed in the remaining second trench. The first initial oxide layer is removed partially, so that the initial epitaxial layer is exposed from part of the surface of the substrate and part of the sidewall of the second trench, the first initial oxide layer remaining in the second trench forms the first oxide layer, and the first initial oxide layer remaining on the surface of the initial epitaxial layer in the third trench and on both sides of the third trench forms a preliminary oxide layer; The second oxide layer is formed on the exposed surface of the shield gate, and a third target oxide layer is formed on the exposed sidewall of the second trench and the surface of the initial epitaxial layer away from the substrate, and the third target oxide layer and the preliminary oxide layer are planarized to obtain the third intermediate oxide layer; The control gate is formed between the second oxide layer and the third intermediate oxide layer on the sidewall of the second trench.

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