Semiconductor device and method of manufacturing the same

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. Provided is a semiconductor device in which light degradation is suppressed. The semiconductor device includes: a gate electrode; a gate insulating layer on the gate electrode; an oxide semiconductor layer having a polycrystalline structure on the gate insulating layer; a source electrode and a drain electrode on the oxide semiconductor layer; and an interlayer insulating layer that covers the source electrode and the drain electrode and is in contact with the oxide semiconductor layer. The interlayer insulating layer has an S value of 1.5 V / dec or more and 2.5 V / dec or less. The oxide semiconductor layer includes: a first region overlapping one of the source electrode and the drain electrode; and a second region in contact with the interlayer insulating layer. The difference between the film thickness of the first region and the film thickness of the second region may be 5 nm or less.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device. In particular, one embodiment of the present invention relates to a semiconductor device using an oxide semiconductor as a channel. In addition, one embodiment of the present invention relates to a method for manufacturing a semiconductor device. Background Art

[0002] In recent years, the development of semiconductor devices using oxide semiconductor films as channels has been progressing instead of using silicon semiconductor films such as amorphous silicon, low-temperature polycrystalline silicon, and single-crystal silicon (for example, see Patent Documents 1 to 6). Like semiconductor devices including amorphous silicon films, semiconductor devices including oxide semiconductor films can be formed with a simple structure and a low-temperature process. It is known that semiconductor devices including oxide semiconductor films have higher field effect mobility than semiconductor devices including amorphous silicon films.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2021-141338

[0006] Patent Document 2: Japanese Patent Application Publication No. 2014-099601

[0007] Patent Document 3: Japanese Patent Application Publication No. 2021-153196

[0008] Patent Document 4: Japanese Patent Application Publication No. 2018-006730

[0009] Patent Document 5: Japanese Patent Application Publication No. 2016-184771

[0010] Patent Document 6: Japanese Patent Application Publication No. 2021-108405 Summary of the invention

[0011] Problems to be solved by the invention

[0012] Since an oxide semiconductor film has light-transmitting properties in the visible light region, a semiconductor device including an oxide semiconductor film has less light degradation than a semiconductor device including a silicon semiconductor film. However, it is also desired to further suppress light degradation in a semiconductor device including an oxide semiconductor film.

[0013] One object of one embodiment of the present invention is to provide a semiconductor device that suppresses light degradation. Another object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device that suppresses light degradation.

[0014] Means for solving problems

[0015] A semiconductor device involved in one embodiment of the present invention includes: a gate electrode; a gate insulating layer on the gate electrode; an oxide semiconductor layer with a polycrystalline structure on the gate insulating layer; a source electrode and a drain electrode on the oxide semiconductor layer; and an interlayer insulating layer covering the source electrode and the drain electrode and connected to the oxide semiconductor layer, wherein the S value is greater than 1.5 V / dec and less than 2.5 V / dec.

[0016] A method for manufacturing a semiconductor device involved in one embodiment of the present invention includes: forming a gate electrode, forming a gate insulating layer on the gate electrode, forming an oxide semiconductor layer with a polycrystalline structure on the gate insulating layer, forming a conductive film on the oxide semiconductor layer, patterning the conductive film by etching to form a source electrode and a drain electrode, and after the source electrode and the drain electrode are formed, annealing the oxide semiconductor layer whose surface is exposed from the source electrode and the drain electrode, and after the annealing, forming an interlayer insulating layer covering the source electrode and the drain electrode and connected to the oxide semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] [ Figure 1 ] is a schematic cross-sectional view showing the structure of a semiconductor device involved in one embodiment of the present invention.

[0018] [ Figure 2 ] is a schematic top view showing the structure of a semiconductor device involved in one embodiment of the present invention.

[0019] [ Figure 3 ] is a flowchart illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0020] [ Figure 4 ] is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0021] [ Figure 5 ] is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0022] [ Figure 6 ] is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0023] [ Figure 7 ] is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0024] [ Figure 8 ] is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0025] [ Fig. 9] is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0026] [ Fig.10 ] is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0027] [ Fig.11 ] is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0028] [ Fig.12 ] is a schematic cross-sectional view showing the structure of a semiconductor device involved in one embodiment of the present invention.

[0029] [ Fig.13 ] is a flowchart illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0030] [ Fig.14 ] is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0031] [ Fig.15 ] is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0032] [ Fig.16 ] is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0033] [ Fig.17 ] is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0034] [ Fig.18 ] is a schematic top view showing an overview of a display device involved in one embodiment of the present invention.

[0035] [ Fig.19 ] is a block diagram showing the circuit structure of a display device involved in one embodiment of the present invention.

[0036] [ Fig. 20 ] is a circuit diagram showing a pixel circuit of a display device according to one embodiment of the present invention.

[0037] [ Fig.21 ] is a schematic cross-sectional view showing the structure of a display device involved in one embodiment of the present invention.

[0038] [ Fig. 22 ] is a circuit diagram showing a pixel circuit of a display device according to one embodiment of the present invention.

[0039] [ Fig.23 ] is a schematic cross-sectional view showing the structure of a display device involved in one embodiment of the present invention.

[0040] [ Fig.24 ] is a graph showing the S value dependence of the threshold voltage shift and field effect mobility in the NBTIS test.

[0041] Description of Reference Numerals

[0042] 10, 10A: semiconductor device, 20: display device, 11: substrate, 12C: wiring, 12GE: gate electrode, 12W: wiring, 14: gate insulating layer, 15: contact hole, 16: gate insulating layer, 18: metal oxide film, 22: oxide semiconductor film, 24: oxide semiconductor layer, 26: oxide semiconductor layer, 28: metal oxide layer, 32C: wiring, 32D: drain electrode, 32S: source electrode, 32W: wiring, 34: interlayer insulating layer, 36: metal oxide film, 38: interlayer insulating layer, 39: insulating layer, 42C: common electrode, 44: insulating layer, 46C: electrode, 46P: pixel electrode, 110: driving transistor, 120: selecting transistor tube, 210: holding capacitor, 211: signal line, 212: gate line, 213: anode power line, 214: cathode power line, 220: liquid crystal area, 240: sealing area, 260: terminal area, 300: array substrate, 301: pixel circuit, 302: source drive circuit, 303: gate drive circuit, 304: source wiring, 305: gate wiring, 306: terminal part, 307: connection wiring, 310: sealing part, 311: liquid crystal element, 320: opposing substrate, 330: flexible printed circuit substrate, 340: chip, 350: holding capacitor, 362: insulating layer, 363: opening, 390: pixel electrode, 392: light-emitting layer, 394: common electrode DETAILED DESCRIPTION

[0043] The following describes various embodiments of the present invention with reference to the accompanying drawings. The following disclosure is only an example. The configuration that can be easily thought of by those skilled in the art by appropriately changing the configuration of the embodiment while maintaining the main purpose of the invention is of course included in the scope of the present invention. With respect to the accompanying drawings, in order to make the description clearer, the width, film thickness and shape of the constituent elements are sometimes schematically indicated compared to the actual method. However, the illustrated shape is only an example and does not limit the interpretation of the present invention. In this specification and the accompanying drawings, for the constituent elements that are the same as the constituent elements described in the accompanying drawings that have appeared, there is a situation where the same figure mark is marked and the detailed description is appropriately omitted.

[0044] In this specification, etc., the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "above". Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "below". Like this, for the convenience of explanation, the phrases "above" or "below" are used for explanation, and the up-and-down relationship between the substrate and the oxide semiconductor layer can also be configured in the opposite direction to that shown in the figure. In addition, as for the expression "oxide semiconductor layer on the substrate", it is only to explain the up-and-down relationship between the substrate and the oxide semiconductor layer, and other components can also be configured between the substrate and the oxide semiconductor layer. Above or below refers to the stacking order in a structure in which multiple layers are stacked. In the case of expressing "pixel electrode above the semiconductor device", it can also be a positional relationship in which the semiconductor device and the pixel electrode do not overlap when viewed from above. On the other hand, in the case of expressing "pixel electrode vertically above the semiconductor device", it indicates the positional relationship in which the semiconductor device and the pixel electrode overlap when viewed from above. It should be noted that the top view refers to observation from a direction perpendicular to the surface of the substrate.

[0045] In this specification, unless otherwise specified, expressions such as “α includes A, B, or C”, “α includes any one of A, B, and C”, or “α includes one selected from the group consisting of A, B, and C” do not exclude the case where α includes a plurality of combinations of A to C. Furthermore, these expressions do not exclude the case where α includes other constituent elements.

[0046] In this specification, "semiconductor device" refers to all devices that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are included in one embodiment of a semiconductor device. The semiconductor device of the embodiment shown below can be, for example, a display device, an integrated circuit (IC) such as a microprocessor (MPU), or a transistor used in a memory circuit.

[0047] In this specification, etc., "display device" refers to a structure that uses an electro-optical layer to display an image. For example, a term such as a display device sometimes refers to a display panel including an electro-optical layer, or sometimes refers to a structure on which other optical components (such as a polarizing component, a backlight source, a touch panel, etc.) are installed on a display unit. As long as there is no technical contradiction, the "electro-optical layer" can include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer. Therefore, in the embodiment, as a display device, a liquid crystal display device including a liquid crystal layer and an organic EL display device including an organic EL layer are described as examples. However, the structure described in the embodiment can be applied to a display device including the above-mentioned other electro-optical layers.

[0048] In this specification and the like, the term "film" and the term "layer" can be used interchangeably as appropriate.

[0049] In this specification, "S value" refers to the increase in gate voltage (Vg) required to increase drain current (Id) by one order of magnitude. For example, the S value can be obtained by calculating the threshold voltage (Vth) when Id = 10nA based on the Id-Vg curve with a voltage difference of 10V between the source electrode and the drain electrode. ＿10nA ) and the threshold voltage (Vth) when Id = 1nA ＿1nA ), and then calculate the difference (Vth ＿10nA -Vth ＿1nA ).

[0050] It should be noted that the following embodiments can be combined with each other as long as there is no technical contradiction.

[0051] <First embodiment>

[0052] Reference Figures 1 to 11 A semiconductor device 10 according to an embodiment of the present invention will be described.

[0053] [Configuration of Semiconductor Device 10]

[0054] Reference Figure 1 and Figure 2 The configuration of a semiconductor device 10 according to an embodiment of the present invention will be described. Figure 1 It is a cross-sectional view showing a schematic structure of a semiconductor device 10 according to one embodiment of the present invention. Figure 2 It is a schematic plan view showing the structure of a semiconductor device 10 according to one embodiment of the present invention. Figure 1 The cross-sectional view shown is similar to that shown by Figure 2 The cross section shown corresponds to the cross section taken along the A1-A2 line.

[0055] like Figure 1 As shown in FIG. 1 , the semiconductor device 10 is provided on the substrate 11. The semiconductor device 10 includes a gate electrode 12GE, gate insulating layers 14 and 16, an oxide semiconductor layer 26, a source electrode 32S, a drain electrode 32D, and interlayer insulating layers 34 and 38. When the source electrode 32S and the drain electrode 32D are not particularly distinguished, they are sometimes collectively referred to as the source electrode and the drain electrode 32. In addition, the gate electrode 12GE, the gate insulating layers 14 and 16, the oxide semiconductor layer 26, and the source electrode and the drain electrode 32 are sometimes referred to as a transistor. The semiconductor device 10 is a so-called bottom-gate transistor in which the gate electrode 12GE is provided below the oxide semiconductor layer 26.

[0056] In this embodiment, a bottom-gate transistor is exemplified as the semiconductor device 10 , but the semiconductor device 10 is not limited to the bottom-gate transistor. For example, the semiconductor device 10 may be a dual-gate transistor in which gate electrodes are provided above and below the oxide semiconductor layer 26 .

[0057] The gate electrode 12GE is provided on the substrate 11. The gate insulating layers 14 and 16 are provided on the substrate 11 and the gate electrode 12GE. The gate insulating layers 14 and 16 have a stacked structure, and the gate insulating layer 16 is provided on the gate insulating layer 14. The oxide semiconductor layer 26 is provided on the gate insulating layers 14 and 16. The source electrode 32S and the drain electrode 32D are provided on the oxide semiconductor layer 26. The interlayer insulating layers 34 and 38 are provided on the oxide semiconductor layer 26 and the source electrode 32S and the drain electrode 32D. The interlayer insulating layers 34 and 38 have a stacked structure, and the interlayer insulating layer 38 is provided on the interlayer insulating layer 34. That is, the interlayer insulating layers 34 and 38 cover the source electrode 32S and the drain electrode 32D, and the interlayer insulating layer 34 is in contact with the oxide semiconductor layer 26.

[0058] like Figure 2 As shown, in a plan view, the oxide semiconductor layer 26 overlaps with the gate electrode 12GE. The D1 direction is a direction connecting the source electrode 32S and the drain electrode 32D, and the D2 direction is a direction orthogonal to the D1 direction. In the semiconductor device 10, the channel length L corresponds to the length of the region (channel region) of the oxide semiconductor layer 26 between the source electrode 32S and the drain electrode 32D in the D1 direction, and the channel width W corresponds to the width of the channel region in the D2 direction. In a plan view, the region of the oxide semiconductor layer 26 overlapping with the source electrode 32S is the source region, and the region of the oxide semiconductor layer 26 overlapping with the drain electrode 32D is the drain region. That is, the channel region is located between the source region and the drain region.

[0059] The wiring 12W and the wiring 32W function as gate wiring. The wiring 32W is electrically connected to the wiring 12W via the contact hole 15. The wiring 12W is formed as the same layer as the gate electrode 12GE, and the details will be described later. In addition, the wiring 32W is formed as the same layer as the source electrode 32S and the drain electrode 32D. It should be noted that the wiring 32W is sometimes not provided on the wiring 12W.

[0060] The oxide semiconductor layer 26 is light-transmissive and has a polycrystalline structure including a plurality of crystal grains. The oxide semiconductor layer 26 having a polycrystalline structure can be formed by using the Poly-OS (Poly-crystalline Oxide Semiconductor) technology, and the details are described later. Therefore, the oxide semiconductor included in the oxide semiconductor layer 26 is sometimes described as Poly-OS below.

[0061] Poly-OS contains two or more metal elements including indium, and the ratio of indium to the two or more metal elements is 50% or more. As metal elements other than indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium (Zr), or lanthanide elements can be used. As the oxide semiconductor layer 26, elements other than the above can be used.

[0062] The crystal grain size of the crystal grains contained in the Poly-OS is 0.1 μm or more, preferably 0.3 μm or more, and more preferably 0.5 μm or more. The crystal grain size can be obtained by, for example, SEM observation, TEM observation, or electron backscattered diffraction (EBSD) of the oxide semiconductor layer 26 .

[0063] As described above, the crystal grains included in the Poly-OS have a crystal grain size of 0.1 μm or more, and therefore, in the oxide semiconductor layer 26 having a film thickness of 10 nm to 30 nm, there is a region including only one crystal grain along the film thickness direction.

[0064] Poly-OS has excellent etching resistance. Poly-OS has excellent etching resistance for the etching solution or etching gas used in the formation of the source electrode 32S and the drain electrode 32D, and the details are described later. Therefore, in the formation of the source electrode 32S and the drain electrode 32D, the oxide semiconductor layer 26 is basically not etched. Therefore, the film thickness of the first region (i.e., the source region or the drain region) of the oxide semiconductor layer 26 overlapping with one of the source electrode 32S and the drain electrode 32D, and the film thickness of the second region (i.e., the channel region) of the oxide semiconductor layer 26 that does not overlap with the source electrode 32S and the drain electrode 32D are substantially the same. In other words, the difference between the film thickness of the first region and the film thickness of the second region is less than 5nm, preferably less than 3nm, and more preferably less than 1nm.

[0065] The film thickness of the channel region affects the electrical characteristics of the semiconductor device. If the film thickness of the channel region has a large deviation, a semiconductor device with stable electrical characteristics cannot be provided. That is, the yield of the semiconductor device will decrease. On the other hand, in the semiconductor device 10, the film thickness of the channel region of the oxide semiconductor layer 26 can be controlled, so the semiconductor device 10 has stable electrical characteristics. For example, in the semiconductor device 10, even if the gate insulating layers 14 and 16 have a large film thickness of more than 300nm, when the channel length L of the channel region is more than 2μm and less than 10μm, and the channel width W of the channel region is more than 2μm and less than 25μm, a 15cm 2 / Vs or above, even 20cm2 Therefore, the voltage resistance of the semiconductor device 10 is improved, and the semiconductor device 10 has stable electrical characteristics even at high voltage.

[0066] In addition, the S value of the semiconductor device 10 is 1.5 V / dec or more and 2.5 V / dec or less. When the S value of the semiconductor device 10 is within the above range, the semiconductor device 10 has a 15 cm 2 / Vs or more, and the offset of the threshold voltage in the NBTIS (Negative Bias Temperature Illumination Stress) test is reduced. That is, if the semiconductor device 10 has an S value within the above range, the light degradation of the semiconductor device 10 is suppressed. In the case of a semiconductor device 10 having a Poly-OS, as the S value increases, the amount of threshold voltage in the NBTIS test decreases. Therefore, if the S value of the semiconductor device 10 is less than 1.5V / dec, the light degradation of the semiconductor device 10 cannot be fully suppressed. In addition, if the S value of the semiconductor device 10 exceeds 2.5V / dec, the field effect mobility decreases. Therefore, in the semiconductor device 10, the S value is adjusted to be within the above range. Below, a method for manufacturing the semiconductor device 10, including a method for adjusting the S value of the semiconductor device 10, is described.

[0067] [Method of Manufacturing Semiconductor Device 10]

[0068] Reference Figure 3 to Figure 11 A method for manufacturing the semiconductor device 10 according to one embodiment of the present invention will be described. Figure 3 This is a flowchart for explaining a method for manufacturing the semiconductor device 10 according to one embodiment of the present invention. Figures 4 to 11 1 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device 10 according to an embodiment of the present invention. Figure 3 Each step of the flowchart shown is described below.

[0069] exist Figure 3 In step S1001 (“GE formation”), a gate electrode 12GE is formed on the substrate 11 (see Figure 4 ).

[0070] As the substrate 11, a glass substrate, a quartz substrate, a sapphire substrate, or other light-transmitting rigid substrate can be used. When the substrate 11 needs to be flexible, a substrate including a polyimide substrate, an acrylic substrate, a siloxane-based substrate, a fluororesin substrate, or a substrate including a resin can be used as the substrate 11. When a substrate including a resin is used as the substrate 11, impurity elements can be introduced into the above-mentioned resin in order to improve the heat resistance of the substrate 11. In addition, when the semiconductor device 10 is used in an integrated circuit, as the substrate 11, a semiconductor substrate such as a silicon substrate, a silicon carbide substrate, a compound semiconductor substrate, or a conductive substrate such as a stainless steel substrate, which is not light-transmitting, can be used.

[0071] The gate electrode 12GE is formed by processing a conductive film formed by a sputtering method. A metal material can be used as the gate electrode 12GE. For example, as the metal material of the gate electrode 12GE, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys thereof or compounds thereof can be used. As the gate electrode 12GE, the above-mentioned metal materials can be used in a single layer or in a stacked manner.

[0072] exist Figure 3 In step S1002 (“GI formation”), gate insulating layers 14 and 16 are formed on the gate electrode 12GE (see Figure 4 The gate insulating layers 14 and 16 are formed by CVD (Chemical Vapor Deposition) or sputtering. As the gate insulating layers 14 and 16, insulating materials can be used. For example, as the insulating material of the gate insulating layers 14 and 16, silicon oxide (SiO x ), silicon oxide nitride (SiO x N y ), Silicon Nitride (SiN x ), silicon oxide nitride (SiN x O y ) and other inorganic insulating materials. The above-mentioned SiO x N y It is a silicon compound containing nitrogen (N) at a ratio (x>y) less than oxygen (O). SiN x O y It is a silicon compound containing oxygen at a ratio smaller than nitrogen (x>y).

[0073] On the substrate 11, a gate insulating layer 14 using an insulating material containing nitrogen and a gate insulating layer 16 using an insulating material containing oxygen are preferably formed in sequence. By using an insulating material containing nitrogen as the gate insulating layer 14, impurities diffusing from the substrate 11 toward the oxide semiconductor layer 26 can be blocked. In addition, by using an insulating material containing oxygen as the gate insulating layer 16, oxygen can be released by heat treatment. The temperature of the heat treatment for releasing oxygen from the insulating material containing oxygen is, for example, below 500° C., below 450° C., or below 400° C. It should be noted that the insulating material containing oxygen can release oxygen when heated in any step of the manufacturing process of the semiconductor device 10.

[0074] The film thickness of the gate insulating layer 14 is preferably greater than the film thickness of the gate insulating layer 16. In this embodiment, for example, silicon nitride is formed to a thickness of 300 nm as the gate insulating layer 14, and for example, silicon oxide is formed to a thickness of 100 nm as the gate insulating layer 16.

[0075] exist Figure 3 In step S1004 (“OS film formation”), an oxide semiconductor film 22 is formed on the gate insulating layers 14 and 16 (see Figure 5 The oxide semiconductor film 22 is formed by sputtering or atomic layer deposition (ALD). The oxide semiconductor film 22 has a film thickness of 10 nm to 50 nm, preferably 10 nm to 40 nm, and more preferably 10 nm to 30 nm.

[0076] As the oxide semiconductor film 22, a metal oxide having semiconductor properties can be used. For example, as the oxide semiconductor film 22, an oxide semiconductor containing two or more metal elements including indium (In) can be used. In addition, the ratio of indium to the two or more metal elements is 50% or more. As metal elements other than indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium (Zr), or lanthanide elements can be used. As the oxide semiconductor film 22, it is preferred to contain Group 13 elements. It should be noted that as the oxide semiconductor film 22, elements other than the above can be used.

[0077] When the oxide semiconductor film 22 is crystallized by OS annealing described later, the oxide semiconductor film 22 after film formation and before OS annealing preferably has an amorphous structure (for example, a structure with a small amount of crystal components of the oxide semiconductor such as amorphous determined by the XRD method). That is, the film formation of the oxide semiconductor film 22 is preferably performed under conditions in which the oxide semiconductor film 22 immediately after film formation is as little crystallized as possible. For example, when the oxide semiconductor film 22 is formed by sputtering, the oxide semiconductor film 22 is formed while controlling the temperature of the object to be formed (the substrate 11 and the structure formed thereon).

[0078] When a film is formed on an object to be formed by sputtering, ions generated in the plasma and atoms recoiled by the sputtering target collide with the object to be formed, so the temperature of the object to be formed rises with the film forming process. If the temperature of the object to be formed rises during the film forming process, the oxide semiconductor film 22 contains microcrystals in the state just after the film is formed. If the oxide semiconductor film 22 contains microcrystals, the crystal grain size cannot be increased by the subsequent OS annealing. In order to control the temperature of the object to be formed, for example, the film can be formed while the object to be formed is cooled. For example, the object to be formed can be cooled from the opposite side of the film forming surface in a manner such that the temperature of the film forming surface of the object to be formed (hereinafter referred to as the "film forming temperature") is below 100°C, below 70°C, below 50°C, or below 30°C. In particular, the film forming temperature of the oxide semiconductor film 22 is preferably below 50°C. By forming the oxide semiconductor film 22 while cooling the substrate 11 , it is possible to obtain the oxide semiconductor film 22 having a small crystal component immediately after film formation.

[0079] In the sputtering process, an oxide semiconductor film 22 having an amorphous structure is formed under the condition of an oxygen partial pressure of less than 10%. If the oxygen partial pressure is high, the oxide semiconductor film 22 immediately after film formation will contain microcrystals due to the excess oxygen contained in the oxide semiconductor film 22. Therefore, it is preferred to form the oxide semiconductor film 22 under the condition of a low oxygen partial pressure. The oxygen partial pressure is, for example, not less than 1% and not more than 5%, preferably not less than 2% and not more than 4%. Under the condition of an oxygen partial pressure of less than 1%, the distribution of oxygen in the film forming device tends to become uneven. As a result, the composition of oxygen in the oxide semiconductor film also becomes uneven, forming an oxide semiconductor film containing a large number of microcrystals, or forming an oxide semiconductor film that does not crystallize even if OS annealing is performed thereafter.

[0080] exist Figure 3 In step S1005 (“OS pattern formation”), a pattern of the oxide semiconductor layer 24 is formed (see Figure 6). The pattern of the oxide semiconductor layer 24 is formed using photolithography. For example, a resist mask (not shown) is formed on the oxide semiconductor film 22, and the oxide semiconductor film 22 is etched using the resist mask. As the etching of the oxide semiconductor film 22, wet etching or dry etching can be used. As wet etching, etching can be performed using an acidic etching solution. As an etching solution, for example, oxalic acid, PAN, sulfuric acid, hydrogen peroxide, or hydrofluoric acid can be used. In this way, an oxide semiconductor layer 24 having a predetermined pattern can be formed. Then, the resist mask is removed.

[0081] The formation of the oxide semiconductor layer 24 having a predetermined pattern (i.e., patterning of the oxide semiconductor film 22) is preferably performed before OS annealing. The poly-OS after OS annealing has high etching resistance and is difficult to pattern by etching. In addition, by performing OS annealing after the formation of the oxide semiconductor layer 24, damage generated during the formation of the oxide semiconductor layer 24 (e.g., oxygen defects in the oxide semiconductor layer 24) can be repaired.

[0082] exist Figure 3 In step S1006 (“OS annealing”), after the oxide semiconductor layer 24 is formed, the oxide semiconductor layer 24 is subjected to heat treatment (OS annealing), thereby forming the oxide semiconductor layer 26 (see Figure 7 ). In the OS annealing, the oxide semiconductor layer 24 is maintained at a predetermined reaching temperature for a predetermined time. The predetermined reaching temperature is 300° C. to 500° C., preferably 350° C. to 450° C. In addition, the holding time at the reaching temperature is 15 minutes to 120 minutes, preferably 30 minutes to 60 minutes. By performing the OS annealing, the oxide semiconductor layer 24 having an amorphous structure is crystallized to form an oxide semiconductor layer 26 having a polycrystalline structure. That is, by the OS annealing, the oxide semiconductor layer 26 containing Poly-OS is formed.

[0083] exist Figure 3 In step S1008 (“contact hole formation”), contact holes are formed in the gate insulating layers 14 and 16 (see Figure 8 ). Thus, the upper surface of the wiring 12W is exposed. It should be noted that, when it is not necessary to connect the wiring 32W to the wiring 12W, the process of step S1008 may not be performed.

[0084] exist Figure 3 In step S1009 (“SD formation”), the source electrode 32S, the drain electrode 32D and the wiring 32W are formed (see Fig. 9). The source electrode 32S, the drain electrode 32D, and the wiring 32W are formed by patterning a conductive film formed by sputtering by etching. As the source electrode 32S and the drain electrode 32D, the same conductive material as the gate electrode 12GE is used. As the source electrode 32S, the drain electrode 32D, and the wiring 32W, the conductive material can be used as a single layer or in a stacked manner. In this embodiment, examples are given of a MoW alloy, a stacked structure of Al and a MoW alloy (MoW / Al / MoW structure), a single-layer structure of a MoW alloy (MoW structure), a single-layer structure of Ti (Ti structure), and a stacked structure of Ti, Al, and Ti (Ti / Al / Ti structure).

[0085] In order to form the source electrode 32S, the drain electrode 32D and the wiring 32W, patterning using wet etching or dry etching is performed. In wet etching, an etching solution is used. For example, as an etching solution, a solution containing at least two selected from the group consisting of phosphoric acid, acetic acid, nitric acid, hydrofluoric acid, hydrochloric acid, sulfuric acid and oxalic acid can be used. Specifically, as an etching solution, a mixed acid etching solution with phosphoric acid, acetic acid and nitric acid as main components can be used. In addition, as an etching solution, a mixed solution of hydrogen peroxide and ammonia water (hereinafter referred to as "H2O2 / NH3 solution") can also be used. In dry etching, an etching gas is used. For example, as an etching gas, a fluorine-containing gas such as sulfur hexafluoride gas (SF6) (hereinafter referred to as "fluorine-based gas") or a chlorine-containing gas such as chlorine (Cl2) (hereinafter referred to as "chlorine-based gas") can be used.

[0086] Poly-OS has excellent etching resistance. Specifically, the etching rate relative to the etching solution or etching gas used in the formation of the source electrode 32S and the drain electrode 32D is very small. This means that Poly-OS is hardly etched by the etching solution or etching gas. Therefore, in the semiconductor device 10, even if a conductive film is directly formed on the oxide semiconductor layer 26 and the conductive film is patterned to form the source electrode 32S and the drain electrode 32D, the channel region of the oxide semiconductor layer 26 is hardly etched.

[0087] For example, the etching rate of the oxide semiconductor layer 26 in the etching solution used in forming the source electrode 32S and the drain electrode 32D is 0.1 nm / sec or less, or 0.01 nm / sec or less. In addition, the etching rate of the oxide semiconductor layer 26 in the etching gas used in forming the source electrode 32S and the drain electrode 32D is 0.5 nm / sec or less, or 0.1 nm / sec or less. For example, the etching rate of the oxide semiconductor layer 26 in the chlorine-based gas is 0.1 nm / sec or less.

[0088] In a semiconductor device using an oxide semiconductor that does not have a polycrystalline structure such as IGZO as an oxide semiconductor layer, when a source electrode and a drain electrode are formed on the oxide semiconductor, the oxide semiconductor layer is also etched due to the etching of the source electrode and the drain electrode. Specifically, the etching rate of IGZO in a chlorine-containing gas is 1.0nm / sec. Considering that the channel region is etched at this etching rate, it is necessary to form the oxide semiconductor film thicker in advance. For example, in the case of a semiconductor device in which the film thickness of the channel region of the oxide semiconductor layer is less than 40nm, it is necessary to form an oxide semiconductor film with a film thickness of about 65nm in advance, and in the formation of the source electrode and the drain electrode, the etching time is adjusted in such a way that the film thickness of the channel region becomes less than 40nm. However, when the etching rate is large, it is difficult to precisely control the film thickness of the channel region by the etching time. In this case, the deviation of the film thickness of the channel region becomes larger.

[0089] In addition, if the film thickness of the channel region is greatly reduced, a recess is formed on the upper surface of the oxide semiconductor layer. The interlayer insulating layer provided on the oxide semiconductor layer is formed in a manner covering the recess, but if the depth of the recess is large, the interlayer insulating layer cannot fully cover the recess. That is, there is a situation where a gap is generated between the oxide semiconductor layer and the interlayer insulating layer, or between the source electrode and the drain electrode and the interlayer insulating layer. This may not only be the main cause of uneven electrical characteristics of the semiconductor device, but also the main cause of uneven reliability.

[0090] In contrast, the oxide semiconductor layer 26 including Poly-OS can have an etching rate of 0.00nm / sec to 0.1nm / sec, preferably 0.00nm / sec to 0.06nm / sec, regardless of whether dry etching or wet etching is performed. That is, for the oxide semiconductor layer 26 including Poly-OS, the etching rate is lower than that of the oxide semiconductor layer including IGZO, and has high etching resistance. Therefore, the film thickness of the channel region can be controlled without considering the reduction in the film thickness of the oxide semiconductor layer caused by etching. Therefore, when the oxide semiconductor film is formed, the film can be formed with a film thickness of more than 10nm and less than 30nm. In addition, the selectivity of the conductive material that can be used as the source electrode 32S, the drain electrode 32D and the wiring 32W is improved. For example, even when the source electrode 32S and the drain electrode 32D are formed by wet etching a conductive film using a stacked structure of MoW / Al / MoW or a MoW structure, the reduction in the film thickness of the oxide semiconductor layer 26 can be suppressed.

[0091] As described above, the etching rate of the oxide semiconductor layer 26 in the etching solution used in the formation of the source electrode 32S and the drain electrode 32D is very low. Therefore, the film thickness of the first region (i.e., the source region or the drain region) of the oxide semiconductor layer 26 overlapping with one of the source electrode 32S and the drain electrode 32D is substantially the same as the film thickness of the second region (i.e., the channel region) of the oxide semiconductor layer 26 not overlapping with the source electrode 32S and the drain electrode 32D. In other words, the difference between the film thickness of the first region and the film thickness of the second region can be controlled to be 5 nm or less, preferably 3 nm or less, and more preferably 1 nm or less. That is, the deviation of the film thickness of the channel region is suppressed.

[0092] exist Figure 3 In step S1010 ("BCH plasma treatment"), the oxide semiconductor layer 26, the source electrode 32S and the drain electrode 32D are subjected to plasma treatment using a prescribed gas. In fact, the surface of the oxide semiconductor layer 26 exposed from the source electrode 32S and the drain electrode 32D (hereinafter sometimes referred to as the "back channel") is subjected to BCH plasma treatment. As the prescribed gas, an inactive gas such as argon or nitrogen can be used, preferably argon. It should be noted that the prescribed gas can be not only one gas, but also two or more gases. In addition, in the BCH plasma treatment, not only one plasma treatment can be performed, but also multiple plasma treatments can be performed using different gases. The time for the plasma treatment is from 5 seconds to 300 seconds, preferably from 10 seconds to 150 seconds, and more preferably from 15 seconds to 90 seconds.

[0093] When the SD formation in step S1009 is performed, impurities may be attached to the back channel due to the etching solution or etching gas. Therefore, BCH plasma treatment is performed to remove the impurities attached to the back channel. For example, when the impurities attached to the back channel are mainly organic matter, the organic matter attached to the back channel can be removed by plasma treatment using argon gas.

[0094] exist Figure 3 In step S1011 ("BCH annealing"), the oxide semiconductor layer 26, the source electrode 32S and the drain electrode 32D are heat treated. In fact, the back channel can be subjected to BCH annealing. In the BCH annealing, the heat treatment is performed in an air atmosphere. The temperature of the BCH annealing is 200°C to 400°C, preferably 200°C to 300°C, and more preferably 200°C to 250°C. In addition, the time of the BCH annealing is 15 minutes to 150 minutes, preferably 30 minutes to 120 minutes, and more preferably 30 minutes to 90 minutes.

[0095] During the BCH plasma treatment and the BCH annealing, the S value of the semiconductor device 10 is adjusted. If the back channel is treated with plasma by the BCH plasma treatment, the S value of the semiconductor device 10 can be increased. On the other hand, if the back channel is thermally treated by the BCH annealing, the S value of the semiconductor device 10 can be reduced. Therefore, the S value of the semiconductor device 10 can be adjusted to a value between 1.5 V / dec and 2.5 V / dec by the BCH plasma and the BCH annealing. It should be noted that in order to adjust the S value of the semiconductor device 10 to within the above range, at least one of the BCH plasma and the BCH annealing can be implemented. In addition, the S value of the semiconductor device 10 can also be adjusted by the treatment time in the BCH plasma treatment, or the temperature and time in the BCH annealing.

[0096] exist Figure 3 In step S1012 ("SiOx formation"), an interlayer insulating layer 34 is formed on the oxide semiconductor layer 26, the source electrode 32S, and the drain electrode 32D. As the interlayer insulating layer 34, an insulating material containing oxygen is preferably used. For example, silicon oxide (SiO x ) or silicon oxide nitride (SiO x N y ) etc. In addition, as the interlayer insulating layer 34, it is preferable to use an insulating film with few defects. For example, when the oxygen composition ratio in the interlayer insulating layer 34 is compared with the oxygen composition ratio in an insulating film with the same composition as the interlayer insulating layer 34 (hereinafter referred to as "other insulating film"), the oxygen composition ratio in the interlayer insulating layer 34 is closer to the stoichiometric ratio for the insulating film than the oxygen composition ratio in the other insulating film. However, silicon oxide (SiO2) is used in each of the interlayer insulating layer 34 and the gate insulating layer 16. x ), the gate insulating layer 16 preferably has a composition ratio closer to the stoichiometric ratio of silicon oxide (SiO 2 ) than the interlayer insulating layer 34. As the interlayer insulating layer 34, a layer in which no defects are observed when evaluated by electron spin resonance (ESR) can be used.

[0097] The interlayer insulating layer 34 can be formed by the same film forming method as the gate insulating layers 14 and 16. In order to increase the oxygen composition ratio in the interlayer insulating layer 34, the film can be formed at a relatively low temperature (for example, a film forming temperature of less than 350° C.). In addition, in order to form an insulating film with few defects as the interlayer insulating layer 34, the interlayer insulating layer 34 can be formed at a film forming temperature of 350° C. or more. Furthermore, after the interlayer insulating layer 34 is formed, a process of injecting oxygen into a part of the interlayer insulating layer 34 can be performed.

[0098] The film thickness of the interlayer insulating layer 34 is not less than 10 nm and not more than 300 nm, not less than 40 nm and not more than 200 nm, or not less than 70 nm and not more than 150 nm.

[0099] exist Figure 3 In step S1013 (“MO film formation”), a metal oxide film 36 is formed on the interlayer insulating layer 34 (see Fig.10 The metal oxide film 36 is formed by sputtering or atomic layer deposition (ALD: Atomic Layer Deposition).

[0100] As the metal oxide film 36, a metal oxide film containing aluminum as a main component can be used. For example, as the metal oxide film 36, aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum nitride (AlN x O y ), or aluminum nitride (AlN x ) or other metal oxide films. A metal oxide film having aluminum as a main component means that the ratio of aluminum contained in the metal oxide film is greater than 1% of the entire metal oxide film. Specifically, the ratio of aluminum contained in the metal oxide film 36 may be greater than 5% and less than 70%, greater than 10% and less than 60%, or greater than 30% and less than 50% of the entire metal oxide film 36. The above ratios may be mass ratios or weight ratios.

[0101] The thickness of the metal oxide film 36 is not less than 1 nm and not more than 50 nm, preferably not less than 1 nm and not more than 30 nm. As the metal oxide film 36, aluminum oxide is preferably used. Aluminum oxide has a high barrier property to gases such as oxygen or hydrogen. Here, the so-called barrier property refers to the function of inhibiting the permeation of gases such as oxygen or hydrogen through aluminum oxide. That is, it means that gases such as oxygen or hydrogen in the layer provided under the aluminum oxide film are not moved to the layer provided on the aluminum oxide film. Alternatively, it means that gases such as oxygen or hydrogen in the layer provided on the aluminum oxide film are not moved to the layer provided under the aluminum oxide film.

[0102] Note that a metal oxide containing a metal other than aluminum as a main component may be used as the metal oxide film 36. For example, the metal oxide film 36 may be indium tin oxide (ITO), indium zinc oxide (IZO), or indium gallium zinc oxide (IGZO).

[0103] exist Figure 3 In step S1014 (“oxidation annealing”), a heat treatment is performed with the interlayer insulating layer 34 and the metal oxide film 36 formed on the oxide semiconductor layer 26 (see Fig.10). Thus, oxygen released from the interlayer insulating layer 34 is supplied to the oxide semiconductor layer 26. The metal oxide film 36 is provided so as to cover the substrate 11, thereby preventing oxygen released from the interlayer insulating layer 34 from being released to the outside of the metal oxide film 36.

[0104] In the process from the formation of the oxide semiconductor layer 26 to the formation of the interlayer insulating layer 34 on the oxide semiconductor layer 26, a large number of oxygen defects are generated in the oxide semiconductor layer 26. However, by the oxidation annealing in step S1014, oxygen released from the interlayer insulating layer 34 is supplied to the oxide semiconductor layer 26, and the oxygen defects are repaired.

[0105] exist Figure 3 In step S1015 ("MO removal"), the metal oxide film 36 is removed (see Fig.11 ). For example, the metal oxide film 36 may be removed using diluted hydrofluoric acid (DHF).

[0106] exist Figure 3 In step S1016 ("SiNx film formation"), an interlayer insulating layer 38 is formed on the interlayer insulating layer 34. As the interlayer insulating layer 38, an insulating material containing nitrogen is preferably used. For example, silicon nitride (SiN x ) or silicon oxide nitride (SiN x O y ) etc. The interlayer insulating layer 38 can be formed by the same film forming method as the gate insulating layers 14 and 16 .

[0107] Through the above steps, it is possible to produce Figure 1 A semiconductor device 10 is shown.

[0108] In the semiconductor device 10 manufactured by the above manufacturing method, the S value can be adjusted to 1.5 V / dec or more and 2.5 V / dec or less. As a result, the semiconductor device 10 has a 15 cm 2 / Vs or more, and light degradation of the semiconductor device 10 can be suppressed.

[0109] <Second embodiment>

[0110] Reference Figure 12 to Figure 17 A semiconductor device 10A according to an embodiment of the present invention will be described. When components of the semiconductor device 10A are the same as components of the semiconductor device 10 , description of the components of the semiconductor device 10A may be omitted.

[0111] [Configuration of Semiconductor Device 10A]

[0112] Fig.12It is a schematic cross-sectional view showing the structure of a semiconductor device 10A according to one embodiment of the present invention. Fig.12 The cross-sectional view shown is similar to that shown by Figure 2 The cross section shown corresponds to the cross section taken along the A1-A2 line.

[0113] like Fig.12 As shown, the semiconductor device 10A is provided on the substrate 11. The semiconductor device 10A includes a gate electrode 12GE, gate insulating layers 14 and 16, a metal oxide layer 28, an oxide semiconductor layer 26, a source electrode 32S, a drain electrode 32D, and interlayer insulating layers 34 and 38. That is, the semiconductor device 10A is different from the semiconductor device 10 and includes the metal oxide layer 28. It should be noted that the gate electrode 12GE, the gate insulating layers 14 and 16, the metal oxide layer 28, the oxide semiconductor layer 26, and the source electrode and the drain electrode 32 are sometimes referred to as a transistor.

[0114] The metal oxide layer 28 is provided on the gate insulating layer 16. In addition, the oxide semiconductor layer 26 is provided on the metal oxide layer 28. The end surface of the metal oxide layer 28 and the end surface of the oxide semiconductor layer 26 are substantially consistent with each other.

[0115] In the semiconductor device 10A, the crystallinity of the Poly-OS in the oxide semiconductor layer 26 can be controlled by the metal oxide layer 28, and the film thickness of the channel region of the oxide semiconductor layer 26 including the Poly-OS can be controlled, so the semiconductor device 10A has more stable electrical characteristics. For example, in the semiconductor device 10A, even when the gate insulating layers 14 and 16 have a large film thickness of 300 nm or more, when the channel length L of the channel region is in the range of 2 μm to 4 μm and the channel width W of the channel region is in the range of 2 μm to 25 μm, a 20 cm 2 / Vs or above, even 30cm 2 Therefore, the voltage resistance of the semiconductor device 10A is improved, and the semiconductor device 10A has stable electrical characteristics even at high voltage.

[0116] In addition, the S value of the semiconductor device 10A is 1.5 V / dec or more and 2.5 V / dec or less. When the S value of the semiconductor device 10A is within the above range, the semiconductor device 10A has a 20 cm 2 / Vs or more, and light degradation of the semiconductor device 10A can be suppressed.

[0117] [Method of Manufacturing Semiconductor Device 10A]

[0118] Reference Figure 13 to Figure 17 A method for manufacturing the semiconductor device 10A according to one embodiment of the present invention will be described. Fig.13 This is a flowchart for explaining a method for manufacturing a semiconductor device 10A according to an embodiment of the present invention. Figure 14 to Figure 17 Schematic cross-sectional views showing a method for manufacturing a semiconductor device 10A according to an embodiment of the present invention. Fig.13 Each step of the flowchart shown in the figure will be described, but the description of part of the steps described in the first embodiment will be omitted.

[0119] exist Fig.13 In step S1003 (“MO film formation”), a metal oxide film 18 is formed on the gate insulating layers 14 and 16 (see Fig.14 The metal oxide film 18 is formed by sputtering or atomic layer deposition (ALD: Atomic Layer Deposition).

[0120] As the metal oxide film 18, a metal oxide film containing aluminum as a main component can be used. For example, as the metal oxide film 18, aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum nitride (AlN x O y ), or aluminum nitride (AlN x ) or other metal oxide films. A metal oxide film having aluminum as a main component means that the ratio of aluminum contained in the metal oxide film is more than 1% of the entire metal oxide film. Specifically, the ratio of aluminum contained in the metal oxide film 18 can be more than 5% and less than 70%, more than 10% and less than 60%, or more than 30% and less than 50% of the entire metal oxide film 18. The above ratios can be mass ratios or weight ratios.

[0121] The thickness of the metal oxide film 18 is, for example, not less than 1 nm and not more than 10 nm, preferably not less than 1 nm and not more than 5 nm. In the present embodiment, aluminum oxide is used as the metal oxide film 18. Aluminum oxide has a high barrier property to gases such as oxygen or hydrogen. In other words, the so-called barrier property refers to the function of inhibiting the permeation of gases such as oxygen or hydrogen through aluminum oxide. That is, even if gases such as oxygen or hydrogen exist in a layer disposed under the aluminum oxide film, the gas does not move to the layer disposed above the aluminum oxide film. Alternatively, even if gases such as oxygen or hydrogen exist in a layer disposed above the aluminum oxide film, the gas does not move to the layer disposed under the aluminum oxide film.

[0122] exist Fig.13 In step S1004 (“OS film formation”), an oxide semiconductor film 22 is formed on the metal oxide film 18 (see Fig.14 ).

[0123] exist Fig.13 In step S1005 (“OS pattern formation”), a pattern of the oxide semiconductor layer 24 is formed (see Fig.15 ).

[0124] exist Fig.13 In step S1006 (“OS annealing”), after the oxide semiconductor layer 24 is formed, the oxide semiconductor layer 24 is subjected to heat treatment (OS annealing), thereby forming the oxide semiconductor layer 26 (see Fig.16 ).

[0125] exist Fig.13 In step S1007 (“MO pattern formation”), the metal oxide film 18 is patterned to form a metal oxide layer 28 (see Fig.17 ). The oxide semiconductor layer 26 that is fully crystallized by heat treatment has high etching resistance. Therefore, when the metal oxide film 18 is patterned using the crystallized oxide semiconductor layer 26 as a mask, the disappearance of the oxide semiconductor layer 26 can be suppressed. The metal oxide film 18 is etched using the oxide semiconductor layer 26 patterned in the above process as a mask. As the etching of the metal oxide film 18, wet etching can be used, or dry etching can be used. As wet etching, for example, diluted hydrofluoric acid (DHF) can be used. By etching the metal oxide film 18 using the oxide semiconductor layer 26 as a mask, the photolithography process can be omitted.

[0126] Fig.13 Steps S1008 to S1016 and Figure 3 Steps S1008 to S1016 are the same, so their description is omitted here.

[0127] Through the above steps, it is possible to produce Fig.13 The semiconductor device 10A is shown.

[0128] In the semiconductor device 10A manufactured by the above manufacturing method, the S value can be adjusted to 1.5 V / dec or more and 2.5 V / dec or less. As a result, the semiconductor device 10A has a 20 cm 2 / Vs or more, and light degradation of the semiconductor device 10A can be suppressed.

[0129] <Third embodiment>

[0130] Reference Figure 18 to Figure 21 A display device 20 using the semiconductor device 10 according to one embodiment of the present invention will be described. In the following embodiment, a circuit configuration in which the semiconductor device 10 described in the first embodiment is applied to a liquid crystal display device will be described.

[0131] [Overview of Display Device 20]

[0132] Fig.18 1 is a schematic top view showing an overview of a display device 20 according to an embodiment of the present invention. Fig.18 As shown, the display device 20 includes an array substrate 300, a sealing portion 310, an opposing substrate 320, a flexible printed circuit substrate 330 (FPC 330), and an IC chip 340. The array substrate 300 and the opposing substrate 320 are bonded together by the sealing portion 310. In the liquid crystal region 220 surrounded by the sealing portion 310, a plurality of pixel circuits 301 are arranged in a matrix. The liquid crystal region 220 is a region that overlaps with a liquid crystal element 311 described later when viewed from above.

[0133] The sealing region 240 provided with the sealing portion 310 is the region around the liquid crystal region 220. The FPC 330 is provided in the terminal region 260. The terminal region 260 is the region where the array substrate 300 is exposed from the counter substrate 320 and is provided outside the sealing region 240. The outside of the sealing region 240 refers to the outside of the region provided with the sealing portion 310 and the region surrounded by the sealing portion 310. The IC chip 340 is provided on the FPC 330. The IC chip 340 supplies a signal for driving each pixel circuit 301.

[0134] [Circuit Configuration of Display Device 20]

[0135] Fig.19 1 is a block diagram showing a circuit configuration of a display device 20 according to an embodiment of the present invention. Fig.19 As shown, a source driving circuit 302 is provided at a position adjacent to the liquid crystal region 220 in the second direction D2 (column direction) with respect to the pixel circuit 301, and a gate driving circuit 303 is provided at a position adjacent to the liquid crystal region 220 in the first direction D1 (row direction). The source driving circuit 302 and the gate driving circuit 303 are provided in the above-mentioned sealing region 240. However, the region where the source driving circuit 302 and the gate driving circuit 303 are provided is not limited to the sealing region 240, and can be any region as long as it is outside the region where the pixel circuit 301 is provided.

[0136] The source wiring 304 extends in the second direction D2 from the source driver circuit 302 and is connected to the plurality of pixel circuits 301 arranged along the second direction D2. The gate electrode 12GE extends in the first direction D1 from the gate driver circuit 303 and is connected to the plurality of pixel circuits 301 arranged along the first direction D1.

[0137] The terminal region 260 is provided with a terminal portion 306. The terminal portion 306 is connected to the source driver circuit 302 by a connection wiring 307. Similarly, the terminal portion 306 is connected to the gate driver circuit 303 by a connection wiring 307. The FPC 330 is connected to the terminal portion 306, so that an external device connected to the FPC 330 is connected to the display device 20, and each pixel circuit 301 provided in the display device 20 is driven by a signal from the external device.

[0138] The semiconductor device 10 described in the first embodiment is used as a transistor included in the pixel circuit 301 , the source driver circuit 302 , and the gate driver circuit 303 .

[0139] [Pixel Circuit 301 of Display Device 20]

[0140] Fig. 20 2 is a circuit diagram showing a pixel circuit 301 of a display device 20 according to an embodiment of the present invention. Fig. 20 As shown, the pixel circuit 301 includes components such as the semiconductor device 10, the storage capacitor 350, and the liquid crystal element 311. The semiconductor device 10 has a gate electrode 12GE, an oxide semiconductor layer 26, a source electrode 32S, and a drain electrode 32D. The gate electrode 12GE is connected to the gate wiring 305. The source electrode 32S is connected to the source wiring 304. The drain electrode 32D is connected to the storage capacitor 350 and the liquid crystal element 311.

[0141] [Configuration of Display Device 20]

[0142] Fig.21 It is a schematic cross-sectional view of a display device 20 according to one embodiment of the present invention. Fig.21 The display device 20 shown uses the semiconductor device 10 .

[0143] like Fig.21 As shown, a gate electrode 12GE is provided on a substrate 11. Gate insulating layers 14 and 16 are provided on the gate electrode 12GE. An oxide semiconductor layer 26 is provided on the gate insulating layers 14 and 16. A source electrode 32S and a drain electrode 32D are provided on the oxide semiconductor layer 26.

[0144] Interlayer insulating layers 34 and 38 are provided on the source electrode 32S and the drain electrode 32D. An insulating layer 39 is provided on the interlayer insulating layers 34 and 38. The insulating layer 39 is provided to alleviate the unevenness caused by the semiconductor device 10. Contact holes are formed in the interlayer insulating layers 34, 38 and the insulating layer 39 so as to expose the upper surface of the source electrode 32S. A common electrode 42C provided in common with a plurality of pixels is provided on the insulating layer 39. An insulating layer 44 is provided on the common electrode 42C. An insulating layer 44 is provided inside the contact hole. By forming the insulating layer 44 from a silicon nitride film, it is possible to suppress the intrusion of moisture from the contact hole through the insulating layer 44. A pixel electrode 46P is provided on the insulating layer 44 and inside the contact hole. The pixel electrode 46P is connected to the drain electrode 32D.

[0145] In addition, wiring 12C is provided on substrate 11, and is connected to wiring 32C via contact holes provided in gate insulating layers 14 and 16. Wiring 12C and wiring 32C function as capacitor wiring. In addition, electrode 46C is provided on insulating layer 39 and inside the opening. Common electrode 42C, insulating layer 44 and electrode 46C form a holding capacitor 350.

[0146] In this embodiment, the semiconductor device 10 is used for the pixel circuit 301 , but the semiconductor device 10 may be used for a peripheral circuit including the source driver circuit 302 and the gate driver circuit 303 .

[0147] <Fourth embodiment>

[0148] Reference Fig. 22 and Fig.23 A display device 20 using the semiconductor device 10 according to an embodiment of the present invention will be described. In this embodiment, a circuit configuration in which the semiconductor device 10 described in the first embodiment is applied to an organic EL display device will be described. Fig.18 and Fig.19 The same as shown, so the description is omitted.

[0149] [Pixel Circuit 301 of Display Device 20]

[0150] Fig. 22 1 is a circuit diagram showing a pixel circuit of a display device 20 according to an embodiment of the present invention. Fig. 22As shown, the pixel circuit 301 includes components such as a driving transistor 110, a selection transistor 120, a holding capacitor 210, and a light-emitting element DO. The driving transistor 110 and the selection transistor 120 have the same structure as the semiconductor device 10. The source electrode of the selection transistor 120 is connected to the signal line 211, and the gate electrode of the selection transistor 120 is connected to the gate line 212. The source electrode of the driving transistor 110 is connected to the anode power line 213, and the drain electrode of the driving transistor 110 is connected to one end of the light-emitting element DO. The other end of the light-emitting element DO is connected to the cathode power line 214. The gate electrode of the driving transistor 110 is connected to the drain electrode of the selection transistor 120. The holding capacitor 210 is connected to the gate electrode and the drain electrode of the driving transistor 110. A grayscale signal that determines the light intensity of the light-emitting element DO is supplied to the signal line 211. A signal for selecting a pixel row in which the grayscale signal is written is supplied to the gate line 212.

[0151] [Cross-sectional structure of display device 20]

[0152] Fig.23 It is a schematic cross-sectional view showing the structure of a display device 20 according to one embodiment of the present invention. Fig.23 The display device 20 shown in FIG. Fig.21 The display device 20 shown is similar, Fig.23 The structure of the display device 20 shown above the insulating layer 39 is similar to Fig.21 The structure of the display device 20 shown above the insulating layer 39 is different. Fig.23 In the configuration of the display device 20 shown in FIG. Fig.21 The display device 20 shown has the same configuration, and the description thereof is omitted, and the differences between the two are described below.

[0153] like Fig.23 As shown, the display device 20 has a pixel electrode 390, a light-emitting layer 392 and a common electrode 394 (light-emitting element DO) above the insulating layer 39. The pixel electrode 390 is arranged on the insulating layer 39 and inside the contact hole, wherein the contact hole is formed in the interlayer insulating layers 34, 38 and the insulating layer 39. An insulating layer 362 is arranged on the pixel electrode 390. An opening 363 is arranged in the insulating layer 362. The opening 363 corresponds to the light-emitting area. That is, the insulating layer 362 defines the pixel. The light-emitting layer 392 and the common electrode 394 are arranged on the pixel electrode 390 exposed through the opening 363. The pixel electrode 390 and the light-emitting layer 392 are separately arranged for each pixel. On the other hand, the common electrode 394 is commonly arranged for a plurality of pixels. Different materials are used for the light-emitting layer 392 according to the display color of the pixel.

[0154] In the second embodiment and the third embodiment, the semiconductor device 10 described in the first embodiment is applied to the configuration of a liquid crystal display device and an organic EL display device. However, the semiconductor device 10 can also be applied to display devices other than these display devices (for example, self-luminous display devices or electronic paper display devices other than organic EL display devices). In addition, the semiconductor device 10 can be applied to small and medium-sized display devices to large display devices without particular limitation. In addition, even when a large-area substrate is used for manufacturing, the deviation of the shape of the oxide semiconductor layer 26 in the semiconductor device 10 is small. Therefore, when the semiconductor device 10 is applied to the display device 20, the display unevenness can be reduced. In addition, the yield rate when manufacturing the display device 20 can be improved.

[0155] Example

[0156] [Sample production]

[0157] Five semiconductor devices (Samples 1 to 5) were manufactured using the method for manufacturing the semiconductor device 10A described in the second embodiment.

[0158] The different manufacturing conditions in Samples 1 to 5 are shown in Table 1. The manufacturing conditions other than the manufacturing conditions shown in Table 1 are common to Samples 1 to 5. Specifically, a gate electrode 12GE is formed on a glass substrate, and gate insulating layers 14 and 16 are formed on the gate electrode 12GE. A 3nm metal oxide film 18 (aluminum oxide) and a 30nm oxide semiconductor film 22 are formed on the gate insulating layers 14 and 16. The oxide semiconductor layer 24 is formed by patterning the oxide semiconductor film 22, and a polycrystalline oxide semiconductor layer 26 (Poly-OS) is formed by performing OS annealing with a temperature controlled in the range of 350°C to 450°C. In addition, the metal oxide film 18 is patterned using the oxide semiconductor layer 26 as a mask to form a metal oxide layer 28.

[0159] A conductive film is formed on the oxide semiconductor layer 26, and a source electrode 32S and a drain electrode 32D are formed by wet etching. Next, a silicon oxide layer is formed as an interlayer insulating layer 34, and then a 10 nm metal oxide film 36 (aluminum oxide) is formed. After oxidation annealing, the metal oxide film 36 is removed. Finally, an interlayer insulating layer 38 is formed on the interlayer insulating layer 34.

[0160] [Table 1]

[0161]

[0162] The difference in the manufacturing conditions in Table 1 is explained. In Sample 1 and Sample 2, the materials of the source electrode and the drain electrode 32 are different. In addition, in Sample 1 and Sample 2, BCE annealing and BCE plasma treatment are not performed, while in Samples 3 to 5, BCE annealing is performed. In addition, in Sample 3, BCH plasma treatment is not performed, but in Samples 4 and 5, BCH plasma treatment is performed. It should be noted that in the implementation of BCH plasma treatment in Samples 4 and 5, in Sample 4, argon gas (Ar gas) is used for plasma treatment, and in Sample 5, chlorine gas (Cl gas) is used for plasma treatment.

[0163] [Sample Evaluation]

[0164] As an evaluation of the fabricated samples 1 to 5, electrical characteristics were measured and an NBTIS test was performed. The NBTIS test is an accelerated test, so samples 1 to 5 were heated to 85° C. and irradiated with light from the back channel side that was not shielded by the gate electrode 12GE. The evaluation results of samples 1 to 5 are shown in Table 2.

[0165] [Table 2]

[0166] Sample 1 Sample 2 Sample 3 Sample 4 Sample 5 Threshold voltage 0.23V 0.72V 3.39V 3.22V 9.37V S value 0.45V / dec 1.04V / dec 2.47V / dec 1.45V / dec 2.63V / dec Field Effect Mobility <![CDATA[26.8cm 2 / Vs]]> <![CDATA[30.2cm 2 / Vs]]> <![CDATA[25.0cm 2 / Vs]]> <![CDATA[25.7cm 2 / Vs]]> <![CDATA[12.9cm 2 / Vs]]> Offset -12.6V -11.0V -4.4V -6.9V -3.87V

[0167] The “field effect mobility” in Table 2 is the linear field effect mobility when the gate voltage is 20 V. In addition, the “shift” in Table 2 is the shift of the threshold voltage after the stress time (1000 seconds) in the NBTIS test.

[0168] Fig.24 This is a graph showing the correlation between the S value and the shift in threshold voltage and field effect mobility in the NBTIS test. Fig.24 , not only the shift of the threshold voltage (circular mark) and the field effect mobility (triangular mark) are plotted, but also an approximate curve (solid line) of the shift of the threshold voltage with respect to the S value is shown.

[0169] like Fig.24 As shown in the figure, as the S value increases, the shift of the threshold voltage decreases, and the light degradation is suppressed. In addition, if the S value is 2.5V / dec or less, a 20cm 2 / Vs or more field effect mobility. However, simply changing the materials of the source electrode and the drain electrode 32 cannot significantly increase the S value (sample 1 and sample 2). In contrast, if BCH annealing or BCH plasma treatment is performed, the S value can be significantly changed (sample 3 to sample 5). Specifically, if BCH annealing is performed, the S value increases, and if BCH plasma treatment is performed using argon gas, the S value decreases (sample 3 and sample 4). In addition, if BCH plasma treatment using chlorine gas is performed, the S value increases (sample 5). However, if the S value is too large, the field effect mobility is significantly reduced (sample 5).

[0170] according to Fig.24 The evaluation results shown show that when the S value is less than 1.5 V / dec, photodegradation cannot be fully suppressed, and when the S value exceeds 2.5 V / dec, the field effect mobility decreases. Therefore, in the semiconductor device 10A (or the semiconductor device 10), one or both of the BCH plasma treatment and the BCH annealing are performed to adjust the S value range to 1.5 V / dec or more and 2.5 V / dec or less. In this way, the semiconductor device 10A (or the semiconductor device 10) having high field effect mobility and suppressed photodegradation can be obtained.

[0171] As the embodiments of the present invention, the embodiments and variations described above can be implemented in appropriate combination as long as they do not contradict each other. In addition, solutions obtained by adding, deleting, or changing the design of components, or solutions obtained by adding, omitting, or changing conditions of processes based on the semiconductor devices and display devices of the embodiments and variations by those skilled in the art are also included in the scope of the present invention as long as they have the gist of the present invention.

[0172] Even if there are other effects different from the effects brought about by the above-mentioned embodiments, effects that are clear from the description of this specification or effects that can be easily predicted by those skilled in the art should of course be regarded as effects brought about by the present invention.

Claims

1. A semiconductor device comprising: a gate electrode; a gate insulating layer on the gate electrode; An oxide semiconductor layer having a polycrystalline structure on the gate insulating layer; A source electrode and a drain electrode on the oxide semiconductor layer; and an interlayer insulating layer covering the source electrode and the drain electrode and in contact with the oxide semiconductor layer, The S value is 1.5V / dec or more and 2.5V / dec or less.

2. The semiconductor device according to claim 1, wherein: The oxide semiconductor layer comprises: a first region overlapping one of the source electrode and the drain electrode; and a second region in contact with the interlayer insulating layer, The difference between the film thickness of the first region and the film thickness of the second region is 5 nm or less.

3. The semiconductor device according to claim 1, wherein: The oxide semiconductor layer includes indium and at least one metal element different from indium, The ratio of the indium to the indium and the at least one metal element is 50% or more. 4 . The semiconductor device according to claim 1 , further comprising a metal oxide layer between the gate insulating layer and the oxide semiconductor layer.

5. The semiconductor device according to claim 4, wherein: The metal oxide layer has a thickness of 10 nm or less.

6. The semiconductor device according to claim 4, wherein: An end face of the metal oxide layer is substantially consistent with an end face of the oxide semiconductor layer.

7. The semiconductor device according to claim 5, wherein the field effect mobility is 20 cm 2 / Vs or above.

8. A method for manufacturing a semiconductor device, comprising: forming a gate electrode, forming a gate insulating layer on the gate electrode, forming an oxide semiconductor layer having a polycrystalline structure on the gate insulating layer, forming a conductive film on the oxide semiconductor layer, The conductive film is patterned by etching to form a source electrode and a drain electrode, After the source electrode and the drain electrode are formed, an annealing treatment is performed on the surface of the oxide semiconductor layer exposed from the source electrode and the drain electrode. After the annealing process, an interlayer insulating layer is formed which covers the source electrode and the drain electrode and is in contact with the oxide semiconductor layer.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: The S value of the semiconductor device is greater than or equal to 1.5 V / dec and less than or equal to 2.5 V / dec.

10. The method for manufacturing a semiconductor device according to claim 8, wherein: The oxide semiconductor layer comprises: a first region overlapping with one of the source electrode and the drain electrode; and a second region in contact with the interlayer insulating layer, The difference between the film thickness of the first region and the film thickness of the second region is 5 nm or less.

11. The method for manufacturing a semiconductor device according to claim 8, wherein: The oxide semiconductor layer includes indium and at least one metal element different from indium, The ratio of the indium to the indium and the at least one metal element is 50% or more.

12. The method for manufacturing a semiconductor device according to claim 8, wherein: The annealing treatment is performed in an air atmosphere.

13. The method for manufacturing a semiconductor device according to claim 8, wherein: Furthermore, before the annealing treatment, a plasma treatment is performed on the oxide semiconductor layer exposed on the surface using a predetermined gas.

14. The method for manufacturing a semiconductor device according to claim 13, wherein: The specified gas is argon or nitrogen.

15. The method for manufacturing a semiconductor device according to claim 8, further comprising: forming a metal oxide film on the gate insulating layer, The metal oxide film is patterned by etching using the oxide semiconductor layer as a mask, thereby forming a metal oxide layer.

16. The method for manufacturing a semiconductor device according to claim 15, wherein: The metal oxide layer has a thickness of 10 nm or less.

17. The method for manufacturing a semiconductor device according to claim 15, wherein: The field effect mobility of the semiconductor device is 20 cm 2 / Vs or above.

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