Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, a barrier layer is formed on the sidewall of the first work function layer, a second work function layer is formed on the sidewall of the barrier layer, the barrier layer separates the second work function layer and the first work function layer, the elements in the second work function layer are not easy to diffuse into the first work function layer through the barrier layer, so that the problem of electrical parameter mismatch between the first transistor and the second transistor is not easy to occur, when the semiconductor structure works, the first work function layer can well adjust the threshold voltage of the subsequently formed first transistor, the second work function layer can well adjust the threshold voltage of the subsequently formed second transistor, which is beneficial to improve the electrical performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] In semiconductor manufacturing, with the development trend of very large-scale integrated circuits (VLSI), the feature size of integrated circuits continues to shrink. To adapt to the smaller feature size, the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) is also continuously shortened. However, as the channel length of the device shortens, the distance between the source and drain of the device also shortens. Therefore, the gate structure's control over the channel becomes worse, and it becomes increasingly difficult to pinch off the channel with the gate voltage. This makes subthreshold leakage, also known as short channel effects (SCE), more likely to occur.

[0003] Therefore, to reduce the impact of short-channel effects, semiconductor manufacturing processes have gradually transitioned from planar MOSFETs to three-dimensional transistors with higher efficiency, such as FinFETs. To address issues such as leakage current and power consumption, the gate material has also changed from the traditional polysilicon gate to a metal gate.

[0004] Threshold voltage regulation is one of the most challenging aspects of metal-gate technology. Layout-dependent effects (LDEs) often result in different threshold voltages for different transistors in a semiconductor device. Summary of the Invention

[0005] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby optimizing the electrical performance of the semiconductor structure.

[0006] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including adjacent first transistor regions and second transistor regions, the first transistor regions being used to form a first transistor, the second transistor regions being used to form a second transistor, the second transistor having a different doping type than the first transistor; forming a first work function layer on the substrate, the first work function layer covering the first transistor regions and exposing the second transistor regions, the first work function layer being used to adjust the threshold voltage of the first transistor; forming a barrier layer on the sidewalls of the first work function layer; and forming a second work function layer on the substrate of the first work function layer, the barrier layer, and the second transistor regions, the second work function layer being used to adjust the threshold voltage of the second transistor.

[0007] Accordingly, embodiments of the present invention also provide a semiconductor structure, comprising: a substrate, the substrate including adjacent first transistor regions and second transistor regions, the first transistor regions being used to form a first transistor, the second transistor regions being used to form a second transistor, the second transistor having a different doping type than the first transistor; a first work function layer located on the substrate, the first work function layer covering the first transistor regions and exposing the second transistor regions, the first work function layer being used to adjust the threshold voltage of the first transistor; a barrier layer located on the sidewall of the first work function layer; and a second work function layer covering the first work function layer, the barrier layer, and the substrate of the second transistor regions, the second work function layer being used to adjust the threshold voltage of the second transistor.

[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0009] In the semiconductor structure formation method provided by this invention, a barrier layer is formed on the sidewall of the first work function layer, and a second work function layer is formed on the sidewall of the barrier layer. The barrier layer isolates the second work function layer from the first work function layer. Elements in the second work function layer are less likely to diffuse through the barrier layer into the first work function layer, reducing the probability of metal boundary effects. Therefore, electrical parameter mismatch is less likely to occur between the first transistor and the second transistor. When the semiconductor structure is working, the first work function layer can effectively regulate the threshold voltage of the subsequently formed first transistor, and the second work function layer can effectively regulate the threshold voltage of the subsequently formed second transistor, which is beneficial to improving the electrical performance of the semiconductor structure.

[0010] In an optional embodiment, the method for forming the semiconductor structure further includes: after providing the substrate and before forming the first work function layer, forming a gate dielectric layer on the substrate of the first transistor region and the second transistor region; in the step of forming the first work function layer, the first work function layer is formed on the gate dielectric layer; in the step of forming the second work function layer, the second work function layer is formed on the first work function layer and the exposed gate dielectric layer of the first work function layer. The barrier layer on the sidewall of the first work function layer increases the lateral spacing between the first work function layer in the first transistor region and the second work function layer in the second transistor region, thereby increasing the lateral spacing between the elements diffusing from the second work function layer to the gate dielectric layer in the second transistor region and the gate dielectric layer in the first transistor region. This makes it less likely for the elements in the gate dielectric layer in the second transistor region to diffuse into the gate dielectric layer in the first transistor region, reducing the probability of metal boundary effects. Therefore, the problem of electrical parameter mismatch between the first transistor and the second transistor is less likely to occur. When the semiconductor structure is working, the first work function layer can effectively regulate the threshold voltage of the subsequently formed first transistor, and the second work function layer can effectively regulate the threshold voltage of the subsequently formed second transistor, which is beneficial to improving the electrical performance of the semiconductor structure. Attached Figure Description

[0011] Figures 1 to 5 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0012] Figures 6 to 20 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure according to the invention. Detailed Implementation

[0013] As the background technology shows, the devices currently being fabricated still suffer from poor performance. This paper analyzes the reasons for this poor performance by examining a semiconductor structure fabrication method.

[0014] refer to Figures 1 to 5 The diagram shows a schematic representation of each step in a method for forming a semiconductor structure.

[0015] like Figure 1As shown, the steps for forming the semiconductor structure include: providing a substrate 2 and a fin 1 located on the substrate 2, the substrate 2 including an N-type transistor region II and a P-type transistor region I, the N-type transistor region II being used to form an NMOS transistor and the P-type transistor region I being used to form a PMOS transistor; forming an isolation structure 3 on the substrate 2 exposed by the fin 1; forming a dummy gate structure (not shown in the figure) across the fin 1 on the substrate 2, the dummy gate structure covering part of the top wall and part of the sidewall of the fin 1; forming an interlayer dielectric layer (not shown in the figure) on the substrate 2 exposed by the dummy gate structure, the interlayer dielectric layer covering the sidewall of the dummy gate structure; removing the dummy gate structure, and forming a gate opening 4 in the interlayer dielectric layer, the gate opening 4 exposing the N-type transistor region II and the P-type transistor region I.

[0016] like Figure 2 As shown, a gate dielectric layer 5 is formed on the fin 1 and the isolation structure 3 exposed by the gate opening 4.

[0017] like Figure 3 As shown, a P-type work function layer 6 is formed on the gate dielectric layer 5 of the P-type transistor region I within the gate opening 4. The material of the P-type work function layer 6 includes TiN.

[0018] like Figure 4 As shown, an N-type work function layer 7 is formed on the gate dielectric layer 5 of the P-type work function layer 6 and the exposed N-type transistor region II of the P-type work function layer 6.

[0019] The material of the N-type work function layer 7 includes TiAl.

[0020] like Figure 5 As shown, a gate layer 8 covering the N-type work function layer 7 is formed on the N-type transistor region II and the P-type transistor region I exposed by the gate opening 4. The gate dielectric layer 5, the P-type work function layer 6, the N-type work function layer 7 and the gate layer 8 serve as the gate structure 10.

[0021] In the aforementioned semiconductor structure, the NMOS transistor and the PMOS transistor share the same gate structure 10. At the boundary between the N-type transistor region II and the P-type transistor region I, the N-type work function layer 7 is directly formed on the sidewall of the P-type work function layer 6. There is an N / P boundary interface between the N-type work function layer 7 and the P-type work function layer 6. The Al element in the N-type work function layer 7 diffuses through the N / P boundary into the P-type work function layer 6, causing the threshold voltages of both the PMOS transistor and the NMOS transistor to increase simultaneously.

[0022] Furthermore, the N-type work function layer 7 is formed on the gate dielectric layer 5 of the N-type transistor region II. The Al element in the N-type work function layer 7 diffuses into the gate dielectric layer 5 of the N-type transistor region II, and the Al element diffused into the gate dielectric layer 5 of the N-type transistor region II diffuses into the gate dielectric layer 5 of the P-type transistor region I, thereby increasing the threshold voltage of both the PMOS transistor and the NMOS transistor.

[0023] The diffusion paths of Al elements in the two types of N-type work function layers 7 mentioned above are called the Metal Boundary Effect (MBE). Both of them lead to a worsening of the electrical parameter mismatch between PMOS and NMOS devices, thereby affecting the electrical performance of the semiconductor structure.

[0024] To address the aforementioned technical problem, this invention provides a method for forming a semiconductor structure. A barrier layer is formed on the sidewall of the first work function layer, and a second work function layer is formed on the sidewall of the barrier layer. The barrier layer isolates the second work function layer from the first work function layer. Elements in the second work function layer are less likely to diffuse through the barrier layer into the first work function layer. Therefore, electrical parameter mismatch is less likely to occur between the first transistor and the second transistor. When the semiconductor structure is operating, the first work function layer can effectively regulate the threshold voltage of the subsequently formed first transistor, and the second work function layer can effectively regulate the threshold voltage of the subsequently formed second transistor, which is beneficial for improving the electrical performance of the semiconductor structure.

[0025] To make the above-mentioned objectives, features and advantages of the embodiments of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0026] Figures 6 to 20 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure according to the invention.

[0027] refer to Figures 6 to 8 A substrate is provided, the substrate including an adjacent first transistor region I and a second transistor region II, the first transistor region I being used to form a first transistor, the second transistor region II being used to form a second transistor, the second transistor being of a different doping type than the first transistor.

[0028] In this embodiment, the different doping types of the second transistor and the first transistor refer to the fact that the doping ion types of the source and drain doping layers in the first transistor are different from those in the second transistor.

[0029] Specifically, the first transistor region I is used to form a P-type transistor; the second transistor region II is used to form an N-type transistor. As an example, the P-type transistor formed in the first transistor region I is a pull-up transistor for Static Random-Access Memory (SRAM), and the N-type transistor formed in the second transistor region II is a pull-down transistor for SRAM.

[0030] like Figure 6 As shown, the step of providing the substrate includes: providing a substrate 100 and a channel structure 101 located on the substrate 100.

[0031] In this embodiment, the substrate 100 is made of silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium. The substrate 100 may also be a silicon substrate on an insulator or a germanium substrate on an insulator.

[0032] In this embodiment, the semiconductor structure formation method is used to form a FinField-Effect Transistor (FinFET), and the channel structure 101 includes fins. The material of the fins includes silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ide. In other embodiments, the semiconductor structure formation method is used to form a Gate-All-Around (GAA) transistor, and the channel structure 101 may further include a plurality of channel layers spaced apart in a direction perpendicular to the surface of the substrate 100.

[0033] The step of providing the substrate further includes: forming an isolation structure 102 (e.g., on the substrate 100 exposed by the channel structure 101) on the substrate 100. Figure 6 As shown, the isolation structure 102 covers a portion of the sidewall of the channel structure 101, and the top of the isolation structure 102 is lower than the top of the channel structure 101. The isolation structure 102 is used to electrically isolate adjacent channel structures 101 and adjacent devices.

[0034] The material of the isolation structure 102 is silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the isolation structure 102 is silicon oxide.

[0035] like Figure 7 As shown, a pseudo-gate structure 103 is formed across the channel structure 101 on the substrate 100, and the pseudo-gate structure 103 covers part of the top wall and part of the side wall of the channel structure 101; an interlayer dielectric layer 104 is formed on the substrate 100 where the pseudo-gate structure is exposed, and the interlayer dielectric layer 104 covers the side wall of the pseudo-gate structure 103.

[0036] The dummy gate structure 103 occupies space for the metal gate structure formed in subsequent processes. The dummy gate structure 103 includes a dummy gate oxide layer that conformally covers part of the top surface and part of the sidewalls of the channel structure 101, and the dummy gate structure 103 also includes a dummy gate layer located on the dummy gate oxide layer.

[0037] In this embodiment, the pseudo-gate structure 103 is a stacked structure. In other embodiments, the pseudo-gate structure may also be a single-layer structure, that is, the pseudo-gate material structure only includes the pseudo-gate layer.

[0038] Specifically, the step of forming the dummy gate structure 103 includes: forming a conformally conformally covering dummy gate oxide material layer (not shown in the figure) covering the channel structure 101, and then forming a dummy gate material layer (not shown in the figure) spanning the channel structure 101 on the dummy gate oxide material layer. The dummy gate material layer and the dummy gate oxide material layer are etched to form a dummy gate oxide layer and a dummy gate layer located on the dummy gate oxide layer, the dummy gate oxide layer and the dummy gate layer covering a portion of the top and a portion of the sidewalls of the channel structure 101.

[0039] In this embodiment, the material of the dummy gate oxide layer is silicon oxide. In other embodiments, the material of the dummy gate oxide layer may also be silicon oxynitride.

[0040] In this embodiment, the dummy gate layer is made of polycrystalline silicon. In other embodiments, the dummy gate layer may also be made of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, or amorphous carbon.

[0041] The interlayer dielectric layer 104 is used to isolate adjacent devices. The material of the interlayer dielectric layer 104 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the interlayer dielectric layer 104 is silicon oxide.

[0042] It should be noted that the method for forming the semiconductor structure further includes: after forming the dummy gate structure and before forming the interlayer dielectric layer 104, forming source / drain doped layers (not shown in the figure) in the channel structures 101 on both sides of the dummy gate structure. Subsequently, the dummy gate structure 103 will be replaced with a metal gate structure. When the semiconductor structure is working, the source / drain doped layers provide stress to the channel below the metal gate structure.

[0043] In this embodiment, the dopant ion types of the source and drain doped layers of the first transistor and the second transistor are different. Specifically, the dopant ions of the source and drain doped layers of the first transistor include one or more of B, Ga, and In, while the dopant ions of the source and drain doped layers of the second transistor include one or more of P, As, and Sb.

[0044] like Figure 8 As shown, after forming the interlayer dielectric layer 104, the dummy gate structure 103 is removed, and a gate opening 105 is formed in the interlayer dielectric layer 104, the gate opening 105 exposing the first transistor region I and the second transistor region II.

[0045] The gate opening 105 provides space for the subsequent formation of the metal gate structure. The gate opening 105 exposes the first transistor region I and the second transistor region II. The corresponding metal gate structure subsequently formed in the gate opening 105 is located on the first transistor region I and the second transistor region II.

[0046] In this embodiment, the extending direction of the gate opening 105 is perpendicular to the extending direction of the boundary between the first transistor region I and the second transistor region II. Correspondingly, the extending direction of the metal gate structure subsequently formed in the gate opening 105 is perpendicular to the extending direction of the boundary between the first transistor region I and the second transistor region II.

[0047] refer to Figures 9 to 12 As shown, Figure 9 yes Figure 8 A partially enlarged schematic diagram of the area within the dashed box. A first work function layer 106 is formed on the substrate (e.g., ...). Figure 12 As shown), the first work function layer 106 covers the first transistor region I and exposes the second transistor region II. The first work function layer 106 is used to adjust the threshold voltage of the first transistor.

[0048] The first transistor is a P-type transistor, and the corresponding first work function layer 106 is used to adjust the threshold voltage of the P-type transistor.

[0049] In this embodiment, the step of forming the first work function layer 106 on the substrate includes: forming a first work function material layer 107 (such as...) on the substrate. Figure 11 As shown in the figure, the first work function material layer 107 covers the first transistor region I and the second transistor region II; a first mask layer (not shown in the figure) is formed on the first work function material layer 107, the first mask layer covers the first transistor region I and exposes the second transistor region II; the first work function material layer 107 is etched with the first mask layer as a mask to form the first work function layer 106.

[0050] In this embodiment, the material of the first work function layer 106 is a P-type work function material. Specifically, the material of the first work function layer 106 is TiN or TaN.

[0051] In this embodiment, the first work function material layer 107 can be formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0052] It should be noted that in the step of forming the first work function material layer 107, the first work function material layer 107 is formed on the bottom surface and sidewall of the gate opening 105. That is to say, the first work function material layer 107 is also formed on the sidewall of the interlayer dielectric layer 104.

[0053] like Figure 10 As shown, the method for forming the semiconductor structure further includes: after providing the substrate and before forming the first work function layer 106, forming a gate dielectric layer 109 on the substrate of the first transistor region I and the second transistor region II.

[0054] The gate dielectric layer 109 is used to achieve electrical isolation between the channel structure 101 and the subsequently formed metal gate structure.

[0055] The step of forming the gate dielectric layer 109 includes forming the gate dielectric layer 109 on the channel structure 101 and the substrate 100 exposed by the channel structure 101.

[0056] The gate dielectric layer 109 is made of a gate dielectric material with a relative permittivity greater than that of silicon oxide. In this embodiment, the gate dielectric layer 109 is made of HfO2. In other embodiments, the gate dielectric layer may also be made of HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, or Al2O3.

[0057] In this embodiment, the gate dielectric layer 109 is formed using atomic layer deposition (ALD). In other embodiments, the gate dielectric layer can also be formed using physical vapor deposition (PVD).

[0058] In this embodiment, in the step of forming the gate dielectric layer 109, the gate dielectric layer 109 is formed on the bottom surface and sidewall of the gate opening 105, that is, the gate dielectric layer 109 is also formed on the sidewall of the interlayer dielectric layer 104.

[0059] It should be noted that, in the step of forming the first work function layer 106, the first work function layer 106 is also formed on the gate dielectric layer 109 on the sidewall of the interlayer dielectric layer 104.

[0060] The method for forming the semiconductor structure further includes: after forming the gate dielectric layer 109 and before forming the first work function layer 106, forming an etch-resistant layer 110 covering the gate dielectric layer 109 (e.g., ...). Figure 10 (As shown).

[0061] During the etching of the first work function material layer 107 to form the first work function layer 106, the etch-resistant layer 110 acts as an etching stop, preventing etching damage to the gate dielectric layer 109. The etch-resistant layer 110 also acts as an etching stop in the subsequent formation of the barrier layer, protecting the gate dielectric layer 109 from etching damage.

[0062] The etch-resistant layer 110 is made of a different material than the first work function layer 106. During the etching step of the first work function material layer 107, the etching rate of the etch-resistant layer 110 is lower than the etching rate of the first work function material layer 107. In this embodiment, the material of the etch-resistant layer 110 is TaN.

[0063] In this embodiment, the etching-resistant layer 110 is formed using atomic layer deposition or chemical vapor deposition.

[0064] In this embodiment, in the step of forming the etch-resistant layer 110, the etch-resistant layer 110 is formed on the bottom surface and sidewall of the gate opening 105. That is, the etch-resistant layer 110 is formed on the substrate of the first transistor region I and the second transistor region II, and on the sidewall of the interlayer dielectric layer 104. Specifically, the etch-resistant layer 110 is formed on the gate dielectric layer 109.

[0065] Continue to refer to Figure 10 The method for forming the semiconductor structure further includes: after forming the gate dielectric layer 109 and before forming the etch-resistant layer 110, forming a barrier layer 111 covering the gate dielectric layer 109.

[0066] Subsequently, a first work function layer 106 and a second work function layer 108 are formed on the barrier layer 111. The barrier layer 111 is used to prevent elements in the first work function layer 106 and the second work function layer 108 from diffusing into the gate dielectric layer 109.

[0067] In this embodiment, the barrier layer 111 is made of TiN. In other embodiments, the barrier layer can be made of other materials such as Ta, Ti, ZrN, and ZrTiN.

[0068] In this embodiment, the barrier layer 111 is formed using physical vapor deposition. In other embodiments, the barrier layer may also be formed using chemical vapor deposition or atomic layer deposition.

[0069] In this embodiment, in the step of forming the barrier layer 111, the barrier layer 111 is formed on the bottom surface and sidewall of the gate opening 105. That is, the barrier layer 111 is formed on the substrate of the first transistor region I and the second transistor region II, and on the sidewall of the interlayer dielectric layer 104. Specifically, the barrier layer 111 is formed on the gate dielectric layer 109.

[0070] refer to Figures 13 to 16 ,in, Figure 15 yes Figure 14 A magnified view of a portion of the image. Figure 16 yes Figure 15 A cross-sectional view at point AA. A barrier layer 112 is formed on the sidewall of the first work function layer 106 (e.g., ...). Figure 15 (As shown).

[0071] A barrier layer 112 is formed on the sidewall of the first work function layer 106. Subsequently, a second work function layer is formed on the sidewall of the barrier layer 112. The barrier layer 112 isolates the second work function layer from the first work function layer 106. Elements in the second work function layer are less likely to diffuse through the barrier layer 112 into the first work function layer 106, reducing the probability of metal boundary effects. Therefore, electrical parameter mismatch is less likely to occur between the first transistor and the second transistor. When the semiconductor structure is working, the first work function layer 106 can effectively regulate the threshold voltage of the subsequently formed first transistor, and the second work function layer can effectively regulate the threshold voltage of the subsequently formed second transistor, which is beneficial to improving the electrical performance of the semiconductor structure.

[0072] Furthermore, the barrier layer 112 on the sidewall of the first work function layer 106 increases the lateral spacing between the first work function layer 106 in the first transistor region I and the second work function layer II in the second transistor region II. As a result, the lateral spacing between the elements diffusing from the second work function layer to the gate dielectric layer in the second transistor region II and the gate dielectric layer 109 in the first transistor region I is larger. This makes it less likely for the elements in the gate dielectric layer 109 in the second transistor region II to diffuse into the gate dielectric layer 109 in the first transistor region I, reducing the probability of metal boundary effects. Therefore, the problem of electrical parameter mismatch between the first transistor and the second transistor is less likely to occur. When the semiconductor structure is working, the first work function layer 106 can effectively regulate the threshold voltage of the subsequently formed first transistor, and the second work function layer can effectively regulate the threshold voltage of the subsequently formed second transistor, which is beneficial to improving the electrical performance of the semiconductor structure.

[0073] In this embodiment, when the temperature exceeds 400°C, the diffusion coefficient of the elements in the second work function layer 108 in the barrier layer 112 is less than 5.6 × 10⁻⁶. -22 m 2 / s. Generally, the higher the temperature, the stronger the diffusion ability of elements in the second work function layer 108. If the temperature exceeds 400℃, the diffusion coefficient of elements in the second work function layer 108 in the barrier layer 112 becomes too high, for example, greater than 5.6 × 10⁻⁶. -22 m 2 At a speed of / s, elements in the second work function layer 108 may pass through the barrier layer 112 and enter the first work function layer 106, which may lead to electrical parameter mismatch between the first transistor and the second transistor.

[0074] Specifically, the material of the barrier layer 112 includes TaN or W.

[0075] In this embodiment, the step of forming a barrier layer 112 on the sidewall of the first work function layer 106 includes: forming a barrier material layer 113 (such as...) on the first work function layer 106 and the substrate exposed by the first work function layer 106. Figure 13 (As shown); Remove the barrier material layer 113 on the top of the first work function layer 106 and on the substrate, and the remaining barrier material layer 113 located on the sidewall of the first work function layer 106 serves as the barrier layer 112.

[0076] In this embodiment, the barrier material layer 113 is formed using atomic layer deposition (ALD). ALD involves multiple ALD cycles, facilitating precise control of the thickness of the barrier material layer 113 and improving its thickness uniformity. Furthermore, ALD offers good gap-filling performance and step coverage, thereby enhancing the conformal coverage capability of the barrier material layer 113, ensuring it conformally covers the first work function layer 106 and exposes the etch-resistant layer 110. In other embodiments, the barrier material layer can also be formed using chemical vapor deposition (CVD).

[0077] It should be noted that, taking the direction perpendicular to the sidewall of the first work function layer 106 as the lateral direction, the lateral dimension of the barrier layer 112 should not be too large or too small. If the lateral dimension of the barrier layer 112 is too large, it will require more processing time and materials to form the barrier material layer 113, and more time to etch the barrier material layer 113 to form the barrier layer 112, which is not conducive to improving the formation efficiency of the semiconductor structure. If the lateral dimension of the barrier layer 112 is too small, it is easy for the barrier layer 112 to fail to effectively block the diffusion of elements in the second work function layer subsequently formed on the sidewall of the barrier layer 112 into the first work function layer 106, which is prone to metal boundary effects. The first work function layer 106 cannot effectively regulate the threshold voltage of the subsequently formed first transistor, resulting in an electrical parameter mismatch between the first transistor and the second transistor, leading to poor electrical performance of the final semiconductor structure. In this embodiment, the lateral dimension of the barrier layer 112 is 10 angstroms to 150 angstroms, with the direction perpendicular to the sidewall of the first work function layer 106 as the lateral direction.

[0078] refer to Figure 17 and Figure 18 A second work function layer 108 is formed on the substrate of the first work function layer 106, the barrier layer 112, and the second transistor region II. The second work function layer 108 is used to adjust the threshold voltage of the second transistor.

[0079] The second transistor is an N-type transistor, and the corresponding second work function layer 108 is used to adjust the threshold voltage of the N-type transistor.

[0080] In this embodiment, the second work function layer 108 can be formed using chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0081] In this embodiment, the material of the second work function layer 108 is an N-type work function material. The material of the second work function layer 108 includes one or more of TiAl, TaAlN, and TiAlN.

[0082] It should be noted that, in the step of forming the second work function layer 108, the second work function layer 108 is also formed on the sidewall of the interlayer dielectric layer 104 exposed by the gate opening 105.

[0083] refer to Figure 19 and Figure 20 , Figure 20 yes Figure 19 The enlarged view shows that the method for forming the semiconductor structure further includes: after forming the second work function layer 108, forming a gate layer 114 in the gate opening 105.

[0084] The gate layer 114, together with the first work function layer 106 and the second work function layer 108, forms a metal gate structure.

[0085] In this embodiment, the gate layer 114 is made of a magnesium-tungsten alloy. In other embodiments, the metal gate structure may also be made of W, Cu, Ag, Au, Pt, Ni, or Ti, etc.

[0086] Accordingly, embodiments of the present invention also provide a semiconductor structure. (See reference...) Figure 19 and Figure 20 The diagram shows a schematic representation of an embodiment of the semiconductor structure of the present invention.

[0087] The semiconductor structure includes: a substrate comprising adjacent first transistor region I and second transistor region II, the first transistor region I being used to form a first transistor, and the second transistor region II being used to form a second transistor, the second transistor having a different doping type than the first transistor; a first work function layer 106 located on the substrate, the first work function layer 106 covering the first transistor region I and exposing the second transistor region II, the first work function layer 106 being used to adjust the threshold voltage of the first transistor; a barrier layer 112 located on the sidewall of the first work function layer 106; and a second work function layer 108 covering the first work function layer 106, the barrier layer 112, and the substrate of the second transistor region II, the second work function layer 108 being used to adjust the threshold voltage of the second transistor.

[0088] The barrier layer 112 is located on the sidewall of the first work function layer 106. The barrier layer 112 isolates the second work function layer 108 from the first work function layer 106. Elements in the second work function layer 108 are less likely to diffuse through the barrier layer 112 into the first work function layer 106, reducing the probability of metal boundary effects. Therefore, electrical parameter mismatch is less likely to occur between the first transistor and the second transistor. When the semiconductor structure is working, the first work function layer 106 can effectively regulate the threshold voltage of the first transistor, and the second work function layer 108 can effectively regulate the threshold voltage of the second transistor, which is beneficial to improving the electrical performance of the semiconductor structure.

[0089] In this embodiment, the different doping types of the second transistor and the first transistor refer to the fact that the doping ion types of the source and drain doping layers in the first transistor are different from those in the second transistor.

[0090] Specifically, the first transistor is a P-type transistor, which is a pull-up transistor for static random-access memory (SRAM), and the second transistor is an N-type transistor, which is a pull-down transistor for static random-access memory.

[0091] In this embodiment, the substrate includes a substrate 100 and a channel structure 101 located on the substrate 100.

[0092] In this embodiment, the substrate 100 is made of silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium. The substrate 100 may also be a silicon substrate on an insulator or a germanium substrate on an insulator.

[0093] In this embodiment, the semiconductor structure includes a FinFET (Fin Field-Effect Transistor), and the channel structure 101 includes fins. The material of the fins includes silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ide. In other embodiments, the semiconductor structure includes a gate-all-around (GAA) transistor, and the channel structure 101 may further include a plurality of channel layers spaced apart in a direction perpendicular to the surface of the substrate 100.

[0094] The substrate further includes an isolation structure 102 located on the exposed substrate 100 of the channel structure 101. The isolation structure 102 covers a portion of the sidewall of the channel structure 101, and the top of the isolation structure 102 is lower than the top of the channel structure 101. The isolation structure 102 is used for electrical isolation between adjacent channel structures 101 and adjacent devices.

[0095] The material of the isolation structure 102 is silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the isolation structure 102 is silicon oxide.

[0096] The semiconductor structure further includes: an interlayer dielectric layer 104 (e.g., ... Figure 8 As shown), located on the substrate 100 and the channel structure 101, the interlayer dielectric layer 104 includes a gate opening 105 that exposes a portion of the substrate 100 and the channel structure 101 (as shown). Figure 8 As shown), the gate opening 105 exposes the first transistor region I and the second transistor region II.

[0097] It should be noted that the extending direction of the gate opening 105 is perpendicular to the extending direction of the junction of the first transistor region I and the second transistor region II.

[0098] The interlayer dielectric layer 104 is used to isolate adjacent devices. The material of the interlayer dielectric layer 104 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the interlayer dielectric layer 104 is silicon oxide.

[0099] It should be noted that, taking the direction perpendicular to the sidewall of the first work function layer 106 as the lateral direction, the lateral dimension of the barrier layer 112 should not be too large or too small. If the lateral dimension of the barrier layer 112 is too large, excessive processing time and materials will be required, which is not conducive to improving the formation efficiency of the semiconductor structure. If the lateral dimension of the barrier layer 112 is too small, the barrier layer 112 will not be able to effectively prevent the elements in the second work function layer 108 from diffusing into the first work function layer 106. The first work function layer 106 will not be able to effectively regulate the threshold voltage of the first transistor, resulting in an electrical parameter mismatch between the first transistor and the second transistor, leading to poor electrical performance of the semiconductor structure. In this embodiment, taking the direction perpendicular to the sidewall of the first work function layer 106 as the lateral direction, the lateral dimension of the barrier layer 112 is 10 angstroms to 150 angstroms.

[0100] In this embodiment, generally, the higher the temperature, the stronger the diffusion ability of the elements in the second work function layer 108. If the temperature exceeds 400°C, the diffusion coefficient of the elements in the second work function layer 108 in the barrier layer 112 becomes too high, for example, greater than 5.6 × 10⁻⁶. -22 m 2 At a speed of / s, elements in the second work function layer 108 may pass through the barrier layer 112 and enter the first work function layer 106, which may lead to electrical parameter mismatch between the first transistor and the second transistor.

[0101] Specifically, the material of the barrier layer 112 includes TaN or W.

[0102] The semiconductor structure further includes a gate dielectric layer 109 located on the substrate of the first transistor region I and the second transistor region II.

[0103] The gate dielectric layer 109 serves as an electrical isolation layer.

[0104] Specifically, the gate dielectric layer 109 is formed on the substrate of the first transistor region I and the second transistor region II exposed by the gate opening 105, and on the sidewall of the interlayer dielectric layer 104.

[0105] The gate dielectric layer 109 is made of a gate dielectric material with a relative permittivity greater than that of silicon oxide. In this embodiment, the gate dielectric layer 109 is made of HfO2. In other embodiments, the gate dielectric layer may also be made of HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, or Al2O3.

[0106] The first transistor is a P-type transistor, and the corresponding first work function layer 106 is used to adjust the threshold voltage of the P-type transistor.

[0107] In this embodiment, the material of the first work function layer 106 is a P-type work function material. Specifically, the material of the first work function layer 106 is TiN or TaN.

[0108] It should be noted that the first work function layer 106 is located in the first transistor region I exposed by the gate opening 105. Correspondingly, the first work function layer 106 is located on the gate dielectric layer 109 of the first transistor region I, specifically on the gate dielectric layer 109 on the substrate and on the gate dielectric layer 109 on the sidewall of the interlayer dielectric layer 104.

[0109] Furthermore, the barrier layer 112 on the sidewall of the first work function layer 106 increases the lateral spacing between the first work function layer 106 in the first transistor region I and the second work function layer 108 in the second transistor region II. As a result, the lateral spacing between the elements diffusing from the second work function layer 108 to the gate dielectric layer in the second transistor region II and the gate dielectric layer in the first transistor region I is larger, making it less likely for the elements in the gate dielectric layer in the second transistor region II to diffuse into the gate dielectric layer in the first transistor region I. This reduces the probability of metal boundary effects. Therefore, the electrical parameter mismatch problem between the first transistor and the second transistor is less likely to occur. When the semiconductor structure is working, the first work function layer 106 can effectively regulate the threshold voltage of the first transistor, and the second work function layer 108 can effectively regulate the threshold voltage of the second transistor, which is beneficial to improving the electrical performance of the semiconductor structure.

[0110] The second transistor is an N-type transistor, and the corresponding second work function layer 108 is used to adjust the threshold voltage of the N-type transistor.

[0111] In this embodiment, the material of the second work function layer 108 is an N-type work function material. Specifically, the material of the second work function layer 108 includes one or more of TiAl, TaAlN, and TiAlN.

[0112] The second work function layer 108 is located on the first work function layer 106 of the first transistor region I and the gate dielectric layer 109 of the second transistor region II. Specifically, the second work function layer 108 is located on the gate dielectric layer 109 of the first transistor region I and the second transistor region II exposed by the gate opening 105.

[0113] It should be noted that the second work function layer 108 is also located on the sidewall of the interlayer dielectric layer 104 exposed by the gate opening 105.

[0114] The semiconductor structure further includes a gate layer 114, located on the first work function layer 106 and the second work function layer 108 of the gate opening 105.

[0115] The gate layer 114, together with the first work function layer 106 and the second work function layer 108, forms a metal gate structure.

[0116] In this embodiment, the gate layer 114 is made of a magnesium-tungsten alloy. In other embodiments, the metal gate structure may also be made of W, Cu, Ag, Au, Pt, Ni, or Ti, etc.

[0117] The semiconductor structure further includes a barrier layer 111 located on the gate dielectric layer 109.

[0118] The barrier layer 111 is used to block the diffusion of elements in the first work function layer 106 and the second work function layer 108 into the gate dielectric layer 109.

[0119] In this embodiment, the barrier layer 111 is made of TiN. In other embodiments, the barrier layer can be made of other materials such as Ta, Ti, ZrN, and ZrTiN.

[0120] In this embodiment, the barrier layer 111 is located on the bottom surface and sidewall of the gate opening 105. Specifically, the barrier layer 111 is located on the substrate of the first transistor region I and the second transistor region II, as well as on the sidewall of the interlayer dielectric layer 104.

[0121] The semiconductor structure further includes an etch-resistant layer 110 located between the first work function layer and the gate dielectric layer in the first transistor region, and between the second work function layer and the gate dielectric layer in the second transistor region.

[0122] The anti-etching layer 110 is used to stop etching during the formation of the barrier layer 112 and also to protect the gate dielectric layer 109 from etching damage.

[0123] The etching resistance layer 110 is made of a different material than the first work function layer 106. In this embodiment, the etching resistance layer 110 is made of TaN.

[0124] Specifically, the etch-resistant layer 110 is located between the first work function layer 106 and the barrier layer 111 in the first transistor region I, and between the second work function layer 108 and the barrier layer 111 in the second transistor region II.

[0125] The semiconductor structure can be formed using the formation method described in the foregoing embodiments, or it can be formed using other formation methods. For a detailed description of the semiconductor structure described in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments; these descriptions will not be repeated here.

[0126] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including an adjacent first transistor region and a second transistor region, the first transistor region being used to form a first transistor, the second transistor region being used to form a second transistor, the second transistor being of a different doping type than the first transistor; A first work function layer is formed on the substrate, the first work function layer covers the first transistor region and exposes the second transistor region, and the first work function layer is used to adjust the threshold voltage of the first transistor; A barrier layer is formed on the sidewall of the first work function layer; A second work function layer is formed on the substrate of the first work function layer, the barrier layer, and the second transistor region. The second work function layer is used to adjust the threshold voltage of the second transistor. When the temperature exceeds 400°C, the diffusion coefficient of the elements in the second work function layer in the barrier layer is less than 5.6 × 10⁻⁶. -22 m 2 / s.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, With the direction perpendicular to the sidewall of the first work function layer as the lateral direction, the lateral dimension of the barrier layer is 10 angstroms to 150 angstroms.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the barrier layer includes: TaN or W.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming a barrier layer on the sidewall of the first work function layer includes: A barrier material layer is formed on the first work function layer and the substrate exposed by the first work function layer; The barrier material layer on the first work function layer and on the substrate is removed, and the remaining barrier material layer located on the sidewall of the first work function layer is used as the barrier layer.

5. The method for forming a semiconductor structure as described in claim 4, characterized in that, The barrier material layer is formed using atomic layer deposition or chemical vapor deposition.

6. The method for forming a semiconductor structure as described in claim 4, characterized in that, The barrier material layer on the first work function layer and on the substrate is removed using a maskless etching process.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the semiconductor structure further includes: after providing the substrate and before forming the first work function layer, forming a gate dielectric layer on the substrate of the first transistor region and the second transistor region; In the step of forming the first work function layer, the first work function layer is formed on the gate dielectric layer; In the step of forming the second work function layer, the second work function layer is formed on the first work function layer and the gate dielectric layer exposed by the first work function layer.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The method for forming the semiconductor structure further includes: after forming the gate dielectric layer and before forming the first work function layer, forming an etch-resistant layer covering the gate dielectric layer, wherein the etch-resistant layer serves to stop etching during the step of forming the barrier layer.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, The steps for providing the substrate include: A substrate and a channel structure located on the substrate are provided; a pseudo-gate structure is formed on the substrate, spanning the channel structure, the pseudo-gate structure covering a portion of the top wall and a portion of the sidewall of the channel structure; an interlayer dielectric layer is formed on the substrate exposed by the pseudo-gate structure, the interlayer dielectric layer covering the sidewall of the pseudo-gate structure; the pseudo-gate structure is removed, and a gate opening is formed in the interlayer dielectric layer, the gate opening exposing a first transistor region and a second transistor region; In the step of forming the first work function layer, the first work function layer is formed in the first transistor region exposed by the gate opening; In the step of forming the second work function layer, the second work function layer is formed in the first transistor region and the second transistor region exposed at the gate opening; The method for forming the semiconductor structure further includes: after forming the second work function layer, forming a gate layer in the gate opening.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The extension direction of the gate opening is perpendicular to the extension direction of the boundary between the first transistor region and the second transistor region.

11. A semiconductor structure, characterized in that, include: The substrate includes an adjacent first transistor region and a second transistor region, the first transistor region being used to form a first transistor, and the second transistor region being used to form a second transistor, wherein the second transistor has a different doping type than the first transistor; A first work function layer is located on the substrate. The first work function layer covers the first transistor region and exposes the second transistor region. The first work function layer is used to adjust the threshold voltage of the first transistor. The barrier layer is located on the sidewall of the first work function layer; A second work function layer covers the first work function layer, the barrier layer, and the substrate of the second transistor region. This second work function layer is used to adjust the threshold voltage of the second transistor. When the temperature exceeds 400°C, the diffusion coefficient of the elements in the second work function layer within the barrier layer is less than 5.6 × 10⁻⁶. -22 m 2 / s.

12. The semiconductor structure as claimed in claim 11, characterized in that, With the direction perpendicular to the sidewall of the first work function layer as the lateral direction, the lateral dimension of the barrier layer is 10 angstroms to 150 angstroms.

13. The semiconductor structure as described in claim 11, characterized in that, The material of the barrier layer includes: TaN or W.

14. The semiconductor structure as claimed in claim 11, characterized in that, The substrate includes: a substrate; a channel structure located on the substrate; and an interlayer dielectric layer located on the substrate and the channel structure, wherein the interlayer dielectric layer includes a gate opening that exposes a portion of the substrate and the channel structure, and the gate opening exposes the first transistor region and the second transistor region. The first work function layer is located in the first transistor region exposed by the gate opening; The second work function layer is located in the first transistor region and the second transistor region exposed by the gate opening; The semiconductor structure further includes a gate layer located on the first work function layer and the second work function layer of the gate opening.

15. The semiconductor structure as described in claim 14, characterized in that, The extension direction of the gate opening is perpendicular to the extension direction of the boundary between the first transistor region and the second transistor region.

16. The semiconductor structure as claimed in claim 11, characterized in that, Semiconductor structures also include: A gate dielectric layer is located on the substrate of the first transistor region and the second transistor region; The first work function layer is located on the gate dielectric layer of the first transistor region; The second work function layer is located on the first work function layer of the first transistor region and the gate dielectric layer of the second transistor region.

17. The semiconductor structure as claimed in claim 16, characterized in that, The semiconductor structure also includes: An etch-resistant layer is located between the first work function layer and the gate dielectric layer in the first transistor region, and between the second work function layer and the gate dielectric layer in the second transistor region.

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