Method for processing a CFET device with embedded side track wiring

Abstract

The present disclosure relates to a method of processing a CFET device (10). The method comprises the steps of: forming a fin structure (23) comprising a first layer stack (23a) and a second layer stack (23b) above the first layer stack (23a); forming a trench (26) in the buffer layer (25) on one side of the fin structure (23), the trench (26) running parallel to the fin structure (23); at least partially filling a first section of the trench (26) with a first metal layer (15), the first metal layer (15) being arranged at the level of the first layer stack (23a); and at least partially filling a second section of the trench (26) with a second metal layer (16), the second metal layer (16) being arranged at the level of the second layer stack (23b); wherein the first metal layer (15) and the second metal layer (16) are arranged in translation with each other in a direction along the length of the trench (26).

Description

Technical Field

[0001] The present disclosure relates to a method for processing a complementary field effect transistor (CFET) device. In particular, the present disclosure proposes an efficient processing method for a CFET device with a side wiring architecture. Background Art

[0002] In CFET, different transistor structures, especially NMOS and PMOS transistors can be stacked on top of each other. For example, compared with nanosheet devices, nanosheet devices include NMOS and PMOS transistors arranged side by side with spacing between them. The stacking of transistor structures can increase the effective channel width.

[0003] In many conventional CFET designs, the bottom device epitaxial portion (e.g., the source or drain of the bottom transistor) should be electrically connected to the top device epitaxial portion (e.g., the source or drain of the top transistor). However, it is challenging to process the wiring routes between the two CFET levels (bottom and top) to achieve this connection.

[0004] For example, the top and bottom devices can be electrically connected via electrical traces on one side of the CFET (side wiring). However, it is difficult to make such side wiring connections that electrically contact the top and bottom transistor devices without damaging other components of the CFET, such as the top epitaxial portion, the bottom MOA layer, or the isolation portion of the CFET.

[0005] Furthermore, it is challenging to laterally contact the top and bottom transistor structures with the side wiring routes without large contact resistance. Summary of the invention

[0006] Therefore, it is an object to provide an improved method for processing CFET devices. In particular, the above-mentioned disadvantages should be avoided.

[0007] This object is achieved by the embodiments provided in the attached independent claim. Advantageous implementations of embodiments of the invention are further defined in the dependent claims.

[0008] A first aspect of the present disclosure provides a method for processing a complementary field effect transistor (CFET) device. The method comprises the following steps: forming a fin structure, the fin structure comprising a first layer stack and a second layer stack above the first layer stack; forming a groove in a buffer layer on one side of the fin structure, wherein the groove runs parallel to the fin structure; at least partially filling a first section of the groove with a first metal layer, wherein the first metal layer is arranged at the level of the first layer stack; and at least partially filling a second section of the groove with a second metal layer, wherein the second metal layer is arranged at the level of the second layer stack; wherein the first metal layer and the second metal layer are arranged translationally relative to each other in a direction along the length of the groove.

[0009] The advantage of this implementation is that CFET devices with embedded side wiring architectures can be efficiently processed. Specifically, this method is more advantageous than forming side wiring with the aid of high aspect ratio (i.e. deep) through holes. The first metal layer can form a side rail (or side wiring) structure of the bottom transistor structure of the CFET device, and the second metal layer can form a side rail (or side wiring) structure of the top transistor structure of the CFET device.

[0010] In particular, the groove is formed at a determined distance from the fin structure so that there is a gap between the groove and the fin structure.

[0011] The first metal layer may be a MOAB layer, and the second metal layer may be a MOAT layer.

[0012] The buffer layer may be an oxide layer, such as SiO2.

[0013] Thus, processing a CFET device may refer to manufacturing or producing a CFET device.

[0014] In an embodiment, the first layer stack includes at least one channel of a first transistor structure of a CFET device, and the second layer stack includes at least one channel of a second transistor structure of the CFET device.

[0015] The first (or bottom) transistor structure can be arranged in a first level (or level) of the CFET device, and the second (or top) transistor structure can be arranged in a second level (or level) of the CFET device, wherein the second level is arranged above the first level. This may result in a stacked transistor structure of the CFET device. However, the two specific transistor structures of the CFET device - one in the first level and the other in the second level - do not have to be arranged directly above each other (relative to the stacking direction of the CFET device, typically in the present disclosure, in the "vertical" direction), but may also be arranged indirectly above each other, meaning that they may deviate in a "horizontal" direction that is perpendicular to the "vertical" or stacking direction. The CFET device may include additional transistor structures or other elements, which may be located directly above or directly below the first and second transistor structures, respectively.

[0016] For example, the first transistor structure and the second transistor structure may form a CFET cell.A CFET device may include one or more CFET cells or portions thereof.

[0017] It should be noted that in the present disclosure, the terms "below" and "above", "bottom" and "top" or similar terms should be interpreted relative to each other. In particular, these terms describe opposite sides of a CFET device, or opposite sides of any element of a CFET device. These terms can describe the relationship of elements of a CFET device (e.g., transistor structures, signal wiring routes, power rails, etc.) along the stacking direction of the layers (or levels) of the CFET device. The stacking direction can therefore be aligned with the arrangement of two layers (or even more than two layers) of the CFET device. That is, two or more layers (or levels) arranged above each other are arranged one after another along a certain direction (stacking direction).

[0018] The transistor structure in the present disclosure may be or may include a transistor, such as a field effect transistor (FET), or may be or may include a more complex semiconductor-based structure that functions similarly to a transistor. For example, the semiconductor-based structure may be a nanosheet structure, a fin structure, or a fork-sheet structure, for example, with a gate partially or completely wrapped around a channel portion. The latter may be, for example, a ring-gate structure.

[0019] The transistor structure of the CFET device of the first aspect may be an NMOS and a PMOS transistor structure. For example, the first transistor structure may be an NMOS transistor structure, and the second transistor structure may be a PMOS transistor structure, or vice versa.

[0020] In an embodiment, the method comprises the further step of forming a first horizontal contact structure electrically connecting the first metal layer with a first source or drain terminal arranged on at least one side of the first layer stack.

[0021] This achieves the advantage that a lateral contact from the (bottom) signal wiring route to the (bottom) source or drain terminal of the first transistor structure can be established. In particular, the first horizontal contact structure and the bottom signal wiring route (first metal layer) can be formed simultaneously or in consecutive steps. Thereby, "lateral" can be relative to the signal wiring route (and for example not relative to the source or drain terminal).

[0022] For example, the first source or drain (S / D) terminal is arranged on or around the channel layer(s) of the first layer stack. In particular, the first source or drain terminal is arranged to electrically contact the channel layer(s) of the first layer stack.

[0023] In one embodiment, before the first horizontal contact structure is formed, the first source or drain terminal is formed by means of an epitaxial growth process.

[0024] In one embodiment, the first horizontal contact structure contacts the first source or drain terminal from the top.

[0025] This achieves the advantage that a larger contact surface is formed between the first horizontal contact structure and the first source or drain terminal, which reduces the contact resistivity.

[0026] In an embodiment, the method comprises the further step of forming a second horizontal contact structure electrically connecting the second metal layer with a second source or drain terminal arranged on at least one side of the second layer stack.

[0027] This achieves the advantage that a lateral contact from the (top) signal wiring route to the (top) source or drain terminal of the second transistor structure can be established. In particular, the second horizontal contact structure and the top signal wiring route (second metal layer) can be formed simultaneously or in consecutive steps. Thus, "lateral" can be relative to the signal wiring route (and, for example, not relative to the source or drain terminal).

[0028] For example, the second source or drain terminal is arranged on or around the channel layer(s) of the second layer stack.In particular, the second source or drain terminal is arranged to electrically contact the channel layer(s) of the second layer stack.

[0029] In one embodiment, before the second horizontal contact structure is formed, the second source or drain terminal is formed by means of an epitaxial growth process.

[0030] In one embodiment, the second horizontal contact structure contacts the second source or drain terminal from the top.

[0031] This achieves the advantage that a larger contact surface is formed between the first horizontal contact structure and the first source terminal or drain terminal, thereby reducing the contact resistivity.

[0032] In one embodiment, the trench is formed by: forming a dummy fin structure close to the fin structure, wherein the dummy fin structure runs parallel to the fin structure; filling areas on both sides of the dummy fin structure with a buffer layer; and at least partially removing the dummy fin structure.

[0033] This has the advantage that the fabrication of the side routing tracks (first and second metal layers) can be facilitated, in particular their alignment with the fin structure and the channels therein. In this way, a "self-aligned" 1D side track routing can be achieved.

[0034] In particular, the dummy fin structure is formed at a determined distance from the fin structure so that there is a gap between the dummy fin structure and the fin structure.

[0035] For example, the dummy fin structure may be completely removed or partially recessed.

[0036] In one embodiment, in a first removing step, a portion of the dummy fin-like structure is removed to expose a first section of the groove; and in a second removing step, another portion of the dummy fin-like structure is removed to expose a second section of the groove.

[0037] In one embodiment, a first metal layer is deposited in the first section of the trench prior to the second removing step.

[0038] This achieves the advantage that the first metal layer (bottom-side track structure) can be manufactured efficiently.

[0039] In one embodiment, the trench is formed by etching into the buffer layer using at least two separate etching steps; wherein, in a first etching step, a portion of the buffer layer is removed to expose a first section of the trench; and, in a second etching step, another portion of the buffer layer is removed to expose a second section of the trench.

[0040] This achieves the advantage that the production of the side wiring tracks (first and second metal layers) can be facilitated.

[0041] In one embodiment, a first metal layer is deposited in the first section of the trench prior to the second etching step.

[0042] This achieves the advantage that the first metal layer (bottom-side track structure) can be manufactured efficiently.

[0043] In one embodiment, the method comprises the further step of: forming a metal through structure in the trench, wherein the metal through structure electrically connects the first metal layer with the second metal layer.

[0044] In this way, electrical contact between the bottom and top side rail structures (first and second metal layers) can be established. Thus, a side rail wiring structure can be generated that spans two CFET levels (or layers) and connects the source or drain terminal of the first (bottom) transistor structure of the CFET device with the source or drain terminal of the second (top) transistor structure.

[0045] At least a portion of the second metal layer may be disposed directly above the first metal layer. Thus, the metal through structure may be a vertical metal through hole.

[0046] In one embodiment, the buffer layer is a silicon dioxide (SiO2) layer, in particular a FCVD (filament chemical vapor deposition) SiO2 layer. The buffer layer can also be formed by bottom-up dielectric filling.

[0047] A second aspect of the present disclosure provides a CFET device obtainable by a method according to the first aspect of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The above aspects and embodiments are explained in the following description of embodiments with reference to the accompanying drawings, in which:

[0049] Figure 1 A- Figure 1 FIG. F shows a process flow of a method for processing a CFET device according to an embodiment;

[0050] Figure 2 A- Figure 2 B shows a different view of a CFET device according to an embodiment;

[0051] Figure 3 shows a perspective view of a CFET device according to an embodiment;

[0052] Figure 4-1 A- Figure 4-7 BB shows a process flow of a method for processing a CFET device according to one embodiment;

[0053] Figure 5-1 A- Figure 5-2 FIG. 1H shows a process flow of a method for fabricating a CFET device according to an embodiment. DETAILED DESCRIPTION

[0054] Figure 1 A- Figure 1FIG. F shows a process flow of a method for processing a CFET device according to an embodiment. Figure 1 A- Figure 1 FIG. 5 shows a cross-sectional view through the xz plane (as indicated by a Cartesian coordinate system), which is perpendicular to the channel direction (y direction) of the CFET device.

[0055] exist Figure 1 A- Figure 1 F(and Figure 4-1 A- Figure 4-7 BB and Figure 5-1 A- Figure 5-2 In the example shown in Figure 1, two structures with the same basic elements are processed side by side, wherein the structures are deviated or staggered in the direction of the channel. These two structures can form different CFET devices or different CFET units or components of a single CFET device. The CFET unit can be a unit cell of a CFET device, wherein the unit cell means that the CFET unit can be repeated once or multiple times in the CFET device. In particular, the same elements of the two structures can be formed simultaneously. In the following, for processing steps that may be the same for two structures, they are generally described with reference to only one of the structures.

[0056] like Figure 1 As shown in A, the method includes forming a fin structure 23, the fin structure 23 including a first layer stack 23a and a second layer stack 23b located above the first layer stack 23a.

[0057] The first layer stack 23a may include at least one channel 11a of a first transistor structure of a CFET device, and the second layer stack 23b may include at least one channel 12a of a second transistor structure of a CFET device. For example, the first transistor structure is a bottom transistor structure of a CFET device, and the second transistor structure is a top transistor structure of a CFET device. The bottom transistor structure may be NMOS, and the top transistor structure may be PMOS, or vice versa.

[0058] The first layer stack 23a and the second layer stack 23b can be arranged directly on top of each other. A dielectric spacer layer stack (e.g., intermediate dielectric isolation, MDI) can be arranged between the first layer stack 23a and the second layer stack 23b. However, the dielectric spacer layer stack can also be part of the first layer stack 23a or the second layer stack 23b.

[0059] like Figure 1As shown in A, the method may also include forming a dummy fin structure 24 near each fin structure 23. By designing a pattern on a substrate including a first layer stack 23a and a second layer stack 23b, for example, by means of 1D EUV lithography and subsequent etching, a fin structure and a dummy fin structure may be formed simultaneously, thereby exposing the fin structure 23 and the dummy fin structure 24. Each dummy fin structure 24 may serve as a placeholder structure for a subsequent side track structure. Therefore, (one or more) dummy fin structures 24 may realize a 1D self-aligned side track wiring pattern.

[0060] like Figure 1 As shown in B, the method also includes forming a groove in the buffer layer 25 on one side (or both sides) of the fin structure 23, wherein the groove runs parallel to the fin structure. The first section of the groove is at least partially filled with the first metal layer 15, wherein the first metal layer 15 is arranged at the level of the first layer stack 23a; and the second part of the groove is at least partially filled with the second metal layer 16, wherein the second metal layer 16 is arranged at the level of the second layer stack 23b. Thus, the first metal layer 15 and the second metal layer 16 are arranged translationally relative to each other in a direction along the length of the groove. Such an arrangement of metal layers can be, for example, Figure 2 A- Figure 2 B and Figure 3 As seen in FIG. , which shows different cross-sectional and perspective views of the resulting CFET device.

[0061] exist Figure 1 In the example shown in B, each trench is formed by selectively removing (at least partially) the dummy fin structure 24, so that the buffer layer 25 remains as a spacer close to the fin structure 23. In this way, a self-aligned block (SAB) for the active pattern can be achieved. The removal of the dummy fin structure 24 can be achieved by a suitable etching process.

[0062] The buffer layer 25 may be a SiO 2 layer, in particular a SiO 2 layer deposited by (thermal) filament chemical vapor deposition (FCVD).

[0063] The method may further include forming a metal through structure 17 in the trench, the metal through structure 17 electrically connecting the first metal layer 15 with the second metal layer 16 (shown as Figure 1 The first metal layer 15, the second metal layer 16 and the metal penetration structure 17 can form a side track structure (also: side wiring structure) of the CFET device. For example, the first metal layer 15 is arranged in a first level (or layer) of the CFET device, and the second metal layer 16 is arranged in a second level or layer of the CFET device. The first metal layer 15 can be a MOAB layer, and the second metal layer 16 can be a MOAT layer.

[0064] The first metal layer 15 and the second metal layer 16 are arranged translationally in the direction of the groove. However, sections of these channels 15, 16 can be arranged above each other and electrically connected by vertical metal through-structures 17, as shown in FIG. Figure 1 The left side track structure of B. Figure 1 In the right side track structure in B, the second metal layer is not arranged above the first metal layer (in the depicted cross-sectional plane). In this area, the first metal layer can be covered by the vertical isolation portion 26a and the SiO2 layer 26b.

[0065] exist Figure 1 In the next step shown in FIG. 3C , the buffer layer 25 may be at least partially recessed to expose the fin structure 23 and the side rail structure.

[0066] Then, if Figure 1 As shown in D, a first source or drain terminal 11b may be formed on at least one side of the first layer stack 23a. Specifically, the first source or drain terminal 11b is arranged to electrically contact the (one or more) channels 11a of the first layer stack 23a. For example, the source or drain terminal 11b may be formed on or around the (one or more) channels 11a by means of an epitaxial growth process.

[0067] In a further step, if Figure 1 As shown in FIG. 1E, a first horizontal contact structure 28a can be formed, which electrically connects the first metal layer 15 to the first source or drain terminal 11b. The first horizontal contact structure can contact the first source or drain terminal 11b from the top. This provides the advantages of a large contact area and thus a low contact resistance. Figure 1 The horizontal contact structure 28a is shown as the right side track structure and fin structure in the cross-sectional plane shown in FIG. E. Similar horizontal contact structures 28a can be formed as the left side track structure and fin structure 23 in a different plane along the channels 11a, 12a.

[0068] The first horizontal contact structure 28a can be an extended MOA structure, which is arranged to bridge the bottom epitaxial portion (source or drain terminal 11b) and the side rail bottom structure (first metal layer 15). In this way, a dual MOA module can be formed. After the formation of the first horizontal contact structure 28, the formation of the metal recess and the vertical isolation can be performed.

[0069] Then, if Figure 1 As shown in FIG. 5 , a second source or drain terminal 12 b may be formed on at least one side of the second layer stack 23 b (eg, on or around the channel 12 a of the second layer stack 23 b). Figure 1In FIG. 5 , the second source or drain terminal 12 b is shown only as the left fin structure 23. However, simultaneously, a similar source or drain terminal 12 b may also be formed as the right fin structure 23. The second source or drain terminal 12 b may be formed by an epitaxial growth process.

[0070] After forming the second source or drain terminal(s) 12b, a second horizontal contact structure 28b may be formed, which contacts the second source or drain terminal 12b from the top. This again provides the advantage of a large contact area and therefore low contact resistance.

[0071] The second horizontal contact structure 28b may be an extended M0T structure or module arranged to bridge the top epitaxial portion (source or drain terminal 12b) and the side rail top structure (second metal layer 16). The through structure 17 and the horizontal contact structure 28b are generally arranged along the channel direction ( Figure 1 A- Figure 1 y direction in F) are arranged translationally relative to each other, such as Figure 2 A and Figure 3 shown.

[0072] Specifically, using the above method, the side track wiring structure can be formed before or during the formation of the active source / drain module, or during the STI (shallow trench isolation) module and before the gate formation (e.g., replacement metal gate module). In these (early) processes, the "integration" of the side track structure formation provides several advantages. For example, by first forming the side track structure (first metal layer 15 and second metal layer 16), and then forming (one or more) bottom source and / or drain terminals 11b (via bottom epitaxial growth) and second source or drain terminals 12b (via top epitaxial growth), damage to the top epitaxial isolation part and the bottom metal contact part can be prevented. For example, when the top and bottom source and / or drain terminals 11b, 12b are first formed via an epitaxial growth process, and then the formation and connection of the side track structure are started. In addition, there is no need for complex 2D lithography to form the side track structure, because all side track wiring (1D) can be made before or during the active S / D pattern design, or during the STI module. Vertical lithography for the vertical contact structures 28a, 28b can be performed by extending the existing MOAB and MOAT lithography techniques.

[0073] Figure 2 A- Figure 2 B shows a different view of a processed CFET device according to an embodiment. Thus, Figure 2 FIG. 4A shows a top view of the bottom transistor structure 21 and the top transistor structure 22 of the CFET device (ie, their extensions in the x-direction and the y-direction, as shown in FIG. 4B ). Figure 2A is shown in the Cartesian coordinate system). Figure 2 B shows Figure 2 A is a cross-sectional view of a CFET device, where Figure 2 The section lines A-A', B-B' and C-C' in A indicate Figure 2 The location of the cross section in B.

[0074] like Figure 2 As shown in A of , the top transistor structure and the bottom transistor structure of the CFET device can each include a plurality of source and / or drain terminals 11b, 12b arranged alternately along (one or more) channels 11a, 12a with gate terminals 11c. The bottom side track structure formed by the first metal layer 15 can be electrically connected to the source and / or drain terminals 11b of the bottom transistor structure, and the top side track structure formed by the second metal layer 16 can be electrically connected to the source and / or drain terminals 12b of the top transistor structure arranged away from the channels 11a, 11b. In addition, a signal wiring route 18 can be arranged at one end of the CFET device.

[0075] like Figure 2 As shown in A of FIG. 1 , both the top side rail structure and the bottom side rail structure and the corresponding horizontal contact portion structures 28a, 28 may have an L-shape.

[0076] The first metal layer 15 and the second metal layer 16 may be electrically connected via a vertical metal through structure 17 , for example in a region where both metal layers 15 , 16 overlap. Figure 2 The CC' cross-sectional view in B shows the resulting side rail structure (on two levels) connecting the first (bottom) transistor structure 21 with the second (top) transistor structure 22 of the CFET device.

[0077] As shown in the CC' cross-sectional view, the first metal layer 15 and the second metal layer 16 are arranged in a direction along the length of the trench (and (one or more) channels 11a, 12a) in a translational (or displacement) manner relative to each other. In this way, the bottom source or drain terminal 11b can be electrically connected to the top source or drain terminal 12b that is not located directly above the bottom source or drain terminal 12b.

[0078] and Figure 1 A- Figure 1 Similar to F, Figure 2 The cross-sectional view in B shows two structures (e.g., different CFET devices or different CFET cells of a device) with corresponding side track structures between them. The side track structures of the two structures can be offset or staggered from each other along the corresponding channels 11a, 12a. For example, Figure 2The BB′ cross section shown in FIG. 1 cuts through the two metal layers 15 , 16 and the metal through structure 17 of the left side track structure, but only cuts through the first metal layer 15 of the right side track structure.

[0079] Figure 2 The AA′ cross-sectional view in FIG. 8 shows a gate terminal (a cut section along the gate terminal) that may wrap around the channels 11 a , 12 a of the first and second transistor structures of the CFET device.

[0080] Figure 3 A perspective view of a CFET device 10 according to an embodiment is shown.

[0081] The CFET device 10 includes a first transistor structure 21 and a second transistor structure 22. A VSS power rail 13 of the CFET device 10 may be disposed on one side of the first and second transistor structures 21, 22, and a side rail structure 16 may be disposed on an opposite side.

[0082] Figure 4-1 A- Figure 4-7 BB shows a process flow of a method for processing a CFET device according to an embodiment. Thus, each of the figures shows AA', BB' and CC' cross-sectional views as indicated in 2A.

[0083] In the first step, Figure 4-1 As shown in A, by active nanosheet pattern design (e.g., pattern design of nanosheet stacking on substrate 14), (one or more) fin structures 23 and (one or more) pseudo-fin structures 24 can be formed on substrate 14. Thus, the pseudo-fin structure 24 runs parallel to the fin structure 23. Each fin structure 23 may include a first layer stack 23a and a second layer stack 23b. Each layer stack may include a plurality of alternating layers, including at least one channel layer (e.g., Si layer) and at least one dielectric layer. For example, each layer stack 23a, 23b may include alternating Si and SiGe layers. The top layer of the fin structure 23 may be a Si3N4 layer. A dielectric separation layer stack (e.g., intermediate dielectric isolation, MDI) may be arranged between the first layer stack 23a and the second layer stack 23b.

[0084] Subsequently, the gap between the fin structure(s) 23 and the dummy fin structure(s) 24 may be filled with a buffer layer 25 (eg, by FCVDSiO2 deposition), as shown in FIG. Figure 4-1 As shown in B, a subsequent CMP (chemical mechanical polishing) process can be performed.

[0085] Then, if Figure 4-1As shown in FIG. 3C , by partially removing the dummy fin structure 24 , the bottom side rail groove pattern design can be performed to expose the first section of the groove 26 . In this way, the self-alignment positioning of the bottom side rail structure can be achieved.

[0086] The first metal layer 15 may then be deposited in the first section into the trench 26, deposited at the same level as the first layer stack 23a, such as Figure 4-1 This can be done by depositing a dielectric liner and a metal liner or tungsten in the trench 26. Subsequent metal recesses can be made to control the metal deposition.

[0087] Then, if Figure 4-2 As shown in FIG. 8E , vertical isolation portions 26 a may be deposited on the first metal layer 15 , for example by filling from the bottom up or by a filling and subsequent etch-back step.

[0088] Then, the remaining pseudo-wing structure 24 ( Figure 4-2 F) can be removed and filled with SiO2 layer 26b (with SiN layer). After the deposition of SiN layer and SiO2 layer 26b, a CMP step can be performed ( Figure 4-2 G).

[0089] like Figure 4-2 As shown in FIG. 1 , the top side rail groove pattern design can then be performed by partially removing the SiO 2 layer 26 b to expose the second section of the groove 26. In this way, a self-aligned positioning of the top side rail structure can be achieved.

[0090] Then, if Figure 4-3 As shown in FIG. 1 , a through pattern design can be performed to expose a through channel between the bottom and top side track structures (i.e., between the M0aT and M0AB layers). Then, the second metal layer 16 can be deposited in the through channel (by pre-fill deposition), and the second section of the groove 26 is at the same level as the second layer stack 23b, as shown in FIG. Figure 4-3 J. The top side track structure may have a metal recess after metallization.

[0091] In a subsequent step, the recess of the SiO2 layer 26b may be formed, such as Figure 4-3 As shown in K, the Si3N4 plug 31 can be formed in the remaining section of the trench 26 ( Figure 4-3 L) 。 A CMP step may be further performed.

[0092] In a subsequent step, the buffer layer 25 may be recessed and the fin structure(s) 23 and the side rail structure(s) may be exposed, such as Figure 4-4 Then, a dummy gate material 32, such as amorphous silicon (aSi) ( Figure 4-4 The dummy gate can then be patterned ( Figure 4-4 O), and source and drain regions can be formed ( Figure 4-4 P), for example, by selectively recessing the fin structure in the pattern design area.

[0093] Then, the bottom source and / or drain terminal(s) 11 b may be formed by means of an epitaxial growth process, such as Figure 4-5 Q, and the dielectric (ILD0) 33 can be deposited, followed by a CMP step, as shown in FIG. Figure 4-5 As shown in R.

[0094] Subsequently, the MOAB pattern design ( Figure 4-5 S and Figure 4-5 Then, a MOA metal recess can be made, such as Figure 4-6 As shown in U, a horizontal contact structure 28a is formed. A vertical isolation 34a (from bottom to top) can be formed on the horizontal contact structure 28a, as shown in Figure 4-6 As shown in V.

[0095] Then, the top source and / or drain terminal(s) 12b may be formed by means of an epitaxial growth process, such as Figure 4-6 As shown in W, and dielectric (ILD0) 35 can be deposited, followed by a CMP step, as Figure 4-6 As shown in X.

[0096] The gate terminal(s) 11c material may then be deposited by a RMG (Replacement Gate Metal) processing step ( Figure 4-7 Subsequently, a horizontal contact structure 28b bridging the second metal layer with the second source or drain terminal 12b may be formed by a M0T pattern, for example, by etching a trench to form a bridge between the second metal layer 16 (M0T) and the top side track structure in the ILD0 layer, and metallization, CMP and metal recess ( Figure 4-7 Z and Figure 4-7 AA). A further plug layer 34b may then be formed on the horizontal contact structure 28b, such as Figure 4-7 BB is shown below.

[0097] Figure 5-1 A- Figure 5-2 FIG. 1 shows another process flow of a method for processing a CFET device according to an embodiment. Figure 4-1 A- Figure 4-7Compared to the process flow shown in BB, no dummy fin structure 24 is used. Instead, the embedded side track structure can be formed during the STI module manufacturing process via photolithography and etching.

[0098] like Figure 5-1 A and Figure 5-1 As shown in FIG. 1B , the first section of the trench 26 is etched directly in the buffer layer 26. The first section can then be filled with a first metal layer 15 (eg, a dielectric liner and a metal liner or tungsten) and a vertical isolation 26a ( Figure 5-1 CMP and / or metal recesses can then be performed. The remaining trenches can then be filled with SiO2 layer 26b and CMP ( Figure 5-1 D).

[0099] Subsequently, a second section of the trench 26 may be etched directly into the buffer layer 25, such as Figure 5-2 As shown in E, and a through recess is formed in the vertical isolation 26a (eg, by a M0AT-M0AB pattern), as shown in FIG. Figure 5-2 As shown in F.

[0100] Then, the second metal layer 16 can be deposited in the through-hole (via prefilling), and the second section of the trench 26 is to be at the same level as the second layer stack 23b, as shown in FIG. Figure 5-2 G. The top side track structure may have a metal recess after metallization.

[0101] In a subsequent step, the recess of the SiO2 layer 26b may be performed, and the Si3N4 plug 31 may be formed in the remaining section of the trench 26. A CMP step ( Figure 5-2 H). Subsequent processing steps can be Figure 4-4 M- Figure 4-7 The steps are the same as shown in BB.

[0102] In addition to the advantages and effects mentioned above, Figure 1 A- Figure 1 F. Figure 4-1 A- Figure 4-7 BB and Figure 5-1 A- Figure 5-2 The method shown in any of the H diagrams can also provide the following advantages:

[0103] - No lateral sidewall epitaxial contacts are required on the bottom source and / or drain terminals 11b. Instead, the MOAB contacts for the epitaxial and embedded bottom side rail metal lines can be formed simultaneously.

[0104] The horizontal contact structures 28a, 28b may have a large contact surface with the source or drain terminal 11b, 12b, which reduces the contact resistivity.

[0105] - Damage to the top epitaxial portion (second source or drain terminal 12b) and vertical isolation and bottom MOA metal contacts, which may occur during side track wiring patterning using a metal gate cutting process (performed after RMG), can be avoided.

[0106] - 2D lithography patterning can be avoided and all side track routing (1D) can be done during active patterning or STI blocks. Vertical lithography patterning can be achieved by extending the existing M0AB and M0AT (first and second level) lithography.

[0107] -Embedded side track routing is compatible with RMG mid-CFET integration scheme.

[0108] In addition, the use of the dummy fin structure 24 facilitates self-alignment of the side rail metal (1D) pattern. Alternatively, the use of Figure 5-1 A- Figure 5-2 The 2x photolithography (non-self-aligned) method shown in H is used to form the embedded side rail structure. In particular, the embedded side rail interconnection method is compatible with the front-end monolithic CFET RMG intermediate integration scheme.

[0109] In the claims and description of the present disclosure, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. A single element may fulfill the functions of multiple entities or items described in the claims. The fact that certain measures are described in mutually different dependent claims does not indicate that a combination of these measures cannot be used in an advantageous implementation.

Claims

1. A method of processing a complementary field effect transistor (CFET) device (10), comprising the following steps: forming a fin structure (23) comprising a first layer stack (23a) and a second layer stack (23b) above the first layer stack (23a); forming a groove (26) in the buffer layer (25) on one side of the fin structure (23), wherein the groove (26) runs parallel to the fin structure (23); at least partially filling a first section of the trench (26) with a first metal layer (15), wherein the first metal layer (15) is arranged at the level of the first layer stack (23a); and at least partially filling a second section of the trench (26) with a second metal layer (16), wherein the second metal layer (16) is arranged at the level of the second layer stack (23b); The first metal layer (15) and the second metal layer (16) are arranged in a manner shifted relative to each other in a direction along the length of the groove (26).

2. The method according to claim 1, characterized in that The first layer stack (23a) includes at least one channel (11a) of a first transistor structure of the complementary field effect transistor device (10), and wherein the second layer stack (23b) includes at least one channel (12a) of a second transistor structure of the complementary field effect transistor device (10).

3. The method according to claim 1 or 2, characterized in that: The method further comprises: A first horizontal contact structure (28a) is formed, which electrically connects the first metal layer (15) to a first source or drain terminal (11b) arranged on at least one side of the first layer stack (23a).

4. The method according to claim 3, characterized in that Before the first horizontal contact structure (28a) is formed, the first source or drain terminal (11b) is formed by means of an epitaxial growth process.

5. The method according to claim 3 or 4, characterized in that: The first horizontal contact structure (28a) contacts the first source or drain terminal (11b) from the top.

6. The method according to any one of the preceding claims, characterized in that The following steps are also included: A second horizontal contact structure (28b) is formed, wherein the second horizontal contact structure connects the second metal layer (16) The second layer stack (23b) is electrically connected to a second source or drain terminal (12b) disposed on at least one side of the second layer stack (23b).

7. The method according to claim 6, characterized in that Before the second horizontal contact structure (28b) is formed, the second source or drain terminal (12b) is formed by means of an epitaxial growth process.

8. The method according to claim 6 or 7, characterized in that: The second horizontal contact structure (28b) contacts the second source or drain terminal (12b) from the top.

9. The method according to any one of the preceding claims, characterized in that The groove (26) is formed by the following arrangement: forming a dummy fin structure (24) adjacent to the fin structure (23), wherein the dummy fin structure (24) runs parallel to the fin structure (23); filling the areas on both sides of the dummy fin structure (24) with the buffer layer (26); and The dummy fin structure (24) is at least partially removed.

10. The method according to claim 9, characterized in that In a first removal step, a portion of the dummy fin structure (24) is removed to expose a first section of the groove (26); and in a second removal step, another portion of the dummy fin structure (24) is removed to expose a second section of the groove (26).

11. The method according to claim 10, characterized in that Prior to the second removal step, the first metal layer (15) is deposited in a first section of the trench (26).

12. The method according to any one of claims 1 to 8, characterized in that The trench (26) is formed by etching into the buffer layer (25) using at least two separate etching steps; In the first etching step, a portion of the buffer layer (25) is removed to expose a first section of the groove (26); and in the second etching step, another portion of the buffer layer (25) is removed to expose a second section of the groove (26).

13. The method according to claim 12, characterized in that Prior to the second etching step, the first metal layer (15) is deposited in a first section of the trench (26).

14. The method according to any one of the preceding claims, characterized in that The following steps are also included: A metal through structure (17) is formed in the groove, and the metal through structure electrically connects the first metal layer (15) and the second metal layer (16).

15. The method according to any one of the preceding claims, characterized in that The buffer layer (25) is a silicon dioxide (SiO2) layer, in particular a FCVD SiO2 layer.

16. A complementary field effect transistor (CFET) device (10) obtained by a method according to any one of the preceding claims.

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