Preparation method of tunneling oxide layer, TOPCon battery and preparation method thereof

Abstract

The present invention relates to a preparation method of a tunneling oxide layer, a TOPCon battery and a preparation method. The preparation method of the tunneling oxide layer adopts atmospheric pressure oxidation to grow silicon dioxide, firstly introduces oxygen under certain temperature and air pressure conditions for preliminary growth, then stops introducing oxygen under the conditions of maintaining temperature and air pressure, and performs a tube-stifling process to reduce the situation where the unstable gas flow rate in the tube causes uneven growth of silicon dioxide, so that silicon dioxide continues to grow for a period of time in a more static environment, and the thickness of the tunneling oxide layer can be uniform. In step S2 and step S3, the process temperature is maintained at 600°C-620°C, which is conducive to the stable growth of the tunneling oxide layer, avoids large fluctuations in the process temperature that cause changes in the growth rate of the tunneling oxide layer, and avoids the resulting reduction in the thickness uniformity of the tunneling oxide layer.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaic technology, and in particular to a method for preparing a tunneling oxide layer, a TOPCon battery and a preparation method thereof. Background Art

[0002] In the photovoltaic field, the front surface of the TOPCon cell (tunneling oxide passivation contact cell) is similar to that of the conventional PERC cell (emitter back passivation cell). The TOPCon cell is characterized by a tunneling oxide layer on the back, and a doped polysilicon layer on the tunneling oxide layer, which together form a passivation contact structure. The passivation contact structure provides good surface passivation for the back of the silicon wafer. The tunneling oxide layer of the TOPCon cell uses the quantum tunneling effect to allow majority electrons to tunnel into the doped polysilicon layer, while blocking the recombination of minority holes. A layer of metal is deposited on it as an electrode to realize the passivation contact structure. Electrons are transported laterally in the doped polysilicon layer and collected by the metal, thereby reducing the recombination at the electrodes of the TOPCon cell and increasing the open circuit voltage and short circuit current.

[0003] The thickness of the tunnel oxide layer is very thin, usually 1 to 2 nm. Improving the thickness uniformity of the tunnel oxide layer and ensuring the role of the tunnel oxide layer are beneficial to improving the performance of the TOPCon battery. At present, the main growth methods of the tunnel oxide layer are wet chemical nitric acid oxidation, plasma-assisted oxidation, thermal oxidation and chemical vapor deposition (CVD). Among them, chemical vapor deposition includes atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD) and low-pressure chemical vapor deposition (LPCVD). Among them, the tunnel oxide layer grown by the PECVD process has poor uniformity, the process is still immature, and the equipment requirements are high; although the tunnel oxide layer grown by the ALD process has good uniformity, it requires additional process steps, which is not conducive to simplifying the process and mass production. Therefore, the industry currently tends to LPCVD process, which has the advantage of being a relatively mature process and having a higher output. However, the uniformity of the tunnel oxide layer grown by the LPCVD process still needs to be improved. Summary of the invention

[0004] Based on this, it is necessary to provide a method for preparing a tunnel oxide layer, a TOPCon cell and a preparation method to improve the uniformity of the tunnel oxide layer grown by the LPCVD process.

[0005] The first aspect of the present invention is to provide a method for preparing a tunneling oxide layer, the scheme is as follows:

[0006] A method for preparing a tunneling oxide layer comprises the following steps:

[0007] Step S1, placing a silicon wafer in a furnace tube of a LPCVD device;

[0008] Step S2, introducing oxygen, the oxygen flow rate is 30000sccm-50000sccm, the furnace tube pressure is 737000mtorr-760000mtorr, the temperature is 600℃-620℃, and the time is 400s-600s;

[0009] Step S3, stop introducing oxygen, maintain the furnace tube pressure at 737000mtorr-760000mtorr, the temperature at 600℃-620℃, and the time at 400s-600s.

[0010] In one embodiment, in step S1, the temperature of the furnace tube is raised to 550° C.-620° C. and maintained at a constant temperature.

[0011] In one embodiment, in step S1, the total time of heating and maintaining the temperature is controlled within 1000s-1800s.

[0012] In one embodiment, in the step S2, a purge gas is also introduced, and the flow rate of the purge gas is 1000-3000 sccm.

[0013] In one embodiment, the purge gas is nitrogen.

[0014] In one embodiment, in step S3, the introduction of the purge gas is stopped;

[0015] In one embodiment, the process temperature of step S2 and step S3 differs by 5°C.

[0016] In one embodiment, the process temperature of step S2 and step S3 remains the same.

[0017] The second aspect of the present invention is to provide a TOPCon battery, the scheme is as follows:

[0018] A TOPCon battery has a tunneling oxide layer prepared by the preparation method described in any one of the above embodiments.

[0019] In one embodiment, the TOPCon cell further includes a silicon substrate, an emitter and a doped polysilicon layer, the silicon substrate having a first side and a second side opposite to each other, the tunneling oxide layer being arranged on the first side, the doped polysilicon layer being arranged on a side of the tunneling oxide layer away from the silicon substrate, and the emitter being arranged on the second side.

[0020] The third aspect of the present invention is to provide a method for preparing a TOPCon battery, the scheme is as follows:

[0021] A method for preparing a TOPCon battery comprises the following steps:

[0022] providing a silicon substrate;

[0023] Forming a tunneling oxide layer on the first side of the silicon substrate by the preparation method described in any one of the above embodiments;

[0024] A doped polysilicon layer is formed on a side of the tunnel oxide layer away from the silicon substrate.

[0025] In one embodiment, the step of forming the doped polysilicon layer comprises:

[0026] Silane is introduced into the furnace tube of the LPCVD equipment, the flow rate of the silane is 1500sccm-1800sccm, the furnace tube pressure is 300mtorr-500mtorr, the temperature is 590℃-600℃, and the time is 1400s-1600s.

[0027] In one embodiment, the preparation method further comprises the following steps:

[0028] An emitter is formed on a second side surface of the silicon substrate, wherein the second side surface is arranged opposite to the first side surface.

[0029] Compared with the traditional solution, the above-mentioned tunneling oxide layer preparation method, TOPCon battery and preparation method have the following beneficial effects:

[0030] The preparation method of the tunneling oxide layer adopts atmospheric pressure oxidation to grow silicon dioxide, firstly introduces oxygen for preliminary growth under certain temperature and pressure conditions, then stops introducing oxygen under the conditions of maintaining temperature and pressure, and performs a tube-stifling process to reduce the situation where the silicon dioxide growth is uneven due to the unstable gas flow rate in the tube, and allows silicon dioxide to continue to grow for a period of time in a more static environment, which can make the thickness of the tunneling oxide layer uniform. The process temperature in step S2 and step S3 is maintained at 600℃-620℃, which is conducive to the stable growth of the tunneling oxide layer, avoids large fluctuations in the process temperature that cause changes in the growth rate of the tunneling oxide layer, and avoids the resulting reduction in the thickness uniformity of the tunneling oxide layer.

[0031] The TOPCon battery has a tunneling oxide layer prepared by the preparation method described in any of the above embodiments, and thus can achieve corresponding technical effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a schematic flow chart of a method for preparing a tunnel oxide layer according to an embodiment;

[0033] Figure 2 Schematic diagram of the structure of a TOPCon battery according to an embodiment.

[0034] Description of reference numerals:

[0035] 100, TOPCon cell; 110, silicon substrate; 120, emitter; 130, tunneling oxide layer; 140, doped polysilicon layer; 150, first anti-reflection layer; 151, first silicon nitride layer; 160, second anti-reflection layer; 161, aluminum oxide layer; 162, second silicon nitride layer; 170, first electrode; 180, second electrode. DETAILED DESCRIPTION

[0036] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific embodiments disclosed below.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art to which the present application belongs. The terms used herein in the specification of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0038] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0039] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, "plurality" means at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0040] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0041] The invention provides a method for preparing a tunneling oxide layer.

[0042] like Figure 1 As shown, a method 10 for preparing a tunnel oxide layer in one embodiment includes the following steps:

[0043] Step S1, placing the silicon wafer in the furnace tube of the LPCVD equipment.

[0044] Step S2, introducing oxygen, the oxygen flow rate is 30000sccm-50000sccm, the furnace tube pressure is 737000mtorr-760000mtorr, the temperature is 600℃-620℃, and the time is 400s-600s.

[0045] Step S3, stop introducing oxygen. The furnace tube pressure is maintained at 737000mtorr-760000mtorr, the temperature is 600℃-620℃, and the time is 400s-600s.

[0046] The preparation method of the tunneling oxide layer adopts atmospheric pressure oxidation to grow silicon dioxide, firstly introduces oxygen for preliminary growth under certain temperature and pressure conditions, then stops introducing oxygen under the conditions of maintaining temperature and pressure, and performs a tube-stifling process to reduce the situation where the silicon dioxide growth is uneven due to the unstable gas flow rate in the tube, and allows silicon dioxide to continue to grow for a period of time in a more static environment, which can make the thickness of the tunneling oxide layer uniform. The process temperature in step S2 and step S3 is maintained at 600℃-620℃, which is conducive to the stable growth of the tunneling oxide layer, avoids large fluctuations in the process temperature that cause changes in the growth rate of the tunneling oxide layer, and avoids the resulting reduction in the thickness uniformity of the tunneling oxide layer.

[0047] In step S2 and step S3, oxidation is performed under a furnace tube pressure of 737,000 mtorr-760,000 mtorr, which can make the grown tunnel oxide layer more dense.

[0048] In addition, in step S3, the introduction of oxygen is stopped, which reduces the consumption of oxygen in the process, saves production costs and improves economic benefits.

[0049] By obtaining a tunnel oxide layer with a more uniform thickness, it is beneficial to improve the efficiency of solar cells.

[0050] In one example, in step S1, the furnace tube is heated to 550°C-620°C and kept at a constant temperature, for example, 550°C, 560°C, 570°C, 580°C, 590°C, 600°C, 610°C, 620°C, etc. Further, the total time of heating and constant temperature is controlled at 1000s-1800s, for example, 1000s, 1100s, 1200s, 1300s, 1400s, 1500s, 1600s, 1700s, 1800s, etc. Before oxygen is introduced, the furnace tube is heated and kept at a constant temperature for a period of time, which is conducive to the stable growth of the tunneling oxide layer in the oxidation step and improves the uniformity of the tunneling oxide layer. Further, in step S1, during the heating process, vacuuming, leak detection and voltage stabilization are completed.

[0051] In one of the examples, in step S2, the flow rate of oxygen is 35000sccm-45000sccm. In one of the examples, in step S2, the furnace tube pressure is 740000mtorr-755000mtorr. In one of the examples, in step S2, the process temperature is 605℃-615℃. In one of the examples, in step S2, the process time is 450s-550s.

[0052] In one example, in step S2, a purge gas, such as nitrogen, is also introduced, and the flow rate of the purge gas is 1000-3000 sccm.

[0053] Furthermore, in step S3, in addition to stopping the introduction of oxygen, the introduction of the purge gas is also stopped to reduce the situation where the unstable gas flow rate in the tube causes uneven growth of silicon dioxide, allowing silicon dioxide to continue to grow for a period of time in a more static environment, so that the thickness of the tunnel oxide layer can be uniform.

[0054] In one example, in step S3, the furnace tube pressure is 740000 mtorr-755000 mtorr. In one example, in step S3, the process temperature is 605° C.-615° C. In one example, in step S3, the process time is 450s-550s.

[0055] The process temperatures of step S2 and step S3 are both maintained at 600°C-620°C, which is conducive to the stable growth of the tunnel oxide layer, avoiding large fluctuations in the process temperature that may cause changes in the growth rate of the tunnel oxide layer, thereby reducing the thickness uniformity of the tunnel oxide layer. In one example, the process temperatures of step S2 and step S3 differ by 5°C. Further, the process temperatures of step S2 and step S3 differ by 4°C, further, the process temperatures differ by 3°C, further, the process temperatures differ by 2°C, and further, the process temperatures differ by 1°C. In one example, the process temperatures of step S2 and step S3 remain the same.

[0056] In one example, the thickness of the tunneling oxide layer formed by the above preparation method is 1nm to 2nm, for example, 1nm, 1.1nm, 1.2nm, 1.3nm, 1.4nm, 1.5nm, 1.6nm, 1.7nm, 1.8nm, 1.9nm, 2nm, etc.

[0057] Furthermore, the present invention also provides a TOPCon battery.

[0058] A TOPCon cell according to an embodiment has a tunneling oxide layer prepared by any of the above-mentioned preparation methods.

[0059] The TOPCon battery has a tunneling oxide layer prepared by the preparation method described in any of the above examples, and thus can achieve corresponding technical effects.

[0060] like Figure 2 As shown, more specifically, the TOPCon cell 100 includes a silicon substrate 110, an emitter 120, a tunneling oxide layer 130, and a doped polysilicon layer 140. The silicon substrate 110 has a first side surface and a second side surface that are oppositely disposed, the tunneling oxide layer 130 is disposed on the first side surface, the doped polysilicon layer 140 is disposed on a side of the tunneling oxide layer 130 away from the silicon substrate 110, and the emitter 120 is disposed on the second side surface.

[0061] The silicon substrate 110 may be N-type silicon or P-type silicon. In one example, the second side surface of the silicon substrate 110 is a pyramid velvet structure, which can achieve an anti-reflection effect.

[0062] The doping type of the emitter 120 is opposite to the doping type of the silicon substrate 110. A PN junction is formed between the emitter 120 and the silicon substrate 110. The doping type of the doped polysilicon layer 140 is the same as the doping type of the silicon substrate 110. For example, the silicon substrate 110 is N-type silicon, the emitter 120 can be a P+ doped layer formed by a boron diffusion process, and the doped polysilicon layer 140 is a phosphorus-doped N-type layer.

[0063] In one example, the thickness of the doped polysilicon layer 140 is 100 nm-200 nm.

[0064] like Figure 2 As shown, in one example, the TOPCon cell 100 further includes a first anti-reflection layer 150 , and the first anti-reflection layer 150 is disposed on the doped polysilicon layer 140 . Further, the first anti-reflection layer 150 includes a first silicon nitride layer 151 .

[0065] like Figure 2 As shown, in one example, the TOPCon cell 100 further includes a second anti-reflection layer 160, which is disposed on the emitter 120. The second anti-reflection layer 160 includes an aluminum oxide layer 161 and a second silicon nitride layer 162, wherein the aluminum oxide layer 161 is located between the emitter 120 and the second silicon nitride layer 162.

[0066] like Figure 2 As shown, in one example, the TOPCon cell 100 further includes a first electrode 170 , and the first electrode 170 is disposed on the first anti-reflection layer 150 .

[0067] like Figure 2 As shown, in one example, the TOPCon cell 100 further includes a second electrode 180 , and the second electrode 180 is disposed on the second anti-reflection layer 160 .

[0068] Furthermore, the present invention also provides a method for preparing a TOPCon battery 100 .

[0069] A method for preparing a TOPCon battery 100 according to an embodiment includes the following steps:

[0070] Providing a silicon substrate 110;

[0071] forming a tunneling oxide layer 130 on a first side of the silicon substrate 110;

[0072] A doped polysilicon layer 140 is formed on a side of the tunnel oxide layer 130 away from the silicon substrate 110 .

[0073] The tunnel oxide layer 130 is prepared by LPCVD process. More specifically, the preparation method of the tunnel oxide layer 130 includes the following steps:

[0074] Step S1, placing the silicon substrate 110 in a furnace tube.

[0075] Step S2, introducing oxygen, the oxygen flow rate is 30000sccm-50000sccm, the furnace tube pressure is 737000mtorr-760000mtorr, the temperature is 600℃-620℃, and the time is 400s-600s.

[0076] Step S3, stop introducing oxygen, maintain the furnace tube pressure at 737000mtorr-760000mtorr, the temperature at 600℃-620℃, and the time at 400s-600s.

[0077] The preparation method of the TOPCon cell 100 adopts atmospheric oxidation to grow silicon dioxide on the silicon substrate 110, firstly introduces oxygen for preliminary growth under certain temperature and pressure conditions, then stops introducing oxygen under the conditions of maintaining temperature and pressure, and performs a tube-stifling process to reduce the situation that the gas flow rate in the tube is unstable and causes the silicon dioxide to grow unevenly, so that the silicon dioxide continues to grow for a period of time in a more static environment, and the thickness of the tunnel oxide layer 130 can be uniform. In step S2 and step S3, the process temperature is maintained at 600°C-620°C, which is conducive to the stable growth of the tunnel oxide layer 130, avoids the large fluctuation of the process temperature causing the growth rate of the tunnel oxide layer 130 to change, and avoids the resulting reduction in the thickness uniformity of the tunnel oxide layer 130.

[0078] In step S2 and step S3, oxidation is performed under a furnace pressure of 737,000 mtorr-760,000 mtorr, which can make the grown tunnel oxide layer 130 more dense.

[0079] In addition, in step S3, the introduction of oxygen is stopped, which reduces the consumption of oxygen in the process, saves production costs and improves economic benefits.

[0080] By obtaining a tunnel oxide layer 130 with a more uniform thickness, the efficiency of the solar cell is improved.

[0081] In one example, the step of forming the doped polysilicon layer 140 includes:

[0082] Silane is introduced into the furnace tube of the LPCVD equipment. The flow rate of silane is 1500sccm-1800sccm, the furnace tube pressure is 300mtorr-500mtorr, the temperature is 590℃-600℃, and the time is 1400s-1600s.

[0083] Furthermore, in one example, the flow rate of silane is 1600 sccm-1700 sccm, the furnace tube pressure is 350 mtorr-450 mtorr, the temperature is 592° C.-598° C., and the time is 1450 s-1550 s.

[0084] The silane may be, but is not limited to, methane.

[0085] It is understood that the step of forming the doped polysilicon layer 140 is performed after the above step S3. More specifically, after step S3, the furnace tube continues to complete the steps of constant temperature, leak detection, constant pressure and vacuuming, and the process time is controlled within 600s-700s, and then the above-mentioned preparation process of the doped polysilicon layer 140 is performed.

[0086] After the preparation of the doped polysilicon layer 140 is completed, the introduction of silane and oxygen into the furnace tube is stopped, and a purge gas such as nitrogen is continued to be introduced for pressure stabilization. Subsequently, the temperature is lowered and the pressure is returned for 300s-400s.

[0087] In one example, the method for preparing the TOPCon battery 100 further includes the following steps:

[0088] A first anti-reflection layer 150 is formed on the doped polysilicon layer 140 .

[0089] In one example, the method for preparing the TOPCon battery 100 further includes the following steps:

[0090] The first electrode 170 is formed on the first anti-reflection layer 150 .

[0091] In one example, the method for preparing the TOPCon battery 100 further includes the following steps:

[0092] An emitter 120 is formed on a second side surface of the silicon substrate 110 , and the second side surface is disposed opposite to the first side surface.

[0093] In one example, the method for preparing the TOPCon battery 100 further includes the following steps:

[0094] The second anti-reflection layer 160 is formed on the emitter 120 .

[0095] In one example, the method for preparing the TOPCon battery 100 further includes the following steps:

[0096] The second electrode 180 is formed on the second anti-reflection layer 160 .

[0097] The present invention is further described below in conjunction with specific embodiments, but the present invention is not limited to the following specific embodiments.

[0098] Example 1

[0099] This embodiment provides a method for preparing a tunneling oxide layer, comprising the following steps:

[0100] Step S11, placing the silicon wafer into the LPCVD furnace tube, maintaining the temperature at 550°C, completing vacuuming, leak detection and voltage stabilization during the heating process, and controlling the heating and constant temperature time between 1650s.

[0101] Step S12, when the furnace tube pressure is stabilized at about 760000 mtorr, the oxygen flow rate is maintained at 30000 sccm, the temperature is controlled at 610°C, and the time is controlled between 450s.

[0102] Step S13, the furnace tube pressure continues to be maintained at about 760000 mtorr, the oxygen flow rate is reduced to 0, and no other gas is introduced, the temperature is controlled at 610°C, and the time is controlled at 550s.

[0103] The thickness of the tunnel oxide layer in the ten-boat sample prepared in this embodiment was tested at multiple locations, and the average thickness of the multiple locations and the uniformity within the chip were calculated. The results are shown in Table 1. The uniformity within the chip was calculated according to the following formula.

[0104] In-chip uniformity = [(Max-Min) / (Max+Min)]*100%

[0105] Among them, Max is the maximum measurement value in the chip, and Min is the minimum measurement value in the chip.

[0106] Table 1 Thickness of the tunneling oxide layer in the ten-boat sample prepared in Example 1

[0107]

[0108]

[0109] Example 2

[0110] This embodiment provides a method for preparing a tunneling oxide layer, comprising the following steps:

[0111] Step S11, placing the silicon wafer into the LPCVD furnace tube, maintaining the temperature at 550°C, completing vacuuming, leak detection and voltage stabilization during the heating process, and controlling the heating and constant temperature time between 1650s.

[0112] Step S12, when the furnace tube pressure is stabilized at about 760000 mtorr, the oxygen flow rate is maintained at 30000 sccm, the temperature is controlled at 610°C, and the time is controlled between 450s.

[0113] Step S13, the furnace tube pressure continues to be maintained at about 760000 mtorr, the oxygen flow rate is reduced to 0, and no other gas is introduced, the temperature is controlled at 610°C, and the time is controlled at 550s.

[0114] The thickness of the tunnel oxide layer in the ten-boat sample prepared in this embodiment was tested at multiple locations, and the average thickness of the multiple locations and the uniformity within the wafer were calculated. The results are shown in Table 2.

[0115] Table 2 Thickness of the tunneling oxide layer in the ten-boat sample prepared in Example 2

[0116]

[0117] Example 3

[0118] The method for preparing the TOPCon battery provided in this embodiment comprises the following steps:

[0119] Step S11, obtaining a silicon wafer, and forming a pyramid texture structure on the front side of the silicon wafer by cleaning and texture making.

[0120] Step S12, performing boron diffusion on the front side of the cleaned and textured silicon wafer to form an emitter.

[0121] Step S13, removing the BSG layer on the front side of the silicon wafer and performing back side polishing.

[0122] Step S14, depositing a tunneling oxide layer and an amorphous silicon layer on the back side of the silicon wafer.

[0123] Step S15 , phosphorus-doping the amorphous silicon layer on the back side to form a doped polysilicon layer and a PSG layer.

[0124] Step S16, using a chain alkali polishing device to remove the polysilicon layer on the front and edge, and the PSG layer on the back.

[0125] Step S17, forming an aluminum oxide layer on the emitter.

[0126] Step S18, forming a first silicon nitride layer on the doped polysilicon layer, and forming a second silicon nitride layer on the aluminum oxide layer.

[0127] Step S19, printing slurry on the front and back sides respectively and sintering to form electrodes.

[0128] Wherein, step S14 comprises:

[0129] Step S141, place the silicon wafer into the LPCVD furnace tube, maintain the temperature at 550°C, complete vacuuming, leak detection and voltage stabilization during the heating process, and control the heating and constant temperature time to 1650s.

[0130] Step S142, when the furnace tube pressure is stabilized at about 760000 mtorr, the oxygen flow rate is maintained at 30000 sccm, the temperature is controlled at 610°C, and the time is controlled at 450s.

[0131] Step S143, the furnace tube pressure continues to be maintained at about 760000 mtorr, the oxygen flow rate is reduced to 0, and no other gas is introduced, the temperature is controlled at 610 ° C, the temperature is maintained at, and the time is controlled at 550s.

[0132] Step S144, continue to complete constant temperature, leak detection, constant pressure, and vacuuming, and the time is controlled within 680s.

[0133] Step S145, control the furnace tube pressure at 300 mtorr, maintain the silane flow rate (front silane 320 sccm, rear silane 1650 sccm), control the temperature at about 600°C, and control the time at 1800 s.

[0134] Step S146, stop introducing silane and oxygen into the furnace tube, and continue to introduce nitrogen and stabilize the pressure.

[0135] Step S147, continue to introduce nitrogen into the furnace tube to reduce the temperature and return the pressure, and keep the time for 330 seconds.

[0136] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0137] The above-mentioned embodiments only express several implementation methods of the present invention, and the description is relatively specific and detailed, but it cannot be understood as limiting the scope of the invention patent. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be based on the attached claims, and the description can be used to interpret the content of the claims.

Claims

1. A method for preparing a tunneling oxide layer, characterized in that: The following steps are involved: Step S1, placing a silicon wafer in a furnace tube of a LPCVD device; Step S2, introducing oxygen, the oxygen flow rate is 30000sccm-50000sccm, the furnace tube pressure is 737000mtorr-760000mtorr, the temperature is 600℃-620℃, and the time is 400s-600s; Step S3, stop introducing oxygen, maintain the furnace tube pressure at 737000mtorr-760000mtorr, the temperature at 600℃-620℃, and the time at 400s-600s.

2. The preparation method according to claim 1, characterized in that In step S1, the furnace tube is heated to 550°C-620°C and kept at a constant temperature; Optionally, in step S1, the total time of heating and maintaining the temperature is controlled within a range of 1000s-1800s.

3. The preparation method according to claim 1, characterized in that: In the step S2, a purge gas is also introduced, and the flow rate of the purge gas is 1000 sccm-3000 sccm; Optionally, the purge gas is nitrogen.

4. The preparation method according to claim 3, characterized in that: In step S3, the supply of the purge gas is stopped.

5. The preparation method according to any one of claims 1 to 4, characterized in that The process temperature of step S2 and step S3 differs by 5°C; Optionally, the process temperatures of step S2 and step S3 remain the same.

6. A TOPCon battery, characterized in that: The invention has a tunneling oxide layer prepared by the preparation method according to any one of claims 1 to 5.

7. The TOPCon battery according to claim 6, characterized in that The TOPCon cell also includes a silicon substrate, an emitter and a doped polysilicon layer, the silicon substrate has a first side and a second side that are opposite to each other, the tunneling oxide layer is arranged on the first side, the doped polysilicon layer is arranged on a side of the tunneling oxide layer away from the silicon substrate, and the emitter is arranged on the second side.

8. A method for preparing a TOPCon battery, characterized in that: The following steps are involved: providing a silicon substrate; Forming a tunneling oxide layer on the first side of the silicon substrate by the preparation method according to any one of claims 1 to 5; A doped polysilicon layer is formed on a side of the tunnel oxide layer away from the silicon substrate.

9. The method for preparing a TOPCon battery according to claim 8, characterized in that: The step of forming the doped polysilicon layer comprises: Silane is introduced into the furnace tube of the LPCVD equipment, the flow rate of the silane is 1500sccm-1800sccm, the furnace tube pressure is 300mtorr-500mtorr, the temperature is 590℃-600℃, and the time is 1400s-1600s.

10. The method for preparing a TOPCon battery according to claim 8 or 9, characterized in that: The preparation method further comprises the following steps: An emitter is formed on a second side surface of the silicon substrate, wherein the second side surface is arranged opposite to the first side surface.

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