A Micro LED table with an ITO buffer layer and a method for preparing the same with uniform etching

Abstract

A Micro LED table with an ITO buffer layer and a method for preparing the etching uniformity thereof belong to the technical field of semiconductor devices and their processing technology. The present invention improves the original process flow, uses the ITO layer as an ICP etching buffer layer, and when etching the Micro LED table, etches at a rate according to the part with a faster etching rate in the wafer, and further over-etches to ensure that the epitaxial layer is etched through. The present invention uses ITO as a buffer layer to protect the underlying structure, and then uses wet etching or physical etching to remove the excess buffer layer to eliminate the impact of uneven etching. Furthermore, since the ITO buffer layer has good conductivity, it can improve the current expansion effect of the chip and enhance the brightness of the chip; to solve the problem of uneven etching rate for the wafer as a whole in the current Micro LED table etching process, and achieve the yield optimization of the Micro LED chip.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices and processing techniques thereof, and in particular relates to a Micro LED table with an ITO buffer layer and a method for preparing the etching uniformity thereof. Background Art

[0002] The most popular Micro LED mesa etching solution is to use inductively coupled plasma (ICP) to etch the epitaxial layer (Guo, W., Tai, J., Liu, J. et al. Process Optimization of Passive Matrix GaN-Based Micro LED Arrays for Display Applications. J. Electron. Mater. 48, 5195–5201 (2019)). Specifically, common etching gases are a certain proportion of boron trichloride (BCl3), chlorine (Cl2), and argon (Ar), and common etched materials are gallium nitride (GaN), indium gallium nitride (InGaN), or aluminum indium phosphide (AlInP). In order to form a patterned mesa, silicon oxide (SiO2) or chromium (Cr) + silicon oxide (SiO2) is used as a mask to block ICP from etching the undesired area. The specific process is as follows Figure 1 As shown, the epitaxial layer is Al x Ga y In 1-x-y P or In x Ga 1-x N, the substrate material is a silicon-based version or a matching integrated circuit version; first, a SiO2 mask layer is prepared on the surface of the epitaxial layer, and then a patterned photoresist mask is prepared on the SiO2 mask layer by a photolithography process, and then the SiO2 mask layer not covered by the photoresist is etched away by an ICP process, and a patterned SiO2 mask layer is formed after de-gumming, and then the patterned SiO2 mask layer is used to protect the Micro LED table, and a table of a specified shape is obtained through the second step of the ICP process, which is the basic unit of light emission in the Micro LED.

[0003] The principle of ICP is that the radio frequency current flows through the coil to generate an electromagnetic field in the chamber to excite the gas to produce plasma. The bias source controls the ion bombardment energy and bombards the sample surface to form physical / chemical etching. The main etching process includes:

[0004] i. Formation of reactive particles;

[0005] ii. The reactive particles reach the wafer surface and are adsorbed;

[0006] iii. Chemical adsorption reaction on the wafer surface to form chemical bonds and reaction products;

[0007] iv. Desorbing the chemical reaction products and removing them from the wafer surface and withdrawing them from the chamber;

[0008] Due to the complex physical and chemical reactions in the etching process, the interaction between the fields (electric field, flow field, force field, etc.) between different neutral particles and charged particles makes the etching process difficult to describe (Nasser, "Fundamentals of Gaseous Ionization and Plasma Electronics", John Wiley & Sons, 1971, Chapman, "Glow Discharge Processes", John Wiley & Sons).

[0009] like Figure 2 As shown, since the reaction gas needs to be extracted in time during the ICP etching process and the temperature of the sample surface is kept controllable by using helium gas passing through the back, the gas flow rate at the edge of the sample is generally faster, which will lead to a significant increase in the edge reaction rate / etching rate. Figure 2 (a) is a schematic diagram of the ICP etching principle. Figure 2 (b) is a photo of a sample with uneven etching. Figure 2 (c) is a schematic diagram of the central structure of the sample after etching. Figure 2 (d) is a schematic diagram of the sample edge structure after etching; due to different etching rates, the etching morphology of the sample center and the sample edge will be different. Figure 1 The uneven etching in the two steps will lead to serious consequences. Take the second step etching result as an example ( Figure 2 (b)), the epitaxial layer is not etched through ( Figure 2 (c) will lead to pixel leakage and crosstalk, that is, energizing a single pixel will cause adjacent pixels to emit light at the same time, making it impossible to achieve the requirement of independent addressing of each pixel; over-etching of the epitaxial layer ( Figure 2 (d)) will cause damage to the substrate material, which usually includes the driving circuit of the MicroLED screen, and may cause the product to fail to emit light normally. Summary of the invention

[0010] The purpose of the present invention is to provide a Micro LED table with an ITO buffer layer and a method for preparing the same with uniform etching. The present invention can solve the problem of uneven etching rate for the entire wafer in the current Micro LED table etching process, thereby optimizing the yield of the Micro LED chip.

[0011] The present invention improves the existing process flow, uses the ITO layer as the ICP etching buffer layer, etches at a rate according to the faster etching rate part of the wafer when etching the Micro LED mesa, and further over-etches to ensure that the epitaxial layer is etched through.

[0012] The Micro LED table with an ITO buffer layer described in the present invention consists of a substrate, a bonding metal layer, a lower ITO buffer layer, an epitaxial layer peeled off from a GaAs substrate, and an upper ITO buffer layer from bottom to top, wherein the bonding metal layer consists of a lower bonding metal layer and an upper bonding metal layer, the lower bonding metal layer consists of 200-400 nm thick Cr, 200-400 nm thick Pt, and 100-300 nm thick Au, and the upper bonding metal layer consists of 100-300 nm thick Au, 200-400 nm thick Pt, and 200-400 nm thick Cr; the epitaxial layer peeled off from the GaAs substrate consists of a 200-400 nm thick P-type AlInP layer, an 80-120 nm thick AlGaInP active region, and a 200-400 nm thick N-type AlInP layer; the thickness of the lower ITO buffer layer is 100-200 The thickness of the upper ITO buffer layer is 100~200 nm. The upper bottom diameter of the Micro LED table with ITO buffer layer is 2~3 μm, the lower bottom diameter is 3~5 μm, and the spacing between the table centers is 3.5~4.5μm.

[0013] The etching uniformity preparation method of a Micro LED table with an ITO buffer layer described in the present invention comprises the following steps:

[0014] (1) Film deposition:

[0015] The typical structure of the epitaxial layer is AlGaInP / GaAs multilayer material, which consists of a 0.5~2 mm thick GaAs substrate (to be removed later), a 200~400 nm thick N-type AlInP layer, an 80~120 nm thick AlGaInP active area, and a 200~400 nm thick P-type AlInP layer from bottom to top; a 100~200 nm thick lower ITO buffer layer is deposited on the surface of the P-type AlInP layer of the epitaxial layer using the EB process (electron beam evaporation), the indium-tin molar ratio of the ITO target is 9:1, and the deposition rate is 1~2 nm / s; then, 200~400 nm thick Cr, 200~400 nm thick Pt and 100~300 nm thick Au are deposited on the lower ITO buffer layer in sequence as the upper bonding metal layer using electron beam evaporation (EB), the target materials are pure chromium, platinum and gold, and the deposition rate is 1~2 nm / s;

[0016] Electron beam evaporation (EB) is used to deposit 200-400 nm thick Cr, 200-400 nm thick Pt and 100-300 nm thick Au as the lower bonding metal layer on the surface of the substrate, and the deposition rate is 1-2 nm / s; the substrate is a silicon-based substrate or an integrated circuit substrate;

[0017] (2) Bond the epitaxial layer to the substrate and remove the GaAs substrate from the epitaxial layer:

[0018] The upper bonding metal layer on the surface of the epitaxial layer is bonded to the lower bonding metal layer on the surface of the substrate, and bonding is performed at a certain temperature and pressure to make the metals melt each other and form a stable electrical-mechanical connection structure to obtain a bonding metal layer; the bonding temperature is 400-500 °C, the bonding pressure is 4000-6000 kg, and the bonding time is 20-40 minutes; then the GaAs substrate in the epitaxial layer is peeled off by laser to expose the N-type AlInP layer in the epitaxial layer, and the laser power is 80-150 W;

[0019] (3) An ITO buffer layer and a SiO2 mask layer are sequentially deposited on the surface of the N-type AlInP layer of the epitaxial layer of the stripped GaAs substrate:

[0020] An upper ITO buffer layer with a thickness of 100-200 nm is deposited on the surface of the N-type AlInP layer of the epitaxial layer peeled off the GaAs substrate by electron beam evaporation (EB), the indium-tin molar ratio of the ITO target is 9:1, and the deposition rate is 1-2 nm / s; then a SiO2 mask layer with a thickness of 200-400 nm is deposited on the surface of the upper ITO buffer layer by plasma enhanced chemical vapor deposition (PECVD); the reaction gas is N2O (flow rate 1400 sccm) + SiH4 (flow rate 500 sccm), the power of the plasma source is 80-150 W, and the deposition temperature is 200-300 °C; micro-nano structures such as electrodes can be prepared in advance on the surface of the epitaxial layer;

[0021] (4) Graphical process (smearing, exposure, development):

[0022] Spin-coat a photoresist (500-3000 nm) on the surface of the SiO2 mask layer obtained in step (3), using a positive photoresist (preferably 5214 photoresist model); after curing the photoresist, perform UV mask exposure, and then use a developer to remove the exposed photoresist (the developer is a TMAH aqueous solution), and the development time is 2-3 minutes; the mask is a first circular structure arranged periodically, that is, the Micro LED mesa structure to be prepared, the inside of the circular structure is a light-shielding area, and the outside of the circular structure is a light-transmitting area. The photoresist in the light-transmitting area is exposed to UV light and removed by the developer to obtain a patterned first photoresist mask layer; the diameter of the first circular structure is 1.5-2.5 μm, and the center spacing of the first circular structure is 3.5-4.5 μm; the diameter of the second circular structure is 2-3 μm, and the center spacing of the second circular structure is 3.5-4.5 μm.

[0023] (5) Using the patterned first photoresist mask layer as a mask, etch and prepare a patterned SiO2 mask layer, and use wet etching to remove the excess upper ITO buffer layer:

[0024] Under the mask of the patterned first photoresist mask layer obtained in step (4), the SiO2 mask layer is etched using an ICP process, the etching gas is CF4+Ar, the CF4 flow rate is 20-30 sccm, the Ar flow rate is 0-10 sccm, the etching time is 300-500 s, and the etching rate is 1-2 nm / s, so as to obtain a patterned SiO2 mask layer with the same structural size as the patterned first photoresist mask layer; this step is over-etching, at which time the SiO2 mask layer without the patterned first photoresist mask layer is completely etched through and removed, and the upper ITO buffer layer without the patterned first photoresist mask layer is also partially etched; after the etching is completed, the device is subjected to water bath ultrasound using acetone or isopropanol, the ultrasound power is 150-300 W, and the ultrasound time is 550-650 s to remove the patterned first photoresist mask layer;

[0025] The upper ITO buffer layer of the non-patterned SiO2 mask layer is wet-etched using an ITO etching solution, thereby exposing the epitaxial layer outside the patterned SiO2 mask layer; the ITO etching solution is a mixed solution of hydrochloric acid (HCl), nitric acid (HNO3) and water (H2O) in a volume ratio of 9:1:6, with an etching rate of 5-8 nm / s and an etching time of 20-30 s;

[0026] (6) Using the patterned SiO2 mask layer as a mask, etch the epitaxial layer and the lower ITO buffer layer outside the patterned SiO2 mask layer:

[0027] The epitaxial layer masked by the unpatterned SiO2 mask layer is etched by the ICP process, the etching gas is Cl2+BCl3+Ar, the Cl2 flow rate is 10~20 sccm, the BCl3 flow rate is 20~30 sccm, the Ar flow rate is 10~20 sccm, the etching time is 200~400 s, the etching rate of the epitaxial layer is 3~5 nm / s, the etching rate of the SiO2 mask layer is 3~5 nm / s, the epitaxial layer masked by the unpatterned SiO2 mask layer is etched through, the lower ITO buffer layer is partially etched, and the patterned SiO2 mask layer is completely etched away;

[0028] (7) Graphical process (smearing, exposure, development):

[0029] Spin-coat a photoresist (500-3000 nm) on the surface of the device obtained in step (6), using a positive photoresist (preferably 5214 photoresist); after curing the photoresist, perform UV mask exposure, and then use a developer to remove the exposed photoresist (the developer is a TMAH aqueous solution), and the development time is 2-3 minutes; the mask is a periodically arranged second circular structure, the inside of the circular structure is a light-shielding area, and the outside of the circular structure is a light-transmitting area, and the photoresist in the light-transmitting area is UV-exposed and removed to obtain a patterned second photoresist mask layer; the patterned second photoresist mask layer and the patterned first photoresist mask layer have symmetry centers that coincide with each other; the diameter of the second circular structure is 2-3 μm, the center interval of the second circular structure is 3.5-4.5 μm, and the diameter of the patterned second photoresist mask layer is larger than the diameter of the patterned first photoresist mask layer;

[0030] (8) Using the patterned second photoresist mask layer as a mask, IBE etches the ITO buffer layer and bonding metal layer to form a Micro LED mesa structure:

[0031] Using the patterned second photoresist mask layer prepared in step (7) as a mask, use IBE (ion beam etching) to etch through the lower ITO buffer layer and the bonding metal layer without the patterned second photoresist mask layer mask; the etching power is 200~400 W, the etching rate is 2~3 nm / s, and the etching time is 500~700 s; at this time, the lower ITO buffer layer and the bonding metal layer without the patterned second photoresist mask layer mask are completely removed. After the etching is completed, use acetone or isopropanol to perform water bath ultrasound on the device, the ultrasound power is 150~300 W, the ultrasound time is 550~650s, and the patterned second photoresist mask layer is removed, thereby obtaining a discrete, complete, and uniform Micro LED mesa structure on the substrate, the upper bottom diameter of the Micro LED mesa with the ITO buffer layer is 2~3 μm, the lower bottom diameter is 3~5 μm, and the center spacing of the mesa is 3.5~4.5 μm.

[0032] The principle analysis of the present invention is as follows:

[0033] In ICP etching, the non-uniformity of the whole sample is common. In the two-step ICP etching in the Micro LED mesa process, namely Figure 3 In steps (5) and (6), ITO is used as a buffer layer to protect the underlying structure, and a large amount of over-etching is used for etching (about 30% over-etching) to ensure that the center and edge of the sample are completely etched through to eliminate unevenness. Figure 3 In step (5), over-etching will etch to the upper ITO buffer layer without causing damage to the top of the epitaxial layer. Wet etching is then used to remove excess ITO. Figure 3 In step (6), over-etching will etch to the lower ITO buffer layer without causing damage to the substrate. Subsequently, ion beam etching (IBE) is used to remove the portion of the buffer layer exposed outside the mesa without causing crosstalk between pixels. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 :Process flow chart of Micro LED table preparation in the prior art;

[0035] Figure 2 : Schematic diagram of ICP etching principle and etching effect in the prior art;

[0036] Figure 3 : The process flow chart of the present invention;

[0037] Figure 4 : Schematic diagram of the etching effect of the process described in step 6 of the embodiment of the present invention. DETAILED DESCRIPTION

[0038] Embodiment 1: The Micro LED table with an ITO buffer layer described in the present invention is composed of a substrate, a bonding metal layer, a lower ITO buffer layer, an epitaxial layer peeled from a GaAs substrate, and an upper ITO buffer layer from bottom to top, wherein the bonding metal layer is composed of a lower bonding metal layer and an upper bonding metal layer, the lower bonding metal layer is composed of 300 nm thick Cr, 300 nm thick Pt, and 200 nm thick Au, and the upper bonding metal layer is composed of 200 nm thick Au, 300 nm thick Pt, and 300 nm thick Cr; the epitaxial layer peeled from the GaAs substrate is composed of a 300 nm thick P-type AlInP layer, a 100 nm thick AlGaInP active region, and a 300 nm thick N-type AlInP layer; the thickness of the lower ITO buffer layer is 150 nm, and the thickness of the upper ITO buffer layer is 150 nm; the upper base diameter of the Micro LED table with an ITO buffer layer is 2.5 μm, and the lower base diameter is 4.5 μm, and the center spacing of the mesas is 4 μm.

[0039] (1) Film deposition:

[0040] The typical structure of the epitaxial layer is AlGaInP / GaAs multilayer material, which is in order of 1 mm thick GaAs substrate (to be removed later), 300 nm thick N-type AlInP layer (called N surface or N side of epitaxial layer), 100 nm thick AlGaInP active area, 300 nm thick P-type AlInP layer (called P surface or P side of epitaxial layer). Electron beam evaporation (EB) is used to deposit a 150 nm thick lower ITO buffer layer on the surface of the P-type AlInP layer in the epitaxial layer. The indium-tin molar ratio of the ITO target is 9:1, and the deposition rate is 1 nm / s. Then, EB is used to deposit 300 nm Cr / 300 nm Pt / 200 nm Au as the upper bonding metal layer on the lower ITO buffer layer. The target materials are pure chromium, platinum, and gold, and the deposition rate is 1 nm / s.

[0041] EB is used to deposit 300 nm Cr / 300 nm Pt / 200 nm Au as a lower bonding metal layer on the substrate at a deposition rate of 1 nm / s; the substrate is a silicon-based substrate or a matching integrated circuit substrate;

[0042] (2) Bond the epitaxial layer to the substrate and remove the GaAs substrate from the epitaxial layer:

[0043] The upper bonding metal layer on the surface of the epitaxial layer is bonded to the lower bonding metal layer on the surface of the substrate, and bonding is performed at a certain temperature and pressure to make the metals melt each other and form a stable electrical-mechanical connection structure to obtain a bonding metal layer; the bonding temperature is 450 ° C, the bonding pressure is 5000 kg, and the bonding time is 30 minutes;

[0044] Then, the GaAs substrate in the epitaxy was peeled off using laser lift-off technology to expose the N-type AlInP layer in the epitaxial layer. The laser power was 100 W.

[0045] (3) An ITO buffer layer and a SiO2 mask layer are sequentially deposited on the surface of the N-type AlInP layer of the epitaxial layer of the stripped GaAs substrate:

[0046] On the surface of the N-type AlInP layer of the epitaxial layer of the peeled GaAs substrate, a 150 nm ITO buffer layer was deposited using EB. The indium-tin molar ratio of the ITO target was 9:1, and the deposition rate was 1 nm / s.

[0047] Then, a 300nm thick SiO2 mask layer is deposited on the upper ITO buffer layer using PECVD (plasma enhanced chemical vapor deposition); the reaction gas is N2O (flow rate 1400 sccm) + SiH4 (flow rate 500 sccm), the power of the plasma source is 100 W, and the deposition temperature is 250 °C; micro-nano structures such as electrodes can be prepared in advance on the surface of the epitaxial layer;

[0048] (4) Graphical process (smearing, exposure, development):

[0049] Spin-coat a photoresist (500-3000 nm, preferably 1500 nm) on the SiO2 mask layer obtained in step (3), using a positive photoresist (preferably 5214 photoresist model); after curing the photoresist, perform UV mask exposure, and then use a developer to remove the exposed photoresist (the developer is a TMAH aqueous solution), and the development time is 2 minutes; the mask is a first circular structure arranged periodically, that is, the Micro LED mesa structure to be prepared, the inside of the circular structure is a light-shielding area, and the outside of the circular structure is a light-transmitting area. The photoresist in the light-transmitting area is exposed to UV light and removed by the developer to obtain a patterned first photoresist mask layer; the diameter of the first circular structure is 2 μm, and the center interval of the first circular structure is 4 μm;

[0050] (5) Using the patterned first photoresist mask layer as a mask, etch and prepare a patterned SiO2 mask layer, and use wet etching to remove the excess upper ITO buffer layer:

[0051] Under the mask of the patterned first photoresist mask layer obtained in step (4), the SiO2 mask layer is etched using an ICP process, the etching gas is CF4+Ar, the CF4 flow rate is 25 sccm, the Ar flow rate is 0 sccm, the etching time is 400 s, and the etching rate is 1 nm / s, so as to obtain a patterned SiO2 mask layer with the same structural size as the patterned first photoresist mask layer; this step is over-etching, at which time the SiO2 mask layer without the patterned first photoresist mask layer is completely etched through (regardless of whether it is in the center or at the edge), and the upper ITO buffer layer without the patterned first photoresist mask layer is also partially etched; after the etching is completed, the device is subjected to water bath ultrasound using acetone or isopropanol, with an ultrasound power of 200 W and an ultrasound time of 600 s to remove the patterned first photoresist mask layer;

[0052] The upper ITO buffer layer without the patterned SiO2 mask layer is wet-etched using an ITO etching solution, thereby exposing the epitaxial layer outside the patterned SiO2 mask layer; the ITO etching solution is hydrochloric acid (HCl): nitric acid (HNO3): water (H2O) = 9:1:6 (volume ratio), the ITO etching rate is 6 nm / s, and the etching time is 25 s;

[0053] (6) Using the patterned SiO2 mask layer as a mask, etch the epitaxial layer and the lower ITO buffer layer outside the patterned SiO2 mask layer:

[0054] The epitaxial layer without the patterned SiO2 mask layer was etched using the ICP process. The etching gas was Cl2+BCl3+Ar, the Cl2 flow rate was 10 sccm, the BCl3 flow rate was 20 sccm, and the Ar flow rate was 10 sccm. The etching time was 300 s, the ICP etching rate for the epitaxial layer was 4 nm / s, and the ICP etching rate for the patterned SiO2 mask layer was 4 nm / s. The epitaxial layer without the patterned SiO2 mask layer was etched through and the lower ITO buffer layer was partially etched. After this step, the patterned SiO2 mask layer was also etched away.

[0055] (7) Graphical process (smearing, exposure, development):

[0056] Spin-coat a photoresist (500-3000 nm, preferably 1500 nm) on the surface of the device obtained in step (6), using a positive photoresist (preferably 5214 photoresist); after curing the photoresist, perform UV mask exposure, and then use a developer to remove the exposed photoresist (the developer is a TMAH aqueous solution), and the development time is 2 minutes; the mask is a periodically arranged second circular structure, the inside of the circular structure is a light-shielding area, and the outside of the circular structure is a light-transmitting area, the photoresist in the light-transmitting area is exposed to UV light and removed by the developer, to obtain a patterned second photoresist mask layer; the diameter of the second circular structure is 2.5 μm, the center interval of the second circular structure is 4 μm, and the symmetry center of the patterned second photoresist mask layer coincides with the center of the patterned first photoresist mask layer;

[0057] (8) Using the patterned second photoresist mask layer as a mask, IBE etches the ITO buffer layer and bonding metal layer to form a Micro LED mesa structure:

[0058] Using the patterned second photoresist mask layer prepared in step (7) as a mask, use IBE (ion beam etching) to etch through the lower ITO buffer layer and the bonding metal layer without the patterned second photoresist mask layer, wherein the diameter of the lower ITO buffer layer is greater than the diameter of the upper ITO buffer layer; the etching power is 300 W, the etching rate is 2 nm / s, and the etching time is 600 s; at this time, the lower ITO buffer layer and the bonding metal layer without the patterned second photoresist mask layer will be completely removed. After etching, use acetone or isopropanol to perform water bath ultrasound on the device, with an ultrasound power of 200 W and an ultrasound time of 600 s to remove the patterned second photoresist mask layer, thereby obtaining a discrete, complete, and uniform Micro LED mesa structure on the substrate, wherein the upper bottom diameter of the Micro LED mesa is 2.5 μm, the lower bottom diameter is 4.5 μm, and the center spacing of the mesa is 4 μm.

[0059] Effects and benefits of the present invention:

[0060] The present invention uses ITO as a buffer layer to protect the underlying structure and improve the non-uniformity caused by the two-step ICP etching in the Micro LED mesa process; then wet etching or physical etching is used to remove the excess buffer layer to eliminate the impact of the non-uniform etching. Furthermore, since the ITO buffer layer has good conductivity, it can improve the current expansion effect of the chip and increase the brightness of the chip. Figure 4 As shown (corresponding to the result of step 6 of Example 1), Figure 4 (a) is a photo of the sample edge. Figure 4(b) is a photo of the center of the sample. The side view of the bottom of the Micro LED mesa shows the over-etched ITO buffer layer. Even though the over-etching amount of the ITO layer in the two pictures is not consistent, the uneven over-etching of the buffer layer will not affect the subsequent process, so the design goal of improving uniformity can be achieved. Since the thickness of the silicon oxide layer was not optimized during the design of this sample, there is still unetched silicon oxide on the top of the Micro LED mesa.

Claims

1. A Micro LED mesa with an ITO buffer layer, characterized in that: From bottom to top, it consists of a substrate, a bonding metal layer, a lower ITO buffer layer, an epitaxial layer peeled off from a GaAs substrate, and an upper ITO buffer layer. The bonding metal layer consists of a lower bonding metal layer and an upper bonding metal layer. The lower bonding metal layer consists of 200~400 nm thick Cr, 200~400 nm thick Pt, and 100~300 nm thick Au, and the upper bonding metal layer consists of 100~300 nm thick Au, 200~400 nm thick Pt, and 200~400 nm thick Cr. The epitaxial layer peeled off from a GaAs substrate consists of a 200~400 nm thick P-type AlInP layer, an 80~120 nm thick AlGaInP active region, and a 200~400 nm thick N-type AlInP layer. The thickness of the lower ITO buffer layer is 100~200 nm, and the thickness of the upper ITO buffer layer is 100~200 nm. nm; the upper base diameter of the Micro-LED table with an ITO buffer layer is 2~3 μm, the lower base diameter is 3~5 μm, and the spacing between the table centers is 3.5~4.5 μm.

2. A method for preparing etching uniformity of a Micro LED table with an ITO buffer layer, characterized in that: The steps are as follows: (1) Film deposition: A 100-200 nm thick lower ITO buffer layer is deposited on the surface of the P-type AlInP layer of the epitaxial layer, and then 200-400 nm thick Cr, 200-400 nm thick Pt and 100-300 nm thick Au are deposited on the lower ITO buffer layer in sequence as an upper bonding metal layer; 200-400 nm thick Cr, 200-400 nm thick Pt and 100-300 nm thick Au are deposited on the surface of the substrate as a lower bonding metal layer; (2) Bonding the epitaxial layer to the substrate and removing the GaAs substrate from the epitaxial layer: The upper bonding metal layer on the surface of the epitaxial layer is bonded to the lower bonding metal layer on the surface of the substrate, and bonding is performed under a certain temperature and pressure to make the metals melt each other and form a stable electrical-mechanical connection structure to obtain a bonding metal layer; then the GaAs substrate in the epitaxial layer is peeled off using a laser to expose the N-type AlInP layer in the epitaxial layer; (3) An ITO buffer layer and a SiO2 mask layer are sequentially deposited on the surface of the N-type AlInP layer of the epitaxial layer of the stripped GaAs substrate: A 100-200 nm thick upper ITO buffer layer is deposited on the surface of the N-type AlInP layer of the epitaxial layer of the stripped GaAs substrate; then a 200-400 nm thick SiO2 mask layer is deposited on the surface of the upper ITO buffer layer; (4) Graphical process: Spin-coat a 500-3000 nm thick photoresist on the surface of the SiO2 mask layer obtained in step (3), using a positive photoresist; After the photoresist is cured, it is exposed to UV mask, and then the exposed photoresist is removed with developer, and the development time is 2 to 3 minutes; The mask is a first circular structure arranged periodically, that is, a Micro LED mesa structure to be prepared. The inside of the circular structure is a light-shielding area, and the outside of the circular structure is a light-transmitting area. The photoresist in the light-transmitting area is exposed to ultraviolet light and removed by a developer to obtain a patterned first photoresist mask layer. (5) Using the patterned first photoresist mask layer as a mask, etch and prepare a patterned SiO2 mask layer, and use wet etching to remove the excess upper ITO buffer layer: Under the mask of the patterned first photoresist mask layer obtained in step (4), the SiO2 mask layer is etched using an ICP process to obtain a patterned SiO2 mask layer having the same structural size as the patterned first photoresist mask layer; This step is over-etching, at which the SiO2 mask layer without the patterned first photoresist mask layer is completely etched through, and the upper ITO buffer layer without the patterned first photoresist mask layer is also partially etched; after the etching is completed, the device is subjected to water bath ultrasound using acetone or isopropanol to remove the patterned first photoresist mask layer; Using an ITO etching solution to wet-etch the upper ITO buffer layer masked by the non-patterned SiO2 mask layer, thereby exposing the epitaxial layer in the area outside the patterned SiO2 mask layer; (6) Using the patterned SiO2 mask layer as a mask, etch the epitaxial layer and the lower ITO buffer layer outside the patterned SiO2 mask layer: The epitaxial layer masked by the non-patterned SiO2 mask layer is etched by the ICP process, the epitaxial layer masked by the non-patterned SiO2 mask layer is etched through and the lower ITO buffer layer is partially etched, and the patterned SiO2 mask layer is completely etched away; (7) Graphical process: Spin-coat a 500-3000 nm thick photoresist on the surface of the device obtained in step (6), using a positive photoresist; After the photoresist is cured, it is exposed to UV mask, and then the exposed photoresist is removed with developer, and the development time is 2 to 3 minutes; The mask is a second circular structure arranged periodically, the inside of the circular structure is a light-shielding area, and the outside of the circular structure is a light-transmitting area. The photoresist in the light-transmitting area is exposed to ultraviolet light and removed to obtain a patterned second photoresist mask layer; The symmetry centers of the patterned second photoresist mask layer and the patterned first photoresist mask layer coincide with each other, and the diameter of the patterned second photoresist mask layer is greater than the diameter of the patterned first photoresist mask layer; (8) Using the patterned second photoresist mask layer as a mask, IBE etches the ITO buffer layer and bonding metal layer to form a Micro LED mesa structure: Using the patterned second photoresist mask layer prepared in step (7) as a mask, etch through the lower ITO buffer layer and bonding metal layer of the non-patterned second photoresist mask layer; At this time, the lower ITO buffer layer and bonding metal layer without the patterned second photoresist mask layer are completely removed. After etching, the device is subjected to water bath ultrasound using acetone or isopropyl alcohol to remove the patterned second photoresist mask layer, thereby obtaining a discrete, complete, and uniform Micro LED mesa structure on the substrate.

3. A method for preparing a Micro LED table with an ITO buffer layer with uniform etching as claimed in claim 2, characterized in that: The structure of the epitaxial layer in step (1) is an AlGaInP / GaAs multilayer material, which is, in order, a 0.5-2 mm thick GaAs substrate, a 200-400 nm thick N-type AlInP layer, an 80-120 nm thick AlGaInP active region, and a 200-400 nm thick P-type AlInP layer; in step (1), electron beam evaporation is used to deposit the lower ITO buffer layer and the upper bonding metal layer, and the deposition rate is 1-2 nm / s.

4. A method for preparing a Micro LED table with an ITO buffer layer with uniform etching as claimed in claim 2, characterized in that: In step (2), the bonding temperature is 400-500 °C, the bonding pressure is 4000-6000 kg, the bonding time is 20-40 minutes, and the laser power is 80-150 W.

5. A method for preparing a Micro LED mesa with an ITO buffer layer with uniform etching as claimed in claim 2, characterized in that: In step (3), an ITO buffer layer is deposited by electron beam evaporation; a SiO2 mask layer is deposited by plasma enhanced chemical vapor deposition, the reaction gas is N2O + SiH4, the power of the plasma source is 80-150 W, and the deposition temperature is 200-300°C.

6. A method for preparing a Micro LED mesa with an ITO buffer layer with uniform etching according to claim 2, characterized in that: In step (4), the diameter of the first circular structure is 1.5-2.5 μm, and the center spacing of the first circular structure is 3.5-4.5 μm.

7. A method for preparing etching uniformity of a Micro LED mesa with an ITO buffer layer according to claim 2, characterized in that: In step (5), the etching gas of the ICP process is CF4+Ar, the CF4 flow rate is 20~30 sccm, the Ar flow rate is 0~10 sccm, the etching time is 300~500 s, and the etching rate is 1~2 nm / s; the ultrasonic power of the water bath ultrasound is 150~300 W, and the ultrasonic time is 550~650 s; the ITO etching solution is a mixed solution of hydrochloric acid, nitric acid and water in a volume ratio of 9:1:6, the etching rate is 5~8 nm / s, and the etching time is 20~30 s.

8. A method for preparing a Micro LED mesa with an ITO buffer layer with uniform etching as claimed in claim 2, characterized in that: In step (6), the etching gas of the ICP process is Cl2+BCl3+Ar, the Cl2 flow rate is 10~20 sccm, the BCl3 flow rate is 20~30 sccm, the Ar flow rate is 10~20 sccm, the etching time is 200~400 s, the etching rate for the epitaxial layer is 3~5 nm / s, and the etching rate for the SiO2 mask layer is 3~5 nm / s.

9. A method for preparing etching uniformity of a Micro LED mesa with an ITO buffer layer according to claim 2, characterized in that: In step (7), the diameter of the second circular structure is 2-3 μm, and the center spacing of the second circular structure is 3.5-4.5 μm.

10. The method for preparing etching uniformity of a Micro LED mesa with an ITO buffer layer according to claim 2, characterized in that: In step (8), the etching power of IBE is 200~400 W, the etching rate is 2~3 nm / s, and the etching time is 500~700 s; the ultrasonic power of water bath ultrasound is 150~300 W, and the ultrasonic time is 550~650 s; the upper bottom diameter of the Micro-LED table with an ITO buffer layer is 2~3 μm, the lower bottom diameter is 3~5 μm, and the center distance between the table is 3.5~4.5 μm.

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