A light emitting diode chip and a method of manufacturing the same

Abstract

The application relates to the field of semiconductor photoelectric devices, and particularly discloses a light-emitting diode chip and a preparation method thereof. The light-emitting diode chip comprises a substrate, an epitaxial layer arranged on the substrate, the epitaxial layer comprising a first semiconductor layer, an active layer and a second semiconductor layer which are sequentially stacked on the substrate, the epitaxial layer being formed with a bare area exposing the first semiconductor layer, a first transparent conductive layer stacked on the second semiconductor layer, a second transparent conductive layer stacked on the first transparent conductive layer, a first electrode arranged on the first semiconductor layer in the bare area and electrically connected with the first semiconductor layer, and a second electrode arranged on the second transparent conductive layer and electrically connected with the second semiconductor layer, wherein the light transmittance of the first transparent conductive layer is less than that of the second transparent conductive layer, and the square resistance of the first transparent conductive layer is less than that of the second transparent conductive layer. The light-emitting efficiency of the light-emitting diode chip can be improved by implementing the application.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor optoelectronic devices, and in particular to a light emitting diode chip and a preparation method thereof. BACKGROUND

[0002] Most of the existing light emitting diodes are GaN-based epitaxial structures, that is, the P-type layer is a P-type GaN layer, and the work function is as high as 7.5eV, which is higher than the metal commonly used to prepare the electrode of the light emitting diode. This causes a high contact resistance between the P-type layer and the electrode, which increases the operating voltage. High voltage will cause an increase in heat production, a decrease in light efficiency, and a decrease in reliability. One of the commonly used methods is to form a transparent conductive film on the P-type layer to reduce the ohmic contact resistance and improve the current lateral expansion capability to avoid current aggregation. The commonly used transparent conductive layer is a tin-doped indium oxide layer (In2O3: Sn). When the doping concentration is high, the sheet resistance is low, which is beneficial to optimizing the ohmic contact between the P-type layer and the metal electrode, but the light transmittance will decrease significantly, which reduces the light efficiency. When the doping concentration is high, although the light transmittance is high, the sheet resistance is large, which leads to high operating voltage of the light emitting diode and poor reliability. In addition, the increase in voltage will also cause a decrease in light efficiency. SUMMARY

[0003] The technical problem to be solved by the present application is to provide a light emitting diode chip and a preparation method thereof, which can improve the light efficiency of the light emitting diode chip and reduce the operating voltage thereof.

[0004] To solve the above technical problems, the present application provides a light emitting diode chip, which comprises:

[0005] a substrate;

[0006] an epitaxial layer provided on the substrate, the epitaxial layer comprising a first semiconductor layer, an active layer and a second semiconductor layer stacked in sequence on the substrate; the epitaxial layer is formed with an exposed area exposing the first semiconductor layer;

[0007] a first transparent conductive layer stacked on the second semiconductor layer;

[0008] a second transparent conductive layer stacked on the first transparent conductive layer;

[0009] a first electrode provided on the first semiconductor layer in the exposed area and electrically connected with the first semiconductor layer; and

[0010] a second electrode provided on the second transparent conductive layer and electrically connected with the second semiconductor layer;

[0011] The first transparent conductive layer has a light transmittance less than that of the second transparent conductive layer and a sheet resistance less than that of the second transparent conductive layer.

[0012] The first transparent conductive layer has a light transmittance of 72% to 85%, and the second transparent conductive layer has a light transmittance of 92% to 98%.

[0013] The first transparent conductive layer has a sheet resistance of 4.6 Ω / sq to 13.8 Ω / sq, and the second transparent conductive layer has a sheet resistance of 18.6 Ω / sq to 24.3 Ω / sq.

[0014] The first transparent conductive layer is an ITO layer, an IZO layer, an AZO layer, an ATO layer or an FTO layer.

[0015] The second transparent conductive layer is an ITO layer, an IZO layer, an AZO layer, an ATO layer or an FTO layer.

[0016] The first transparent conductive layer and the second transparent conductive layer are both ITO layers.

[0017] The In content of the first transparent conductive layer is greater than or equal to the In content of the second transparent conductive layer.

[0018] The first transparent conductive layer is an ITO layer, and the In content of the ITO layer is 8 wt% to 15 wt%, and the thickness of the ITO layer is 100 nm to 300 nm.

[0019] The second transparent conductive layer is an ITO layer, and the In content of the ITO layer is 2 wt% to 5 wt%, and the thickness of the ITO layer is 100 nm to 300 nm.

[0020]

[0021] The first transparent conductive layer has a plurality of through holes arranged in an array to divide the first transparent conductive layer into a plurality of arrayed conductive units, and the second transparent conductive layer at least partially contacts the second semiconductor layer through the through holes.

[0022] The ratio of the cross-sectional area of the first transparent conductive layer to the cross-sectional area of the second transparent conductive layer is 5:100 to 30:100.

[0023] The cross section of the conductive unit is circular, rectangular or triangular, and the width of the cross section is 5 μm to 50 μm.

[0024] As the improvement of the above technical scheme, the first current blocking layer is arranged between the first electrode and the first semiconductor layer and is covered by the first electrode.

[0025] The second current blocking layer is arranged between the first transparent conductive layer and the second semiconductor layer and is arranged below the second electrode.

[0026] The second current blocking layer is provided with at least one conductive unit.

[0027] As the improvement of the above technical scheme, the first conductive layer is provided with a plurality of through holes in an array to divide the first conductive layer into a plurality of arrayed conductive units.

[0028] The through holes are filled with a third transparent conductive layer, and the third transparent conductive layer is a periodic structure, each period including a Sc2O3 layer and a Sc, Sn co-doped In2O3 layer stacked in sequence.

[0029] As the improvement of the above technical scheme, the thickness of the Sc2O3 layer is 1-2 nm.

[0030] The thickness of the Sc, Sn co-doped In2O3 layer is 10-15 nm, the Sc doping concentration is 5-10%, and the Sn doping concentration is 15-20%.

[0031] Correspondingly, the application also discloses a preparation method of the LED chip.

[0032] Forming an epitaxial layer on a substrate; the epitaxial layer includes a first semiconductor layer, an active layer and a second semiconductor layer stacked in sequence on the substrate.

[0033] Etching the epitaxial layer to form a bare area exposing the first semiconductor layer.

[0034] Forming a first transparent conductive layer and a second transparent conductive layer in sequence on the second semiconductor layer.

[0035] Forming a second electrode on the second transparent conductive layer and forming a first electrode on the first semiconductor layer in the bare area.

[0036] The light transmittance of the first transparent conductive layer is less than that of the second transparent conductive layer, and the sheet resistance of the first transparent conductive layer is less than that of the second transparent conductive layer.

[0037] As the improvement of the above technical solution, the step of sequentially forming the first transparent conductive layer and the second transparent conductive layer on the second semiconductor layer comprises:

[0038] forming a plurality of conductive units on the second semiconductor layer to obtain the first transparent conductive layer, and the plurality of conductive units are provided with the through hole;

[0039] forming the third transparent conductive layer in the through hole;

[0040] forming the second transparent conductive layer on the first transparent conductive layer and the third transparent conductive layer;

[0041] annealing at 500-600℃ in O2 atmosphere for 10-20min.

[0042] The present application has the following beneficial effects:

[0043] Referring to Figure 1 In the light emitting diode chip of one embodiment of the present application, the first transparent conductive layer and the second transparent conductive layer are sequentially arranged on the second semiconductor layer, wherein the light transmittance of the first transparent conductive layer is less than that of the second transparent conductive layer, and the sheet resistance of the first transparent conductive layer is less than that of the second transparent conductive layer. Based on the light emitting diode chip of the embodiment, the first transparent conductive layer is in contact with the second semiconductor layer, has small sheet resistance and strong current lateral expansion capability, can improve the current expansion capability and improve the ohmic contact between the electrode and the second semiconductor layer; and the second transparent conductive layer only needs to transmit current to the second transparent conductive layer, so a material with large sheet resistance and large light transmittance is used, which has little effect on the working voltage and can improve the light extraction efficiency. Through the cooperation of the two, the light emitting efficiency of the light emitting diode chip can be improved, and the working voltage can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0044] Figure 1 is a structure schematic diagram of the light emitting diode chip in one embodiment of the present application;

[0045] Figure 2 is a structure schematic diagram of the light emitting diode chip in another embodiment of the present application;

[0046] Figure 3 is a structure schematic diagram of the light emitting diode chip in another embodiment of the present application;

[0047] Figure 4 is a structure schematic diagram of the third transparent conductive layer in one embodiment of the present application. DETAILED DESCRIPTION

[0048] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings. It is hereby declared that the directional terms such as up, down, left, right, front, back, inside, and outside used in this text are based solely on the accompanying drawings and are not intended to specifically limit the invention.

[0049] See Figure 1 According to one embodiment of the present invention, a light-emitting diode chip is provided, which includes a substrate 1, an epitaxial layer 2, a first transparent conductive layer 3, a second transparent conductive layer 4, a first electrode 5, and a second electrode 6. The epitaxial layer 2 is disposed on the substrate 1 and includes a first semiconductor layer 21, an active layer 22, and a second semiconductor layer 23 sequentially stacked on the substrate 1. An exposed region 24 exposing the first semiconductor layer 21 is also formed on the epitaxial layer 2. The first transparent conductive layer 3 is stacked on the second semiconductor layer 23. The second transparent conductive layer 4 is stacked on the first transparent conductive layer 3. The first electrode 5 is disposed on the first semiconductor layer 21 within the exposed region 24 and is electrically connected to the first semiconductor layer 21. The second electrode 6 is disposed on the second transparent conductive layer 4 and is electrically connected to the second semiconductor layer 23. The transmittance of the first transparent conductive layer 3 is less than that of the second transparent conductive layer 4, and the sheet resistance of the first transparent conductive layer 3 is less than that of the second transparent conductive layer 4. In the LED chip of this embodiment, the first transparent conductive layer 3 is in contact with the second semiconductor layer 23. Its low sheet resistance and strong lateral current diffusion capability enhance current diffusion and improve the ohmic contact between the electrode and the second semiconductor layer 23. The second transparent conductive layer 4 only needs to transmit current; therefore, it uses a material with high sheet resistance and high light transmittance, which has minimal impact on the operating voltage and improves light extraction efficiency. Through the combination of these two components, the luminous efficiency of the LED chip can be improved, and its operating voltage can be reduced.

[0050] Specifically, substrate 1 can be a sapphire substrate, a silicon substrate, a silicon carbide substrate, a gallium oxide substrate, or a zinc oxide substrate, but is not limited thereto. Preferably, it is a sapphire substrate. More preferably, it is a patterned sapphire substrate.

[0051] Specifically, different types of the epitaxial layer 2 can be selected according to different light-emitting wavelengths of the light-emitting LED chip. Specifically, the light-emitting diode chip of the present application can be a red, green, yellow or violet LED chip, and different types of the first semiconductor layer 21, the active layer 22 and the second semiconductor layer 23 can be selected based on the control of the light-emitting wavelength. For example, in one embodiment of the present application, when the light-emitting diode chip is a blue LED chip or a green LED chip, the first semiconductor layer 21 can be an N-type GaN layer, the active layer 22 can be an InGaN-GaN multi-quantum well layer, and the second semiconductor layer 23 can be a P-type GaN layer. In another embodiment of the present application, when the light-emitting diode chip is a violet LED chip, the first semiconductor layer 21 can be an N-type AlGaN layer, the active layer 22 can be an AlGaN-AlGaN multi-quantum well layer, and the second semiconductor layer 23 can be a P-type AlGaN layer, but the present application is not limited thereto. Preferably, in the present embodiment, the first semiconductor layer 21 is an N-type GaN layer, the active layer 22 is an InGaN-GaN multi-quantum well layer, and the second semiconductor layer 23 can be a P-type GaN layer.

[0052] Specifically, the first transparent conductive layer 3 is an ITO layer, an IZO layer, an AZO layer, an ATO layer or an FTO layer, but the present application is not limited thereto. Preferably, the first transparent conductive layer 3 is an ITO layer. The second transparent conductive layer 4 is an ITO layer, an IZO layer, an AZO layer, an ATO layer or an FTO layer. Preferably, the second transparent conductive layer 4 is an ITO layer. It should be noted that the materials of the first transparent conductive layer 3 and the second transparent conductive layer 4 can be the same or different. When the materials of the first transparent conductive layer 3 and the second transparent conductive layer 4 are the same and both are ITO layers (i.e. Sn-doped In2O3 layers), the In content of the first transparent conductive layer 3 is greater than or equal to the In content of the second transparent conductive layer 4. By controlling the In content, the sheet resistance of the first transparent conductive layer 3 can be lower and the light transmittance of the first transparent conductive layer 3 can be smaller, while the sheet resistance of the second transparent conductive layer 4 can be higher and the light transmittance of the second transparent conductive layer 4 can be higher, thereby achieving the effects of reducing the working voltage and improving the light-emitting efficiency at the same time. More specifically, the In content of the first transparent conductive layer 3 is 8wt% to 15wt%, and the In content of the second transparent conductive layer 4 is 2wt% to 5wt%.

[0053] Specifically, in one embodiment, the light transmittance of the first transparent conductive layer 3 is 72% to 85%, and the sheet resistance thereof is 4.6Ω / sq to 13.8Ω / sq. The light transmittance of the first transparent conductive layer 3 is 92% to 98%, and the sheet resistance thereof is 18.6Ω / sq to 24.3Ω / sq. Based on the control of the light transmittance and the sheet resistance, the first transparent conductive layer 3 and the second transparent conductive layer 4 can be well matched, and the effects of reducing the working voltage and improving the light-emitting efficiency can be achieved at the same time.

[0054] Specifically, in one embodiment, the thickness of the first transparent conductive layer 3 is 1000nm to 2000nm. The thickness of the second transparent conductive layer 4 is 1000nm to 2000nm.

[0055] Specifically, the first electrode 5 and the second electrode 6 are each a metal single-layer or a stacked-layer structure common in the art, which can be made of one or more of Cr, Al, Ti, Pt, Ni, Au, Cu, and Ag, for example.

[0056] Preferably, referring to Figure 2 In one embodiment of the present application, a plurality of through holes 31 are arranged on the first conductive layer to divide the first transparent conductive layer 3 into a plurality of arrayed conductive units 32; based on this implementation, the uniformity of current distribution is improved while the light extraction efficiency is also improved, further improving the light emitting efficiency.

[0057] Specifically, in this embodiment, the ratio of the sum of the cross-sectional areas of the conductive units 32 (i.e. the cross-sectional area of the first transparent conductive layer 3) to the cross-sectional area of the second transparent conductive layer 4 is 5:100-30:100; if the area of the first transparent conductive layer 3 is too small, it will affect the ohmic contact between the second electrode 6 and the second semiconductor layer 23.

[0058] Specifically, the cross-sectional shape of the conductive unit 32 can be circular, rectangular, or triangular, but is not limited thereto. The width of the conductive unit 32 is wherein the width is a characteristic dimension of the conductive unit 32, for example, when the cross-section of the conductive unit 32 is circular, the width is the diameter thereof; when the cross-section of the conductive unit 32 is rectangular, the width is the length dimension thereof; when the cross-section of the conductive unit 32 is triangular, the width is the longest side length thereof.

[0059] Preferably, referring to Figure 2 In one embodiment, the light emitting diode chip further comprises a first current blocking layer 7 and a second current blocking layer 8, the first current blocking layer 7 is arranged between the first electrode 5 and the first semiconductor layer 21 and is covered by the first electrode 5; the second current blocking layer 8 is arranged between the first transparent conductive layer 3 and the second semiconductor layer 23, and is arranged below the second electrode 6, the projection of the second electrode 6 on the surface of the second current blocking layer 8 covers the second current blocking layer 8; at least one conductive unit 32 is arranged on the second current blocking layer 8. The first current blocking layer 7 and the second current blocking layer 8 can improve the uniformity of current distribution and improve the light emitting efficiency.

[0060] Preferably, referring to Figure 3 and Figure 4In another embodiment of the present application, the via 31 between the conductive units 32 is filled with a third transparent conductive layer 9, the third transparent conductive layer 9 is a periodic structure, each period includes a Sc2O3 layer 91 and a Sc, Sn co-doped In2O3 layer 92 stacked in sequence. Specifically, the third transparent conductive layer 9 can further improve the light transmittance, and reduce the contact resistance of the electrode and the epitaxial layer 2, and reduce the operating voltage of the LED chip. Through the cooperation of the first transparent conductive layer 3, the second transparent conductive layer 4 and the third transparent conductive layer 9 of the structure, one can greatly improve the luminous efficiency and reduce the operating voltage; two, can cancel the current blocking layer in the traditional light emitting diode chip, save the process. Three, due to the difference in refractive index between the first transparent conductive layer 3 and the third transparent conductive layer 9, the light will change the exit angle when passing through the structure composed of the first transparent conductive layer 3 and the third transparent conductive layer 9, preventing the light from entering the etched sidewall (i.e. the sidewall of the exposed area 24), improving the light extraction efficiency, especially for Micro-LED, which can greatly improve the luminous efficiency.

[0061] Specifically, the period number of the third transparent conductive layer 9 is 3-20, the thickness of the Sc2O3 layer 91 is 1-2 nm; the thickness of the Sc, Sn co-doped In2O3 layer 92 is 10-15 nm, the Sc doping concentration is 5-10%, and the Sn doping concentration is 15-20%. Among them, the doping concentration of Sn refers to the ratio of the number of Sc atoms to the total number of Sc, Sn and In atoms.

[0062] It should be noted that the light emitting diode chip in the present application can also include a passivation layer and other structures commonly used in the art, but is not limited thereto.

[0063] Correspondingly, the present application also discloses a preparation method of a light emitting diode chip, for preparing the light emitting diode chip described above, which comprises the following steps:

[0064] (1) forming an epitaxial layer 2 on a substrate 1;

[0065] Specifically, the epitaxial layer 2 can be formed on the substrate 1 by MOCVD, but is not limited thereto.

[0066] (2) etching the epitaxial layer 2 to form an exposed area 24 exposing the first semiconductor layer 21;

[0067] Specifically, the epitaxial layer 2 is etched by ICP or RIE etching equipment, the first exposed area 24, and the first exposed area 24 is etched to the first semiconductor layer 21.

[0068] (3) forming a first transparent conductive layer 3 and a second transparent conductive layer 4 on the second semiconductor layer 23 in sequence;

[0069] Specifically, the first transparent conductive layer 3, the second transparent conductive layer 4 and the third transparent conductive layer 9 can be formed by PVD, electron beam evaporation and other processes, but are not limited thereto.

[0070] Specifically, in one embodiment, in order to form the first transparent conductive layer 3 composed of a plurality of light-transmitting units, a method of first forming a whole layer and then etching, or a method of first forming a specific photoresist pattern and then forming light-transmitting units according to the pattern can be adopted. Correspondingly, in forming the third transparent conductive layer 9, in order to ensure that it is accurately filled in the through hole 31, a process of first forming a whole layer and then etching, or forming through a photoresist pattern can also be adopted. But are not limited thereto.

[0071] More specifically, in one embodiment, step (3) comprises:

[0072] (3.1) forming a plurality of conductive units 32 on the second semiconductor layer 23 to obtain the first transparent conductive layer 3; the plurality of conductive units 32 are provided with through holes 31 therebetween;

[0073] (3.2) forming the third transparent conductive layer 9 in the through hole 31;

[0074] (3.3) forming the second transparent conductive layer 4 on the first transparent conductive layer 3 and the third transparent conductive layer 9;

[0075] (3.4) annealing at 500-600℃ in an O2 atmosphere for 10-20min.

[0076] Through annealing, the crystal quality of the first transparent conductive layer 3, the second transparent conductive layer 4 and the third transparent conductive layer 9 can be improved, the light transmittance is improved, and the light emitting efficiency of the light emitting diode chip is improved.

[0077] (4) forming the second electrode 6 on the second transparent conductive layer 4, and forming the first electrode 5 on the first semiconductor layer 21 of the exposed area 24;

[0078] Specifically, the first electrode 5 and the second electrode 6 can be formed by an evaporation process, which can be formed simultaneously or in steps, but are not limited thereto.

[0079] The present application will be further described below with specific embodiments:

[0080] Embodiment 1

[0081] This embodiment provides a light emitting diode chip, which comprises a sapphire substrate, an epitaxial layer (N-GaN layer, InGaN-GaN multi-quantum well layer and P-GaN layer) provided on the sapphire substrate, and an exposed area exposing the N-GaN layer formed by etching on the epitaxial layer. The N-GaN layer in the exposed area is provided with a first electrode.

[0082] The first transparent conductive layer and the second transparent conductive layer are sequentially arranged on the P-GaN layer, the first transparent conductive layer is an integral layer structure, which is an ITO layer, the In content of the ITO layer is 10wt%, and the thickness of the ITO layer is The second transparent conductive layer is an integral layer structure, which is an ITO layer, the In content of the ITO layer is 5wt%, and the thickness of the ITO layer is

[0083] The second transparent conductive layer is further provided with a second electrode.

[0084] The preparation method of the light emitting diode chip in the embodiment is as follows:

[0085] (1) forming an epitaxial layer on a sapphire substrate;

[0086] (2) etching the epitaxial layer to form a bare area exposing the first semiconductor layer;

[0087] (3) sequentially forming a first transparent conductive layer and a second transparent conductive layer on the second semiconductor layer; after the growth is completed, annealing at 550℃ for 15min.

[0088] (4) forming a second electrode on the second transparent conductive layer and a first electrode on the first semiconductor layer in the bare area.

[0089] Embodiment 2

[0090] The embodiment provides a light emitting diode chip, which is different from the embodiment 1 in that:

[0091] The first transparent conductive layer comprises a plurality of circular conductive units, the diameter of the conductive units is The conductive units are arrayed on the P-type GaN layer. The plurality of conductive units are formed with a through hole. The total cross-sectional area of the conductive units is 45% of the cross-sectional area of the second transparent conductive layer.

[0092] Correspondingly, in the preparation method, a photoresist is first formed into a pattern, then the first transparent conductive layer is deposited, and finally the photoresist is removed.

[0093] The rest is the same as the embodiment 1.

[0094] Embodiment 3

[0095] The embodiment provides a light emitting diode chip, which is different from the embodiment 2 in that:

[0096] The third transparent conductive layer is filled in the through hole. The third transparent conductive layer is a periodic structure, and the number of periods is 10. Each period comprises a Sc2O3 layer and a Sc, Sn co-doped In2O3 layer which are stacked in sequence. The thickness of the Sc2O3 layer is 1.5 nm. The thickness of the Sc, Sn co-doped In2O3 layer is 13.5 nm, the Sc doping concentration of which is 7.5%, and the Sn doping concentration of which is 17.6%.

[0097] Correspondingly, the preparation method further comprises a step of preparing the third transparent conductive layer.

[0098] Comparative Example 1

[0099] The present comparative example provides a light emitting diode chip, which is different from the example 1 in that:

[0100] The second transparent conductive layer is not included, the first transparent conductive layer is an ITO layer, the In content of which is 8%, and the thickness of which is

[0101] The rest is the same as the example 1.

[0102] The light emitting diode chips obtained from the example 1 to the example 3 and the comparative example 1 are tested, and the specific results are as follows:

[0103] Brightness (mW) Voltage (V) Example 1 115.4 3.096 Example 2 120.5 3.102 Example 3 132.5 2.814 Comparative Example 1 110.3 3.125

[0104] The above is the preferred embodiment of the present application. It should be noted that for those skilled in the art, without departing from the principles of the present application, a number of improvements and refinements can be made, which are also considered within the scope of protection of the present application.

Claims

1. A light emitting diode chip, characterized by The application relates to a transparent conductive film, which comprises the following components: a substrate; an epitaxial layer arranged on the substrate, the epitaxial layer comprising a first semiconductor layer, an active layer and a second semiconductor layer which are sequentially arranged on the substrate; the epitaxial layer is formed with a bare area exposing the first semiconductor layer; a first transparent conductive layer is arranged on the second semiconductor layer; a second transparent conductive layer is arranged on the first transparent conductive layer; a first electrode is arranged on the first semiconductor layer in the bare area and is electrically connected with the first semiconductor layer; and a second electrode is arranged on the second transparent conductive layer and is electrically connected with the second semiconductor layer; wherein the light transmittance of the first transparent conductive layer is less than that of the second transparent conductive layer, and the sheet resistance of the first transparent conductive layer is less than that of the second transparent conductive layer; a plurality of through holes are arranged in the first transparent conductive layer to divide the first transparent conductive layer into a plurality of arrayed conductive units; the through holes are filled with a third transparent conductive layer, and the third transparent conductive layer is a periodic structure, each period comprising a Sc2O3 layer and a Sc and Sn co-doped In2O3 layer which are sequentially arranged; the thickness of the Sc2O3 layer is 1-2 nm; the thickness of the Sc and Sn co-doped In2O3 layer is 10-15 nm, the Sc doping concentration is 5-10%, and the Sn doping concentration is 15-20%; the light transmittance of the first transparent conductive layer is 72-85%, and the light transmittance of the second transparent conductive layer is 92-98%; the sheet resistance of the first transparent conductive layer is 4.6-13.8 ohm / sq, and the sheet resistance of the second transparent conductive layer is 18.6-24.3 ohm / sq; the first transparent conductive layer is an ITO layer, an IZO layer, an AZO layer, an ATO layer or an FTO layer; the second transparent conductive layer is an ITO layer, an IZO layer, an AZO layer, an ATO layer or an FTO layer; the first transparent conductive layer and the second transparent conductive layer are both ITO layers; the In content in the first transparent conductive layer is greater than or equal to the In content in the second transparent conductive layer; the first transparent conductive layer is an ITO layer, the In content is 8-15 wt%, and the thickness is 600-2100 angstrom; the second transparent conductive layer is an ITO layer, the In content is 2-5 wt%, and the thickness is 150-450 angstrom; the first transparent conductive layer is provided with a plurality of through holes to divide the first transparent conductive layer into a plurality of arrayed conductive units; the ratio of the cross-sectional area of the first transparent conductive layer to the cross-sectional area of the second transparent conductive layer is 5:100-30:100; the cross section of the conductive unit is circular, rectangular or triangular, and the width is 2000-45000 angstrom; and the first transparent conductive layer is provided with a first current blocking layer and a second current blocking layer, the first current blocking layer is arranged between the first electrode and the first semiconductor layer and is covered by the first electrode. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 2. The light emitting diode chip of claim 1, wherein, ​ ​ ​ ​ 3. The light emitting diode chip of claim 1, wherein the first and second electrodes are formed of a material selected from the group consisting of titanium, nickel, gold, platinum, silver, and alloys thereof. ​ ​ 4. The light emitting diode chip according to any one of claims 1 to 3, wherein ​ ​ 5. The light emitting diode chip of claim 1, wherein the first and second layers of the first and second superlattices are formed of a plurality of layers of alternating AlGaN and GaN. ​ ​ ​ 6. The light emitting diode chip of claim 5, wherein the first and second layers of transparent material are formed of a material having a refractive index of about 2.0 or greater. ​ The second current blocking layer is arranged between the first transparent conductive layer and the second semiconductor layer, and is arranged below the second electrode, a projection of the second electrode on a surface where the second current blocking layer is located covers the second current blocking layer; At least one conductive unit is arranged on the second current blocking layer.

7. A method for producing a light emitting diode chip, for producing a light emitting diode chip according to any one of claims 1 to 6, characterized in that Comprise: forming an epitaxial layer on a substrate; the epitaxial layer comprises a first semiconductor layer, an active layer and a second semiconductor layer which are sequentially stacked on the substrate; etching the epitaxial layer to form an exposed area exposing the first semiconductor layer; forming a first transparent conductive layer and a second transparent conductive layer on the second semiconductor layer in sequence; forming a second electrode on the second transparent conductive layer and a first electrode on the first semiconductor layer in the exposed area; wherein the light transmittance of the first transparent conductive layer is less than that of the second transparent conductive layer, and the square resistance of the first transparent conductive layer is less than that of the second transparent conductive layer; wherein the step of forming a first transparent conductive layer and a second transparent conductive layer on the second semiconductor layer in sequence comprises: forming a plurality of conductive units on the second semiconductor layer to obtain a first transparent conductive layer; a through hole is arranged between the plurality of conductive units; forming a third transparent conductive layer in the through hole; forming a second transparent conductive layer on the first transparent conductive layer and the third transparent conductive layer; annealing at 500-600 DEG C in an O2 atmosphere for 10-20 min.

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