Synchronization of load / store operations of predetermined class

Abstract

For a predetermined class of load / store operations, the load / store processing circuitry buffers stored data of the predetermined class of store operations in a predetermined class of store buffer and controls store-to-load forwarding of the stored data from the buffer to the predetermined class of load operations. A predetermined class of load / store synchronization instruction controls the load / store processing circuitry such that: a predetermined class of load / store synchronization instruction; for a latter non-predetermined category load / store operation of the risk occurring in program order after the predetermined category load / store synchronization instruction and a earlier predetermined category store operation of the risk occurring in program order before the predetermined category load / store synchronization instruction (wherein the address ranges overlap), the predetermined category load / store operation of the risk occurring in program order after the predetermined category load / store synchronization instruction. The later non-predetermined class load / store operation of the risk observes the result of the earlier predetermined class store operation of the risk. In a case where there is no interventional predetermined class load / store synchronization instruction between a given earlier predetermined class store operation and a given later non-predetermined class load / store operation having an overlapping address range, the predetermined class load / store synchronization instruction is synchronized with the predetermined class store operation. The given, later, non-predetermined category of load / store operation is permitted not to observe the results of the given, earlier, predetermined category of store operation.

Description

Background Art Technical Field

[0001] The present technology relates to the field of data processing. Technical Background

[0003] Load / store operations are operations performed by the data processing system to request access to data in a memory system. Load / store operations may also be used by the processor core to control components of the data processing system (such as I / O devices or hardware accelerators) that communicate with the processor core via a memory system interconnect by triggering a read / write request to be issued to the memory system that specifies a memory address mapped to the component.

[0004] There may be challenges in controlling the ordering of load / store operations so that a later load / store operation processed after an earlier load / store operation for an overlapping address range observes the results of the earlier load / store operation. The hardware circuit logic for managing such ordering enforcement may be expensive and complex to implement. Summary of the invention

[0005] At least some examples of the present technology provide an apparatus comprising:

[0006] a load / store processing circuit configured to process a load / store operation, wherein for a predetermined category of load / store operations, the load / store processing circuit is configured to: buffer storage data of the predetermined category of storage operations in a predetermined category of storage buffers, and control store-to-load forwarding of the storage data from the predetermined category of storage buffers to the predetermined category of load operations; and

[0007] an instruction decoder, the instruction decoder being responsive to a predetermined class load / store synchronization instruction, for controlling the load / store processing circuitry so that: for a hazard's later non-scheduled class load / store operation that occurs in program order after the predetermined class load / store synchronization instruction and an hazard's earlier predetermined class store operation that occurs in program order before the predetermined class load / store synchronization instruction, the hazard's later non-scheduled class load / store operation observes a result of the hazard's earlier predetermined class store operation, wherein an address range accessed by the hazard's later non-scheduled class load / store operation overlaps an address range accessed by the hazard's earlier predetermined class store operation; wherein:

[0008] The load / store processing circuitry is configured to permit a given earlier predetermined class store operation to produce a result that fails to observe a result of the given earlier predetermined class store operation in the absence of any intervening predetermined class load / store synchronization instructions occurring in program order between the given later non-scheduled class load / store operation, wherein an address range accessed by the given earlier predetermined class store operation overlaps an address range accessed by the given later non-scheduled class load / store operation.

[0009] At least some examples of the present technology provide a non-transitory computer-readable medium for storing a computer-readable code for manufacturing an apparatus, the apparatus comprising:

[0010] a load / store processing circuit configured to process a load / store operation, wherein for a predetermined category of load / store operations, the load / store processing circuit is configured to: buffer storage data of the predetermined category of storage operations in a predetermined category of storage buffers, and control store-to-load forwarding of the storage data from the predetermined category of storage buffers to the predetermined category of load operations; and

[0011] an instruction decoder, the instruction decoder being responsive to a predetermined class load / store synchronization instruction, for controlling the load / store processing circuitry so that: for a hazard's later non-scheduled class load / store operation that occurs in program order after the predetermined class load / store synchronization instruction and an hazard's earlier predetermined class store operation that occurs in program order before the predetermined class load / store synchronization instruction, the hazard's later non-scheduled class load / store operation observes a result of the hazard's earlier predetermined class store operation, wherein an address range accessed by the hazard's later non-scheduled class load / store operation overlaps an address range accessed by the hazard's earlier predetermined class store operation; wherein:

[0012] The load / store processing circuitry is configured to permit a given earlier predetermined class store operation to produce a result that fails to observe a result of the given earlier predetermined class store operation in the absence of any intervening predetermined class load / store synchronization instructions occurring in program order between the given later non-scheduled class load / store operation, wherein an address range accessed by the given earlier predetermined class store operation overlaps an address range accessed by the given later non-scheduled class load / store operation.

[0013] At least some examples of the present technology provide a method comprising:

[0014] For a predetermined class of load / store operations, buffering store data of the predetermined class of store operations in a predetermined class of store buffers, and controlling store-to-load forwarding of the store data from the predetermined class of store buffers to the predetermined class of load operations;

[0015] In response to a predetermined class load / store synchronization instruction, the load / store processing circuit is controlled to control: for a hazard's later non-scheduled class load / store operation that occurs after the predetermined class load / store synchronization instruction in program order and an earlier predetermined class store operation of the hazard that occurs before the predetermined class load / store synchronization instruction in program order, the hazard's later non-scheduled class load / store operation observes a result of the hazard's earlier predetermined class store operation, wherein an address range accessed by the hazard's later non-scheduled class load / store operation overlaps an address range accessed by the hazard's earlier predetermined class store operation; wherein:

[0016] In the absence of any intervening scheduled class load / store synchronization instructions occurring in program order between a given earlier scheduled class store operation and a given later non-scheduled class load / store operation, permitting the given later non-scheduled class load / store operation to produce a result of failing to observe a result of the given earlier scheduled class store operation, wherein an address range accessed by the given earlier scheduled class store operation overlaps with an address range accessed by the given later non-scheduled class load / store operation.

[0017] At least some examples of the present technology provide an apparatus comprising:

[0018] load / store processing circuitry for processing load / store operations including protected control stack (GCS) load / store operations for accessing a GCS data structure for protecting return status information for returning from a function call or an exception; and

[0019] an instruction decoder responsive to a GCS synchronization instruction for controlling the load / store processing circuitry so that: for a hazard's later non-GCS load / store operation that occurs after the GCS synchronization instruction in program order and a hazard's earlier GCS store operation that occurs before the GCS synchronization instruction in program order, the hazard's later non-GCS load / store operation observes a result of the hazard's earlier GCS store operation, wherein an address range accessed by the hazard's later non-GCS load / store operation overlaps an address range accessed by the hazard's earlier GCS store operation; wherein:

[0020] The load / store processing circuitry is configured to permit a given earlier GCS store operation to produce a result that fails to observe a result of the given earlier GCS store operation in the absence of any intervening GCS synchronization instructions occurring in program order between the given earlier GCS store operation and a given later non-GCS load / store operation, wherein an address range accessed by the given earlier GCS store operation overlaps with an address range accessed by the given later non-GCS load / store operation.

[0021] At least some examples of the present technology provide a non-transitory computer-readable medium for storing a computer-readable code for manufacturing an apparatus, the apparatus comprising:

[0022] load / store processing circuitry for processing load / store operations including protected control stack (GCS) load / store operations for accessing a GCS data structure for protecting return status information for returning from a function call or an exception; and

[0023] an instruction decoder responsive to a GCS synchronization instruction for controlling the load / store processing circuitry so that: for a hazard's later non-GCS load / store operation that occurs after the GCS synchronization instruction in program order and a hazard's earlier GCS store operation that occurs before the GCS synchronization instruction in program order, the hazard's later non-GCS load / store operation observes a result of the hazard's earlier GCS store operation, wherein an address range accessed by the hazard's later non-GCS load / store operation overlaps an address range accessed by the hazard's earlier GCS store operation; wherein:

[0024] The load / store processing circuitry is configured to permit a given earlier GCS store operation to produce a result that fails to observe a result of the given earlier GCS store operation in the absence of any intervening GCS synchronization instructions occurring in program order between the given earlier GCS store operation and a given later non-GCS load / store operation, wherein an address range accessed by the given earlier GCS store operation overlaps with an address range accessed by the given later non-GCS load / store operation.

[0025] At least some examples of the present technology provide a method comprising:

[0026] Processing load / store operations including guarded control stack (GCS) load / store operations for accessing a GCS data structure for protecting return status information for returning from a function call or an exception; and

[0027] In response to a GCS synchronization instruction, controlling the load / store processing circuitry such that: for a hazard's later non-GCS load / store operation that occurs after the GCS synchronization instruction in program order and a hazard's earlier GCS store operation that occurs before the GCS synchronization instruction in program order, the hazard's later non-GCS load / store operation observes a result of the hazard's earlier GCS store operation, wherein an address range accessed by the hazard's later non-GCS load / store operation overlaps an address range accessed by the hazard's earlier GCS store operation; wherein:

[0028] Permitting a given earlier GCS store operation to produce a result that fails to observe a result of the given earlier GCS store operation in the absence of any intervening GCS synchronization instructions occurring between the given earlier GCS store operation and a given later non-GCS load / store operation in program order, wherein an address range accessed by the given earlier GCS store operation overlaps with an address range accessed by the given later non-GCS load / store operation.

[0029] Further aspects, features and advantages of the present technology will be apparent from the following description of examples read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 An example of a data processing apparatus is illustrated;

[0031] Figure 2 An example of a function call is illustrated;

[0032] Figure 3 Examples of protected control stack (GCS) push and pop operations are illustrated;

[0033] Figure 4 An example of a load / store processing circuit is illustrated;

[0034] Figure 5 Demonstrates methods for handling load / store operations;

[0035] Figure 6 Demonstrates access permission checking for GCS load / store operations;

[0036] Figure 7 Demonstrates access permission checking for non-GCS load / store operations;

[0037] Figure 8 The processing of GCS storage operations is illustrated;

[0038] Fig. 9 The processing of the GCS loading operation is illustrated;

[0039] Fig.10 illustrates processing of a GCS synchronization instruction, which is an example of a predetermined class of load / store synchronization instructions;

[0040] Fig.11 illustrates the processing of non-GCS load / store operations; and

[0041] Fig.12 The generation of a GCS storage buffer prefetch request is illustrated. DETAILED DESCRIPTION

[0042] An apparatus includes a load / store processing circuit for processing load / store operations, wherein for a predetermined class of load / store operations, the load / store processing circuit buffers storage data of the predetermined class of storage operations in a predetermined class of storage buffers, and controls store-to-load forwarding of the storage data from the predetermined class of storage buffers to the predetermined class of load operations. Store-to-load forwarding is a technique that allows some load requests to be processed without issuing access requests to a cache or memory. Store data associated with a pending store operation may be buffered in a store buffer (implemented in hardware) associated with the load / store processing circuit, and then, in the event that the load operation corresponds to an address of the buffered store data, at least a portion of the data for the load operation may be obtained from the store buffer instead of requesting the data from the cache. Forwarding the data of the store buffer may implement the ordering of stores and loads more efficiently than if the load had to wait for the data to be available in the cache, and may also help improve the performance of other load / store operations because the demand imposed on the cache to service cache requests for loads is reduced (which may benefit from store-to-load forwarding), thereby freeing up some cache bandwidth for servicing other requests.

[0043] The apparatus has an instruction decoder responsive to a predetermined class load / store synchronization instruction, the instruction decoder being used to control a load / store processing circuit so that: for a hazard's later non-scheduled class load / store operation that occurs after the predetermined class load / store synchronization instruction in program order and an hazard's earlier predetermined class store operation that occurs before the predetermined class load / store synchronization instruction in program order, the hazard's later non-scheduled class load / store operation observes a result of the hazard's earlier predetermined class store operation, wherein an address range accessed by the hazard's later non-scheduled class load / store operation overlaps with an address range accessed by the hazard's earlier predetermined class store operation. The load / store processing circuitry permits a given earlier predetermined class store operation to produce a result that fails to observe a result of the given earlier predetermined class store operation in the absence of any intervening predetermined class load / store synchronization instructions occurring in program order between the given later non-scheduled class load / store operation, wherein an address range accessed by the given earlier predetermined class store operation overlaps an address range accessed by the given later non-scheduled class load / store operation.

[0044] With this approach, no ordering requirements need to be enforced between an earlier predetermined class store operation and a later load / store operation that is not of the predetermined class, unless a predetermined class load / store synchronization instruction occurs in program order between an earlier predetermined class store operation and a later non-scheduled class load / store operation. This is unusual because normally one would expect that all later load / store operations should observe the results of any earlier store operation to the same address.

[0045] However, the inventors recognize that there may be a predetermined class of load / store operations where the addresses accessed by the class of load / store operations are relatively unlikely to be accessed by load / store operations that are not of the predetermined class. Therefore, by providing instructions that can be used by a programmer or compiler to identify rare scenarios when synchronization is required between a predetermined class of store operations and a load / store operation that is not of the predetermined class, this greatly simplifies the hardware circuit logic for handling the predetermined class of load / store operations, which in most scenarios does not require checking for address hazards between the predetermined class of load / store operations and the non-predetermined class of load / store operations, and therefore, for example, does not require having full control logic for conventional load / store operations to check for address hazards and implement sequencing.

[0046] The load / store processing circuit may not be able to use the predetermined class storage buffer to perform store-to-load forwarding of storage data from the predetermined class storage operation to the non-predetermined class load operation. Therefore, store-to-load forwarding using the predetermined class storage buffer may be supported between the predetermined class load / store operations, but not between the predetermined class load / store operation and the load / store operation that is not the predetermined class. This can simplify circuit logic and reduce circuit area and power consumption. This may take advantage of the fact that since it is expected that the load / store operation that is not the predetermined class accesses the same address as the load / store operation of the predetermined class, it may be unreasonable to incur circuit area and power costs of circuit logic in order to implement the forwarding of storage data from the predetermined class storage operation to the non-predetermined class load operation. If the predetermined class load / store synchronization instruction is executed, and therefore a given later non-predetermined class load / store operation does need to observe the result of the earlier predetermined class storage operation, this can be implemented without using store-to-load forwarding, for example by delaying the processing of the given later non-predetermined class load / store operation, as discussed further below.

[0047] The predetermined class storage buffer can be separated from the non-predetermined class storage buffer used by the load / store processing circuit to buffer the storage data of the non-predetermined class storage operation. This has several advantages. Considering the looser ordering implementation (e.g., weak memory model) for the instructions of the predetermined class as discussed above, providing a dedicated storage buffer for the storage operation of the predetermined class makes the control logic to be used for the operation of the predetermined class simpler than the control logic provided for the non-predetermined class storage operation. In addition, separating the storage operation of the predetermined class into a buffer separate from the buffer for the non-predetermined class storage operation means that the entries of the non-predetermined class storage buffer supporting the more complex form of hazard / forwarding logic are not used by the operations of the predetermined class that are unlikely to need the more complex logic. By utilizing more complex hazard / forwarding circuit logic to save those entries of the non-predetermined class storage operation that are more likely to benefit from the circuit logic, performance can be improved because when the predetermined class storage operation does not consume entries in the non-predetermined class storage buffer, the non-predetermined class storage operation is less likely to be blocked because there is not enough space in the non-predetermined class storage operation to handle the operation.

[0048] The load / store processing circuitry may use the unscheduled class store buffer to support store-to-load forwarding from an unscheduled class store operation to an unscheduled class load operation.

[0049] The load / store processing circuitry may process the predetermined class of load / store operations using a load / store pipeline separate from a load / store pipeline for non-predetermined class of load / store operations. Again, this may make the overall system more efficient in terms of performance and circuit area because the predetermined class of load / store operations need not be processed using a more complex pipeline circuit that supports functions not available for the predetermined class of load / store operations, thereby saving slots for the more complex pipeline circuit that does support those non-predetermined class of load / store operations.

[0050] The load / store processing circuitry may perform address translation lookups for predetermined classes of load / store operations in a level 1 address translation cache that is separate from the level 1 address translation cache that is looked up for non-predetermined class load / store operations. As described above, it is relatively likely that predetermined classes of load / store operations may access a different set of memory addresses than non-predetermined class load / store operations, and therefore if both predetermined class load / store operations and non-predetermined class load / store operations share the same level 1 address translation cache, these operations may contend for limited address translation cache capacity, and there may be a greater amount of cache thrashing that causes performance loss, due to one of these classes of load / store operations causing address translation data used by another of these classes of load / store operations to be evicted. By providing a separate level 1 address translation cache for predetermined classes of load / store operations, conflicts between addresses assigned to the address translation cache for the corresponding classes of load / store operations may be eliminated, thereby improving the performance of both classes of load / store operations.

[0051] The load / store processing circuitry may issue cache read / write requests triggered by a predetermined class of load / store operations to another level of cache, thereby bypassing the first level of cache for handling cache read / write requests triggered by a non-predetermined class of load / store operations. For example, the other level of cache may be a level 2 or level 3 cache of a cache hierarchy, which will be accessed after a miss in the first level (level 1) cache for a non-predetermined class of load / store operations. For some examples of predetermined class of load / store operations (e.g., the stack access example discussed below), it may be practical that most instances of predetermined class of load operations are serviceable based on store-to-load forwarding from a predetermined class of storage buffers, such that no access to the cache hierarchy is required to service those predetermined class of load operations. For non-predetermined class of load operations, it may be more common that the address of the non-predetermined class of load operations does not correspond to any address associated with the storage data currently buffered in the non-predetermined class of storage buffers, such that access to the level 1 cache is required. Since cache accesses for the predetermined class of load / store operations can be expected to be rare, the performance cost of directing those cache accesses to the level 2 cache (or another level of cache) rather than the level 1 cache for the predetermined class of load / store operations can be relatively limited, but this can have the following advantages: those cache accesses triggered by the predetermined class of load / store operations do not use up any level 1 cache bandwidth that can be more advantageously used for non-predetermined class load / store operations. Therefore, by issuing cache read and write requests triggered by the predetermined class of load / store operations to another level of cache, thereby bypassing the first level of cache, this can improve the performance of non-predetermined class load / store operations.

[0052] In response to the instruction decoder decoding the predetermined class load / store synchronization instruction, the load / store processing circuitry may trigger a writeback of storage data from the predetermined class storage buffer to the memory system, the storage data being associated with one or more earlier predetermined class storage operations that occurred in program order before the predetermined class load / store synchronization instruction. By triggering the writeback of buffered storage data from the predetermined class storage buffer in response to the predetermined class load / store synchronization instruction, this may speed up the storage data from becoming visible to non-scheduled class load / store operations, which is useful because the occurrence of the predetermined class load / store synchronization instruction is such a hint that a subsequent non-scheduled class load / store operation may require data at an address previously specified by a predetermined class storage operation.

[0053] In response to the instruction decoder decoding a predetermined class load / store synchronization instruction, the load / store processing circuitry may cause the processing of a hazard's later non-scheduled class load / store operation to be delayed to give time for the store data of the hazard's earlier predetermined class store operation to be drained from the predetermined class store buffer to a point where the store data can be observed by the hazard's later non-scheduled class load / store operation. This provides a technique for implementing a hazard's later non-scheduled class load / store operation to give a result of observing the result of the hazard's earlier predetermined class store operation, which simplifies circuit implementation compared to implementations that support store-to-load forwarding from the hazard's earlier predetermined class store operation to the hazard's later predetermined class load / store operation using a store buffer. Because scenarios where synchronization is required between an earlier predetermined class store operation and a later non-scheduled class load / store operation are expected to be very rare, incurring occasional delays in processing the later non-scheduled class load / store operation when synchronization is required may be acceptable and justify a simpler approach to handling hazards by delaying rather than forwarding.

[0054] The point at which the store data of the risky earlier predetermined class store operation is observable to the risky later non-predetermined class load / store operation may be, for example, another level of cache (e.g., level 2 cache or level 3 cache) as described above. Alternatively, the point at which the store data may be observable may be a cache write buffer associated with another level of cache that buffers pending write requests waiting to be serviced in the other level of cache, from which data may be returned to a subsequent load without actually having been written to the cache store itself. Such a cache write buffer is separate from the previously mentioned predetermined class store buffer.

[0055] In response to the instruction decoder decoding the predetermined class load / store synchronization instruction, the load / store processing circuitry may prevent store-to-load forwarding of store data from a predetermined class store buffer associated with an earlier predetermined class store operation that occurs in program order before the predetermined class load / store synchronization instruction to the predetermined class load operation. When the predetermined class load / store synchronization instruction is executed, this indicates that there may be some interaction between the predetermined class load / store operation and the non-predetermined class load / store operation, and therefore it is no longer guaranteed that if the later predetermined class load / store operation specifies the same address as the earlier predetermined class store operation (there are no intervening predetermined class load / store operations for addresses between the earlier predetermined class store and the later load / store of the predetermined class), the store data of the earlier predetermined class store operation can be unambiguously forwarded to the later predetermined class load / store operation because there may have been an intervening non-predetermined class store operation between the processing of the earlier predetermined class store operation and the later predetermined class load / store operation, and the intervening non-predetermined class store operation may modify the data associated with the specified address. Providing circuit logic for detecting whether such an intervening non-predetermined class store operation has occurred may be relatively complex (particularly where the corresponding classes of loads / stores are processed in different pipelines), and may not be justified given that the need for synchronization between predetermined class load / store operations and non-predetermined class loads / stores is expected to be very rare. In response to a predetermined class load / store synchronization instruction, it may be simpler (and therefore more efficient with respect to circuit area and power consumption) to disable store-to-load forwarding for entries associated with predetermined class store operations that precede the predetermined class load / store synchronization instruction in program order.

[0056] The predetermined class of load / store operations may include load / store operations triggered by decoding of the predetermined class of load / store instructions by the instruction decoder. Thus, the dedicated class of instructions may be identified by the instruction decoder (e.g., based on its instruction opcode or other portion of the instruction encoding, or based on other ISA features, such as mode bits stored in a configuration register or the presence of a preceding prefix instruction that modifies the behavior of the instruction), and the instruction decoder may then generate a signal indicating whether the corresponding load / store operation is to be processed as a predetermined class of load / store operation or a non-predetermined class of load / store operation.

[0057] The techniques discussed above may be applied to any class of load / store operations that are expected to be relatively unlikely to access addresses that overlap with addresses that would be accessed by other load / store operations that are not of the predetermined class. For example, the predetermined class of load / store operations may be a type of load / store operation that will perform a dedicated control function using a memory area that is not expected to be accessed by regular program code.

[0058] In one example, a predetermined class of load / store operations may include a stack access load / store operation for performing a stack pop / push operation, wherein the target address of the stack pop / push operation depends on the stack pointer. For example, a predetermined class of load / store operations may maintain some control data on a dedicated stack structure that is not expected to be used by other classes of load / store operations. By using a dedicated storage buffer for stack pop / push operations (rather than sharing a storage buffer with other classes of load / store operations), it is more likely that the address of the storage data stored in the buffer will still be located in the buffer when the corresponding stack pop operation is performed, making it relatively possible to service many predetermined classes of stack pop operations without requiring cache access.

[0059] A predetermined class storage buffer prefetch circuit can be provided to prefetch data to a predetermined class storage buffer for an address predicted based on a stack pointer. This can further help reduce the number of times that a stack pop operation requires data that is not yet in a predetermined class storage buffer. Considering the expected pattern in the stack pointer evolution (advancing incrementally through the address space before and after in response to the stack pop / push operation), the prediction of what data will be needed next for the stack pop operation can be relatively accurate, so for the stack pop operation, prefetching can greatly reduce the miss rate in the predetermined class storage buffer, and therefore reduce the number of urgently needed cache accesses required for such stack pop operations. Performance can be improved by bringing the data predicted to be required for the stack pop operation into the predetermined class storage buffer before the time when the stack pop operation is actually requested.

[0060] In one example, in response to a stack pop / push operation for a predetermined class load / store operation (which triggers the stack pointer to be updated to be within a predetermined distance of a cache line boundary), the predetermined class storage buffer prefetch circuitry may prefetch a subsequent cache line into the predetermined class storage buffer. When the stack pointer approaches a cache line boundary, it may be relatively likely that a subsequent cache line beyond the cache line boundary will be needed soon, and therefore if the subsequent cache line is not already within the predetermined class storage buffer, the subsequent cache line may be prefetched when a subsequent stack pop or push operation will target an address in the subsequent cache line (note that even if the subsequent operation is a stack push operation, prefetching the subsequent cache line may still be useful because the stack push operation may need to merge its data into other portions of the subsequent cache line).

[0061] In some examples, in response to detecting that a stack pointer points to an address that does not have a valid entry in a predetermined class storage buffer, the predetermined class storage buffer prefetch circuitry may prefetch a cache line selected based on the stack pointer into the predetermined class storage buffer. This may be useful, for example, if a stack pointer update occurs that is not triggered by a stack push or pop operation. In more arbitrary stack pointer updates (such as a change in a stack pointer on a conflicting switch between two different software processes that may use different stack structures in memory), it may be useful to prefetch the cache line associated with the updated stack pointer into the predetermined class storage buffer so that some of the delays associated with subsequent cache push / pop operations may be reduced compared to a situation where a request for the cache line is made only when a subsequent cache push / pop operation of the predetermined class is actually processed.

[0062] In some examples, the load / store processing circuitry may inhibit writeback of stored data from a given entry of a predetermined class of storage buffers when evicting stored data from the given entry after one or more stack pop operations cause the stack pointer to cross an address range associated with the given entry of the predetermined class of storage buffers. For a predetermined class of load / store operations (stack push / pop operations), once data pushed to the stack has been consumed by a subsequent stack pop operation, the data may no longer be needed, and thus once the stack pointer has left a given cache line after one or more stack pop operations, there may be little value in writing the data back to the cache, even if the data is dirty. By inhibiting writeback of stored data from entries associated with an address range that has been crossed by the stack pointer after an update caused by one or more stack pop operations, the number of memory writes to the cache and downstream memory systems is reduced, thereby improving performance by saving cache / memory bandwidth for other operations.

[0063] In one specific example, the predetermined class of load / store operations includes load / store operations for accessing a protected control stack (GCS) data structure, which is used to protect return status information for returning from a function call or an exception. Such GCS access load / store operations can be used as a defensive measure against return-oriented programming (ROP) attacks. A protected GCS data structure can be established, which has at least one defensive measure that limits the ability to write data in the GCS data structure, thereby providing some additional protection relative to normal memory areas. Since the GCS data structure can be managed as a stack (last in first out, LIFO) structure, the evolution of the stack pointer address can be predictable as discussed above, and since the push and pop of the data structure can be used for the dedicated purpose of maintaining a set of protected return status information, the set of protected return status information is protected from tampering by an attacker, it is generally desirable to avoid other non-GCS access load / store operations that interact with addresses mapped to the GCS data structure, so there is relatively little need to implement ordering requirements and hazard checks between GCS load / store accesses and non-GCS load / store accesses. Thus, the techniques discussed above may be particularly useful for applications when the predetermined class of load / store operations includes GCS load / store operations and the non-predetermined class of load / store operations includes other operations not intended to access GCS data structures.

[0064] In response to determining that the memory region corresponding to the target address is designated by the memory attribute data as a GCS region for storing a GCS data structure, the load / store processing circuitry may reject non-predetermined class storage operations that specify the target address. By limiting the ability to write to the GCS region to storage operations of a predetermined class of GCS access types, other more general storage instructions cannot tamper with the contents of the GCS data structure, thereby providing greater security assurance for the protected return status information stored in the GCS data structure. This reduces the attack surface available for an attacker to exploit when attempting to mount a ROP attack.

[0065] Similarly, in response to determining that the memory region corresponding to the target address is designated by the memory attribute data as a region other than a GCS region for storing GCS data structures, the load / store circuitry may reject a predetermined class of load / store operations that designate the target address. Thus, access to a memory region that is not designated for GCS data structures may be rejected if the access is triggered by an instruction of the GCS access type. This avoids instructions of the GCS access type from being misused to access memory regions that are not intended for storing GCS data structures, and gives confidence that GCS reads will be directed to memory regions that cannot have been modified by non-GCS access instructions, to defend against ROP attacks.

[0066] The predetermined class load / store synchronization instruction may not impose additional ordering constraints between an earlier non-predetermined class load / store instruction that occurs before the predetermined class load / store synchronization instruction in program order and a later non-predetermined class load / store instruction that occurs after the predetermined class load / store synchronization instruction in program order. Thus, unlike a more general type of memory barrier, the predetermined class load / store synchronization instruction may be an instruction that is specific to implementing synchronization between a regular load / store operation that is not of the predetermined class and an earlier load / store operation of the predetermined class.

[0067] A specific example of the predetermined category load / store synchronization instruction described previously is a GCS synchronization instruction, which is handled in the same manner as the predetermined category load / store synchronization instruction described above, but wherein the predetermined category load / store operation is a GCS load / store operation for accessing a GCS data structure, which is used to protect return status information for returning from a function call or an exception, and the non-predetermined category load / store operation includes a load / store operation other than the GCS load / store operation.

[0068] Therefore, in one example, a load / store processing circuit is provided to process load / store operations including a protected control stack (GCS) load / store operation for accessing a GCS data structure for protecting return status information for returning from a function call or an exception. The instruction decoder is responsive to a GCS synchronization instruction to control the load / store processing circuit so that: for a hazard's later non-GCS load / store operation that occurs after the GCS synchronization instruction in program order and a hazard's earlier GCS store operation that occurs before the GCS synchronization instruction in program order, the hazard's later non-GCS load / store operation observes a result of the hazard's earlier GCS store operation, wherein an address range accessed by the hazard's later non-GCS load / store operation overlaps an address range accessed by the hazard's earlier GCS store operation. The load / store processing circuitry is configured to permit a given earlier GCS store operation to produce a result that fails to observe a result of the given earlier GCS store operation in the absence of any intervening GCS synchronization instructions occurring in program order between the given later non-GCS load / store operation and the given later non-GCS load / store operation, wherein an address range accessed by the given later non-GCS load / store operation overlaps with an address range accessed by the given later non-GCS load / store operation.

[0069] By supporting instructions in the instruction set architecture supported by the instruction decoders that can be used to signal the (relatively rare) case when synchronization is required between GCS accesses and non-GCS accesses, this gives the microarchitecture hardware designer greater flexibility in design choices than would be the case if GCS accesses were by definition assumed to be ordered with respect to other memory accesses in the same manner as any other kind of memory access. For example, by placing the burden on the software developer to explicitly mark (using a GCS synchronization instruction) when a non-GCS access needs to observe the effects of a prior GCS access, this means that the hardware designer can (although is not required to) utilize a more basic form of hazard between GCS accesses and non-GCS accesses to provide a simpler processing path for GCS accesses that is separate from the path for non-GCS accesses, which processing path does not need to be invoked unless a GCS synchronization instruction is executed.

[0070] Figure 1 An example of a data processing apparatus 2 is schematically illustrated. The data processing apparatus has a processing pipeline 4 including a plurality of pipeline stages. In this example, the pipeline stages include: a fetch stage 6 for fetching instructions from an instruction cache 8; a decode stage 10 for decoding the fetched program instructions to generate micro-operations (decoded instructions) to be processed by the remaining stages of the pipeline; an issue stage 12 for checking whether the operands required for the micro-operation are available in a register file 14, and issuing the micro-operation for execution once the operands required for a given micro-operation are available; an execution stage 16 for executing the data processing operation corresponding to the micro-operation by processing the operands read from the register file 14 to generate a result value; and a write-back stage 18 for writing the result of the processing back to the register file 14. It should be understood that this is only one example of a possible pipeline architecture, and other systems may have additional stages or different stage configurations. For example, in an out-of-order processor, a register renaming stage may be included that is used to map architectural registers specified by program instructions or micro-operations to physical register descriptors that identify physical registers in register file 14. In some examples, there may be a one-to-one relationship between program instructions decoded by decode stage 10 and corresponding micro-operations processed by the execute stage. It is also possible that there is a one-to-many or many-to-one relationship between program instructions and micro-operations, such that, for example, a single program instruction may be split into two or more micro-operations, or two or more program instructions may be fused to be processed as a single micro-operation.

[0071] The execution stage 16 (an example of a processing circuit) includes a plurality of processing units for performing different categories of processing operations. For example, the execution units may include: a scalar arithmetic / logic unit (ALU) 20 for performing arithmetic or logic operations on scalar operands read from the register 14; a floating point unit 22 for performing operations on floating point values; a branch unit 24 for evaluating the results of branch operations and adjusting the program counter representing the current execution point accordingly; and a load / store unit 26 for performing load / store operations to access data in the memory system 8, 30, 32, 34. A memory management unit (MMU) 28 is provided as an example of a memory management circuit for performing address translation between a virtual address specified by the load / store unit 26 based on an operand of a data access instruction and a physical address identifying a storage location of the data in the memory system. The MMU has a translation lookaside buffer (TLB) 29 for caching address translation data from page tables stored in the memory system, wherein page table entries of the page tables define address translation mappings and govern access permissions such as whether a given process executing on the pipeline is allowed to read or write data or execute instructions for a given memory region. The MMU 28 may have circuitry for requesting memory access during a page table walk when traversing the page table structure to locate a page table entry corresponding to a desired address.

[0072] In this example, the memory system includes a level one data cache 30, a level one instruction cache 8, a shared level two cache 32, and a main system memory 34. It should be understood that this is only one example of a possible memory hierarchy, and other cache arrangements may also be provided. The specific type of processing units 20 to 26 shown in the execution stage 16 is only one example, and other specific implementations may have a different set of processing units or may include multiple instances of the same type of processing unit so that multiple micro-operations of the same type can be handled in parallel. It should be understood that Figure 1 This is only a simplified representation of some components of a possible processor pipeline implementation, and the processor may include many other elements that are not shown for the sake of brevity. Figure 1 A single processor core is shown having access to the memory 34 , but the device 2 may also have one or more further processor cores that share access to the memory 34 , with each core having a respective cache 8 , 30 , 32 .

[0073] Figure 2An example of calling a function (labeled fn1 for ease of reference) and returning from the function is illustrated. A function (also called a procedure) is a sequence of instructions that can be called from another part of a program and when completed returns processing to the part of the program flow from which the function was called. The same function can be called from multiple different locations in a program, and therefore the function return address is stored when the function is called so that the function return can distinguish which address the program flow should be returned to.

[0074] For example, Figure 2 As shown, the branch with link instruction BLR can be executed at the point where the function is to be called (represented by the address #add1) to cause the program flow to branch to the instruction at the branch target address #add2 specified using the operand of the branch with link instruction. The branch with link instruction also causes the processing circuit to set the link register (a designated register for tracking the function return address) to the address of the next instruction after the branch with link instruction (in this example, the function return address is #add1+4). After the branch has been made, multiple instructions (e.g., LD, MUL, ADD, etc.) are executed within the function code, and a return branch instruction RET is executed when the function is completed, which causes the instruction indicated by the return address stored in the link register to be branched.

[0075] If no other functions are called from within fn1, and no exception occurs before the return branch at the end of fn1 is reached, the address in the link register should still be the same as it was set when fn1 was called.

[0076] However, the first function fn1, which is usually called by the background code, may itself call another function (e.g., fn2) in a nested manner, and in this case, the function call to fn2 will overwrite the return address stored in the link register, and therefore before calling the other function, the function code of the first function fn1 should include instructions for saving the return address from the link register to a data structure in memory (e.g., a stack structure operating in a last-in-first-out (LIFO) manner), and after returning from fn2, the function code of fn1 should restore the return address to the link register before executing the return branch. The responsibility for saving and restoring function return states (such as return addresses) usually lies with software (there may be no architecturally implemented hardware mechanism for saving return addresses).

[0077] However, when a function return address is stored in memory, it may be vulnerable to an attacker modifying that data, for example using another thread executing on another processor core, or by interrupting the called function and concurrently executing other code that overwrites the return address stored in memory. Alternatively, an attacker may execute some instructions that are intended to modify the address operand of the instruction that restores the return address from memory to a register, so that the data loaded from memory is not the same as the return address that was originally saved to memory before calling the nested function. If an attacker can cause the return branch to branch to a point in the program flow other than the instruction following the function call branch, the attacker may be able to cause the software to behave incorrectly, and may be able to circumvent certain security protections or cause unexpected operations to be performed.

[0078] Function call is an example of an operation that generates return status information, which provides information about the state to which the processing circuit will be restored later. Another scenario that can capture return status information can be when an exception occurs, when the exception handling circuit or software exception handler provided in the hardware can capture exception return status information, such as indicating the exception return address of the address of the instruction to be executed after returning from the handling exception, and / or indicating the mode or execution state that the processor will execute after returning from the exception. The processor state information saved can indicate which exception level the exception is from, and other information about the operating state of the processor when the acquisition occurs. As with function calls, exceptions can be nested, and therefore the exception return state captured for an exception can be saved to a memory (automatically saved in hardware, or saved by a software exception handler) when another exception occurs, and therefore it may be easily tampered by an attacker when it is stored in a memory. These types of attacks can be referred to as return-oriented programming (ROP) attacks. It is desirable to provide an architectural countermeasure for such attacks.

[0079] Figure 3 A method for protecting against ROP attacks using a protected data structure 40 in memory called a "protected control stack" (GCS) is illustrated. The location of the GCS data structure within the memory address space can be selected by software, but the hardware provides architectural features designed to protect the GCS data structure from tampering by malicious attackers.

[0080] Registers 14 may include control registers including one or more protected control stack pointer (GCS pointer) registers for storing a stack pointer indicating an address on a GCS data structure. In some examples, the GCS pointer registers may be a set of grouped registers provided separately for at least two execution states (e.g., exception levels) so that software operating in different execution states can reference different GCS structures in memory without reprogramming the shared stack pointer register after each transition of the execution state. Other examples may use a single GCS pointer register, and the software may update the stack pointer stored in the GCS pointer register when transitioning between execution states.

[0081] like Figure 3 As shown, the GCS data structure 40 is stored in a memory region designated as a GCS memory region by a memory attribute specified directly or indirectly by an associated page table entry of a page table used by a memory management unit (MMU) 28 to control address translation and access permission checking. The GCS region attribute may be specified directly within the encoding of a corresponding page table entry for a memory region that includes at least a portion of the GCS data structure, or may be referenced indirectly within a register referenced by the page table entry.

[0082] When a memory region is identified as a GCS region, then write access to the region is limited to write requests triggered by the processing circuit 16 when a certain subset of GCS access instructions is executed. General storage instructions used by software for general storage operations that do not intend to access GCS structures are not considered to be one of the restricted subset of GCS access instructions. The MMU 28 may still allow the use of general load instructions to read GCS structures, which general load instructions cause read requests that are not GCS memory access requests to be issued. When a memory access request is requesting access to a GCS region, the request is a write request, and the request is not a GCS memory access request triggered by one of the restricted subset of GCS access instructions, then the memory access request is denied and a fault is signaled. The subset of GCS access instructions may include at least a GCS push instruction, which causes return status information (such as a function return address from a link register, or an exception return address or a saved processor state captured when an exception occurs) to be pushed to a location on the GCS structure determined using the stack pointer indicated in the GCS pointer register 58. The GCS push instruction also causes the stack pointer to advance an amount that depends on the size of the stack frame pushed to the GCS (e.g., by incrementing the stack pointer by the size of the stack frame if the GCS is managed as an ascending stack, or by decrementing the stack pointer by the size of the stack frame if the GCS is managed as a descending stack). The GCS access instruction may also include at least one form of GCS pop instruction that pops protected return information from the GCS structure. In addition to returning the return information popped from the stack, the GCS pop instruction also causes the stack pointer to be adjusted in a direction opposite to the direction in which the stack pointer was adjusted for the GCS push instruction (e.g., by decrementing the stack pointer by the size of the stack frame if the GCS is managed as an ascending stack, or by incrementing the stack pointer by the size of the stack frame if the GCS is managed as a descending stack).

[0083] GCS access instructions may not be allowed to access memory areas that are not specified as GCS area types by page table attributes. Therefore, if an attempt is made to perform a GCS access when the memory area targeted by the access is not marked as a GCS area type, a fault may be signaled. By prohibiting the use of GCS access instructions for accessing non-GCS areas, the programmer is prevented from using GCS access instructions to reduce the attack surface available to attackers unless the GCS access instructions are indeed intended to be GCS accesses. In addition, this provides confidence that the data accessed by the GCS pop-up instruction cannot be modified by a non-GCS instruction.

[0084] The GCS structure is separate from any data structure used by software to maintain saved return status information in memory to handle nesting of function calls or exceptions. Thus, the GCS structure is not intended to eliminate the need for the software itself to track the saving and restoration of return status information when function calls or exceptions are nested (software-triggered saving of return status can continue in the same manner as on processors that do not support the architectural measures for GCS protection discussed above). Instead, the GCS structure provides an area of ​​protected memory that is protected from tampering with compromised code, which can be used to provide information for verifying return status information intended to be used by software to return from the handling of function calls or exceptions.

[0085] In some implementations, the GCS pop instruction that causes the protected return state information to be popped from the GCS structure may also cause the processing circuit 16 to compare the popped return state with current return state information stored in a register (e.g., a link register for a function return, or an exception return address register and / or a saved processor state register for an exception return), and signal a fault if there is a mismatch between the return state information popped from the GCS structure 40 and the expected return state information intended by the software for a function / exception return. Thus, software may be protected from tampering by including instances of the GCS push instruction and the GCS pop instruction within program code to be executed around a function call / return or exception entry / return.

[0086] Other implementations may define separate instructions for verifying that the expected return status information is valid, separate from the instructions for popping the return status information from GCS structure 40 .

[0087] Alternatively, a GCS pop instruction may pop the protected return state from the GCS directly into one or more registers that specify the return state for an exception return or function return (or may be combined with an exception / function return instruction to pop the protected return state and use that state to control the exception / function return), in which case it is not necessary to perform the step of verifying that the expected return state information provided by the software is valid, because in such implementations, the GCS protected return state is used directly to control the exception / function return. For example, for GCS protection of a function return address, the function return address may be popped directly into the link register, thereby replacing any software-managed function return address that the software may have placed there based on its own management stack structure.

[0088] In addition, other types of GCS access instructions may also be supported. Some instructions having other functions in a mode that disables the use of the GCS may cause the processing circuit 16 to perform additional functions (such as additional GCS mode specific security checks) when executed when the GCS mode is enabled (the control state in the control register may control whether the GCS mode is enabled).

[0089] In general, by providing architectural support for defining GCS memory region types for use by the GCS structure 40, and restricting write access to the GCS region types to a limited subset of GCS access instructions (which may not be allowed to access memory regions other than the GCS region types), this reduces the attack surface available to attackers attempting to tamper with protected return status information stored on the GCS structure 40.

[0090] GCS access instructions (such as the GCS push instructions and GCS pop instructions described above) are examples of instructions that trigger a predetermined class of load / store operations, where it may be beneficial to handle the class of load / store operations separately from other types of load / store operations. GCS push / pop instructions may introduce additional memory read / write operations as part of each function call / return that would not be needed if support for GCS was not present. For some types of processor cores, if handled as normal load / store operations, the overhead of these additional memory reads and writes may become too high in terms of both performance and power consumption. The probability that a GCS load / store operation accesses the same address as a conventional load / store operation is relatively low, and therefore the more complex hazard and ordering control logic that is typically used to maintain the ordering between conventional load / store operations and the circuitry for supporting store-to-load forwarding to / from conventional load / store operations may not be necessary for handling GCS load / store operations. The vast majority of GCS load operations may only access addresses that have previously been stored by a GCS store operation but are not accessed by other classes of load / stores.

[0091] A small, weakly-ordered, dedicated pipeline coupled with a GCS store (sync) buffer is proposed that can significantly reduce the overhead of implementing GCS accesses by handling most GCS memory reads / writes without accessing the conventional data-side cache and without utilizing (and contending for bandwidth on) the normal load / store pipelines and memory paths.

[0092] Sometimes, a programmer or compiler may wish that a conventional load / store operation accesses an address previously written by a GCS store (push) operation. For example, a function return state sequence pushed into the GCS by a series of GCS store (push) operations can provide call path information, which can be useful for understanding the path of the program flow taken by the program, and therefore the software may wish to copy the function return information from the GCS data structure to another area of ​​the memory to allow the analysis of program flow behavior. In this case, the interaction between a conventional load / store operation and a GCS load / store operation may be required. However, for most instances of performing a GCS load / store operation, this type of interaction with a conventional load / store operation is not required, and therefore providing the same circuit logic for controlling risk, ordering implementation and storage to load forwarding may be unreasonable for a GCS load / store operation.

[0093] Therefore, in the techniques discussed below, a dedicated GCS store buffer is provided that is separate from the store buffer used for conventional store operations (as a microarchitectural buffer implemented in hardware circuitry rather than as a data structure maintained in memory). In the absence of a GCS synchronization instruction occurring between an earlier GCS store operation and a later non-GCS load / store operation in program order, the later non-GCS load / store operation need not provide a result that observes the result of the earlier GCS store operation. Thus, the later non-GCS load / store operation can be irrelevant relative to the earlier GCS store operation, so that even if they specify the same address, the later non-GCS load / store operation can obtain the data value associated with the address before the execution of the earlier GCS store operation. This simplifies control logic by avoiding the need for hazard or forwarding data between GCS store operations and non-GCS load / store operations. When a GCS synchronization instruction is executed, it is signaled that a later non-GCS load / store operation is required to observe the results of any earlier GCS store operations to overlapping addresses that precede the GCS synchronization instruction in program order, and then make the address associated with the data in the GCS store buffer available for address hazard with the later non-GCS load / store operation, but because this scenario is expected to be rare, it is acceptable to use a lower cost circuit implementation for the hazard, which may be less performance efficient but may be cheaper to implement (e.g., by delaying the later non-GCS load / store operation until the store data associated with the earlier GCS store operation has arrived in the cache to deal with any hazard, rather than implementing store-to-load forwarding from the GCS store operation to the non-GCS load / store operation). Therefore, as part of the instruction set architecture supported by the instruction decoder 10 and the processing circuitry 16, by supporting the GCS synchronization instruction, it is helpful to support more power efficient implementation options while still allowing software to cause a given non-GCS load / store operation to see the results of an earlier GCS store operation when needed.

[0094] Figure 4An example of a portion of the load / store unit 26 (an example of a load / store processing circuit) is illustrated. The load / store unit 26 has a general load / store pipeline 50 for processing load / store operations other than GCS load / store operations. The general load / store pipeline 50 has multiple pipeline stages that are used to control different aspects of the processing of load or store operations, such as address generation, address translation and page table attribute lookup, ordering / hazard checking, and cache read / write request processing. Any known load / store pipeline design can be used for the general load / store pipeline. The general load / store pipeline looks up the virtual address of the load / store operation in a general level 1 (L1) TLB (translation lookaside buffer) 52, which is a cache of address translation information derived from page tables stored in memory. If the virtual address being looked up hits in the general L1 TLB 52, the corresponding address translation information (including address mapping and / or memory access control attributes, such as attributes indicating whether the address corresponds to a GCS region, as discussed above) is returned to the pipeline for use in controlling the processing of the corresponding load / store operation. If the virtual address being looked up does not hit in the general level 1 TLB 52, a further lookup of the address is performed in the level 2 (L2) TLB 54. If the required information is found in the L2 TLB 54, it is returned to the pipeline 50 and may also be allocated to the general L1 TLB 52, while if the address does not hit in the L2 TLB 54, another lookup may optionally be performed in another TLB structure, and if the address does not hit in all TLB hierarchies provided, a page table walk is performed to trigger a series of memory accesses for traversing one or more levels of the page table to obtain the required address translation information.

[0095] After the relevant address translation information has been obtained, any memory attributes are checked, and a fault is signaled if the memory attributes indicate that the load / store operation cannot be processed (e.g., if the memory region being accessed is a region type that is not allowed to be accessed by the current request). A fault may also be triggered if the address translation information is not defined in the page table for the memory region being accessed. If the memory attributes indicate that the current load / store operation is allowed, the operation continues based on the physical address, which is translated from the virtual address based on the address translation mapping returned in the TLB lookup or returned by the page table walk.

[0096] For load operations, the address associated with the load is assigned to a load order buffer 56, which is used to implement ordering between load / store operations. For example, the load order buffer 56 can be used to detect read after read (RAR) hazards or read after write (RAW) hazards. For store operations, an entry is allocated in a (non-GCS) store buffer 58 for the address of the store operation, and once the data is available, the store data (read from the register 14, or once calculated, forwarded from an earlier instruction) is written to the store buffer entry. The hazard check circuit 60 compares the address of the load processed by the load / store pipeline 50 with the address of the store data buffered in the store buffer 58, so that when a later load accesses an address range that overlaps at least a portion of the address range accessed by an earlier store having an entry located in the store buffer 58, the relevant store data can be forwarded from the store buffer 58 to the load operation, so that the load operation can be serviced without issuing a request to read the data from the cache 30, 32. Any known store-to-load forwarding technique can be used to control the forwarding of store data from non-GCS stores to non-GCS loads.

[0097] Once the store data for a given store is available and there is sufficient bandwidth available to issue a write request to the L1 cache 30, the store data for the pending store operation is transferred from the store buffer 58 to the cache 30. For load operations that cannot be serviced based on store-to-load forwarding alone, a read request is issued by the general load / store pipeline 50 to request that the data associated with the address of the load be read from the L1 cache 30. If there is a miss in the L1 cache 30, the read / write request issued by the load / store pipeline 50 to the L1 cache 30 may be serviced as needed based on access to the L2 cache 32, another level of cache (if provided), or main memory 34.

[0098] The load / store unit 26 also includes a GCS load / store pipeline 70 that is separate from the pipeline 50 that handles non-GCS load / store operations. This makes the circuitry for handling GCS load / store operations simpler and avoids the circuit area and power consumption incurred by providing more complex hazard checking functions that are rarely needed in GCS load / store operations. It also avoids GCS load / store operations from consuming slots in the general load / store pipeline 50, load order buffer 56, store buffer 58, and L1 cache access path that would otherwise be used for non-GCS load / store operations, thereby improving performance.

[0099] The GCS load / store pipeline 70 performs its address lookups in a GCS L1 TLB 72 that is separate from the general L1 TLB 52 used by the general load / store pipeline 50. The GCS L1 TLB 72 may have a smaller cache capacity (capable of caching address translation information for fewer addresses) than the general L1 TLB 52. Providing a dedicated L1 TLB 72 for GCS accesses may be useful because GCS accesses may typically access a different subset of addresses for conventional load / store operations, and thus separating the address translation cache capacity for the two types of operations may help reduce conflicts in address translation cache allocations, thereby improving performance. If an address translation lookup for an address of a GCS load / store operation misses in the GCS L1 TLB 72, a lookup is performed in the shared L2 TLB 54, which may be the same structure as that which is looked up in the general L1 TLB 52 in response to a miss in a general non-GCS load / store operation. Similarly, page table walk control circuitry (for walking the page table structures to obtain address translation information not found in any level of the TLB) may be shared between normal load / store operations and GCS load / store operations. The various TLB structures 52, 54, 72 may be viewed as Figure 1 Portions of MMU 28 are shown.

[0100] The GCS load / store pipeline 70 also has access to a GCS store buffer 74, which is a microarchitectural buffer implemented in hardware and is separate from the non-GCS store buffer 58 used by the general load / store pipeline 50. The capacity of the GCS store buffer 74 can be less than the capacity of the store buffer 58, for example, accommodating as little as one or two cache lines of store data. The GCS load / store pipeline 70 supports store-to-load forwarding between GCS store operations and GCS load operations using the GCS store buffer 74, but does not support store-to-load forwarding between GCS store operations and non-GCS load operations. Similarly, store-to-load forwarding to GCS load operations cannot be performed for store data associated with non-GCS store operations. In addition, for most entries in the GCS store buffer 74, those addresses do not need to be hazard checked relative to the addresses processed by the general load / store pipeline 50.

[0101] When a GCS synchronization instruction is executed, the GCS store buffer 74 marks any pending valid entries (associated with GCS stores that precede the GCS synchronization instruction in program order) as requiring synchronization, and then makes the addresses associated with those entries available to the hazard check circuit 60 for comparison with the addresses of later non-GCS load / store operations tracked by the load order buffer 56 and the store buffer 58. If a hazard to overlapping addresses is detected between an entry of the GCS store buffer 74 that requires synchronization and a later non-GCS load / store operation, the non-GCS load / store operation is delayed until the store data associated with the entry that requires synchronization has been drained from the GCS store buffer 74 to a point where it can be observed by the later non-GCS load / store operation (in practice, this point may be the cache hierarchy, but it may also be an intervening buffer, such as a buffer local to the cache that queues write requests issued to the cache). To reduce the delay until the store data associated with the entry of the GCS store buffer 74 that needs to be synchronized becomes visible to later non-GCS stores, the GCS synchronization instruction may also trigger the GCS store buffer 74 to begin writing back the store data of the entry of the GCS store buffer that needs to be synchronized to the cache hierarchy 30, 32.

[0102] Although it will be possible that cache read / write requests initiated by the GCS load / store pipeline 70 will be directed to the L1 cache 30, this will cause such cache read / write requests to compete for cache access bandwidth with requests made by the general load / store pipeline 50. In practice, unless a very large number of nested function calls are made, the GCS stack pointer will likely change within only a few cache lines when a GCS push / pop operation is performed, so it is likely that most GCS load operations can be serviced based solely on store-to-load forwarding from the GCS store buffer 74, and no cache access is required. This may be particularly the case if GCS store buffer prefetch circuitry 80 is provided that manages the prefetching of data into the GCS store buffer 74 prior to explicit requests based on GCS load / store operations. For example, when a series of GCS push / pop operations brings the GCS stack pointer close to a cache line boundary, the GCS storage buffer prefetch circuitry 80 may issue a prefetch request to fetch in the next cache line after the boundary, such that it is possible that once a further GCS push / pop operation is performed, the further GCS push / pop operation can be serviced from an existing entry in the GCS storage buffer and no cache access is required. If there are more arbitrary GCS stack pointer update operations to update the GCS stack pointer in a manner other than an incremental update in response to a push / pop operation, the fact that the GCS stack pointer does not now correspond to any of the cache lines already allocated to the GCS storage buffer 74 may be detected by the prefetch circuitry 80 and used to trigger a prefetch request to prefetch the cache line associated with the new value of the GCS stack pointer after the update. Thus, the likelihood that a GCS load / store will require a cache access is relatively low.

[0103] Therefore, in order to reduce contention for level 1 cache accesses (since level 1 cache accesses are more likely to provide performance benefits for general load / store operations rather than GCS load / stores), then in those rare scenarios where a GCS load / store operation does trigger a demand cache access, the corresponding cache read / write request may be issued to the level 2 cache 32, thereby bypassing the level 1 cache 30. Similarly, prefetch requests issued by the GCS store buffer prefetch circuitry 80 may be issued to the level 2 cache 32, and bypass the level 1 cache 30. This may help improve the performance of general load / store operations, which may benefit from faster access to the level 1 cache 30 because there is less contention for the level 1 cache bandwidth.

[0104] If the allocation of a new entry in the GCS store buffer 74 requires the eviction of an existing entry, it is not always necessary to write the data associated with the evicted entry back to memory, even if the data is dirty. If the data in the evicted entry has been consumed by a GCS pop operation, the data will no longer be needed and therefore may simply be discarded and the corresponding write back to the L2 cache 32 may be eliminated.

[0105] Therefore, in summary, Figure 4 The specific implementation proposed in provides a small GCS pipeline 70 with a dedicated L1 TLB 72 and a physically addressed micro-architectural GCS storage buffer 74. Memory reads and writes generated as part of the GCS push / pop instructions insert new load / store operations into the GCS pipeline 70. The GCS pipeline 70 and the GCS storage buffer 74 are not connected to the L1 cache 30, the non-GCS storage buffer 58, or the like, but are connected to the L2 cache 32. In one example, the micro-architectural GCS storage buffer 74 is capable of accommodating one or two cache lines of data. When the GCS pointer points beyond the range currently available in the micro-architectural GCS buffer 74, the GCS storage buffer prefetch circuit 80 uses input / output coherent reads to prefetch data into the GCS storage buffer 74. When the GCS pointer approaches a cache line boundary, the prefetch circuit 80 also prefetches the next cache line, thereby significantly reducing the possibility of a GCS buffer miss and the associated performance loss.

[0106] When a GCS push instruction is executed, the associated memory write of the GCS push instruction is merged into the relevant (partial) cache line in the GCS buffer. Similarly, when the GCS is popped, the associated memory read is read only from the relevant entry of the GCS buffer. Therefore, the microarchitectural GCS buffer behaves like a merged storage buffer. However, if the return sequence causes the entire cache line of data present in the GCS buffer to be out of the field of view of the current GCS pointer (i.e., the GCS pointer has passed the address associated with the cache line), the cache line is not written back, thereby reducing the number of memory writes to downstream memory. If the GCS storage buffer 74 needs to evict an existing entry that is still within the GCS pointer, an I / O coherent write is used to write the cache line to the L2 cache 34.

[0107] Unlike the non-GCS storage buffer 58, the micro-architectural GCS storage buffer 74 is not directly readable or writable via conventional (non-GCS) load / store operations. Instead, in order to make it visible, it is first synchronized using a GCS synchronization instruction. The GCS synchronization instruction causes the GCS storage buffer 74 to mark the entries in the GCS storage buffer as "synchronized", and these "synchronized" entries can then no longer be read for GCS load operations triggered by the GCS pop instruction. The addresses of the "synchronized" entries become visible to normal loads and stores to perform hazards for the hazard check circuit 60. The GCS storage buffer 74 triggers writes to the L2 cache 32 for the "synchronized" entries, regardless of whether those entries need to be evicted, so the decoding of the GCS synchronization instruction by the instruction decoder 10 causes the GCS storage buffer 74 to automatically start draining the storage data from the synchronized entries into the L2 cache to become visible. Normal loads and stores perform hazards for the "synchronized" entries (normal loads / stores are delayed until the corresponding storage data has been drained from the micro-architectural GCS buffer and entered into the L2 cache). Once the entries have been drained, loads and stores may access the cache line via a normal L1 cache refill (which may trigger a line fill from the updated data in the L2 cache that has been drained from the GCS store buffer 74).

[0108] Therefore, this specific implementation provides the following advantages:

[0109] • There is no additional L1 data cache pressure or load / store bandwidth on the general load / store pipeline 50 caused by the introduction of GCS load / store operations.

[0110] ●The number of cache write-backs is reduced (by omitting write-backs for data outside the view of the architectural GCS pointer / buffer).

[0111] ● Reduced power by not using the more expensive conventional load / store paths, address generation, and L1 TLB.

[0112] therefore, Figure 4 An example of load / store processing circuitry 26 is shown that can provide more efficient processing for both predetermined class load / store operations and non-predetermined class load / store operations other than the predetermined class, which is useful when the likelihood of addresses accessed by the predetermined class load / store operations overlapping with addresses accessed by the non-predetermined class load / store operations is low. Figure 4 In the example of FIG. 5 , the predetermined category of load / store operations is a GCS load / store operation triggered by a GCS push or pop instruction, but similar techniques may be used for other categories of load / store operations.

[0113] In addition, although Figure 4 In the example of , the general load / store pipeline 50 is used to process all other load / store operations except the predetermined category of GCS load / store operations, but other examples may also have a dedicated pipeline for the third category of load / store operations, which is separate from the pipelines for GCS load / store operations and other general load / store operations. This may be useful if there is another category of load / store operations for which a dedicated control function is desired. Therefore, it is not necessary to use the general load / store pipeline 50 to process all other load / store operations that are not of the predetermined category.

[0114] Figure 5 1 is a flow chart illustrating a method of processing a predetermined class of load / store operations (such as the GCS load / store operations described above). At step 100, the load / store processing circuitry 26 buffers storage data associated with the predetermined class storage operation in the predetermined class storage buffer 74. At step 102, the load / store processing circuitry 26 controls store-to-load forwarding of the storage data from the predetermined class storage buffer 74 to the predetermined class load operation. That is, the predetermined class load operation is provided with at least a portion of the storage data of an entry written to the predetermined class storage buffer 74 for an earlier (in program order) predetermined class storage operation specifying a corresponding address, the corresponding address being associated with an address range that overlaps with the address range specified by the predetermined class load operation. Store-to-load forwarding from the predetermined class storage buffer 74 is not supported between the predetermined class storage operations processed by the GCS load / store pipeline 70 and the non-predetermined class load / store operations processed by the general load / store pipeline 50.

[0115] At step 104, the load / store processing circuitry 26 determines whether the instruction decoder has decoded a predetermined class load / store synchronization instruction (e.g., the GCS synchronization instruction described above) that occurs in program order between an earlier predetermined class store operation and a later non-scheduled class load / store operation that accesses an address range that overlaps with the address range accessed by the earlier predetermined class store operation. If such an intervening predetermined class load / store synchronization instruction has been present, then at step 106, the load / store processing circuitry 26 controls the processing of the later non-scheduled class load / store operation to ensure that the later non-scheduled class load / store operation observes the result of the earlier predetermined class store operation. This may be achieved, for example, by delaying the processing of the later non-scheduled class load / store operation until the store data of the earlier predetermined class store operation has arrived at a cache (e.g., the L2 cache 32). If there have not been any intervening scheduled class load / store synchronization instructions between the earlier scheduled class store operation and the later non-scheduled class load / store operation, then at step 108, the later non-scheduled class load / store operation is permitted to produce a result that fails to observe the result of the given earlier scheduled class store operation. For example, it is possible that, since no hazard is detected between the later non-scheduled class load / store operation and the earlier scheduled class store operation (even if they correspond to the same address), the later operation may return the value associated with the address before being updated by the earlier scheduled class store operation. This is architecturally correct in the absence of any intervening synchronization instructions. Effectively, the scheduled task load / store synchronization instructions act as a hint to the hardware that some hazard checks are required between the scheduled class load / store operation and other load / store operations. The responsibility is passed to the programmer or compiler to include synchronization instructions to ensure that the synchronization is performed in the case of expected interactions between the scheduled class load / store operation and other load / stores. In the absence of synchronization instructions, a more relaxed (weak memory ordering) approach may be taken to allow for cheaper circuit implementations with lower power costs when handling predetermined classes of load / store operations.

[0116] Figure 6is a flow chart illustrating an access permission check for a GCS load / store operation. At step 110, the GCS load / store pipeline 70 determines the target address of the GCS load / store operation based on the GCS stack pointer. At step 112, the GCS load / store pipeline 70 (or, in some cases, the memory management unit 28) looks up the address in the GCS L1 TLB 72 to obtain the memory attributes of the target address of the GCS load / store operation. At step 114, the GCS load / store pipeline 70 or the MMU 28 determines whether the target address corresponds to a GCS memory region, which is a special type of memory region for storing GCS data structures. If the target address does not correspond to the GCS memory region type, then at step 116, the GCS load / store operation is rejected. A fault is signaled, which can interrupt the processing being executed and cause the exception handler to deal with the cause of the fault. By suppressing GCS access to regions not marked as a GCS memory region type, this prevents GCS load / store instructions from being misused to access non-GCS memory, and also means that the protected return status returned by GCS load operations can be trusted as it cannot be tampered with by non-GCS instructions.

[0117] If it is determined at step 114 that the target address corresponds to a GCS memory region, then at step 118, the GCS load / store pipeline 70 or MMU 28 determines whether any other access permission checks have been passed. These checks may check other attributes, such as read / write permission information indicating whether read requests and write requests are respectively permitted for the memory region, or attributes defining a subset of the execution state of the processor 2 in which access to the region is allowed. If any other access permission check fails, then at step 116, the GCS load / store operation is again denied and a fault is signaled. The fault type information set by the processor when the fault occurs may differ depending on whether the cause of the fault is a GCS access to a non-GCS memory region or another type of access permission violation. If all other access permission checks are passed, then at step 120, the GCS load / store operation is permitted. GCS load / store operations are examples of the predetermined class of load / store operations described previously.

[0118] Figure 7 1 shows similar access permission checks performed for non-GCS load / store operations. Steps 130, 132, and 134 are similar to Figure 6 110, 112, 114 of , except that the target address of the non-GCS load / store operation is determined by the general load / store pipeline 50 instead of the GCS load / store pipeline 70, and at step 112, the memory attribute lookup is performed in the general L1 TLB 52 instead of the GCS L1 TLB 72. Figure 6 In comparison, Figure 7 At step 134, the check on whether the target address corresponds to the GCS memory region is responded to in the opposite manner for non-GCS load / store operations as compared to GCS load / store operations, in that when the target address corresponds to the GCS memory region, the non-GCS store operation is rejected, whereas in the case where the target address does not correspond to the GCS memory region, the GCS load / store operation is rejected.

[0119] Thus, if it is determined at step 134 that the target address corresponds to a GCS memory region, and it is determined at step 135 that the current load / store operation is a non-GCS store operation, then at step 136 the non-GCS load / store operation is denied and a failure is signaled. Subject to the results of any other access permission checks performed at step 138, non-GCS load operations may potentially be allowed even if they target a GCS memory region. If any other access permission checks fail, then the non-GCS load / store operation is again denied. Otherwise, if the target address does not correspond to a GCS memory region (no at step 134) or the non-GCS operation is a load operation (no at step 135), and any other access permission checks (not related to the GCS access check) are passed at step 138, then at step 140 the non-GCS load / store operation is permitted. Non-GCS load / store operations are examples of non-predetermined class load / store operations described previously.

[0120] Figure 8 The processing of a GCS store operation using the GCS load / store pipeline 70 is illustrated ( Figure 8 The access permission check for GCS storage operations is omitted, as in Figure 6 At step 150, a GCS store operation is received by the GCS load / store pipeline. This is a store operation triggered by a GCS push instruction decoded by the instruction decoder 10. At step 152, the GCS load / store pipeline 70 checks whether the address of the GCS store operation already has a corresponding entry allocated in the GCS store buffer 74. If so, the store data of the GCS store operation is merged into the existing entry corresponding to the address of the GCS store operation.

[0121] If there is no existing entry in the GCS storage buffer 74 for the address of the GCS storage operation, then at step 154, the GCS load / store pipeline 70 checks whether an invalid GCS storage buffer entry is available, and if available, at step 155, the storage data of the GCS storage operation is allocated to the invalid GCS storage buffer entry.

[0122] If no invalid GCS store buffer entry is available, then at step 156, a victim entry of the GCS store buffer is selected (some implementations of the GCS store buffer may have only one entry, in which case that entry is the victim entry, but if the GCS store buffer has more than one entry, any known victim selection strategy may be applied to select which entry is evicted). The GCS load / store pipeline 70 determines whether the victim entry is marked as not requiring writeback on eviction (see discussion below). Fig. 9 , which explains how a "write-back-not-needed" state may be set in response to a GCS load operation. If the victim entry is marked as not requiring write-back-on-eviction, then at step 158, write-back of data from the victim entry to the memory system is suppressed, even if the data is dirty. If the victim entry is not marked as not requiring write-back-on-eviction, then if there is any dirty data in the evicted entry, then at step 160 a request is issued to write the data from the victim entry back to the memory system (e.g., to the L2 cache 32). Regardless of whether write-back is suppressed or performed, at step 162, the store data of the GCS store operation is allocated to the victim entry.

[0123] Fig. 9 The processing of a GCS load operation is illustrated. At step 170, a GCS load operation is received by the GCS load / store pipeline. This is a load operation triggered by a GCS pop instruction decoded by the instruction decoder 10. Similarly, in Fig. 9 No access permission check for instructions is shown, but can be Figure 6 Any access permission check is performed as shown. At step 172, the GCS load / store pipeline 70 checks whether the address of the GCS load operation has a corresponding entry allocated in the GCS store buffer 74. If not, then at step 174, the GCS load / store pipeline issues a read request to request that the data required for the GCS load operation be read from the L2 cache 32. If the address of the GCS load operation hits in the GCS store buffer, then at step 176, the store data corresponding to the address is forwarded from the GCS store buffer 74 to the GCS load operation, and the GCS load / store pipeline can then forward the data for the write-back stage 18 of the processing pipeline 4 to write back to the destination register of the GCS load operation.

[0124] At step 178, the GCS load / store pipeline determines whether any stack pointer updates made for the stack pop operation corresponding to the GCS load operation have caused the GCS stack pointer to pass the given entry of the GCS store buffer 74 (after previously being at the address corresponding to the given entry). If so, this means that the data associated with the given entry has been consumed by the GCS pop operation and is therefore unlikely to be needed again. Therefore, the given entry is marked as not requiring writeback when evicted from the GCS store buffer 74. This will mean that if the entry is selected as described above for Figure 8 For the victim entry in question, writeback of that entry may be suppressed to save power and improve the execution of other load / store operations that may require cache access.

[0125] Fig.10 Processing of a GCS synchronization instruction is illustrated, which is an example of a predetermined class of load / store synchronization instructions described previously. At step 180, the instruction decoder 10 decodes the GCS synchronization instruction. In response, the instruction decoder 10 controls the load / store processing circuit 26 to mark any valid entry of the GCS storage buffer 74 as being in a state requiring synchronization. For example, each GCS storage buffer entry may have a corresponding flag indicating whether the entry is in a state requiring synchronization. Alternatively, if the GCS storage buffer 74 has only a single entry, there may be a flag indicating whether the GCS storage buffer as a whole is considered to require synchronization or not.

[0126] Additionally, in response to decoding the GCS sync instruction, the GCS load / store pipeline 70 performs a plurality of operations that may be performed in any order relative to each other and thus in any order. Fig.10 Although shown in parallel, the multiple operations may also be performed sequentially.

[0127] At step 184, the GCS load / store pipeline 70 prevents forwarding of store data from the synchronization-required entry to the GCS load operation. Once the GCS synchronization instruction has signaled that a non-GCS load / store operation may interact with the address specified by a given synchronization-required entry of the GCS store buffer, there is a risk that an intervening non-GCS store operation may change the value of the data associated with the address in the time period between an earlier GCS store and a later GCS load that accesses the address, such that forwarding of the data from the earlier GCS store to the later GCS load is no longer safe. Providing circuitry to check for the presence of an intervening non-GCS load / store operation to an overlapping address would require more complex circuit logic, so it may be more efficient to simply prevent forwarding of store data from the synchronization-required entry of the GCS store buffer to other GCS load operations.

[0128] Additionally, at step 186, the GCS load / store operations make the addresses of the entries of the GCS store buffer that require synchronization available for hazard checking by hazard checking circuitry 60 associated with the general load / store pipeline 50. This ensures that general load / store operations can be made hazardous for addresses associated with GCS stores that precede the GCS synchronization instruction in program order to ensure that they observe the results of such earlier GCS stores.

[0129] In addition, at step 188, the GCS load / store pipeline 70 triggers a writeback of the store data from the entry of the GCS store buffer 74 that requires synchronization to the memory system (e.g., to the L2 cache 32). This operation is performed even if the entry that requires synchronization does not yet need to be evicted from the GCS store buffer to make way for an entry to be assigned to a different address. By triggering the draining of the store data from the GCS store buffer 74 to the memory system in response to the GCS synchronization instruction, the store data becomes visible to later non-GCS load / store operations more quickly.

[0130] Fig.11 The processing of a non-GCS load / store operation using the general load / store pipeline 50 is illustrated. At step 190, a non-GCS load / store operation is received. This is a load / store operation triggered by the instruction decoder 10 decoding an instruction other than one of the instructions of the GCS access type. Figure 7 Access permission check shown.

[0131] At step 192, the hazard checking circuitry 60 associated with the general load / store pipeline 50 performs hazard checking for non-GCS load / store operations, including checking the addresses of the non-GCS load / store operations against any synchronization-required addresses (if any) provided from the GCS load / store pipeline. For example, the signal path used to transmit the addresses of GCS store buffer entries that require synchronization to the hazard checking circuitry 60 may qualify those addresses with indicators that indicate whether a synchronization-required state has been asserted for those addresses, such that those addresses are ignored for hazard checking purposes unless those addresses have been identified as requiring synchronization.

[0132] At step 194, the hazard check circuit 60 determines whether a given later non-GCS load / store operation is hazarding for an address of an earlier GCS store operation that has been identified as requiring synchronization (due to an intervening GCS synchronization instruction occurring in program order between the instruction that triggered the earlier GCS store operation and the given later non-GCS load / store operation). If so, then at step 196, processing of the given later non-GCS load / store operation is delayed. For example, the later non-GCS load / store operation may be removed from the general load / store pipeline for later reissue, or may be assigned to a replay queue that queues delayed load / store operations and may be retried at some later time: after an arbitrary retry time interval (the elapse of which is not necessarily triggered by any confirmation that the cause of the hazard has been resolved), or once a signal has been received indicating that the hazard has been resolved (e.g., when any entries of the GCS store buffer 74 requiring synchronization have been flushed to a point where the store data can be observed by the later non-GCS load / store operation). If there are no hazards for non-GCS load / store operations against earlier GCS store operations where synchronization is required, then at step 198, the hazard checking circuitry checks for any other hazards detected between the corresponding non-GCS load / store operations. This may be performed according to any known hazard checking technique, and may include enforcing architectural ordering constraints (such as ensuring that load / store operations to the same address are handled in program order, or enforcing any memory barriers), performing store-to-load forwarding from non-GCS store operations to non-GCS load operations, and merging store data of later stores into entries previously allocated by earlier stores in the store buffer 58. Unlike synchronization between GCS load / store operations and non-GCS load / store operations, for corresponding non-GCS load / store operations, no intervening synchronization instructions need to be executed to enforce the later non-GCS load / store to observe the results of the earlier non-GCS store.

[0133] Fig.12 The prefetching of data into the GCS storage buffer 74 by the GCS storage buffer prefetch circuit 80 is illustrated. At step 200, the GCS storage buffer prefetch circuit 80 detects whether the GCS stack pointer has exceeded the range of any entry allocated in the GCS storage buffer. For example, it is detected whether the GCS stack pointer is outside any address range associated with valid entries of the GCS storage buffer 74. If so, then at step 202, the GCS storage buffer prefetch circuit 80 generates a prefetch request to request that data associated with an address selected based on the GCS stack pointer value be prefetched into the GCS storage buffer 74.

[0134] At step 204, the GCS storage buffer prefetch circuitry also checks whether a GCS push or pop operation has caused the GCS stack pointer to be updated to be within a predetermined distance of a cache line boundary that marks the boundary of the address range corresponding to a given entry allocated in the GCS storage buffer. This may be an indication that a future GCS push or pop operation may access a subsequent cache line beyond that cache line boundary. Therefore, at step 260, the GCS storage buffer prefetch circuitry 80 generates a GCS storage buffer prefetch request to request that data associated with the address of the subsequent cache line be brought from the cache 32 to the GCS storage buffer 74.

[0135] For all flow charts shown in this application, it should be understood that although the steps are shown sequentially in a certain order, the steps can be re-ordered so that the steps are performed in a different order or at least partially in parallel.

[0136] The concepts described herein may be embodied in computer readable code for making devices embodying the described concepts. For example, the computer readable code may be used at one or more stages of the semiconductor design and fabrication process, including the electronic design automation (EDA) stage, to fabricate integrated circuits including devices embodying the concepts. The computer readable code may additionally or alternatively enable the definition, modeling, simulation, verification, and / or testing of devices embodying the concepts described herein.

[0137] For example, computer readable code for making an apparatus embodying the concepts described herein may be embodied in code defining a hardware description language (HDL) representation of the concepts. For example, the code may define a register transfer level (RTL) abstraction of one or more logic circuits for defining an apparatus embodying the concepts. The code may define an HDL representation of one or more logic circuits embodying the apparatus in Verilog, SystemVerilog, Chisel, or VHDL (Very High Speed ​​Integrated Circuit Hardware Description Language), as well as intermediate representations such as FIRRTL. The computer readable code may provide definitions of concepts embodying the concepts using system-level modeling languages ​​such as SystemC and SystemVerilog, or other behavioral representations of the concepts that may be interpreted by a computer to enable simulation, functional and / or formal verification, and testing of the concepts.

[0138] Additionally or alternatively, the computer readable code may define a low-level description of an integrated circuit component embodying the concepts described herein, such as one or more netlists or integrated circuit layout definitions, including representations such as GDSII. One or more netlists or other computer readable representations of integrated circuit components may be generated by applying one or more logic synthesis processes to the RTL representation to generate definitions for making devices embodying the present invention. Alternatively or additionally, one or more logic synthesis processes may generate from the computer readable code a bitstream to be loaded into a field programmable gate array (FPGA) to configure the FPGA to embody the described concepts. The FPGA may be deployed for the purpose of verifying and testing concepts before making integrated circuits, or the FPGA may be deployed directly in a product.

[0139] The computer readable code may include a mixture of code representations for making a device, such as a mixture including one or more of an RTL representation, a netlist representation, or another computer readable definition used in a semiconductor design and fabrication process to make a device embodying the invention. Alternatively or additionally, concepts may be defined in a combination of a computer readable definition used in a semiconductor design and fabrication process to make a device and computer readable code defining instructions to be executed by the defined device once fabricated.

[0140] Such computer readable code may be provided in any known transient computer readable medium (such as wired or wireless transmission of code over a network) or non-transitory computer readable medium such as a semiconductor, magnetic disk, or optical disk. An integrated circuit fabricated using the computer readable code may include components such as one or more of the following: a central processing unit, a graphics processing unit, a neural processing unit, a digital signal processor, or other components that embody the concept individually or collectively.

[0141] In this application, the words "configured to..." are used to mean that elements of a device have a configuration that enables the performance of a defined operation. In this context, "configuration" means the arrangement or manner of interconnection of hardware or software. For example, the device may have dedicated hardware that provides the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured to" does not mean that the device elements need to be changed in any way in order to provide the defined operation.

[0142] In the present application, a feature list beginning with the phrase "at least one of..." means that any one or more of those features may be provided individually or in combination. For example, "at least one of [A], [B], and [C]" covers any of the following options: only A (without B or C), only B (without A or C), only C (without A or B), a combination of A and B (without C), a combination of A and C (without B), a combination of B and C (without A), or a combination of A, B, and C.

[0143] Although exemplary embodiments of the present invention have been described in detail herein with reference to the accompanying drawings, it should be understood that the invention is not limited to those precise embodiments and that various changes and modifications may be effected therein by those skilled in the art without departing from the scope of the invention as defined in the appended claims.

Claims

1. A device, comprising: a load / store processing circuit, the load / store processing circuit being configured to process load / store operations, wherein for a predetermined category of load / store operations, the load / store processing circuit is configured to: buffer storage data of the predetermined category of storage operations in a predetermined category of storage buffers, and control store-to-load forwarding of storage data from the predetermined category of storage buffers to the predetermined category of load operations; and an instruction decoder responsive to a predetermined class load / store synchronization instruction for controlling the load / store processing circuitry so that: for a hazard's later non-scheduled class load / store operation that occurs in program order after the predetermined class load / store synchronization instruction and a hazard's earlier predetermined class store operation that occurs in program order before the predetermined class load / store synchronization instruction, the hazard's later non-scheduled class load / store operation observes a result of the hazard's earlier predetermined class store operation, wherein an address range accessed by the hazard's later non-scheduled class load / store operation overlaps an address range accessed by the hazard's earlier predetermined class store operation; wherein: In the absence of any intervening predetermined class load / store synchronization instructions occurring in program order between a given earlier predetermined class store operation and a given later non-predetermined class load / store operation, the load / store processing circuitry is configured to permit the given later non-predetermined class load / store operation to produce a result that fails to observe a result of the given earlier predetermined class store operation, wherein an address range accessed by the given earlier predetermined class store operation overlaps with an address range accessed by the given later non-predetermined class load / store operation.

2. The apparatus of claim 1 , wherein the load / store processing circuitry is incapable of using the predetermined class store buffer to perform store-to-load forwarding of store data from a predetermined class store operation to a non-predetermined class load operation.

3. An apparatus according to any preceding claim, wherein the predetermined class store buffer is separate from a non-predetermined class store buffer used by the load / store processing circuitry to buffer store data for non-predetermined class store operations.

4. An apparatus according to any preceding claim, wherein the load / store processing circuitry is configured to process the predetermined class of load / store operations using a load / store pipeline separate from a load / store pipeline for non-predetermined class of load / store operations.

5. An apparatus as claimed in any preceding claim, wherein the load / store processing circuitry is configured to perform address translation lookups for load / store operations of the predetermined class in a level 1 address translation cache separate from a level 1 address translation cache looked up for load / store operations of non-predetermined classes.

6. An apparatus according to any preceding claim, wherein: The load / store processing circuit is configured to issue cache read / write requests triggered by the predetermined category of load / store operations to another level of cache, thereby bypassing the first level of cache for handling cache read / write requests triggered by non-predetermined category of load / store operations.

7. An apparatus according to any preceding claim, wherein in response to the instruction decoder decoding the predetermined category load / store synchronization instruction, the load / store processing circuit is configured to trigger a writeback of storage data from the predetermined category storage buffer to a memory system, the storage data being associated with one or more earlier predetermined category storage operations that occurred in program order before the predetermined category load / store synchronization instruction.

8. An apparatus according to any preceding claim, wherein: In response to the instruction decoder decoding the predetermined class load / store synchronization instruction, the load / store processing circuitry is configured to cause processing of the hazard's later non-scheduled class load / store operation to be delayed to give time for: store data of the hazard's earlier predetermined class store operation to be drained from the predetermined class store buffer to a point where the store data can be observed by the hazard's later non-scheduled class load / store operation.

9. An apparatus according to any preceding claim, wherein in response to the instruction decoder decoding the predetermined class load / store synchronization instruction, the load / store processing circuit is configured to prevent store-to-load forwarding of store data from the predetermined class store buffer to a predetermined class load operation, the predetermined class store buffer being associated with an earlier predetermined class store operation that occurs in program order before the predetermined class load / store synchronization instruction.

10. Apparatus according to any preceding claim, wherein the predetermined class of load / store operations comprises load / store operations triggered by decoding of a predetermined class of load / store instructions by the instruction decoder.

11. An apparatus according to any preceding claim, wherein the predetermined class of load / store operations comprises stack access load / store operations for performing stack pop / push operations, wherein a target address of the stack pop / push operation depends on a stack pointer.

12. The apparatus of claim 11, comprising a predetermined category storage buffer prefetch circuit to prefetch data into the predetermined category storage buffer for an address predicted based on the stack pointer.

13. The device according to claim 12, wherein: In response to a stack pop / push operation triggering the stack pointer to be updated to be within a predetermined distance of a cache line boundary for a predetermined class load / store operation, the predetermined class storage buffer prefetch circuit is configured to prefetch a subsequent cache line into the predetermined class storage buffer.

14. The device according to any one of claims 12 and 13, wherein: In response to detecting that the stack pointer points to an address having no valid entry in the predetermined category storage buffer, the predetermined category storage buffer prefetch circuit is configured to prefetch a cache line selected based on the stack pointer into the predetermined category storage buffer.

15. The device according to any one of claims 11 to 14, wherein: The load / store processing circuitry is configured to inhibit writeback of the storage data from a given entry of the predetermined category storage buffer when the storage data is evicted from the given entry of the predetermined category storage buffer after one or more stack pop operations cause the stack pointer to cross an address range associated with the given entry of the predetermined category storage buffer.

16. An apparatus according to any preceding claim, wherein the predetermined category of load / store operations comprises load / store operations for accessing a protected control stack (GCS) data structure, the protected control stack (GCS) data structure being used to protect return status information for returning from a function call or an exception.

17. The apparatus of claim 16, wherein the load / store processing circuit is configured to, in response to determining that a memory region corresponding to a target address is designated by memory attribute data as a GCS region for storing the GCS data structure, reject a non-predetermined class storage operation that specifies the target address.

18. An apparatus according to any one of claims 16 and 17, wherein the load / store processing circuit is configured to: in response to determining that the memory area corresponding to the target address is specified by memory attribute data as an area other than the GCS area for storing the GCS data structure, reject a predetermined category load / store operation specifying the target address.

19. An apparatus according to any preceding claim, wherein the predetermined class load / store synchronization instruction does not impose additional ordering constraints between an earlier non-scheduled class load / store instruction that occurs before the predetermined class load / store synchronization instruction in program order and a later non-scheduled class load / store instruction that occurs after the predetermined class load / store synchronization instruction in program order.

20. A non-transitory computer readable medium storing a computer readable code for manufacturing an apparatus, the apparatus comprising: a load / store processing circuit, the load / store processing circuit being configured to process load / store operations, wherein for a predetermined category of load / store operations, the load / store processing circuit is configured to: buffer storage data of the predetermined category of storage operations in a predetermined category of storage buffers, and control store-to-load forwarding of storage data from the predetermined category of storage buffers to the predetermined category of load operations; and an instruction decoder responsive to a predetermined class load / store synchronization instruction for controlling the load / store processing circuitry so that: for a hazard's later non-scheduled class load / store operation that occurs in program order after the predetermined class load / store synchronization instruction and a hazard's earlier predetermined class store operation that occurs in program order before the predetermined class load / store synchronization instruction, the hazard's later non-scheduled class load / store operation observes a result of the hazard's earlier predetermined class store operation, wherein an address range accessed by the hazard's later non-scheduled class load / store operation overlaps an address range accessed by the hazard's earlier predetermined class store operation; wherein: In the absence of any intervening predetermined class load / store synchronization instructions occurring in program order between a given earlier predetermined class store operation and a given later non-scheduled class load / store operation, the load / store processing circuitry is configured to permit the given later non-scheduled class load / store operation to produce a result in which a result of the given earlier predetermined class store operation is not observed, wherein an address range accessed by the given earlier predetermined class store operation overlaps with an address range accessed by the given later non-scheduled class load / store operation.

21. A method comprising: For a predetermined class of load / store operations, buffering store data of the predetermined class of store operations in a predetermined class of store buffers, and controlling store-to-load forwarding of the store data from the predetermined class of store buffers to the predetermined class of load operations; In response to a predetermined class load / store synchronization instruction, controlling the load / store processing circuitry to control: for a hazard's later non-scheduled class load / store operation that occurs after the predetermined class load / store synchronization instruction in program order and an hazard's earlier predetermined class store operation that occurs before the predetermined class load / store synchronization instruction in program order, the hazard's later non-scheduled class load / store operation observes a result of the hazard's earlier predetermined class store operation, wherein an address range accessed by the hazard's later non-scheduled class load / store operation overlaps an address range accessed by the hazard's earlier predetermined class store operation; wherein: In the absence of any intervening scheduled class load / store synchronization instructions occurring in program order between a given earlier scheduled class store operation and a given later non-scheduled class load / store operation, permitting the given later non-scheduled class load / store operation to produce a result in which a result of the given earlier scheduled class store operation is not observed, wherein an address range accessed by the given earlier scheduled class store operation overlaps with an address range accessed by the given later non-scheduled class load / store operation.

22. A device, comprising: a load / store processing circuit for processing load / store operations including a protected control stack (GCS) load / store operation for accessing a GCS data structure for protecting return status information for returning from a function call or an exception; and an instruction decoder responsive to a GCS synchronization instruction for controlling the load / store processing circuitry such that: for a hazard later non-GCS load / store operation occurring in program order after the GCS synchronization instruction and a hazard earlier GCS store operation occurring in program order before the GCS synchronization instruction, the hazard later non-GCS load / store operation observes a result of the hazard earlier GCS store operation, wherein an address range accessed by the hazard later non-GCS load / store operation overlaps an address range accessed by the hazard earlier GCS store operation; wherein: The load / store processing circuitry is configured to permit a given earlier GCS store operation to produce a result that fails to observe a result of the given earlier GCS store operation in the absence of any intervening GCS synchronization instructions occurring in program order between the given earlier GCS store operation and a given later non-GCS load / store operation, wherein an address range accessed by the given earlier GCS store operation overlaps with an address range accessed by the given later non-GCS load / store operation.

23. A non-transitory computer readable medium storing a computer readable code for manufacturing an apparatus comprising: a load / store processing circuit for processing load / store operations including a protected control stack (GCS) load / store operation for accessing a GCS data structure for protecting return status information for returning from a function call or an exception; and an instruction decoder responsive to a GCS synchronization instruction for controlling the load / store processing circuitry such that: for a hazard later non-GCS load / store operation occurring in program order after the GCS synchronization instruction and a hazard earlier GCS store operation occurring in program order before the GCS synchronization instruction, the hazard later non-GCS load / store operation observes a result of the hazard earlier GCS store operation, wherein an address range accessed by the hazard later non-GCS load / store operation overlaps an address range accessed by the hazard earlier GCS store operation; wherein: The load / store processing circuitry is configured to permit a given earlier GCS store operation to produce a result that fails to observe a result of the given earlier GCS store operation in the absence of any intervening GCS synchronization instructions occurring in program order between the given earlier GCS store operation and a given later non-GCS load / store operation, wherein an address range accessed by the given earlier GCS store operation overlaps with an address range accessed by the given later non-GCS load / store operation.

24. A method comprising: processing load / store operations including guarded control stack (GCS) load / store operations for accessing a GCS data structure for protecting return status information for returning from a function call or an exception; and In response to a GCS synchronization instruction, controlling the load / store processing circuitry such that: for a hazard later non-GCS load / store operation that occurs in program order after the GCS synchronization instruction and a hazard earlier GCS store operation that occurs in program order before the GCS synchronization instruction, the hazard later non-GCS load / store operation observes a result of the hazard earlier GCS store operation, wherein an address range accessed by the hazard later non-GCS load / store operation overlaps with an address range accessed by the hazard earlier GCS store operation; wherein: Permitting a given earlier GCS store operation to produce a result that fails to observe a result of the given earlier GCS store operation in the absence of any intervening GCS synchronization instructions occurring between the given later non-GCS load / store operation in program order, wherein an address range accessed by the given earlier GCS store operation overlaps with an address range accessed by the given later non-GCS load / store operation.

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