Matrix product state based decoder for stabilizing subcodes under device noise for quantum computing and information processing

Abstract

An enhanced matrix product state based decoder is generated and employed to almost optimally detect and correct errors within quantum computing and information handling systems. The decoder takes as input a detector-level error model that describes physical error channels and error detection sets. This error model is improved using experimental data.

Description

[0001] Priority declaration

[0002] This application claims priority to U.S. Provisional Application No. 63 / 389,165 (Agent Docket No. GGLQ-136-P), filed on July 14, 2022, and entitled “MATRIXPRODUCT STATE-BASEDDECODERS FOR STABILIZER CODES UNDER DEVI CE NOI SE FOR QUANTUM COMPUTI NG AND|I NFORMATION PROCESSING,” the contents of which are incorporated herein in their entirety. This application also claims priority to U.S. Provisional Application No. 63 / 436,313 (Attorney Docket No. GGLQ-136-P2), filed December 30, 2022, and entitled “MATRIX PRODUCT STATE-BASED DECODERS FOR STABILIZER CODES UNDER DEVICE NOI SE FOR QUANTUM COMPUTI NG AND|I NFORMATION PROCESSING,” the contents of which are incorporated herein in their entirety. Technical Field

[0003] The present disclosure relates generally to quantum computing systems and, more particularly, to decoders for quantum error correction. Background Art

[0004] Quantum computing is a computing method that uses quantum effects (such as superposition of basis states and entanglement) to perform certain calculations more efficiently than classical digital computers. Compared to digital computers that store and manipulate information in the form of bits (e.g., "1" or "0"), quantum computing systems can use quantum bits ("qubits") to manipulate information. A quantum bit can refer to a quantum device that can superimpose multiple states (e.g., data in "0" and "1" states), and / or refers to the superposition of the data itself in multiple states. According to conventional terminology, the superposition of "0" and "1" states in a quantum system can be expressed as, for example, a|0>+b|1>. The "0" and "1" states of a digital computer are similar to the |0> and |1> basis states of a quantum bit, respectively. Summary of the invention

[0005] Aspects and advantages of embodiments of the present disclosure will be set forth in part in the following description, or may be learned from the description, or may be learned through practice of the embodiments.

[0006] An example aspect of the present disclosure relates to a method for operating a quantum computing system (QCS). More specifically, an embodiment may be used to detect and / or correct quantum errors occurring in a QCS. The method may include accessing an error model for the QCS. The error model may encode a set of error channels corresponding to a set of quantum error patterns. A set of detected quantum errors may be accessed. The set of detected quantum errors may be encoded in a set of experimental measurements performed on the QCS. A tensor network may be generated. The tensor network may encode correlations between quantum error patterns in a set of quantum error patterns and detected quantum errors in a set of detected quantum errors. A matrix product state (MPS) may be generated based on the tensor network. To generate the MPS, the tensor network may be contracted via tensor contraction. A fault-tolerant system having a decoder and an error correction code (e.g., a code) may be generated for the QCS. At least the decoder of the fault-tolerant system may be based on the MPS. That is, the MPS may affect the decoder of the fault-tolerant system. The error correction code may be deployed to the QCS. Once deployed, the error correction codes can be used to detect errors that occur during the runtime of the QCS. The error correction codes can be used to correct the detected errors.

[0007] Other aspects of the present disclosure relate to various systems, methods, apparatus, non-transitory computer-readable media, computer-readable instructions, and computing devices.

[0008] These and other features, aspects and advantages of various embodiments of the present disclosure will be better understood with reference to the following description and appended claims.The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate example embodiments of the present disclosure and, together with the description, explain the relevant principles. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] A detailed discussion of the embodiments for those skilled in the art is set forth in this specification with reference to the accompanying drawings, in which:

[0010] Figure 1 An example quantum computing system is depicted according to an example embodiment of the present disclosure.

[0011] Figure 2 An example error model according to an example embodiment of the present disclosure is depicted.

[0012] Figure 3 Depicted are examples of local correlations between detectors within an error model.

[0013] Figure 4 Depicted Figure 2 The multi-dimensional tensor network of can be efficiently collapsed into a one-dimensional matrix product state.

[0014] Figure 5 Depicted is the construction of a matrix product state that generates approximate joint probabilities according to various embodiments.

[0015] Figure 6 Experimental data indicating convergence of logic error probability as a function of bond distance are depicted.

[0016] Figure 7 Depicted is a flow chart of an example method for detecting and correcting quantum errors in a quantum computing system according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0017] Example aspects of the present disclosure relate to enhanced systems and methods for calibrating composite quantum gates (e.g., two-qubit quantum gates) in quantum computing systems. Quantum gates can be used as building blocks of quantum circuits implemented by quantum computing systems for quantum computing and quantum information processing. As used herein, the term "composite quantum gate" may refer to an object (e.g., a quantum circuit, device, and / or structure) that performs operations on more than one input qubit (e.g., two qubits, three qubits). As used throughout, when discussing composite quantum gates, the terms "quantum gate" and "gate" for short may refer to composite quantum gates. These two terms may additionally be used to refer to single-qubit quantum gates (e.g., quantum gates that perform operations on a single qubit). When a distinction is required in the discussion, the terms composite gate and single-qubit gate may be employed. Various embodiments and physical implementations of composite quantum gates are discussed in Foxen et al., "Demonstrating a Continuous Set of Two-Qubit Gates for Near-Term Quantum Algorithms," Phys. Rev. Lett. 125, 120504 (2020), the contents of which are incorporated in their entirety. This incorporated paper can be found at the archive server http: / / arxiv.org / abs / 2001.08343.

[0018] Quantum computing and information processing (QC&IP) may require that the wave functions of the physical manifestation of the information encoding mechanism (e.g., qubits) be isolated from the rest of the universe, e.g., the quantum states associated with the qubits of the system are subject to decoherence and are therefore relatively fragile. Therefore, the noise threshold that a QC&IP system can tolerate is relatively low. Therefore, in some implementations, quantum error correction (QEC) may be a key feature of a QC&IP system. QEC mechanisms detect and correct errors within quantum signals, where the signal is encoded in an "interference" pattern of coherent qubits. That is, when a system supporting QEC detects an error, the system can deploy a mechanism to correct the detected error rather than simply rerunning the calculation. QEC codes can provide such a mechanism. Classical error correction codes (e.g., Hamming codes) typically encode redundant information bits in the signal being processed. This redundant information enables reconstruction of classical information that becomes corrupted when storing, transmitting, and / or processing the signal.

[0019] QEC codes are somewhat similar to classical error correction codes. However, and compared to encoding redundant information in "extra" bits, QEC codes can "spread" or distribute information over multiple qubits via the entanglement of the quantum states of the qubits. The act of "spreading" a signal (e.g., encoding information to be processed) over multiple qubits is generally referred to as encoding. The act of extracting the information spread over multiple qubits is generally referred to as decoding. Therefore, in order to construct an error-correcting quantum computer, encoding and decoding are key aspects of implementing the QEC protocol.

[0020] A quantum decoder is generally responsible for inferring whether a logical error has occurred in a QC&IP system. More specifically, the decoder takes as input a specific set of experimental measurements and an error model. The decoder may be (or generate) a probabilistic description of how errors may occur in a QC&IP system. The probabilistic description may be based on the set of experimental measurements and the error model. Discrete elements of the set of experimental measurements may be referred to as detection events and / or detectors.

[0021] Example embodiments are directed to an enhanced decoder that employs tensor contraction to generate an almost exact probabilistic description of how errors may occur in a QC&IP system. Mapping a set of detection events and error models to a description of errors can be computationally complex. For example, as the size of a QEC code grows linearly, the computational resources required to analytically compute such a mapping also grow exponentially.

[0022] Conventional decoders typically use heuristics to generate approximate mappings rather than directly computing such mappings. Such heuristics typically result in less than ideal QEC performance. For example, a conventional decoder may attempt to generate a mapping by searching for reasonable misconfigurations consistent with an experimental measurement set. Such conventional decoders generate mappings via graph matching techniques. These conventional decoders only generate approximate mappings because only a subset of misconfigurations consistent with the experimental measurement set are mapped.

[0023] Compared to conventional decoders, the example embodiments of the present disclosure use tensor networks, and more specifically, matrix product states. As discussed below, the example embodiments generate and evaluate tensor networks via tensor contraction (e.g., contraction of one or more indices in tensors and / or tensor products). Embodiments include matrix product state decoders that can be decoded almost optimally. The matrix product state decoder can also be used as a framework for approximate decoders. The enhanced decoder takes a detector-level error model describing a physical error channel as input. This error model can be improved using experimental data.

[0024] Various aspects of the present disclosure provide a variety of technical effects and benefits. For example, an enhanced decoder can map a detector-level error model describing physical error channels and the measurements they affect to a tensor network. Conventional decoders only successfully do this for finely tuned error models. The resulting tensor network can be almost exactly evaluated by an enhanced algorithm (via tensor contraction). This algorithm works by mapping irregular tensor network contraction to efficient matrix product state (MPS) evolution. The enhanced MPS includes a hypothesis (e.g., an initial evidence guess) for encoding a probability distribution associated with a detector (e.g., an experimental measurement or detection event) and logical bit information. The hypothesis can be updated (e.g., trained) via machine learning techniques. Once trained, the hypothesis can be used to efficiently evaluate the possibility of different logical measurement results. The possibility (or probability) of different logical measurement results can then be used to determine whether a logical error has occurred. As input, the decoder uses an error model (e.g., encoding the probability of different measurement results). The error model can be iteratively updated (or trained) by using additional experimental data and MPS hypothesis.

[0025] Figure 1 An example quantum computing system 100 is depicted. System 100 is an example of a system of one or more classical computers and / or quantum computing devices located at one or more locations in which the systems, components, and techniques described below may be implemented. One of ordinary skill in the art, using the disclosure provided herein, will appreciate that other quantum computing devices or systems may be used without departing from the scope of the present disclosure.

[0026] System 100 includes quantum hardware 102 in data communication with one or more classical processors 104. Classical processor 104 can be configured to execute computer-readable instructions stored in one or more memory devices to perform operations, such as any of the operations described herein. Quantum hardware 102 includes components for performing quantum computations. For example, quantum hardware 102 includes quantum system 110, control device 112, and readout device 114 (e.g., readout resonator). Quantum system 110 may include one or more multi-level quantum subsystems, such as registers of qubits (e.g., qubit 120). In some implementations, the multi-level quantum subsystem may include superconducting qubits, such as flux qubits, charge qubits, transmon qubits, gmon qubits, spin-based qubits, and the like.

[0027] The type of multi-level quantum subsystem used by system 100 may vary. For example, in some cases, it may be convenient to include one or more readout devices 114 attached to one or more superconducting qubits (e.g., tran smon qubits, flux qubits, gmon qubits, xmon qubits, or other qubits). In other cases, ion traps, photonic devices, or superconducting cavities may be used (e.g., using which qubits may not be required to prepare states). Additional examples of implementations of multi-level quantum subsystems include fluxmon qubits, silicon quantum dots, or phosphorus impurity qubits.

[0028] A quantum circuit may be constructed and applied to a qubit register included in the quantum system 110 via a plurality of control lines coupled to one or more control devices 112. An example control device 112 operating the qubit register may be used to implement a quantum gate or a quantum circuit having a plurality of quantum gates, such as a Pauli gate, a Hadamard gate, a controlled NOT (CNOT) gate, a controlled phase gate, a T gate, a multi-qubit quantum gate, a coupler quantum gate, etc. The one or more control devices 112 may be configured to operate the quantum system 110 through one or more corresponding control parameters (e.g., one or more physical control parameters). For example, in some implementations, the multi-level quantum subsystem may be a superconducting qubit, and the control device 112 may be configured to provide a control pulse to the control line to generate a magnetic field to adjust the frequency of the qubit.

[0029] The quantum hardware 102 may also include a readout device 114 (e.g., a readout resonator). The measurement results 108 obtained via the measurement device may be provided to the classical processor 104 for processing and analysis. In some implementations, the quantum hardware 102 may include a quantum circuit, and the control device 112 and the readout device 114 may implement one or more quantum logic gates that operate the quantum hardware 102 through physical control parameters (e.g., microwave pulses) sent through wires included in the quantum hardware 102. Additional examples of control devices include arbitrary waveform generators, where a DAC (digital-to-analog converter) creates a signal.

[0030] The readout device 114 can be configured to perform quantum measurements on the quantum system 110 and send the measurement results 108 to the classical processor 104. In addition, the quantum hardware 102 can be configured to receive data specifying physical control qubit parameter values ​​106 from the classical processor 104. The quantum hardware 102 can use the received physical control qubit parameter values ​​106 to update the actions of the control device 112 and the readout device 114 on the quantum system 110. For example, the quantum hardware 102 can receive data specifying a new value representing the voltage intensity of one or more DACs included in the control device 112, and the quantum hardware can update the actions of the DACs on the quantum system 110 accordingly. The classical processor 104 can be configured to initialize the quantum system 110 with an initial quantum state, for example, by sending data specifying an initial parameter set 106 to the quantum hardware 102.

[0031] In some implementations, the readout device 114 can measure the state of an element (e.g., a qubit) by using the impedance difference of the |0> and |1> states of an element (e.g., a qubit) of a quantum system. For example, due to the nonlinearity of the qubit, the resonant frequency of the readout resonator can take on different values ​​when the qubit is in state |0> or state |1>. Therefore, the microwave pulse reflected from the readout device 114 carries an amplitude and phase shift that depends on the state of the qubit. In some implementations, a Purcell filter can be used in conjunction with the readout device 114 to block the propagation of microwaves at the qubit frequency.

[0032] In some embodiments, quantum system 110 may include, for example, a plurality of qubits 120 arranged in a two-dimensional grid 122. For clarity, Figure 1The two-dimensional grid 122 depicted in FIG. 1 includes 4×4 qubits, however, in some implementations, system 110 may include a fewer or greater number of qubits. In some embodiments, multiple qubits 120 may interact with each other through multiple qubit couplers (e.g., qubit coupler 124). The qubit coupler may define the nearest neighbor interaction between multiple qubits 120. In some implementations, the strength of the multiple qubit couplers is an adjustable parameter. In some cases, the multiple qubit couplers included in quantum computing system 100 may be couplers with fixed coupling strengths.

[0033] In some implementations, plurality of qubits 120 may include data qubits, such as qubit 126, and measurement qubits, such as qubit 128. A data qubit is a qubit that participates in a computation performed by system 100. A measurement qubit is a qubit that can be used to determine the result of a computation performed by a data qubit. That is, during a computation, the unknown state of the data qubit is transferred to the measurement qubit using an appropriate physical operation and measured via an appropriate measurement operation performed on the measurement qubit.

[0034] In some implementations, each qubit in plurality of qubits 120 may be operated using a corresponding operating frequency (such as an idle frequency and / or an interaction frequency and / or a readout frequency and / or a reset frequency). The operating frequencies of different qubits may be different. For example, each qubit may be idle at a different operating frequency. The operating frequency of qubit 120 may be selected before performing a computation.

[0035] Figure 1 An example quantum computing system that can be used to implement methods and operations according to example aspects of the present disclosure is depicted. Other quantum computing systems can be used without departing from the scope of the present disclosure.

[0036] Figure 2 A graphical depiction of an example error model 200 is depicted in accordance with an example embodiment of the present disclosure. Figure 2 As shown, the error model 200 can be encoded via a bipartite graph 210 including an error channel 220 and a detector 230. The error channel 220 includes a graph node on the left side of the graph 210, and the detector 230 includes a graph node on the right side of the graph 200. The error channel 220 can be a physical error channel. The error model 200 can be a detector-level error model that encodes the physical error channel 220 (e.g., corresponding to the left node of the bipartite graph). The error model 200 can additionally encode the detector 230 affected by each of the error channels 220 (e.g., the corresponding node on the right side of the bipartite graph). The bipartite graph 200 can be referred to as a circuit-level Tanner graph.

[0037] like Figure 2 As indicated, each error channel 220 (e.g., a node or vertex on the left) can have an associated probability. Detectors 230 (e.g., right nodes (or vertices)) are indexed as: D0 to DN, corresponding to detector (or measurement) variables. Therefore, the right nodes (or vertices) indexed as D0 to DN can be referred to as detector bits. The right nodes indexed as L0 to LM correspond to logic bit variables. The right nodes indexed as L0 to LM can be referred to as logic bits. The logic bit variable can change value by activating the error channel connected to it. If an odd number of adjacent error channels are activated, each detector or logic bit changes value.

[0038] Figure 2 The decoding process 240 is shown on the right side of . More specifically, the sum of the probabilities of all possible error configurations can be consistent with some detector bit results and logic bit results, equal to the likelihood of the configuration. By comparing the probabilities corresponding to all possible results of the logic measurement (e.g., likelihood comparison 250), the most likely logic bit likelihood can be estimated. Therefore, it can be inferred whether a logic error has occurred with a certain confidence. Figure 2 The bipartite graph 210 in can represent a multi-dimensional tensor network. Computing this exponentially large probability sum involves collapsing the underlying tensor network (e.g., via tensor collapsing). In order to efficiently collapse this tensor network, a protocol can be employed. The protocol converts Figure 2 into a circuit corresponding to the evolution of a one-dimensional tensor network called a matrix product state (MPS) or tensor train.

[0039] Figure 3 An example of local correlation between detectors within an error model is depicted. The locality of the correlation between detectors indicates a finite maximum bond dimension used to parameterize the tensor network, as discussed below.

[0040] Turn your attention to Figure 4 , which depicts Figure 2 The multi-dimensional tensor network (e.g., Figure 210) is efficiently collapsed into a one-dimensional matrix product state (MPS) 460. Figure 4 The circuit diagram 410 is for a tensor network (eg, Figure 2 In the circuit diagram 410, the left node of the diagram 210 is encoded with Figure 2The error channels 420 correspond to the error channels 420 of the tensor network of the underlying tensor network, while the vertical lines represent the detector bits and logic bits of the underlying tensor network, which are marked with L and D to indicate the corresponding logic bits and detector bits, respectively. The error channel set 420 forms a one-dimensional MPS 460, which can now be evolved from left to right by contracting it with the detectors. By setting the maximum bond dimension that allows the evolution of the MPS 460 to complete the contraction, the tensor network can be approximately evaluated for a given set of detection events and logic bit values. In practice, the bond dimension required for small to medium-sized error correction codes is not too large.

[0041] The related decoding technique uses the fact that the contraction of this tensor network produces an MPS on the detector bit variables and logic bit variables before they are assigned their corresponding values. The MPS can be used directly on these variables as an anatomy of their joint probability distribution. This anatomy can also be trained to match experimental data.

[0042] Figure 5 Depicted is a construction of a matrix product state that generates approximate joint probabilities according to various embodiments. Thus, embodiments can be used to implement a near-optimal (e.g., enhanced) decoder that maps a prior distribution to a tensor network. Various embodiments of a prior distribution are discussed in Acharya et al., "Suppressing Quantum Error by Scaling aSurface Code Logical Qubit," arXiv:2207.06431v2 [quant-ph] (July 2021), the contents of which are incorporated in their entirety. This incorporated paper can be found at the archive server https: / / arxiv.org / abs / 2207.06431v2.

[0043] Given a configuration of detection events and a choice of logical frame changes, the contraction of this tensor network can be used to estimate the joint probability. It is achieved by summing the probabilities of all wrong configurations that are compatible with the set of detection events and logical frame changes considered. The decoder guesses the more plausible logical frame change by comparing the likelihood of two outcomes. For more than a single logical qubit, the decoder guesses the most plausible logical frame change among all outcomes where there are 2 logical qubits (# logical qubits). Compared to conventional decoders, embodiments use device-level noise rather than gate-level noise as input correlation.

[0044] The resulting tensor network has a contraction complexity of d 2 grows exponentially, where d is the distance of the code. In practice, the contraction is an evolution of a matrix product state (MPS) with a finite maximum bond dimension χ (e.g. Figures 4 to 5 The complexity of this approximate contraction is χ 3 increase.

[0045] Figure 6 Experimental data indicating convergence of the probability of logical errors as a function of bond distance are plotted. That is, Figure 6 The graph 600 of φ shows the convergence of the probability of logical errors as a function of the parameter χ. Figure 6 As shown, the convergence 610 of the graph 600 occurs at approximately χ=30. This convergence 610 is achieved by orderly collapsing the tensor network from the error channel tensor toward the detector tensor. Therefore, in various embodiments, the key parameter value χ=30 can be used to decode the error.

[0046] To generate Figure 6 Graph 600 of the probability of logical errors for a distance 5, Z-basis, 25-round experiment with 50,000 shots as a function of the maximum bond dimension χ used in the tensor network contraction. The error bars represent the standard error of the mean. It is observed that the probability of logical errors stabilizes at χ=30.

[0047] Figure 7 A flow chart of an example method 700 for detecting and correcting quantum errors in a quantum computing system according to an example embodiment of the present disclosure is depicted. The method 700 begins at block 702, where a quantum error model may be accessed. The quantum error model may encode a set of quantum error channels. The quantum error model may additionally encode one or more relationships of quantum error channels to detector results. At block 704, a set of detector results is accessed. The set of detected quantum errors may include a set of experimental measurements. At block 706, a tensor network is generated. The tensor network may encode a correlation between a quantum error pattern and a detector result. The correlation may be based on the quantum error model and the measured detector results. At block 708, a matrix product state (MPS) protocol may be generated based on a contraction of the tensor network. At block 710, the MPS protocol may be deployed to infer the presence of one or more quantum errors in the quantum computing system.

[0048] Additional Embodiments

[0049] An example aspect of the present disclosure relates to a method for operating a quantum computing system (QCS). More specifically, an embodiment may be used to detect and / or correct quantum errors occurring in a QCS. The method may include accessing an error model for the QCS. The error model may encode a set of error channels corresponding to a set of quantum error patterns. A set of detected quantum errors may be accessed. The set of detected quantum errors may be encoded in a set of experimental measurements performed on the QCS. A tensor network may be generated. The tensor network may encode correlations between quantum error patterns in a set of quantum error patterns and detected quantum errors in a set of detected quantum errors. A matrix product state (MPS) may be generated based on the tensor network. In order to generate the MPS, the tensor network may be contracted via tensor contraction. A fault-tolerant system having a decoder and an error correction code (e.g., a code) may be generated for the QCS. At least the decoder of the fault-tolerant system may be based on the MPS protocol. That is, the MPS protocol may affect the decoder of the fault-tolerant system. The error correction code may be deployed to the QCS. Once deployed, the error correction codes can be used to detect errors that occur during the runtime of the QCS. The error correction codes can be used to correct the detected errors.

[0050] In at least one embodiment, the MPS protocol may be deployed to infer errors that occur during the runtime of the QCS. The MPS protocol may be deployed to correct errors that occur during the runtime of the QCS. The MPS protocol may be generated by contracting a tensor network. Contracting the tensor operation may include summing the probabilities associated with a subset of error patterns that are compatible with a detected set of quantum errors. Generating the MPS protocol may be parameterized with a maximum bond dimension. The maximum bond dimension may be set to a value of about 30. The MPS protocol may be generated by employing an anthropomorphism for encoding a probability distribution associated with a detected set of quantum errors and logical bit information. The method may also include training the anthropomorphism.

[0051] In various embodiments, the method further comprises encoding the error model and the set of detected quantum errors in a bipartite graph. A circuit diagram may be generated. The bipartite graph may be generated based on the generated circuit diagram. Generating the circuit diagram may be based on the bipartite graph. The MPS protocol may be generated based on the circuit diagram.

[0052] The digital, classical and / or quantum subject matter and implementations of digital function operations and quantum operations described in this specification may be implemented in digital electronic circuit systems, suitable quantum circuit systems or more generally quantum computing systems, in tangibly implemented digital and / or quantum computer software or firmware, in digital and / or quantum computer hardware (including the structures disclosed in this specification and their structural equivalents), or in a combination of one or more of them. The term "quantum computing system" may include, but is not limited to, a quantum computer / computing system, a quantum information processing system, a quantum cryptographic system, or a quantum simulator.

[0053] The implementation of the digital and / or quantum subject matter described in this specification may be implemented as one or more digital and / or quantum computer programs, i.e., one or more modules of digital and / or quantum computer program instructions encoded on a tangible, non-transitory storage medium for execution by a data processing device or for controlling the operation of the data processing device. The digital and / or quantum computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, one or more qubits / qubit structures, or a combination of one or more of them. Alternatively or additionally, the program instructions may be encoded on an artificially generated propagation signal (e.g., a machine-generated electrical, optical, or electromagnetic signal) capable of encoding digital and / or quantum information, which is generated to encode digital and / or quantum information for transmission to an appropriate receiver device for execution by the data processing device.

[0054] The terms quantum information and quantum data refer to information or data carried, stored or stored by a quantum system, wherein the smallest non-trivial system is a qubit, i.e., a system that defines a unit of quantum information. It should be understood that the term "qubit" encompasses all quantum systems that can be appropriately approximated as a two-level system in the corresponding context. Such quantum systems may include multi-level systems, e.g., having two or more levels. For example, such systems may include atoms, electrons, photons, ions, or superconducting qubits. In many implementations, the computational fundamental states are identified by the ground state and the first excited state, however, it should be understood that other arrangements in which the computational states are identified by higher-level excited states (e.g., qubits) are also possible.

[0055] The term "data processing device" refers to digital and / or quantum data processing hardware, and includes all types of devices, apparatuses and machines for processing digital and / or quantum data, including, for example, a programmable digital processor, a programmable quantum processor, a digital computer, a quantum computer or a plurality of digital and quantum processors or computers, and combinations thereof. The device may also be or further include a dedicated logic circuit, such as an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit), or a quantum simulator, i.e., a quantum data processing device designed to simulate or generate information about a specific quantum system. Specifically, a quantum simulator is a special-purpose quantum computer that does not have the ability to perform general-purpose quantum computations. In addition to the hardware, the device may optionally include code that creates an execution environment for a digital and / or quantum computer program, for example, code constituting processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.

[0056] A digital or classical computer program, which may also be referred to or described as a program, software, software application, module, software module, script or code, may be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages; and it may be deployed in any form, including as a standalone program or as a module, component, subroutine or other unit suitable for use in a digital computing environment. A quantum computer program, which may also be referred to or described as a program, software, software application, module, software module, script or code, may be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and translated into a suitable quantum programming language, or may be written in a quantum programming language such as QCL, Quipper, Ci rq, etc.

[0057] A digital and / or quantum computer program may, but does not necessarily correspond to a file in a file system. A program may be stored in a portion of a file that stores other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordination files (e.g., files storing one or more modules, subroutines, or code portions). A digital and / or quantum computer program may be deployed to be executed on a digital computer or a quantum computer or on multiple digital and / or quantum computers, which are located at a site or distributed on multiple sites and interconnected by a digital and / or quantum data communication network. A quantum data communication network is understood to be a network that can transmit quantum data using a quantum system (e.g., qubit). Generally, a digital data communication network cannot transmit quantum data, while a quantum data communication network can transmit quantum data and digital data simultaneously.

[0058] The processes and logic flows described in this specification may be performed by one or more programmable digital and / or quantum computers operating in conjunction with one or more digital and / or quantum processors, where appropriate, executing one or more digital and / or quantum computer programs to perform functions by operating on input digital and quantum data and generating output. The processes and logic flows may also be performed by a dedicated logic circuit (e.g., an FPGA or an ASIC or a quantum simulator), and the device may also be implemented as the dedicated logic circuit, or by a combination of a dedicated logic circuit or a quantum simulator and one or more programmed digital and / or quantum computers.

[0059] For a system of one or more digital and / or quantum computers or processors to be "configured to" or "operable to" perform specific operations or actions, it is meant that the system has installed thereon software, firmware, hardware, or a combination thereof that, in operation, causes the system to perform those operations or actions. For one or more digital and / or quantum computer programs to be configured to perform specific operations or actions, it is meant that the one or more programs include instructions that, when executed by a digital and / or quantum data processing device, cause the device to perform those operations or actions. A quantum computer can receive instructions from a digital computer that, when executed by a quantum computing device, cause the device to perform an operation or action.

[0060] A digital and / or quantum computer suitable for executing a digital and / or quantum computer program may be based on a general or special purpose digital and / or quantum microprocessor or both, or any other kind of central digital and / or quantum processing unit. In general, the central digital and / or quantum processing unit will receive instructions and digital and / or quantum data from a read-only memory, or a random access memory, or a quantum system suitable for transmitting quantum data (e.g. photons), or a combination thereof.

[0061] Some example elements of a digital and / or quantum computer are a central processing unit for executing or implementing instructions and one or more memory devices for storing instructions and digital and / or quantum data. The central processing unit and the memory may be supplemented by or incorporated into a dedicated logic circuit or quantum simulator. Generally, a digital and / or quantum computer will also include one or more mass storage devices for storing digital and / or quantum data, such as magnetic disks, magneto-optical disks or optical disks, or quantum systems suitable for storing quantum information, or operably coupled to receive digital and / or quantum data from or transmit digital and / or quantum data to the mass storage device or both. However, a digital and / or quantum computer need not have such devices.

[0062] Digital and / or quantum computer readable media suitable for storing digital and / or quantum computer program instructions and digital and / or quantum data include all forms of non-volatile digital and / or quantum memory, media and memory devices, including, for example, semiconductor memory devices, such as EPROM, EEPROM and flash memory devices; magnetic disks, such as internal hard disks or removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks; as well as quantum systems, such as trapped atoms or electrons. It should be understood that quantum memory is a device capable of storing quantum data with high fidelity and efficiency for a long time, such as a light-matter interface that uses light for transmission, uses matter for storage, and preserves quantum characteristics such as superposition or quantum coherence of quantum data.

[0063] The control of the various systems or parts thereof described in this specification may be implemented in a digital and / or quantum computer program product, which includes instructions stored on one or more tangible, non-transitory machine-readable storage media and executable on one or more digital and / or quantum processing devices. The systems or parts thereof described in this specification may be implemented as an apparatus, method or electronic system, respectively, which may include one or more digital and / or quantum processing devices and a memory for storing executable instructions to perform the operations described in this specification.

[0064] Although this specification contains many specific implementation details, these details should not be interpreted as limitations on the scope of what may be claimed, but rather as descriptions of features that are specific to a particular implementation. Certain features described in this specification in the context of separate implementations may also be implemented in a single implementation in combination. Conversely, individual features described in the context of a single implementation may also be implemented in multiple implementations individually or in any suitable subcombination. In addition, although features are described above as acting in certain combinations and even initially claimed, one or more features from a claimed combination may be separated from the combination in some cases, and a claimed combination may be directed to a subcombination or a change in a subcombination.

[0065] Similarly, although operations are depicted in a particular order in the accompanying drawings, this should not be understood as requiring that the operations be performed in the particular order shown or in a continuous order, or that all of the operations shown be performed, to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. In addition, the separation of various system modules and components in the implementation described above should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged in multiple software products.

[0066] Specific implementations of the subject matter have been described. Other implementations are within the scope of the appended claims. For example, the actions recited in the claims can be performed in a different order and still achieve the desired results. As an example, the processes depicted in the accompanying drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In some cases, multitasking and parallel processing may be advantageous.

Claims

1. A method for operating a quantum computing system (QCS), the method comprising: accessing an error model for the QCS, wherein the error model encodes a set of error channels and a relationship to detector results; Access the measured detector result set; generating a tensor network that encodes correlations between quantum error patterns in a set of quantum error patterns and the set of measured detector results; as well as A matrix product state (MPS) protocol is generated based on the tensor network.

2. The method of claim 1, further comprising: The MPS protocol is deployed to detect errors occurring during runtime of the QCS.

3. The method of claim 2, further comprising: The MPS protocol is deployed to correct errors that occur during runtime of the QCS.

4. The method of claim 1, wherein the MPS protocol is generated by collapsing the tensor network.

5. The method of claim 4, wherein collapsing the tensor operation comprises summing the probabilities associated with a subset of the error patterns that are compatible with the detected set of quantum errors. The method of claim 1 , wherein the MPS protocol is generated to be parameterized with a maximum bond dimension. The method of claim 6 , wherein the maximum key dimension is set to a value of approximately 30.

8. The method of claim 1, wherein the MPS protocol is generated by employing an anatomy for encoding a probability distribution associated with the set of detected quantum errors and logical bit information.

9. The method of claim 8, further comprising: Training the proposed configuration.

10. The method of claim 1, further comprising: generating a circuit diagram based on the error model and the set of detected quantum errors; generating a bipartite graph based on the circuit diagram; as well as The MPS protocol is generated based on at least one of the circuit diagram and the bipartite graph.

11. A system comprising: One or more memory devices storing computer-readable instructions that, when executed by one or more processors, cause operations to be performed, the operations comprising: accessing an error model for a quantum computing system (QCS), wherein the error model encodes a set of error channels corresponding to a set of quantum error patterns; accessing a set of detected quantum errors encoded in a set of experimental measurements performed on the QCS; generating a tensor network that encodes correlations between quantum error patterns in the set of quantum error patterns and detected quantum errors in the set of detected quantum errors; generating a matrix product state (MPS) protocol based on the tensor network; and The probability that a logical error has occurred is calculated by employing the MPS protocol to generate an error-corrected QCS.

12. The system of claim 11, wherein the operations further comprise: The MPS protocol is deployed to detect errors occurring during runtime of the QCS.

13. The system of claim 11, wherein the operations further comprise: The MPS protocol is deployed to correct errors that occur during runtime of the QCS.

14. The system of claim 11, wherein the MPS protocol is generated by collapsing the tensor network.

15. The system of claim 14, wherein collapsing the tensor network comprises summing probabilities associated with a subset of the error patterns that are compatible with the set of detected quantum errors.

16. The system of claim 11, wherein the MPS protocol is generated to be parameterized with a maximum bond dimension.

17. The system of claim 16, wherein the maximum key dimension is set to a value of approximately 30.

18. The system of claim 11, wherein the operations further comprise: generating a circuit diagram based on the error model and the set of detected quantum errors; generating a bipartite graph based on the circuit diagram; as well as The MPS protocol is generated based on at least one of the circuit diagram and the bipartite graph.

19. One or more non-transitory computer-readable media storing instructions for operating a quantum computing system (QCS) and which, when executed by one or more processors, cause the one or more processors to perform operations comprising: accessing an error model for the QCS, wherein the error model encodes a set of error channels and a relationship to detector results; Access the measured detector result set; generating a tensor network that encodes correlations between quantum error patterns in a set of quantum error patterns and the set of measured detector results; as well as A matrix product state (MPS) protocol is generated based on the tensor network.

20. The computer readable medium of claim 19, wherein the operations further comprise: generating a circuit diagram based on the error model and the set of detected quantum errors; generating a bipartite graph based on the circuit diagram; as well as The MPS protocol is generated based on at least one of the circuit diagram and the bipartite graph.

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