Local annealing of ferroelectric dielectrics

Abstract

A semiconductor device includes a ferroelectric random access memory (FeRAM) cell. The FeRAM includes a ferroelectric dielectric that is annealed by a directed current flow and heating process to reach its ferroelectric phase. Current flow may be directed through a temporary wire that heats the FeRAM cell. The heating or annealing of the ferroelectric dielectric may crystallize the ferroelectric dielectric to embody or result in having ferroelectric properties. Unlike a global heating or annealing process in which the entire semiconductor device or a relatively larger region of the semiconductor device is heated to an annealing temperature of the ferroelectric dielectric, the directed current flow and heating process is substantially confined to the FeRAM cell and the ferroelectric dielectric therein.

Description

Background Art

[0001] The present disclosure relates generally to the field of semiconductor device technology, and more particularly to localized annealing of ferroelectric dielectrics within a ferroelectric random access memory (FeRAM).

[0002] Embodiments of the present disclosure recognize that FeRAM is a non-volatile solid-state memory technology that exploits the presence or absence of charge in a capacitor comprising a ferroelectric dielectric between electrodes. The basic storage unit ("cell") can be programmed into at least two states or levels, both of which exhibit different charge characteristics. The programmable cell states can be used to represent different data values, enabling the storage of information.

[0003] Embodiments of the present disclosure relate to FeRAM cells and their associated wiring and signal transistors. Each cell typically operates in conjunction with a signal transistor. Data can be stored as the presence or absence of charge in a ferroelectric dielectric, where the absence of charge typically represents "0" and the presence of charge represents "1". Writing is achieved by applying a field across the ferroelectric dielectric, which charges the electrodes on both ends of the ferroelectric dielectric, forcing the atoms inside to an "upward" or "downward" orientation (depending on the polarity of the charge), thereby storing "1" or "0". Reading the cell can be achieved by forcing the cell to a specific state (say "0") through a signal transistor. If the cell holds "0", no change appears in the output line. If the cell holds "1", the reorientation of the atoms in the film will result in a short pulse of current in the output because the atoms push electrons away from the metal to the "downward" side. The presence of this pulse means that the cell holds "1". Since the process overwrites the cell, reading FeRAM is a destructive process and requires the cell to be rewritten.

[0004] Embodiments of the present disclosure recognize that materials such as hafnium oxide (HfO 2 ) are promising materials for electronic synaptic devices, memristor devices for brain-like computing, and non-volatile memory devices. In order to integrate ferroelectric dielectrics into FeRAM cells, higher (e.g., greater than 400°C) annealing temperatures may be required to achieve a ferroelectric phase of the ferroelectric dielectric, in which the ferroelectric dielectric embodies or possesses ferroelectric properties such that spontaneous electric polarization can be reversed by applying an external electric field. Subjecting the entire wafer, device, etc. to such high temperatures may damage, melt, etc. other features or materials associated therewith. Therefore, in contrast to such overall heating of a wafer, device, or the like, embodiments of the present disclosure relate to local annealing of ferroelectric dielectrics, wherein appropriate heat is applied to the ferroelectric dielectric without globally heating the entire wafer, device, etc. Since the entire wafer, device, etc. is not subjected to the temperature required to properly anneal the ferroelectric dielectric, damage to other features, components, or materials associated therewith can be limited or reduced. Summary of the invention

[0005] In an embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided. The method includes forming a ferroelectric random access memory (FeRAM) cell of a ferroelectric dielectric, the ferroelectric dielectric being contained between a top electrode and a bottom electrode. The method also includes forming a cell vertical interconnect channel (VIA) on the FeRAM cell. The method also includes forming a temporary wire on the cell VIA. The method also includes annealing the ferroelectric dielectric by directing a current flow through the temporary wire to reach a ferroelectric phase. The ferroelectric dielectric may be a hafnium oxide ferroelectric dielectric.

[0006] In an embodiment of the present disclosure, another method for manufacturing a semiconductor device is provided. The method includes forming a bottom conductor above a substrate. The method also includes forming a bottom heater contact on the bottom conductor. The method also includes forming a ferroelectric random access memory (FeRAM) cell on the bottom heater contact. The FeRAM cell includes a ferroelectric dielectric between a top electrode and a bottom electrode. The method also includes forming a cell vertical interconnect channel (VIA) on the FeRAM cell. The method also includes forming a temporary conductor on the cell VIA. The method also includes annealing the ferroelectric dielectric by directing a current flow through the temporary conductor to reach a ferroelectric phase.

[0007] The method may further include removing the temporary conductive line after annealing the ferroelectric dielectric. Removing the temporary conductive line may include mechanically grinding away the temporary conductive line and leaving at least a portion of the cell VIA thereunder.

[0008] In an embodiment of the present disclosure, a semiconductor device is provided. The semiconductor device includes a bottom heater contact. The semiconductor device includes a ferroelectric random access memory (FeRAM) cell on the bottom heater contact. The FeRAM cell includes a hafnium oxide ferroelectric dielectric between a top electrode and a bottom electrode. The semiconductor device also includes a cell vertical interconnect channel (VIA) on the FeRAM cell.

[0009] Embodiments of the present disclosure generally allow or provide for the integration of ferroelectric dielectrics in FeRAM cells, which typically require ferroelectric dielectric annealing temperatures to reach their ferroelectric phase. Subjecting the entire wafer, device, etc. to such high temperatures may cause other features or materials associated therewith to be damaged, melted, etc. Therefore, embodiments of the present disclosure are directed to localized annealing of ferroelectric dielectrics, wherein appropriate heat is applied to the ferroelectric dielectric by directing the flow of current through the FeRAM cell without the need for global heating of the entire wafer, device, etc. Since the entire wafer, device, etc. is not subjected to the temperatures required to properly anneal the ferroelectric dielectric, damage to other features, components, or materials associated therewith can be limited or reduced.

[0010] The above and other aspects, features and advantages of various embodiments of the present disclosure will become more apparent from the following description in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects, features and advantages of various embodiments of the present disclosure will become more apparent from the following description in conjunction with the accompanying drawings.

[0012] Figures 1 to 15 , a cross-sectional manufacturing view depicting a method of fabricating a semiconductor device including a FeRAM cell having a locally annealed ferroelectric dielectric according to an embodiment of the present disclosure.

[0013] Fig.16 A method of fabricating a semiconductor device including a FeRAM cell having a locally annealed ferroelectric dielectric according to an embodiment of the present disclosure is described. DETAILED DESCRIPTION

[0014] It should be understood in advance that although a detailed description of an exemplary FeRAM architecture including a locally annealed ferroelectric dielectric is provided herein, the implementation of the teachings recorded herein is not limited to the FeRAM architecture described herein. Instead, the embodiments of the present disclosure can be implemented in conjunction with any other suitable type of memory, semiconductor or integrated circuit (IC) device known in the art or developed later.

[0015] The various embodiments of the present disclosure are described herein with reference to the relevant drawings. Alternative embodiments may be designed without departing from the scope of the present disclosure. Note that in the following description and drawings, various connections and positional relationships (e.g., above, below, adjacent, etc.) between elements are described. Unless otherwise specified, these connections and / or positional relationships may be direct or indirect, and the present disclosure is not intended to be limited in this respect. Therefore, the coupling of entities may refer to direct coupling or indirect coupling, and the positional relationship between entities may be a direct or indirect positional relationship. As an example of an indirect positional relationship, it is mentioned in this description that forming layer "A" on layer "B" includes the case where one or more intermediate layers (e.g., layer "C") are between layer "A" and layer "B", as long as the relevant characteristics and functions of layer "A" and layer "B" are not substantially changed by the intermediate layer.

[0016] For the purpose of description hereinafter, the terms "upper", "lower", "right", "left", "vertical", "horizontal", "top", "bottom" and their derivatives relate to structures and methods as oriented as described in the accompanying drawings. The terms "superimposed on", "above", "on top", "placed on" or "placed on top" mean that a first element (such as a first structure) is placed on a second element (such as a second structure), wherein an intervening element (such as an interface structure) may exist between the first element and the second element. The term "direct contact" or similar expressions means that a first element (such as a first structure) and a second element (such as a second structure) are connected without any intermediate conductive, insulating or semiconducting layer at the interface of the two elements. It should be noted that the term "selective to", such as, for example, "the first element is selective relative to the second element" means that the first element can be etched and the second element can serve as an etch stop.

[0017] The terms "about," "substantially," "approximately," and variations thereof are intended to encompass the range of error associated with measuring a particular quantity based on equipment available at the time the application is filed. For example, substantial coplanarity between various materials may include approximate manufacturing tolerances of ±8%, ±5%, ±2%, etc., between coplanar materials.

[0018] For the sake of brevity, conventional techniques related to semiconductor device and IC manufacturing may or may not be described in detail herein. In addition, the various tasks and processes described herein may be incorporated into more comprehensive procedures or processes with additional steps or functions not described in detail herein. The various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known, so for the sake of brevity, many conventional steps will only be briefly mentioned herein, or omitted entirely without providing well-known process details.

[0019] Generally speaking, the various processes used to form microchips that will be packaged into ICs are divided into four major categories, namely, deposition, removal / etching, semiconductor doping and patterning / lithography. Deposition, electroforming, etc. are any processes that grow, coat or otherwise transfer materials to wafers. Available technologies include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and atomic layer deposition (ALD) in recent years. The removal / etching process is any process that removes materials from a wafer. Examples include etching processes (wet or dry) and chemical mechanical planarization (CMP), etc. Semiconductor doping is to change electrical properties by doping, for example, the source and drain of a transistor (usually by diffusion and / or ion implantation). These doping processes are followed by furnace annealing or rapid thermal annealing (RTA). Annealing is used to activate implanted dopants. Thin films of both conductors (e.g., polysilicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate transistors and their components. Selective doping of different areas of a semiconductor substrate allows the conductivity of the substrate to vary with applied voltage. By building structures of these different components, millions of transistors can be built and wired together to form the complex circuits of modern microelectronic devices. Semiconductor lithography is the process of forming a three-dimensional relief image or pattern on a semiconductor substrate for the subsequent transfer of the pattern to the substrate. In semiconductor lithography, the pattern is formed from a photosensitive polymer called a photoresist. The lithography and etching pattern transfer steps are repeated many times in order to build the complex structures that make up the transistors and the many wires that connect the millions of transistors of the circuit. Each pattern printed on the wafer is aligned with the previously formed pattern, and conductors, insulators, and selectively doped areas are slowly built up to form the final device.

[0020] Figures 1 to 15 Depicted are cross-sectional views of fabrication stages of a fabrication method of forming a semiconductor device 100 including one or more FeRAM cells according to various embodiments of the present disclosure. In the depicted exemplary fabrication stage, the FeRAM cell includes a locally annealed ferroelectric dielectric.

[0021] For the purposes of the description below, the terms "upper," "lower," "right," "left," "vertical," "horizontal," "top," "bottom," and their derivatives relate to structures and methods as oriented as depicted in the accompanying drawings. The terms "superimposed on," "over," "on top of," "placed on," or "placed on top of" mean that a first element (such as a first structure) is placed on a second element (such as a second structure) wherein an intervening element (such as an interface structure) may exist between the first element and the second element. The term "direct contact" or similar expressions means that a first element (such as a first structure) and a second element (such as a second structure) are connected without any intervening conductive, insulating, or semiconducting layer at the interface of the two elements. It should be noted that the term "selective to," for example, "the first element is selective to the second element" means that the first element may be etched and the second element may serve as an etch stop.

[0022] The terms "about," "substantially," "approximately," and variations thereof are intended to encompass the range of error associated with measuring a particular quantity based on equipment available at the time the application is filed. For example, substantial coplanarity between various materials may include approximate manufacturing tolerances of ±8%, ±5%, ±2%, etc., between coplanar materials.

[0023] For the sake of brevity, conventional techniques related to semiconductor device and IC manufacturing may or may not be described in detail herein. In addition, the various tasks and processes described herein may be incorporated into more comprehensive procedures or processes with additional steps or functions not described in detail herein. The various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known, so for the sake of brevity, many conventional steps will only be briefly mentioned herein, or omitted entirely without providing well-known process details.

[0024] Thin films of both conductors (e.g., polysilicon, aluminum, copper, etc.) and insulating materials (e.g., various forms of silicon dioxide, silicon nitride, etc.) can be used to connect components. Selectively doping different areas of a semiconductor device allows the conductivity of the semiconductor device to vary with applied voltage. By building structures of these different components, millions of semiconductor microdevices (such as FeRAM cells) can be built and wired together to form the complex circuits of modern microelectronics. Semiconductor lithography refers to the formation of a three-dimensional relief image or pattern on a semiconductor substrate for subsequent transfer of the pattern to the substrate. In semiconductor lithography, the pattern is formed by a photosensitive polymer called a photoresist. The lithography and etching pattern transfer steps are repeated many times in order to build the complex structures that make up the microdevices and the many wires that connect the millions of transistors of the circuit. Each pattern printed on the semiconductor device layer is aligned with the previously formed pattern, and the conductors, insulators, and selectively doped areas are slowly built to form the final semiconductor device, integrated circuit package, etc.

[0025] Figure 1 Depicted are cross-sectional views of fabrication stages for forming a semiconductor device according to various embodiments of the present disclosure. After the current fabrication stage, the semiconductor device 100 includes a substrate 102 and one or more bottom conductive lines 104 .

[0026] The substrate 102 is typically formed of a semiconductor or dielectric material. In a preferred implementation, the substrate 102 may be formed of a low-k dielectric material (i.e., a material with a smaller dielectric relative to silicon dioxide, such as SiCOH). In some implementations, the substrate 102 may be an interlayer dielectric (ILD) layer, where the additional layer(s) of the semiconductor device 100 have been previously fabricated below it. In these implementations, electrical micro devices such as transistors, diodes, capacitors, resistors, etc. may be formed within the additional layer(s) of the semiconductor device 100 by any suitable formation method.

[0027] The substrate 102 and / or additional layers of the semiconductor 100 may include semiconductor materials such as germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates may also be used, such as multilayer substrates or gradient substrates.

[0028] In some implementations, the bottom conductor 104 may be part of or below a metallization layer of the semiconductor device 100. The metallization layers may be denoted as Mx, where x=0, 1, 2, ..., where M0 represents the lowest (i.e., closest to the substrate 102) metallization layer, and the index x increases by 1 for each additional metallization layer. In some implementations, conductive features (such as wires, contacts, and / or vias) provide electrical connections from the bottom conductor 104 to features above and / or below the bottom conductor 104 (such as micro devices below it or wiring features above it). In some implementations, the bottom conductor 104 may also be referred to as pads, plugs, planes, traces, etc., respectively.

[0029] In some implementations, the bottom conductive line 104 includes an inner conductive region and (one or more) conductive barrier layers (not shown) lining the sidewalls and bottom surfaces of the inner conductive region. The conductive barrier layer can be formed of titanium, titanium nitride, tantalum, tantalum nitride, cobalt, combinations thereof, etc. The inner conductive region can be formed of, for example, copper, aluminum, tungsten, cobalt, alloys thereof, etc. For example, one or more electrical paths can connect the bottom conductive line 104 to a FeRAM memory controller to sense resistance across an associated FeRAM cell, etc.

[0030] The formation of the bottom conductive line 104 may include etching a portion of the substrate 102 to form an opening, forming a blanket conductive barrier layer extending to the opening, depositing metal over the blanket conductive barrier layer, and performing a planarization process (such as a CMP process or a mechanical grinding process) to remove excess portions of the blanket conductive barrier layer and excess portions of the internal conductive region so that the top surface of the substrate 102 is coplanar with the bottom conductive line 104.

[0031] Figure 2 Depicted are cross-sectional views of manufacturing stages in forming a semiconductor device 100 according to various embodiments of the present disclosure. At the current manufacturing stage, a heater layer 106 is formed on the substrate 102 and on one or more bottom conductive lines 104 .

[0032] The heater layer 106 may be, for example, a silicon layer or a silicon-based layer, such as a silicon nitride layer. The heater layer 106 may be formed by depositing a blanket dielectric layer to a thickness between 1 and 100 nm. In a preferred implementation, the heater layer 106 may be formed to a thickness between 5 and 20 nm. The heater layer 106 may be a dielectric layer in which a bottom heater, bottom contact, etc. of a FeRAM cell is formed.

[0033] Figure 3Depicted are cross-sectional views of fabrication stages in forming a semiconductor device 100 according to various embodiments of the present disclosure. At the current fabrication stage, the heater layer 106 is patterned by forming one or more bottom contact trenches 108 therein.

[0034] The bottom contact groove 108 can be formed by photolithography. For example, a photoresist (not shown) can be formed on the heater layer 106. The photoresist can be applied to the heater layer 106 as a liquid, which dries and is patterned to generally form grooves in the photoresist. The photoresist can also be a semi-solid film coated, laminated or otherwise formed on the heater layer 106. For example, the photoresist can have a thickness ranging from about 10um to about 500um, although thicknesses less than 40um and greater than 500um are also considered. In one implementation, the photoresist can be about 150um to 175um thick.

[0035] A pattern can be formed in the photoresist by removing portions of the photoresist. For example, portions of the photoresist can be exposed to radiation, such as deep ultraviolet light or an electron beam. Once the patterning of the photoresist is completed, portions of the photoresist can be retained, and portions of the photoresist can be etched away by removing the etchant of the photoresist. The retained portions of the photoresist can form a patterned photoresist. The etched portions of the photoresist form resist grooves that can expose the heater layer 106 below. Using the patterned photoresist as a mask, portions of the heater layer 106 below are exposed or protected, and the exposed or unprotected portions of the heater layer 106 below are etched or removed. This patterning or removal of portions of the heater layer 106 can effectively form one or more bottom contact grooves 108. Each of the one or more bottom grooves 108 can expose the corresponding lower portion of the associated bottom conductive line 104.

[0036] Figure 4 Depicted are cross-sectional views of manufacturing stages in forming a semiconductor device 100 according to various embodiments of the present disclosure. At the current manufacturing stage, a bottom contact 110 is formed within the bottom contact trench 108 .

[0037] The bottom contact 110 can be formed by depositing a conductive material on the heater layer 106 and on the bottom conductive line 104 filling the contact trench(es) 108. CMP or other grinding techniques can remove excess bottom contact 110 material. This planarization can result in the upper surface of the heater layer 106 being coplanar with the upper surface of the one or more bottom contacts 110. The bottom contact 110 material can be any common conductive material used as an electrode, for example, tungsten, platinum, titanium nitride, tantalum nitride, titanium aluminum nitride, alloys thereof, etc.

[0038] In some implementations, the bottom contact 110 includes an inner conductive region and a conductive barrier layer(s) (not shown) lining the sidewalls and bottom surface of the inner conductive region. The conductive barrier layer may be formed of, for example, titanium, titanium nitride, tantalum, tantalum nitride, cobalt, combinations thereof, etc. The inner conductive region may be formed of a metal such as copper, aluminum, tungsten, cobalt, tungsten, platinum, titanium nitride, tantalum nitride, titanium aluminum nitride, alloys thereof, etc.

[0039] The formation of the bottom contact 110 may include forming a blanket conductive barrier layer extending into the bottom contact trench, depositing metal over the blanket conductive barrier layer, and performing a planarization process (such as a CMP grinding process) to remove excess portions of the blanket conductive barrier layer and excess portions of the internal conductive region so that the top surfaces of the heater layer 106 and the bottom contact 110 are coplanar.

[0040] Figure 5 Depicted are cross-sectional views of fabrication stages in forming a semiconductor device 100 in accordance with various embodiments of the present disclosure. At the current fabrication stage, a FeRAM cell build-up layer 120 is formed over the heater layer 106 and the bottom contact 110 .

[0041] The FeRAM cell stacking layer 120 may be formed by first depositing a bottom electrode layer 112 on the heater layer 106 and the bottom contact 110 , depositing a ferroelectric dielectric layer 114 on the bottom electrode layer 112 , depositing a top electrode layer 116 on the ferroelectric dielectric layer 114 , and depositing a resistor layer 118 on the top electrode layer 116 .

[0042] The bottom electrode layer 112 can be formed on the heater layer 106 by depositing a conductive electrode material (such as titanium nitride, tantalum nitride, tungsten, etc.) onto the heater layer 106 and the bottom contact 110. The bottom electrode layer 112 can be formed to a thickness between 5 and 75 nm. In a specific implementation, the bottom electrode layer 112 can be formed to a thickness between 20 and 30 nm. The bottom electrode layer 112 can be formed by any suitable process or any suitable combination of processes, including but not limited to atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, electroplating, evaporation, ion beam deposition, electron beam deposition, laser assisted deposition, chemical solution deposition, etc.

[0043] The bottom electrode layer 112 may include any suitable conductive material, including but not limited to metals (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), hafnium (Hf), zirconium (Zr), cobalt (Co), nickel (Ni), copper (Cu), aluminum (Al), platinum (Pt), tin (Sn), silver (Ag), gold (Au)), conductive metal composites (e.g., tantalum nitride (TaN), titanium nitride (TiN), tantalum carbide (TaC), titanium carbide (TiC), titanium aluminum carbide (TiAlC), tungsten silicide (WSi), tungsten nitride (WN), ruthenium oxide (RuO 2 ), cobalt silicide (CoSi), nickel silicide (NiSi)), transition metal aluminides (e.g., Ti3Al, ZrAl), TaC, TaMgC, and appropriate combinations or alloys of these metals, etc.

[0044] The ferroelectric dielectric material (such as but not limited to HfO) 2 , TaO, TaNO, HfNO, TiO, TiNO, WO, WNO, ZrO, ZrNO, CeO, CeNO and mixtures thereof (such as HfZnO)) are deposited onto the bottom electrode layer 112 to form a ferroelectric dielectric layer 114 on the bottom electrode 112. The ferroelectric dielectric layer 114 may be formed to a thickness between 10 and 100 nm. In a specific implementation, the ferroelectric dielectric layer 114 may be formed to a thickness between 40 and 50 nm. The ferroelectric dielectric 114 may be an undoped material layer or alternatively a doped material layer. For example, the ferroelectric dielectric layer 114 may be a ferroelectric dielectric layer doped with silicon (Si), aluminum (Al), zirconium (Zr), nitrogen (N), yttrium (Y), lanthanum (La), etc.

[0045] A top electrode layer 116 may be formed on the ferroelectric dielectric layer 114 by depositing a conductive electrode material on the ferroelectric dielectric layer 114. The top electrode layer 116 may be formed to a thickness between 5 and 75 nm. In one implementation, the top electrode layer 116 may be formed to a thickness between 15 and 25 nm. The top electrode layer 116 may be formed by any applicable process or any applicable combination of processes, including but not limited to atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, electroplating, evaporation, ion beam deposition, electron beam deposition, laser assisted deposition, chemical solution deposition, etc. The top electrode layer 116 is typically, but not necessarily, formed of the same material as the bottom electrode material layer 112.

[0046] A resistor layer 118 may be formed on the top electrode layer 116 by depositing a dielectric material such as aluminum gallium nitride (AlGaN), nitrogen-rich tantalum nitride, etc. on the top electrode layer 116. The resistor layer 118 may be formed to a thickness between 1 and 20 nm. In a specific implementation, the resistor layer 118 may be formed to a thickness between 2 and 10 nm. In some implementations, the resistor layer 118 may be used as a resistor for current input and / or output FeRAM cells.

[0047] Figure 6 Depicted are cross-sectional views of fabrication stages in forming a semiconductor device 100 in accordance with various embodiments of the present disclosure. At the current fabrication stage, the FeRAM cell build-up layer 120 is patterned to form one or more FeRAM cells 122 .

[0048] Photolithography techniques may be used to develop or pattern the FeRAM cell stacking layer 120. For example, a photoresist may be formed on the resistor layer 118, and a pattern may be formed in the photoresist by removing portions of the photoresist. In a specific implementation, a portion of the photoresist may be exposed to radiation, such as deep ultraviolet light or an electron beam. Once the patterning of the photoresist is completed, portions of the photoresist may be retained, and portions of the photoresist may be etched away by an etchant that removes the photoresist. The retained portions of the photoresist may form a patterned photoresist. The etched portions of the photoresist form resist grooves that may reveal the FeRAM cell stacking layer 120 below. Using the patterned photoresist as a mask, portions of the FeRAM cell stacking layer 120 below are exposed or protected, and the exposed, unprotected portions of the FeRAM cell stacking layer 120 below are etched or removed. Such patterning or removal of portions of the FeRAM cell build-up layer 120 may effectively form one or more FeRAM cells 122 and may expose a top surface of one or more portions of the heater layer 106 and may further expose a top surface of one or more bottom contacts 110 .

[0049] The etching technique used to remove the FeRAM cell build-up layer 120 may be a physical or dry etching technique or a chemical wet etching. In a preferred implementation, the etching is a physical dry etching, and therefore, there is less risk of damage to one or more FeRAM cells 122 (e.g., limited lateral etching of the FeRAM cell build-up layer 120 may be experienced due to the lack of a chemical etchant).

[0050] After formation, the FeRAM cell 122 may include a bottom electrode 124 formed by a retained portion of the bottom electrode layer 112, may include a ferroelectric dielectric 126 formed by a retained portion of the ferroelectric dielectric layer 114, may include a top electrode 128 formed by a retained portion of the top electrode layer 116, and may include a resistor 130 formed by a retained portion of the resistor layer 118.

[0051] Figure 7 Depicted are cross-sectional views of fabrication stages for forming semiconductor device 100 according to various embodiments of the present disclosure. At the current fabrication stage, encapsulation layer 132 is formed on and around FeRAM cell 122 and on heater layer 106 and bottom contact 110 .

[0052] The encapsulation layer 132 may be, for example, a silicon layer or a silicon-based layer, such as a silicon nitride layer. The encapsulation layer 132 may be formed by depositing a blanket dielectric layer to a thickness between 5 and 200 nm. In a specific implementation, the encapsulation layer 132 may be formed to a thickness between 3 and 50 nm. In some implementations, a portion of the encapsulation layer 132 located on the top surface of the FeRAM cell 122 and / or on the top surface of the bottom heater 110 and / or on the top surface of the heater layer 106 may be removed, while a portion of the encapsulation layer 132 located on the sidewalls of the FeRAM cell 122 may be retained. In other words, the encapsulation layer 132 may be formed as a spacer on the sidewalls of the FeRAM cell 122.

[0053] Figure 8 Depicted are cross-sectional views of fabrication stages in forming a semiconductor device 100 according to various embodiments of the present disclosure. At the current fabrication stage, an inter-layer dielectric (ILD) 134 is formed on the encapsulation layer 132 above the FeRAM cell 122 .

[0054] If the encapsulation layer 132 takes the form of spacers on the sidewalls of the FeRAM cell 122 , the ILD 134 may be formed on the FeRAM cell 122 and around the encapsulation layer 132 spacers and on the top surface and / or top region of the bottom heater 110 .

[0055] As the case may be or as desired, the ILD 134 may be formed by blanket deposition of dielectric material, such as a low-k dielectric material, on the encapsulation layer 132, over the heater layer 106, and over the bottom contact 110. The ILD 132 may be formed to a height substantially greater than the FeRAM cell 122 or to a height substantially at an upper surface of the FeRAM cell 122 and / or an upper surface of the encapsulation layer 132 on a top surface of the FeRAM cell 122.

[0056] Fig. 9 Depicted are cross-sectional views of manufacturing stages in forming a semiconductor device 100 according to various embodiments of the present disclosure. At the current manufacturing stage, cell vertical interconnect vias (VIAs) 142 and temporary conductive lines 144 are formed within the ILD 134 .

[0057] The cell VIA 142 and the temporary wire 144 may be formed simultaneously by dual damascene techniques. For example, a selective removal technique may remove an unneeded portion of the ILD 134 substantially above a portion of the FeRAM cell 122 to form a VIA trench, and remove an unneeded portion of the ILD 134 substantially above the VIA trench to form a temporary wire trench. The VIA trench may expose at least a portion of the resistor 130 of the FeRAM cell 122. The temporary wire trench may form a groove or trench, and may intersect or otherwise be associated with one or more VIA trenches.

[0058] As shown, etching techniques can be used to form wiring trenches with orthogonal sidewalls (i.e., parallel to the sidewalls of the NVM cell), or to form wiring trenches with inclined sidewalls. In one implementation, resistor 130 is used as an etch stop layer. The etching technique can be physical or dry etching, or chemical wet etching. In a preferred implementation, the etching can be chemical wet etching, and resistor 130 is configured as a wet etch stop.

[0059] Subsequently, unit VIA 142 is formed in the VIA groove, and temporary wire 144 is formed in the temporary wire groove. In the current implementation, unit VIA 142 and temporary wire 144 can be formed simultaneously by dual damascene technology. For example, unit VIA 142 and temporary wire 144 can be formed simultaneously by depositing conductive materials such as copper in the VIA groove and the temporary wire groove respectively.

[0060] The cell VIA 142 may directly contact the resistor 130 of the FeRAM cell 122. For example, the cell VIA 142 contacts the entire upper surface or a portion of the upper surface of the resistor 130. Because the cell VIA 142 contacts or is connected to the resistor 130 of the FeRAM cell 122, rather than directly contacting the top electrode 128, the current flowing into the FeRAM cell 122 may be limited by the impedance of the resistor 130 (which is tunable based on the selection of the material and / or size of the resistor 130). By limiting the current entering the FeRAM cell with the resistor 130, the durability of the FeRAM cell 122 may be improved, and negative impacts on components adjacent to the FeRAM cell 122 may be limited. The temporary wire 144 may be electrically connected or otherwise associated with one or more underlying cell VIAs 142, such that current may flow through the temporary wire 144 and enter the FeRAM cell 122 through the associated cell VIA 142.

[0061] For clarity, the temporary wire 144 is considered temporary or disposable because the temporary wire 144 is subsequently removed. Because the temporary wire 144 is removed, the geometry of the temporary wire 144 can be specifically selected to achieve sufficient current flow through the FeRAM cell 122. For example, a larger (i.e., lower impedance) temporary wire 144 can be fabricated relative to a replacement wire or other conductive feature that is subsequently formed over the FeRAM cell 122 and / or cell VIA 142, which may not achieve sufficient current flow through the FeRAM cell 122 to anneal the ferroelectric dielectric 126. In addition, space requirements may not allow such a larger replacement wire or other conductive feature to achieve sufficient current flow through the FeRAM cell 122 to anneal the ferroelectric dielectric 126. Therefore, the temporary wire 144 can be specifically fabricated to achieve such sufficient current flow through the FeRAM cell 122, and then removed to allow a relatively smaller replacement wire or other conductive feature to meet the space requirements.

[0062] Fig.10 Depicted are cross-sectional views of fabrication stages for forming a semiconductor device 100 according to various embodiments of the present disclosure. At the current fabrication stage, the ferroelectric dielectric 126 is annealed by a directed current flow and heating process 150 to achieve its ferroelectric phase.

[0063] The guided current flow and heating process 150 occurs when the current flow is guided through the temporary wire 144 and the associated cell VIA 142 (which causes heating of the FeRAM cell). The induced heating or annealing of the ferroelectric dielectric 126 can crystallize the ferroelectric dielectric 126, so that the ferroelectric dielectric 126 embodies or has ferroelectric properties (for example, the spontaneous electric polarization of the ferroelectric dielectric 126 can be reversed by applying an external electric field, etc.).

[0064] The guided current flow and heating process 150 is a local annealing technique in which heating is substantially confined to the FeRAM cell 122 and the ferroelectric dielectric 126 therein because of the guided current flow through the temporary wire 144, as distinguished from a global heating or annealing process in which the entire semiconductor device 100 or a relatively large area of ​​the semiconductor device 100 is heated to the necessary annealing temperature of the ferroelectric dielectric 126. The guided current flow and heating process 150 may be referred to as an electron charging process in which the temporary wire 144 is charged with electrons resulting in the guided current flow through the temporary wire 144.

[0065] In a specific implementation, the directed current flow and heating process 150 may be a technique or process in which an external device or system directs the flow of current across the temporary wire 144 and the associated cell VIA 142 into the FeRAM cell 122. For example, a plasma generation tool or an electron beam generation tool may be used to direct the flow of current across the temporary wire 114 and the associated cell VIA 142 into the FeRAM cell 122, thereby heating the ferroelectric dielectric 126. The plasma generation tool may be an inductively coupled plasma (ICP) tool, a capacitively coupled plasma (CCP) tool, a microwave generated plasma tool, etc. The electron beam generation tool may be a field emission based electron beam generation tool, a plasma based electron beam tool, etc.

[0066] In a specific implementation, when the FeRAM cell 122 has a square pillar geometry with a width between 10 and 1000 nm and a height between 1 and 500 nm, the guided current flow and heating process 150 can generate a current of 100 to 500 uA across the temporary wire 144 and the associated cell VIA 142 into the FeRAM cell 122 to achieve the HfO 2 The temperature at which the ferroelectric dielectric 126 is fully annealed.

[0067] The geometry and materials of the cell VIA 142 and temporary conductor 144 can be selected to achieve or allow a predetermined desired guided current flow therethrough to generate a desired annealing temperature of the ferroelectric dielectric 126 while remaining below a predetermined maximum temperature of the cell VIA 142 and temporary conductor 144. By remaining below a predetermined maximum temperature of the cell VIA 142 and temporary conductor 144, temperature-based damage to semiconductor device 100 components or materials adjacent to or substantially proximate to the cell VIA 142 and temporary conductor 144 can be limited, and the guided current flow and heating process 150 can be appropriately localized. In some implementations, the predetermined maximum temperature of the cell VIA 142 and temporary conductor 144 can be 100=1000°C, and the predetermined desired guided current flow can be 100uA-1mA.

[0068] Fig.11 Depicted are cross-sectional views of manufacturing stages in forming the semiconductor device 100 according to various embodiments of the present disclosure. At the current manufacturing stage, the temporary conductive lines 144 are removed, and the top surface of the ILD 134 and one or more cell VIAs 142 are planarized.

[0069] The temporary conductive lines 144 may be removed by a planarization process, such as a CMP process or a mechanical grinding process, to remove the temporary conductive lines 144 and achieve coplanarity of a top surface of the ILD 134 and a corresponding top surface of one or more unit VIAs 142 .

[0070] Figures 12 to 15 A cross-sectional view of an alternative manufacturing stage of semiconductor device 100 including sequential fabrication of cell VIA 142 and temporary conductive line 144 is depicted. Figures 12 to 15 The manufacturing stages depicted in the figure can take place in Figure 8 After the manufacturing stages depicted in .

[0071] Fig.12 Depicted are cross-sectional views of manufacturing stages in forming a semiconductor device 100 according to various embodiments of the present disclosure. At the current manufacturing stage, one or more cell VIAs 142 are formed within the ILD 134 .

[0072] Cell VIA 142 may be formed by damascene techniques. For example, a selective removal or etching technique may remove an undesired portion of ILD 134 that is typically over a portion of FeRAM cell 122 to form a VIA trench 152. VIA trench 152 may expose at least a portion of resistor 130 of FeRAM cell 122.

[0073] As shown, the etching technique can be used to form the VIA trench 152 with orthogonal sidewalls (i.e., parallel to the sidewalls of the FeRAM cell 122), or to form the VIA trench 152 with inclined sidewalls. In one implementation, the resistor 130 is used as an etch stop layer. The etching technique can be a physical or dry etch or a chemical wet etch. In a preferred implementation, the etching technique can be a chemical wet etch, and the resistor 130 is configured as a wet etch stop.

[0074] Subsequently, the unit VIA 142 is formed in the VIA trench 152. For example, the unit VIA 142 may be formed by depositing a conductive material such as copper in the VIA trench 152.

[0075] The cell VIA 142 may directly contact the resistor 130 of the FeRAM cell 122. For example, the cell VIA 142 contacts the entire upper surface or a portion of the upper surface of the resistor 130. Because the cell VIA 142 contacts or is connected to the resistor of the FeRAM cell 122, rather than directly contacting the top electrode 128, the flow of current entering the FeRAM cell 122 may be limited by the impedance of the resistor 130. By limiting the current entering the FeRAM cell 122 with the resistor 130, the durability of the FeRAM cell 122 may be improved, and negative impacts on components adjacent to the FeRAM cell 122 may be limited.

[0076] Fig.13 Depicted are cross-sectional views of manufacturing stages for forming a semiconductor device 100 according to various embodiments of the present disclosure. At the current manufacturing stage, one or more cell temporary conductive lines 144 are formed on the ILD 134 and the cell VIA 142 .

[0077] One or more temporary conductive lines 144 may be formed by photolithography. For example, a photoresist (not shown) may be formed on the ILD 134 and the cell VIA 142. The photoresist may be applied as a liquid on the ILD 134 and the cell VIA 142, and the liquid may dry and be patterned to form grooves substantially in the photoresist. The photoresist may also be a semi-solid film coated, laminated or otherwise formed on the ILD 134 and the cell VIA 142.

[0078] A pattern can be formed in the photoresist by removing portions of the photoresist. For example, portions of the photoresist can be exposed to radiation, such as deep ultraviolet light or an electron beam. Once the patterning of the photoresist is completed, portions of the photoresist can be retained and portions of the photoresist can be etched away by removing the etchant of the photoresist. The retained portions of the photoresist can form a patterned photoresist. The etched portions of the photoresist form conductive grooves that can reveal or expose the lower portions of the ILD 134 and the underlying unit VIA 142.

[0079] One or more temporary conductive lines 144 may be further formed by depositing metal within the temporary conductive line trenches and on the underlying portions of the exposed ILD 134 and the underlying cell VIA 142 , performing a planarization process such as a CMP process or a mechanical grinding process to remove excess portions of the temporary conductive lines 144 , and removing the photolithographic resist.

[0080] Fig.14 Depicted are cross-sectional views of fabrication stages for forming a semiconductor device 100 according to various embodiments of the present disclosure. At the current fabrication stage, the ferroelectric dielectric 126 is annealed to its ferroelectric phase by a directed current flow and heating process 150. Details of the directed current flow and heating process 150 have been disclosed above and therefore will not be repeated.

[0081] Fig.15 Depicted are cross-sectional views of manufacturing stages in forming the semiconductor device 100 according to various embodiments of the present disclosure. At the current manufacturing stage, the temporary conductive lines 144 are removed, and the top surface of the ILD 134 and one or more cell VIAs 142 are planarized.

[0082] The temporary conductive line 144 may be removed by a planarization process such as a CMP process or a mechanical grinding process for removing the temporary conductive line 144 and achieving coplanarity of the top surface ILD 134 and the corresponding top surface of the one or more cell VIAs 142 .

[0083] For clarity, the semiconductor device 100 may undergo further manufacturing stages to manufacture a final semiconductor device, IC device, IC chip, etc. For example, the semiconductor device 100 may undergo a back-end-of-line (BEOL) manufacturing stage to manufacture one or more M0-Mx wiring layers including one or more conductive lines, potential planes, etc., which may be electrically connected to the cell VIA 142 and / or the bottom conductive line 104.

[0084] Fig.16A method 200 of fabricating a semiconductor device 100 including a FeRAM cell 122 having a locally annealed ferroelectric dielectric 126 according to various embodiments of the present disclosure is depicted.

[0085] The method 200 may include forming one or more bottom conductive lines 104 on or within a substrate 102 (block 202 ), and may subsequently include forming a heating layer 106 on the one or more bottom conductive lines 104 and the substrate 102 (block 204 ).

[0086] The method 200 may further include forming one or more bottom heaters 110 within the heating layer 106. For example, one or more bottom contact trenches 108 are formed within the heating layer 106. Each of the one or more bottom contact trenches 108 may expose a portion of a top surface of the corresponding one or more bottom conductive lines 104. Subsequently, a bottom heater 110 may be formed within each of the one or more bottom contact trenches 108, and a planarization process may cause the corresponding top surface of the bottom heater 110 to be coplanar with the top surface of the heating layer 106.

[0087] The method 200 may also include forming a FeRAM build-up layer 120 on the heater layer 106 and the one or more bottom heaters 110 (block 208). The FeRAM cell build-up layer 120 may be formed by depositing a bottom electrode layer 112 on the heater layer 106 and the bottom contact 110, depositing a ferroelectric dielectric layer 114 on the bottom electrode layer 112, depositing a top electrode layer 116 on the ferroelectric dielectric layer 114, and depositing a resistor layer 118 on the top electrode layer 116.

[0088] The method 200 may also include forming a FeRAM cell 122 from the FeRAM cell build-up layer 120 (block 210). The FeRAM cell 122 may be formed by retaining one or more portions of the FeRAM cell build-up layer 120 and removing one or more portions of the FeRAM cell build-up layer 120. The respective, retained one or more portions of the FeRAM cell build-up layer 120 may be arranged into a stack of FeRAM cell build-up layer 120 portions having coplanar sidewalls. Each FeRAM cell 122 may be directly located on the bottom heater 110.

[0089] After formation, the FeRAM cell 122 may include a bottom electrode 124 formed by a retained portion of the bottom electrode layer 112, a ferroelectric dielectric 126 formed by a retained portion of the ferroelectric dielectric layer 114, a top electrode 128 formed by a retained portion of the top electrode layer 116, and a resistor 130 formed by a retained portion of the resistor layer 118.

[0090] The method 200 may also include forming an encapsulation layer 132 at least on the sidewalls of the one or more FeRAM cells 112 (block 212). The encapsulation layer 132 may also be formed on the top surface of the one or more FeRAM cells 122. Encapsulation may also be formed on the respective top surfaces of the one or more bottom heaters 110 and the top surface of at least a portion of the heating layer 106.

[0091] The method 200 may further include forming an ILD 134 on the encapsulation layer 132 (block 214). If the encapsulation layer 132 is not fabricated on the top surface of the FeRAM cell 122, the ILD 134 may further be formed on the top surface of the FeRAM cell 122. If the encapsulation layer 132 is not formed on the corresponding top surface of the one or more bottom heaters 110 and is not formed on the top surface of at least a portion of the heating layer 106, the ILD 134 may further be formed thereon.

[0092] The method 200 may further include forming VIA 142 within the ILD 134 and on the FeRAM cell 122 (block 216), and may further include forming temporary conductive lines 144 within or on the ILD 134 and on the cell VIA 142 (block 218). The formation of the cell VIA 142 and the temporary conductive lines 144 may occur simultaneously (i.e., in the same dual damascene fabrication process) or sequentially (i.e., in sequential different single damascene processes), as described herein.

[0093] The method 200 may also include subjecting the temporary wire 144 to a directed current flow and heating process 150 to direct current flow through the temporary wire 144 across the associated FeRAM cell 122 (block 220) to locally heat or anneal the ferroelectric dielectric 126 (block 222). The resulting heating or annealing of the ferroelectric dielectric 126 may crystallize the ferroelectric dielectric 126 such that the ferroelectric dielectric 126 embodies or has ferroelectric properties. The geometry and materials of the cell VIA 142 and the temporary wire 144 may be selected to achieve or allow a predetermined desired directed current flow therethrough to generate a desired annealing temperature of the ferroelectric dielectric 126 while remaining below a predetermined maximum temperature of the cell VIA 142 and the temporary wire 144. By staying below a predetermined maximum temperature of the cell VIA 142 and temporary conductors 144 , temperature-based damage to components or materials of the semiconductor device 100 adjacent or substantially proximate to the cell VIA 142 may be limited, and the directed current flow and heating process 150 may be appropriately localized.

[0094] The method 200 may continue by removing the temporary conductive lines 144 (block 224 ). For example, a mechanical grinding or CMP process may remove the temporary conductive lines 144 and may make the top surface of the one or more VIAs 142 coplanar with the top surface of the ILD 134 .

[0095] The description of the various embodiments of the present disclosure is provided for the purpose of illustration and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations are apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications or technical improvements based on existing technologies in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a ferroelectric random access memory (FeRAM) cell, the FeRAM cell comprising a ferroelectric dielectric between a top electrode and a bottom electrode; forming a cell vertical interconnection channel (VIA) on the FeRAM cell; forming a temporary conductive line on the unit VIA; as well as The ferroelectric dielectric is annealed to a ferroelectric phase by directing a flow of electric current through the temporary wire.

2. The method for manufacturing a semiconductor device according to claim 1, wherein the ferroelectric dielectric is formed of hafnium oxide.

3. The method for manufacturing a semiconductor device according to claim 1, further comprising: After annealing the ferroelectric dielectric, the temporary conductive line is removed. 4 . The method for manufacturing a semiconductor device according to claim 1 , wherein the cell VIA and the temporary wiring are simultaneously formed by a dual damascene process.

5. The method for manufacturing a semiconductor device according to claim 1, wherein directing the current flow through the temporary conductive line comprises: A current flow is directed from the temporary conductive line through the cell VIA and into the FeRAM cell. 6 . The method for manufacturing a semiconductor device according to claim 1 , wherein annealing the ferroelectric dielectric comprises crystallizing the ferroelectric dielectric to achieve a ferroelectric phase.

7. The method for manufacturing a semiconductor device according to claim 6, wherein the ferroelectric dielectric reaches the ferroelectric phase when electric polarization of the ferroelectric dielectric is reversible by applying an electric field to the ferroelectric dielectric. 8 . The method for manufacturing a semiconductor device according to claim 3 , wherein removing the temporary wire comprises mechanically grinding away the temporary wire and leaving at least a portion of the unit VIA. 9 . The method for manufacturing a semiconductor device according to claim 1 , wherein directing the flow of current through the temporary conductive line comprises electron-charging the temporary conductive line.

10. A method for manufacturing a semiconductor device, comprising: forming a bottom conductive line over the substrate; forming a bottom heater contact on the bottom conductor; forming a ferroelectric random access memory (FeRAM) cell on the bottom heater contact, the FeRAM cell comprising a ferroelectric dielectric between a top electrode and a bottom electrode; forming a cell vertical interconnection channel (VIA) on the FeRAM cell; forming a temporary conductive line on the unit VIA; as well as The ferroelectric dielectric is annealed to a ferroelectric phase by directing a flow of electric current through the temporary wire.

11. The method for manufacturing a semiconductor device according to claim 10, wherein the ferroelectric dielectric is formed of hafnium oxide.

12. The method for manufacturing a semiconductor device according to claim 10, further comprising: After annealing the ferroelectric dielectric, the temporary conductive line is removed. 13 . The method for manufacturing a semiconductor device according to claim 10 , wherein the cell VIA and the temporary wire are simultaneously formed by a dual damascene process.

14. The method for manufacturing a semiconductor device according to claim 10, wherein: Directing the flow of current through the temporary conductor includes: A current flow is directed from the temporary conductor through the cell VIA and into the FeRAM cell.

15. The method for manufacturing a semiconductor device according to claim 10, wherein annealing the ferroelectric dielectric comprises crystallizing the ferroelectric dielectric to achieve a ferroelectric phase.

16. The method for manufacturing a semiconductor device according to claim 15, wherein the ferroelectric dielectric reaches the ferroelectric phase when electric polarization of the ferroelectric dielectric is reversible by applying an electric field to the ferroelectric dielectric. 17 . The method for manufacturing a semiconductor device according to claim 12 , wherein removing the temporary wire comprises mechanically grinding away the temporary wire and leaving at least a portion of the unit VIA. 18 . The method for manufacturing a semiconductor device according to claim 10 , wherein directing the flow of current through the temporary conductive line comprises electronically charging the temporary conductive line. 19 . The method for manufacturing a semiconductor device according to claim 10 , wherein the FeRAM cell further comprises a resistor on the top electrode.

20. A semiconductor device comprising: bottom heater contacts; a ferroelectric random access memory (FeRAM) cell on the bottom heater contact, the FeRAM cell comprising a hafnium oxide ferroelectric dielectric between a top electrode and a bottom electrode; and A cell vertical interconnection channel (VIA) is provided on the FeRAM cell.

21. The semiconductor of claim 20, wherein the FeRAM cell further comprises a resistor on the top electrode. 22 . The semiconductor device according to claim 21 , wherein the unit VIA directly contacts an upper surface of the resistor.

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