Semiconductor device

Abstract

A novel semiconductor device is provided. A vertical channel transistor is stacked on the capacitor. A ferroelectric is used as the dielectric layer of the capacitor. The ferroelectric preferably contains hafnium, zirconium, or at least one element selected from the group consisting of Group 13 to 15 elements. By using an oxide semiconductor for a semiconductor layer of a vertical channel type transistor, the insulating withstand voltage between a source electrode and a drain electrode is improved, and the channel length can be shortened.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device.

[0002] In addition, one embodiment of the present invention is not limited to the above-mentioned technical field. The technical field of the invention disclosed in this specification, etc. relates to an object, method or manufacturing method. In addition, one embodiment of the present invention relates to a process, machine, product or composition of matter.

[0003] Therefore, as examples of technical fields according to one embodiment of the present invention, there can be cited semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, camera devices, storage devices, signal processing devices, processors, electronic devices, systems, their driving methods, their manufacturing methods, their inspection methods or their usage methods, etc. Background Art

[0004] In recent years, semiconductor devices such as LSI, CPU, memory (storage device) have been developed. These semiconductor devices are used in various electronic devices such as computers and portable information terminals. In addition, various storage methods of memory have been developed according to the purpose of temporary storage during the execution of calculation processing and long-term storage of data. As typical storage methods of memory, DRAM, SRAM and flash memory can be cited.

[0005] In addition, as shown in Non-Patent Document 1, research and development of ferroelectric memory is active. In addition, as the next generation of ferroelectric memory, research on ferroelectric HfO2 materials (Non-Patent Document 2), research on the ferroelectricity of hafnium oxide thin films (Non-Patent Document 3), research on the ferroelectricity of HfO2 thin films (Non-Patent Document 4), and research on the use of ferroelectric HfO2 thin films are also being carried out. 0.5 Zr 0.5 There is also active research on hafnium oxide, such as demonstration of integration of O2 FeRAM (Ferroelectric Random Access Memory) and CMOS (Non-Patent Document 5). [Prior technical literature] [Non-patent literature]

[0006] [Non-patent document 1] TS Boescke, et al., “Ferroelectricity in hafnium oxide thin films”, APL99, 2011 [Non-patent document 2] Zhen Fan, et al, "Ferroelectric HfO2-based materials for next-generation ferroelectric memories", JOURNAL OF ADVANCED DIELECTRICS, Vol.6, No.2, 2016 [Non-patent document 3] Jun Okuno, et al., “SoC compatible 1T1C FeRAM memory arraybased on ferroelectric Hf 0.5 Zr 0.5 O2", VLSI 2020 [Non-patent document 4] Akira Toriumi, "Strong electromagnetic properties of HfO2 thin films", Society for Applied Physics, Volume 88, No. 9, 2019 [Non-patent document 5] T. Francois, et al., "Demonstration of BEOL-compatible ferroelectric Hf 0.5 Zr 0.5 O2 scaled FeRAM co-integrated with 130nm CMOS forembedded NVM applications”, IEDM 2019 Summary of the invention Technical problem to be solved by the invention

[0007] One of the purposes of one embodiment of the present invention is to provide a novel semiconductor device. Another purpose of one embodiment of the present invention is to provide a semiconductor device with a small footprint. Another purpose of one embodiment of the present invention is to provide a semiconductor device with high reliability. Another purpose of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Another purpose of one embodiment of the present invention is to provide a semiconductor device with large storage capacity.

[0008] Note that the purpose of one embodiment of the present invention is not limited to the purposes listed above. The purposes listed above do not prevent the existence of other purposes. Other purposes refer to purposes other than those listed above that will be described in the following description. A person skilled in the art can derive and appropriately extract purposes other than those listed above from the description in the specification or drawings, etc. In addition, one embodiment of the present invention does not need to achieve all of the above-mentioned purposes and other purposes. In addition, one embodiment of the present invention achieves at least one of the above-mentioned purposes and other purposes. Solutions to technical problems

[0009] One embodiment of the present invention is a semiconductor device comprising: a capacitor; and a transistor on the capacitor, wherein the capacitor comprises: a first conductive layer; a first insulating layer on the first conductive layer; and a second conductive layer on the first insulating layer, and the transistor comprises: a second insulating layer on the second conductive layer; a third conductive layer on the second insulating layer; openings provided in the second insulating layer and the third conductive layer; a semiconductor layer covering the openings; a third insulating layer on the semiconductor layer; and a fourth conductive layer on the third insulating layer, wherein the opening overlaps with the second conductive layer, and the first insulating layer has a ferroelectric.

[0010] Another embodiment of the present invention is a semiconductor device, comprising: a plurality of stacked layers; and a first electrode passing through the plurality of layers, wherein the plurality of layers each include: a capacitor; and a transistor on the capacitor, the capacitor including: a first conductive layer; a first insulating layer on the first conductive layer; and a second conductive layer on the first insulating layer, the transistor including: a second insulating layer on the second conductive layer; a third conductive layer on the second insulating layer; openings provided in the second insulating layer and the third conductive layer; a semiconductor layer covering the openings; a third insulating layer on the semiconductor layer; and a fourth conductive layer on the third insulating layer, the opening overlapping the second conductive layer, the first insulating layer having a ferroelectric, and the third conductive layer being electrically connected to the first electrode.

[0011] The angle formed by the side surface of the second insulating layer in the opening and the bottom surface of the second insulating layer is preferably not less than 45 degrees and not more than 90 degrees.

[0012] In addition, it is preferable that the semiconductor device is stored and maintained at an ambient temperature of 150° C. for 10 days or more.

[0013] The second insulating layer may also include a fourth insulating layer, a fifth insulating layer on the fourth insulating layer, and a sixth insulating layer on the fifth insulating layer. For example, the fourth insulating layer and the sixth insulating layer may also both contain nitrogen and silicon. For example, the fifth insulating layer may also contain oxygen and silicon. In addition, the fourth insulating layer and the sixth insulating layer may also both contain hydrogen.

[0014] For example, an oxide semiconductor may be used as the semiconductor layer. The semiconductor layer preferably contains at least one of indium and zinc and oxygen. The first electrode may also contain a plurality of conductive layers. The first insulating layer preferably contains hafnium, zirconium and oxygen. The first conductive layer and the second conductive layer preferably contain titanium and nitrogen. Effects of the Invention

[0015] According to one embodiment of the present invention, a novel semiconductor device can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with a small footprint can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with high reliability can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with large storage capacity can be provided.

[0016] Note that the effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not prevent the existence of other effects. Therefore, one embodiment of the present invention sometimes does not have the effects listed above. Other effects refer to effects other than those described above that will be described in the following description. A person of ordinary skill in the art can derive and appropriately extract effects other than those described above from the description in the specification or drawings, etc. In addition, one embodiment of the present invention has at least one of the effects listed above and other effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1A and Figure 1B is a diagram showing a structural example of a semiconductor device. Figure 1C and Figure 1D It is an equivalent circuit diagram of a semiconductor device. FIG. 2A to FIG. 2C is a diagram showing a structural example of a semiconductor device. FIG. 3A to FIG. 3E is a diagram showing a structural example of a semiconductor device. Figure 4A and Figure 4B is a diagram showing a structural example of a semiconductor device. Figure 5A and Figure 5B is a diagram showing a structural example of a semiconductor device. FIG. 6A to FIG. 6C is a diagram showing a structural example of a semiconductor device. 7A to 7C is a diagram showing a structural example of a semiconductor device. FIG. 8A to FIG. 8C is a diagram showing a structural example of a semiconductor device. Fig.9A and Fig. 9B is a diagram showing a structural example of a semiconductor device. Fig. 9C It is an equivalent circuit diagram of a semiconductor device. Fig.10 is a diagram showing a structural example of a semiconductor device. Fig.11 It is an equivalent circuit diagram of a semiconductor device. Fig.12 is a diagram showing a structural example of a semiconductor device. Fig.13 It is an equivalent circuit diagram of a semiconductor device. Fig.14A A diagram illustrating an example of a circuit configuration of a memory cell. Fig. 14B is a graph showing an example of hysteresis characteristics. Fig. 14C is a timing chart showing an example of a driving method of a memory cell. FIG. 15A to FIG. 15C is a diagram showing a configuration example of a storage device. Fig.16A is a diagram showing a configuration example of a storage device. Fig. 16B is a schematic diagram showing a storage string included in a storage device. Fig.17A is a diagram showing a configuration example of a storage device. Fig. 17B is a schematic diagram of a storage string included in a storage device. Fig.18 is a diagram showing an example of a cross-sectional structure of a storage device. Fig.19A and Fig.19B FIG. 1 is a schematic diagram of a semiconductor device according to one embodiment of the present invention. Fig. 20A and Fig. 20B It is a perspective view showing an example of an electronic component. FIG. 21A to FIG. 21J It is a diagram for explaining an example of an electronic device. FIG. 22A to FIG. 22E It is a diagram for explaining an example of an electronic device. FIG. 23A to FIG. 23C It is a diagram for explaining an example of an electronic device. Fig.24 is a diagram showing an example of space equipment. Modes for Carrying Out the Invention

[0018] The following describes the embodiments with reference to the accompanying drawings. However, a person skilled in the art can easily understand that the embodiments can be implemented in a plurality of different forms, and the methods and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the embodiments shown below.

[0019] In this specification, etc., a semiconductor device refers to a device that utilizes semiconductor characteristics and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.) and a device having the circuit. In addition, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. For example, as examples of semiconductor devices, there are integrated circuits, chips with integrated circuits, and electronic components that contain chips in packages. In addition, storage devices, display devices, light-emitting devices, lighting devices, and electronic devices themselves are semiconductor devices, and sometimes include semiconductor devices.

[0020] In the drawings and the like according to this specification, the size, thickness of the layer or the area are sometimes exaggerated for the sake of clarity. Therefore, the present invention is not limited to the size or aspect ratio in the drawings. In addition, in the drawings, ideal examples are schematically shown, so the present invention is not limited to the shapes or numerical values ​​shown in the drawings.

[0021] Note that in the structure of the invention in the embodiment, the same reference numerals are sometimes used in common in different drawings to indicate the same part or part having the same function, and repeated description is omitted. In addition, when indicating parts having the same function, the same hatching is sometimes used without adding a reference numeral. In a stereogram or a top view, for the sake of clarity, the illustration of some constituent elements is sometimes omitted.

[0022] Note that arrows indicating the X direction (the direction along the X axis), the Y direction (the direction along the Y axis), and the Z direction (the direction along the Z axis) are sometimes attached in the drawings, etc. Note that in this specification, etc., the "X direction" refers to the direction along the X axis, and sometimes the forward and reverse directions are not distinguished except for the cases clearly stated. The same is true for the "Y direction" and the "Z direction". In addition, the X direction, the Y direction, and the Z direction are directions that intersect each other. More specifically, the X direction, the Y direction, and the Z direction are directions that are orthogonal to each other. In this specification, etc., sometimes one of the X direction, the Y direction, and the Z direction is referred to as the "first direction". In addition, sometimes the other one is referred to as the "second direction". In addition, sometimes the remaining one is referred to as the "third direction".

[0023] In this specification, etc., ordinal numbers such as "first", "second", and "third" are added to avoid confusion among constituent elements. Therefore, the ordinal numbers do not limit the number of constituent elements. In addition, the ordinal numbers do not limit the order of the constituent elements. For example, a constituent element with "first" in one of the embodiments of this specification, etc. may be attached with "second" in other embodiments or claims, etc. In addition, for example, a constituent element with "first" in one of the embodiments of this specification, etc. may be omitted in other embodiments or claims, etc.

[0024] In this specification, etc., for the sake of convenience, words and phrases indicating configurations such as "upper", "lower", "above" or "below" are sometimes used to explain the positional relationship of constituent elements with reference to the drawings. In addition, the positional relationship of constituent elements is appropriately changed according to the direction in which each structure is described. Therefore, the words and phrases described in the specification, etc. are not limited, and the words and phrases can be appropriately replaced according to the situation. For example, if it is an expression of "an insulator located on the top surface of a conductor", by rotating the direction of the illustrated drawing by 180 degrees, it can be replaced with "an insulator located below the conductor".

[0025] In addition, the words "above" and "below" are not limited to the case where the positional relationship of the components is "directly above" or "directly below" and in direct contact. For example, if it is an expression "electrode B on insulating layer A", it is not necessarily necessary that electrode B is formed on insulating layer A in direct contact, and the case where other components are included between insulating layer A and electrode B may also be included.

[0026] In this specification, etc., the words "overlap" and the like do not limit the state of the stacking order of the constituent elements. For example, "electrode B overlapping with insulating layer A" is not limited to the state where electrode B is formed on insulating layer A, but also includes the state where electrode B is formed under insulating layer A or the state where electrode B is formed on the right side (or left side) of insulating layer A, etc.

[0027] In this specification, the words "adjacent" and "close to" do not limit the state of direct contact between components. For example, if it is an expression "electrode B adjacent to insulating layer A", it does not necessarily mean that insulating layer A and electrode B are in direct contact, and it may also include the case where other components are included between insulating layer A and electrode B.

[0028] In addition, in this specification, etc., depending on the situation, the words "film" and "layer" can be interchanged with each other. For example, "conductive layer" can sometimes be replaced with "conductive film". In addition, "insulating film" can sometimes be replaced with "insulating layer". In addition, depending on the situation or state, other words can be used instead of words "film" and "layer". For example, "conductive layer" or "conductive film" can sometimes be replaced with "conductive body". In addition, "conductive body" can sometimes be replaced with "conductive layer" or "conductive film". In addition, for example, "insulating layer" or "insulating film" can sometimes be replaced with "insulator". In addition, "insulator" can sometimes be replaced with "insulating layer" or "insulating film".

[0029] Note that voltage refers to the difference between the potentials of two points, while potential refers to the electrostatic energy (potential energy) of a unit charge in an electrostatic field at a certain point. Note that, in general, the potential difference between the potential of a certain point and a standard potential (such as ground potential) is referred to as potential or voltage, and potential and voltage are synonymous in many cases. Therefore, in this specification, "potential" may be referred to as "voltage", and "voltage" may be referred to as "potential", except for special cases.

[0030] Note that in this specification, etc., the words "electrode", "wiring", "terminal", etc. do not functionally limit their constituent elements. For example, sometimes an "electrode" is used as a part of a "wiring", and vice versa. Furthermore, "electrode" or "wiring" also includes a case where a plurality of "electrodes" or "wiring" are formed as one, etc. In addition, for example, sometimes a "terminal" is used as a part of a "wiring" or "electrode", and vice versa. Furthermore, the word "terminal" includes a case where a plurality of "electrodes", "wiring", "terminals", etc. are formed as one, etc. Therefore, for example, an "electrode" can be a part of a "wiring" or a "terminal", for example, a "terminal" can be a part of a "wiring" or an "electrode". In addition, the words "electrode", "wiring", "terminal", etc. are sometimes replaced with words such as "region".

[0031] In this specification, etc., depending on the situation or state, the words "wiring", "signal line" and "power line" can be interchanged with each other. For example, "wiring" can sometimes be interchanged with "signal line". In addition, for example, "wiring" can sometimes be interchanged with "power line", etc. Vice versa, "signal line" or "power line" can sometimes be interchanged with "wiring". "Power line" etc. can sometimes be interchanged with "signal line", etc. Vice versa, "signal line" etc. can sometimes be interchanged with "power line", etc. In addition, depending on the situation or state, the "potential" applied to the wiring can be interchanged with "signal". Vice versa, "signal" can sometimes be interchanged with "potential".

[0032] In this specification, etc., "capacitor" can be, for example, a circuit element having an electrostatic capacitance value higher than 0F, a region of wiring having an electrostatic capacitance value higher than 0F, a parasitic capacitance, or a gate capacitance of a transistor. In addition, "capacitor", "parasitic capacitance" or "gate capacitance" can sometimes be replaced by "capacitor". In contrast, "capacitor" can sometimes be replaced by "capacitor", "parasitic capacitance" or "gate capacitance". In addition, "capacitor" (including "capacitor" with more than three terminals) has a structure including an insulator and a pair of conductors sandwiching the insulator. Therefore, the "pair of conductors" of "capacitor" can be replaced by "a pair of electrodes", "a pair of conductive areas", "a pair of areas" or "a pair of terminals". In addition, sometimes "one of a pair of terminals" is referred to as "a terminal" or "a first terminal". In addition, sometimes "the other of a pair of terminals" is referred to as "another terminal" or "a second terminal". The electrostatic capacitance value can be, for example, more than 0.05fF and less than 10pF. In addition, for example, it can also be more than 1pF and less than 10μF.

[0033] In addition, when using transistors with different polarities or when the current direction of the circuit operation changes, the functions of the "source" and "drain" of the transistor are sometimes interchanged. Therefore, in this specification, etc., "source" and "drain" can be interchanged.

[0034] In this specification, "gate" refers to a part or all of a gate electrode and a gate wiring. A gate wiring is a wiring for electrically connecting a gate electrode of at least one transistor to another electrode or another wiring.

[0035] In this specification, etc., "source" refers to a part or all of a source region, a source electrode, and a source wiring. A source region refers to a region in a semiconductor layer whose resistivity is less than a certain value. A source electrode refers to a conductive layer including a portion connected to a source region. A source wiring refers to wiring for electrically connecting a source electrode of at least one transistor to other electrodes or other wiring.

[0036] In this specification, etc., "drain" refers to a part or all of a drain region, a drain electrode, and a drain wiring. The drain region refers to a region in a semiconductor layer whose resistivity is less than a certain value. The drain electrode refers to a conductive layer including a portion connected to the drain region. The drain wiring refers to a wiring used to electrically connect the drain electrode of at least one transistor to other electrodes or other wirings.

[0037] In addition, unless otherwise specified, the transistors shown in this specification, etc. are enhancement-type (normally closed) field-effect transistors. In addition, when the transistors shown in this specification, etc. are n-channel transistors and there is no special description, the threshold voltage (also referred to as "Vth") of the transistor is greater than 0V. In addition, when the transistors shown in this specification, etc. are p-channel transistors and there is no special description, the threshold voltage (also referred to as "Vth") of the transistor is less than 0V. In addition, when there is no special description, the Vth of multiple transistors of the same conductivity type are equal.

[0038] In addition, in this specification, etc., unless otherwise specified, the off-state current refers to the current ("drain current" or "Id") flowing between the source and the drain when the transistor is in the off state (also called "non-conducting state" or "blocking state"). Unless otherwise specified, in an n-channel transistor, the off state refers to a state in which the potential difference between the gate and the source (also called "gate voltage" or "Vg") with respect to the source is lower than the threshold voltage, and in a p-channel transistor, the off state refers to a state in which Vg is higher than the threshold voltage. For example, sometimes the off-state current of an n-channel transistor refers to the drain current when Vg is lower than Vth.

[0039] In this specification, the off-state current may be referred to as leakage current. In this specification, the off-state current may refer to, for example, current flowing between a source and a drain when a transistor is in an off state.

[0040] In this specification, etc., unless otherwise specified, the on-state current refers to the Id when the transistor is in the on state (also referred to as the "on state"). Unless otherwise specified, the on state in an n-channel transistor refers to a state where Vg is greater than Vth, and the on state in a p-channel transistor refers to a state where Vg is less than Vth. For example, the on-state current of an n-channel transistor sometimes refers to the drain current when Vg is greater than Vth.

[0041] In this specification, etc., "parallel" refers to a state where the angle formed by two straight lines is greater than -10 degrees and less than 10 degrees. Therefore, a state where the angle is greater than -5 degrees and less than 5 degrees is also included. "Approximately parallel" refers to a state where the angle formed by two straight lines is greater than -30 degrees and less than 30 degrees. In addition, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80 degrees and less than 100 degrees. Therefore, a state where the angle is greater than 85 degrees and less than 95 degrees is also included. In addition, "approximately perpendicular" refers to a state where the angle formed by two straight lines is greater than 60 degrees and less than 120 degrees.

[0042] In this specification, etc., unless otherwise stated, the case where count values ​​or measurement values ​​are "same", "identical", "equal", or "uniform" (including synonyms of these words) includes a variation of ±20% as an error.

[0043] In this specification, when the same symbol is used for a plurality of components and it is necessary to distinguish them, a symbol such as "A", "b", "-1", "[n]", "[m, n]" is sometimes added to the symbol for identification. For example, the conductive layer 242 is sometimes divided into the conductive layer 242a and the conductive layer 242b for illustration.

[0044] (Implementation Method 1) A semiconductor device 10A according to one embodiment of the present invention will be described. The semiconductor device 10A includes a capacitor 110 and a transistor 100 on the capacitor 110 . Figure 1A It is a top view of the semiconductor device 10A. Figure 1B From the Y direction Figure 1A The cross-sectional view of the portion indicated by the dot-dash line A1-A2 in FIG. Figure 1A In the top view, some components are omitted for clarity.

[0045] Figure 1C and Figure 1D is an equivalent circuit diagram of the semiconductor device 10A. Figure 1C and Figure 1D In the embodiment, one of the source and the drain of the transistor 100 is electrically connected to the wiring BL, and the other is electrically connected to one electrode of the capacitor 110. The gate of the transistor 100 is electrically connected to the wiring WL. In addition, the other electrode of the capacitor 110 is electrically connected to the wiring PL. The semiconductor device 10A is used as a memory circuit (also referred to as a "memory element" or a "memory cell").

[0046] Figure 1C and Figure 1D These are an equivalent circuit diagram when the capacitor 110 has a ferroelectric and an equivalent circuit diagram when the capacitor 110 does not have a ferroelectric.

[0047] in addition, Figure 2A From the X direction Figure 1A A cross-sectional view of the portion indicated by the dot-dash line A3-A4 in FIG. Figure 2B It is enlarged and viewed from the Z direction Figure 2A FIG. 1 is a cross-sectional view of the portion indicated by the dashed line B1-B2. Figure 2C It is enlarged and viewed from the Z direction Figure 2A FIG. 5 is a diagram of a cross section of a portion indicated by a dashed line B3-B4.

[0048] A semiconductor device 10A according to one embodiment of the present invention includes an insulating layer 153 and a conductive layer 151 and a conductive layer 152 formed in a manner embedded in the insulating layer 153. The conductive layer 151 and the conductive layer 152 can be formed simultaneously using the same material and the same manufacturing process. In addition, it is preferred to make the positions (positions in the Z direction) of the top surfaces of the insulating layer 153, the conductive layer 151, and the conductive layer 152 consistent or approximately consistent by using a chemical mechanical polishing (CMP) method or the like. By performing CMP treatment, the unevenness of the sample surface can be reduced, thereby improving the coverage of the insulating layer and the conductive layer to be formed later.

[0049] In addition, an insulating layer 154 is provided over the insulating layer 153, the conductive layer 151, and the conductive layer 152, and a conductive layer 155 is provided over the insulating layer 154. The conductive layer 151 and the conductive layer 155 have a region overlapping with each other with the insulating layer 154 interposed therebetween.

[0050] In addition, the semiconductor device 10A includes an insulating layer 157 on the insulating layer 154 and the conductive layer 155, an insulating layer 158 on the insulating layer 157, and an insulating layer 159 on the insulating layer 158. The insulating layer 157, the insulating layer 158, and the insulating layer 159 are sometimes collectively referred to as an insulating layer 156 or a spacer. In addition, a conductive layer 161 is included on the insulating layer 159.

[0051] In a region overlapping with a portion of the conductive layer 155, the conductive layer 161, the insulating layer 159, the insulating layer 158, and the insulating layer 157, an opening 162 is provided (see Figure 1B and Figure 2A ). The semiconductor device 10A includes a semiconductor layer 163 covering the opening 162. In addition, the semiconductor layer 163 has a region overlapping with the bottom of the opening 162 and a region overlapping with the side of the opening 162. That is, the semiconductor layer 163 has a region in contact with the insulating layer 156. Figure 1B In the embodiment, the semiconductor layer 163 has a region in contact with a side surface of the insulating layer 157 , a region in contact with a side surface of the insulating layer 158 , and a region in contact with a side surface of the insulating layer 159 .

[0052] In addition, the semiconductor layer 163 has a region in contact with the conductive layer 155 and a region in contact with the conductive layer 161. That is, a portion of the semiconductor layer 163 is electrically connected to the conductive layer 155, and another portion of the semiconductor layer 163 is electrically connected to the conductive layer 161. In addition, the semiconductor layer 163 may have a region extending beyond the end of the conductive layer 161 (see Figure 1A and Figure 2A ).

[0053] In addition, an insulating layer 164 is provided over the insulating layer 159, the conductive layer 161, and the semiconductor layer 163. In addition, a conductive layer 165 is provided over the insulating layer 164. The conductive layer 165 has a region overlapping with the opening 162, and in this region, has a region overlapping with the side and bottom of the opening 162 via the insulating layer 164 and the semiconductor layer 163 (see Figure 1B , Figure 2A , Figure 2B and Figure 2C ).

[0054] The thickness of the semiconductor layer 163 is preferably 1 nm or more, 3 nm or more, or 5 nm or more and 20 nm or less, 15 nm or less, 12 nm or less, or 10 nm or less. The thickness of the insulating layer 164 is preferably 0.5 nm or more and 15 nm or less, more preferably 0.5 nm or more and 12 nm or less, and further preferably 0.5 nm or more and 10 nm or less. At least a portion of the insulating layer 164 may be a region having the above thickness.

[0055] In addition, an insulating layer 166 is included on the insulating layer 164. It is preferable that the top surface positions (positions in the Z direction) of the conductive layer 165 and the insulating layer 166 are aligned or substantially aligned. For example, by performing a CMP process or the like to make the top surface positions (positions in the Z direction) of the conductive layer 165 and the insulating layer 166 aligned or substantially aligned, the coverage of the insulating layer and the conductive layer to be formed later can be improved.

[0056] In addition, an insulating layer 167 is included over the conductive layer 165 and the insulating layer 166. In addition, a conductive layer 168 embedded in the insulating layer 167, the insulating layer 166, the insulating layer 164, the conductive layer 161, the insulating layer 159, the insulating layer 158, the insulating layer 157, and a portion of the insulating layer 154 is included in a region overlapping with the conductive layer 152. The conductive layer 168 is electrically connected to the conductive layer 161 and the conductive layer 152. The conductive layer 168 and the conductive layer 152 function as a contact plug.

[0057] In addition, conductive layer 155 serves as one electrode of capacitor 110. Conductive layer 151 serves as the other electrode of capacitor 110. A region of insulating layer 154 that overlaps conductive layer 155 and conductive layer 151 serves as a dielectric of capacitor 110.

[0058] Conductive layer 165 and conductive layer 151 both extend in the Y direction. Conductive layer 165 is used as wiring WL or a part of wiring WL, and conductive layer 151 is used as wiring PL or a part of wiring PL. Also, conductive layer 168 and conductive layer 152 are used as wiring BL or a part of wiring BL.

[0059] In the semiconductor device 10A according to one embodiment of the present invention, a transistor 100 and a capacitor 110 are provided in an overlapping manner. By providing the transistor 100 and the capacitor 110 in an overlapping manner, the occupied area of ​​the semiconductor device 10A can be reduced.

[0060] <Transistor 100> The conductive layer 161 is used as one of the source electrode and the drain electrode of the transistor 100. In addition, the conductive layer 155 is used as the other of the source electrode and the drain electrode of the transistor 100. For example, when the conductive layer 161 is used as the drain electrode of the transistor 100, the conductive layer 155 is used as the source electrode of the transistor 100. It can also be said that the conductive layer 161 is used as the wiring BL or a part of the wiring BL.

[0061] The semiconductor layer 163 is used as a semiconductor layer (a semiconductor layer including a channel formation region) for forming a channel of the transistor 100 , the insulating layer 164 is used as a gate insulating layer, and the conductive layer 165 is used as a gate electrode. Therefore, it can be said that the transistor 100 is provided in a region including the opening 162 .

[0062] In transistor 100, the source electrode and the drain electrode are arranged in the Z direction. That is, the source and the drain of transistor 100 are arranged at different heights. In other words, the source and the drain of transistor 100 are arranged at different positions in the Z direction. This transistor is also called a "vertical channel transistor", "vertical channel transistor", "vertical transistor" or "VFET (Vertical Field Effect Transistor)".

[0063] In a vertical channel transistor according to one embodiment of the present invention, the source electrode and the drain electrode are arranged in the Z direction. That is, the channel formation region, the source region, and the drain region are arranged in the Z direction. When a vertical transistor is used, the occupied area of ​​the transistor 100 can be reduced compared to a conventional transistor in which the channel formation region, the source region, and the drain region are separately provided on the XY plane.

[0064] In addition, by using a vertical channel transistor in a semiconductor device, the occupied area of ​​the semiconductor device can be reduced. By using a vertical channel transistor in a semiconductor device, high integration of the semiconductor device can be achieved. In addition, the storage capacity per unit area of ​​a storage device using the semiconductor device can be increased.

[0065] In addition, the channel length of the existing transistor is set according to the exposure limit of the photolithography method. A vertical channel transistor according to one embodiment of the present invention can set the channel length according to the thickness of the insulating layer 156 or the insulating layer 158. Therefore, the channel length of the transistor 100 can be set to a very fine structure below the exposure limit of the photolithography method (for example, less than 60nm, less than 50nm, less than 40nm, less than 30nm, less than 20nm or less than 10nm and more than 1nm or more than 5nm). As a result, the on-state current of the transistor 100 is increased, and the frequency characteristics can be improved. By using a vertical channel transistor, a semiconductor device with a high operating speed can be provided.

[0066] The channel length L, channel width W, etc. of the transistor 100 will be described in detail later.

[0067] <Capacitor 110> The region where the conductive layer 151 and the conductive layer 155 overlap each other via the insulating layer 154 is used as a capacitor 110. A ferroelectric is preferably used as the insulating layer 154. Ferroelectrics have the property that polarization occurs internally when an electric field is applied from the outside and polarization remains even when the electric field is reduced to 0. Therefore, by using a capacitor using this material as a dielectric (also called a ferroelectric capacitor), a nonvolatile memory element can be formed.

[0068] When capacitor 110 is used as a ferroelectric capacitor, conductive layer 151 and conductive layer 155 in contact with ferroelectric insulating layer 154 are preferably made of a material that easily polarizes insulating layer 154. For example, conductive layer 151 and conductive layer 155 are preferably made of titanium nitride.

[0069] A nonvolatile memory element using a ferroelectric capacitor is sometimes referred to as "FeRAM" or "ferroelectric memory", etc. Materials that can have ferroelectricity will be described in detail later.

[0070] In addition, a material with a high relative dielectric constant (also referred to as a "high-k material") may be used for the insulating layer 154. By using a high-k material as the insulating layer 154, the electrostatic capacitance required for the capacitor 110 can be ensured and the thickness of the insulating layer 154 can be increased. By thickening the insulating layer 154, the dielectric withstand voltage between the conductive layer 151 and the conductive layer 155 is improved and electrostatic breakdown is suppressed. Therefore, the reliability of the capacitor 110 is improved. As a result, the reliability of the semiconductor device using the capacitor 110 is improved.

[0071] <Materials Constituting Semiconductor Devices> An example of a material that can be used for the semiconductor device 10A according to one embodiment of the present invention will be described.

[0072] [Substrate] When the semiconductor device 10A is disposed on a substrate, there is no particular restriction on the material used for the substrate. The material can be determined based on the purpose, such as whether it is necessary to have light transmittance and heat resistance to withstand heat treatment. As the substrate, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used. As the insulating substrate, for example, a glass substrate such as barium borosilicate glass and aluminoborosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (yttria stabilized zirconia substrate, etc.) can be used. In addition, a semiconductor substrate, a flexible substrate, a resin substrate, etc. can also be used.

[0073] For example, as the semiconductor substrate, there can be cited a semiconductor substrate composed of silicon or germanium, or a compound semiconductor substrate using silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, etc. as its material. In addition, there can also be cited a semiconductor substrate having an insulator region inside the above semiconductor substrate, such as an SOI (Silicon On Insulator) substrate, etc. In addition, the semiconductor substrate can be a single crystal semiconductor or a polycrystalline semiconductor.

[0074] Examples of the conductive substrate include graphite substrates, metal substrates, alloy substrates, conductive resin substrates, etc. Alternatively, examples include substrates containing metal nitrides, substrates containing metal oxides, etc. In addition, examples include insulator substrates provided with a conductor or a semiconductor, semiconductor substrates provided with a conductor or an insulator, and conductive substrates provided with a semiconductor or an insulator.

[0075] As materials for flexible substrates or resin substrates, for example, the following materials can be used: polyester resins such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile resins, acrylic resins, polyimide resins, polymethyl methacrylate resins, polycarbonate (PC) resins, polyether sulfone (PES) resins, polyamide resins (nylon, aromatic polyamide, etc.), polysiloxane resins, cycloolefin resins, polystyrene resins, polyamide-imide resins, polyurethane resins, polyvinyl chloride resins, polyvinylidene chloride resins, polypropylene resins, polytetrafluoroethylene (PTFE) resins, ABS resins, and cellulose nanofibers, etc.

[0076] By using the above materials as the substrate, a lightweight semiconductor device including the transistor 100 can be provided. Also, by using the above materials as the substrate, a semiconductor device with high impact resistance can be provided. Also, by using the above materials as the substrate, a semiconductor device that is not easily damaged can be provided.

[0077] Alternatively, a substrate having an element provided over these substrates may be used. Examples of the element provided over the substrate include a capacitor, a resistor, a switching element, a light emitting element, and a memory element.

[0078] [Insulation layer] As the insulating layer, insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, metal oxynitrides, etc. can be used. For example, as the insulating layer, a single layer or a stack of insulating materials selected from the following can be used: aluminum nitride, aluminum oxide, aluminum nitride oxide, aluminum oxynitride, magnesium oxide, silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, aluminum silicate, etc. In addition, a material obtained by mixing multiple types of oxide materials, nitride materials, oxynitride materials, and nitride oxide materials can also be used.

[0079] In this specification, etc., nitrogen oxide refers to a material containing more nitrogen than oxygen. In addition, oxynitride refers to a material containing more oxygen than nitrogen. In addition, for example, the content of each element can be measured using Rutherford Backscattering Spectrometry (RBS).

[0080] When miniaturization and high integration of transistors are carried out, problems such as leakage current sometimes occur due to the thin film of the gate insulating layer. By using a high-k material (a high dielectric constant material. A material with a high relative dielectric constant) as an insulating layer used as a gate insulating layer, the gate potential of the transistor can be reduced while maintaining the physical thickness. In addition, materials with high dielectric constants such as lead zirconate titanate (PZT), strontium titanate (SrTiO3), (Ba, Sr)TiO3 (BST) can sometimes be used as an insulating layer. On the other hand, by using a material with a low relative dielectric constant for an insulating layer used as an interlayer film, the parasitic capacitance generated between the wirings can be reduced. Therefore, it is preferable to select the material according to the function required of the insulating layer.

[0081] In addition, as materials with a high relative dielectric constant, there are gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0082] In addition, as materials with a relatively low dielectric constant, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having pores, or resins can be cited.

[0083] The method for forming the insulating material is not particularly limited, and various formation methods such as vapor deposition, ALD, CVD, sputtering, and spin coating can be used.

[0084] In particular, the insulating layer 153 and the insulating layer 167 are preferably formed using an insulating material that is not easily permeable to impurities. For example, a single layer or a stack of insulating materials containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used. For example, as an example of an insulating material that is not easily permeable to impurities, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, silicon nitride, etc. can be cited.

[0085] By using an insulating material that does not easily allow impurities to pass through as the insulating layer 153, diffusion of impurities from below the insulating layer 153 can be suppressed, and the reliability of the transistor 100 can be improved. In other words, the reliability of the semiconductor device including the transistor 100 can be improved. By using an insulating material that does not easily allow impurities to pass through as the insulating layer 167, diffusion of impurities from above the insulating layer 167 can be suppressed, and the reliability of the transistor 100 can be improved. In other words, the reliability of the semiconductor device including the transistor 100 can be improved.

[0086] In addition, as the insulating layer, an insulating layer used as a planarization layer can also be used. As the material used as the planarization layer, acrylic resin, polyimide, epoxy resin, polyamide, polyimide amide, siloxane resin, benzocyclobutene resin, phenolic resin and precursors of these resins can be cited. In addition, in addition to the above-mentioned organic materials, low-k materials (low dielectric constant materials. Materials with a small relative dielectric constant.), siloxane resins, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can also be used. In addition, multiple insulating layers formed of these materials can also be stacked.

[0087] Siloxane resin is equivalent to a resin containing Si-O-Si bonds formed from a siloxane material as a starting material. Siloxane resin can also use an organic group (such as an alkyl group or an aryl group) or a fluoro group as a substituent. In addition, the organic group can also have a fluoro group.

[0088] In addition, a three-layer insulating layer (also called "ZAZ") of aluminum oxide sandwiched between two layers of zirconium oxide may be used as the insulating layer 154 serving as the dielectric of the capacitor 110. ZAZ is a material with a high relative dielectric constant, and by using ZAZ as the dielectric of the capacitor 110, the occupied area of ​​the capacitor 110 can be reduced.

[0089] As described above, it is preferable to use a material having ferroelectricity as the insulating layer 154 and use the capacitor 110 as a ferroelectric capacitor.

[0090] As a material having ferroelectricity, for example, hafnium oxide is preferably used. Alternatively, zirconium oxide, HfZrO X (X is a real number greater than 0. Hereinafter, it is also referred to as "HfZrOx") and other metal oxides. Alternatively, as a material that can have ferroelectricity, a material in which an element J1 is added to hafnium oxide (here, the element J1 is one or more selected from zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) can be used.

[0091] Here, the atomic ratio of hafnium atoms to element J1 can be appropriately set. For example, the atomic ratio of hafnium atoms to zirconium atoms can be set to 1:1 or thereabouts. Alternatively, as a material that can have ferroelectricity, a material in which element J2 is added to zirconium oxide (here, element J2 is one or more selected from hafnium (Hf), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) can be used. In addition, the atomic ratio of zirconium atoms to element J2 can be appropriately set. For example, the atomic ratio of zirconium atoms to element J2 can be set to 1:1 or thereabouts. In addition, as a material that can have ferroelectricity, lead titanate (PbTiO X ), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), barium titanate and other piezoelectric ceramics with perovskite structure.

[0092] In addition, as a material that can have ferroelectricity, aluminum scandium nitride (Al 1-a Sc a N b(a is a real number greater than 0 and less than 0.5, and b is a value of 1 or its vicinity. It is hereinafter referred to as AlScN)), Al-Ga-Sc nitride, Ga-Sc nitride, etc. In addition, as a material that can have ferroelectricity, a metal nitride containing an element M1, an element M2, and nitrogen can be used. Here, the element M1 is one or more selected from aluminum (Al), gallium (Ga), indium (In), etc. In addition, the element M2 is one or more selected from boron (B), scandium (Sc), yttrium (Y), lanthanide elements (lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb) and lutetium (Lu)), actinide elements (fifteen elements from actinium (Ac) to lawrencium (Lr)), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), etc. In addition, the atomic ratio of the element M1 to the element M2 can be appropriately set. In addition, a metal oxide containing the element M1 and nitrogen sometimes has ferroelectricity even if it does not contain the element M2. In addition, as a material that can have ferroelectricity, a material obtained by adding element M3 to the above-mentioned metal nitride can be used. Note that element M3 is one or more selected from magnesium (Mg), calcium (Ca), strontium (Sr), zinc (Zn), cadmium (Cd), etc. Here, the atomic ratio of element M1, element M2 and element M3 can be appropriately set. Note that since the above-mentioned metal nitride contains at least nitrogen of group 13 elements and group 15 elements, the metal nitride is sometimes referred to as group 13-group 15 ferroelectric, group 13 nitride ferroelectric, etc.

[0093] In addition, as a material that can have ferroelectricity, perovskite-type oxynitrides such as SrTaO2N and BaTaO2N, GaFeO3 of κ-type alumina, etc. can be used.

[0094] In addition, as a material that can have ferroelectricity, for example, a mixture or compound composed of a plurality of materials selected from the above materials can be used. In addition, the material that can have ferroelectricity can have a stacked structure composed of a plurality of materials selected from the above materials. In addition, the crystal structure or characteristics of the materials listed above may change not only due to deposition conditions but also due to various processes, so in this specification, etc., the material that exhibits ferroelectricity is not only called a ferroelectric but also called a material that can have ferroelectricity or a material that has ferroelectricity.

[0095] As a material having ferroelectricity, a material containing hafnium oxide or a material containing hafnium oxide and zirconium oxide (typically HfZrOx) is preferably used because these materials can have ferroelectricity even when processed into a thin film of several nm.

[0096] Here, the thickness of the insulating layer 154 is preferably 100 nm or less, more preferably 50 nm or less, further preferably 20 nm or less, and further preferably 10 nm or less (typically, 2 nm or more and 9 nm or less). For example, the thickness of the insulating layer 154 is preferably 8 nm or more and 12 nm or less.

[0097] Alternatively, as a material that can have ferroelectricity, aluminum scandium nitride (AlScN) is preferably used because it can be formed by sputtering to reduce the impurity concentration in the film or form a dense film. When aluminum scandium nitride (AlScN) is used as a material that can have ferroelectricity, it is expected that a film with high reliability can be formed.

[0098] In addition, the thickness of the material having ferroelectricity can be less than 100nm, preferably less than 50nm, more preferably less than 20nm, and further preferably less than 10nm (typically, more than 2nm and less than 9nm). For example, the thickness is preferably more than 8nm and less than 12nm. By setting the thickness of the material having ferroelectricity to the above thickness, thin filmization and ferroelectricity can be achieved. By thin filmization, the ferroelectric layer can be sandwiched between a pair of electrodes of a capacitor, and the capacitor can be combined with semiconductor elements such as miniaturized transistors to form a semiconductor device. In other words, a semiconductor device with a reduced occupied area can be easily realized.

[0099] In addition, in this specification, etc., a material that can have ferroelectricity is sometimes referred to as a ferroelectric material. In addition, in this specification, etc., a material that can have ferroelectricity formed into a layer is sometimes referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. In addition, in this specification, etc., a device including a ferroelectric layer, a metal oxide film, or a metal nitride film is sometimes referred to as a "ferroelectric device."

[0100] In addition, when HfZrOx is used as a material that can have ferroelectricity, it is preferably deposited using an ALD method, especially a thermal ALD method. In addition, when a material that can have ferroelectricity is deposited by a thermal ALD method, it is preferably used as a precursor that does not contain hydrocarbons (Hydro Carbon, also referred to as HC). When the material that can have ferroelectricity contains one or both of hydrogen and carbon, the crystallization of the material that can have ferroelectricity is sometimes blocked. Therefore, it is preferred that, as described above, the concentration of one or both of hydrogen and carbon in the material that can have ferroelectricity is reduced by using a precursor that does not contain hydrocarbons. For example, chlorine-based materials can be cited as precursors that do not contain hydrocarbons. In addition, when a material containing hafnium oxide and zirconium oxide (HfZrOx) is used as a material that can have ferroelectricity, HfCl4 and / or ZrCl4 can be used as precursors. On the other hand, dopants (typically silicon, carbon, etc.) for controlling the polarization state can also be added to the material that can exhibit ferroelectricity. In this case, as one of the means for adding carbon as a dopant, a formation method using a material containing hydrocarbon as a precursor may be adopted.

[0101] In addition, when depositing a film using a material that can have ferroelectricity, a high-purity intrinsic ferroelectric film can be formed by completely eliminating impurities in the film, which refers to one or more of hydrogen, hydrocarbons and carbon. The manufacturing process integration between the high-purity intrinsic ferroelectric film and the high-purity intrinsic oxide semiconductor shown in the following embodiment is very high. Therefore, a method for manufacturing a semiconductor device with high productivity can be provided.

[0102] In addition, the impurity concentration of the material that can have ferroelectricity is preferably low. In particular, the lower the concentration of hydrogen (H) and carbon (C), the better. Specifically, the hydrogen concentration of the material that can have ferroelectricity is preferably 5×10 20 atoms / cm 3 Less than, more preferably 1×10 20 atoms / cm 3 In addition, the carbon concentration of the material that can have ferroelectricity is preferably 5×10 19 atoms / cm 3 Less than, more preferably 1×10 19 atoms / cm 3 the following.

[0103] When HfZrOx is used as the material that can have ferroelectricity, it is preferable to alternately deposit hafnium oxide and zirconium oxide by a thermal ALD method so as to have a composition of 1:1.

[0104] In addition, when a material having ferroelectricity is deposited by the ALD method, H2O or O3 can be used as an oxidant. Note that the oxidant in the ALD method is not limited thereto. For example, the oxidant in the ALD method may also include any one or more selected from O2, O3, N2O, NO2, H2O, and H2O2.

[0105] In particular, when the material that can have ferroelectricity has an orthorhombic crystal structure, it exhibits ferroelectricity, so it is preferred. In addition, it can also have other crystal structures in addition to the orthorhombic crystal structure. For example, it can also have one or more crystal structures selected from the isometric system, the tetragonal system and the monoclinic system in addition to the orthorhombic crystal structure. In addition, a layer that improves crystallinity can also be formed before forming the material that can have ferroelectricity. For example, when HfZrOx is used as the material that can have ferroelectricity, the layer that improves crystallinity can use metal oxides such as hafnium oxide or zirconium oxide, or hafnium or zirconium.

[0106] In addition, when AlScN is used as a material having ferroelectricity, it is preferred to have a hexagonal crystal structure. In addition, it may also have other crystal structures in addition to the hexagonal crystal structure. As a layer to improve crystallinity, it is preferred to use a metal nitride such as aluminum nitride or scandium nitride, or aluminum or scandium.

[0107] Alternatively, a layer for improving crystallinity may be formed after forming a material that can have ferroelectricity. Alternatively, a composite structure having an amorphous structure and a crystalline structure may be used as the material that can have ferroelectricity.

[0108] [Conductive layer] As conductive materials for conductive layers of various wirings and electrodes constituting semiconductor devices, metal elements selected from aluminum (Al), chromium (Cr), copper (Cu), silver (Ag), gold (Au), platinum (Pt), tantalum (Ta), nickel (Ni), titanium (Ti), molybdenum (Mo), tungsten (W), hafnium (Hf), vanadium (V), niobium (Nb), manganese (Mn), magnesium (Mg), zirconium (Zr), beryllium (Be), etc., alloys containing the above metal elements as components, or alloys combining the above metal elements, etc. can be used.

[0109] For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. are preferably used. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel are conductive materials that are not easily oxidized or materials that maintain conductivity even when absorbing oxygen, so they are preferred. In addition, semiconductors with high conductivity represented by polycrystalline silicon containing impurity elements such as phosphorus and silicides such as nickel silicide can also be used. There is no particular limitation on the method for forming the conductive material, and various formation methods such as evaporation, atomic layer deposition (ALD: Atomic Layer Deposition) method, CVD method, sputtering method, spin coating method, etc. can be used.

[0110] In addition, as a conductive material, a Cu-X alloy (X is Mn, Ni, Cr, Fe, Co, Mo, Ta or Ti) can also be used. The layer formed using the Cu-X alloy can be processed by a wet etching process, thereby suppressing the manufacturing cost. In addition, as a conductive material, an aluminum alloy containing one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium and scandium can also be used.

[0111] As the conductive material that can be used for the conductive layer, conductive materials containing oxygen such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon oxide, etc. can also be used. In addition, conductive materials containing nitrogen such as titanium nitride, tantalum nitride, tungsten nitride, etc. can also be used. In addition, the conductive layer can also adopt a laminated structure in which conductive materials containing oxygen, conductive materials containing nitrogen, and materials containing the above-mentioned metal elements are appropriately combined.

[0112] For example, the conductive layer can adopt a single-layer structure of an aluminum layer containing silicon, a two-layer structure of a titanium layer stacked on an aluminum layer, a two-layer structure of a titanium layer stacked on a titanium nitride layer, a two-layer structure of a tungsten layer stacked on a titanium nitride layer, a two-layer structure of a tungsten layer stacked on a tantalum nitride layer, and a three-layer structure of a titanium layer, an aluminum layer, and a titanium layer stacked in sequence.

[0113] In addition, a plurality of conductive layers formed of the above-mentioned conductive materials may be stacked. For example, the conductive layer may also adopt a laminated structure in which a material containing the above-mentioned metal element and a conductive material containing oxygen are combined. For example, the conductive layer may also adopt a laminated structure in which a material containing the above-mentioned metal element and a conductive material containing oxygen are combined. For example, the conductive layer may also adopt a laminated structure in which a material containing the above-mentioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined.

[0114] For example, the conductive layer may also have a three-layer structure in which a conductive layer containing at least one of indium and zinc and oxygen, a conductive layer containing copper, and a conductive layer containing at least one of indium and zinc and oxygen are sequentially stacked. In this case, it is preferred that the side of the conductive layer containing copper is also covered with a conductive layer containing at least one of indium and zinc and oxygen. In addition, for example, as the conductive layer, a plurality of conductive layers containing at least one of indium and zinc and oxygen may be stacked.

[0115] When capacitor 110 is used as a ferroelectric capacitor, conductive layer 151 and conductive layer 155 in contact with ferroelectric insulating layer 154 are preferably made of a material that easily polarizes insulating layer 154. For example, conductive layer 151 and conductive layer 155 are preferably made of titanium nitride.

[0116] [Semiconductor layer] As the semiconductor layer 163, a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination. As the semiconductor material, for example, silicon or germanium can be used. In addition, a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, or a nitride semiconductor can also be used. As the compound semiconductor, an organic substance having semiconductor characteristics or a metal oxide having semiconductor characteristics (also referred to as an oxide semiconductor) can be used. Note that these semiconductor materials may also contain impurities as dopants.

[0117] For example, single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon may be used as the semiconductor layer 163. As the polycrystalline silicon, for example, low temperature polycrystalline silicon (LTPS: Low Temperature Poly Silicon) may be used.

[0118] A transistor using amorphous silicon as the semiconductor layer 163 can be formed on a large glass substrate and can be manufactured at low cost. A transistor using polycrystalline silicon as the semiconductor layer 163 has high field effect mobility and can operate at high speed. In addition, a transistor using microcrystalline silicon as the semiconductor layer 163 has high field effect mobility compared to a transistor using amorphous silicon and can operate at high speed.

[0119] The semiconductor layer 163 may also include a layered material used as a semiconductor. A layered material is a general term for a group of materials having a layered crystalline structure. A layered crystalline structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked by bonds such as van der Waals forces that are weaker than covalent bonds and ionic bonds. The layered material has high conductivity in a unit layer, that is, has high two-dimensional conductivity. By using a material used as a semiconductor and having high two-dimensional conductivity in a channel formation region, a transistor with a large on-state current can be provided.

[0120] As the above-mentioned layered material, for example, graphene, silicene, chalcogenides, etc. can be cited. Chalcogenides are compounds containing oxygen group elements (elements belonging to group 16). In addition, as chalcogenides, transition metal chalcogenides, group 13 chalcogenides, etc. can be cited. Transition metal chalcogenides that can be used as semiconductor layers of transistors include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), zirconium selenide (typically ZrSe2), etc.

[0121] In addition, the band gap of the oxide semiconductor is more than 2eV, so the off-state current of the transistor (also called "OS transistor") using an oxide semiconductor of one of the metal oxides in the semiconductor layer in which the channel is formed is extremely small. As a result, the power consumption of the semiconductor device including the OS transistor can be reduced. In addition, the OS transistor operates stably even in a high temperature environment, and the characteristics vary less. For example, even in a high temperature environment, the off-state current hardly increases. Specifically, even at an ambient temperature above room temperature and below 200°C, the off-state current hardly increases. In addition, even in a high temperature environment, the on-state current is not easy to drop. Therefore, the semiconductor device including the OS transistor operates stably even in a high temperature environment and has high reliability.

[0122] Therefore, in a storage device that does not use a ferroelectric capacitor as a capacitor, written data can be maintained for a long time. For example, in a general DRAM, the refresh operating frequency needs to be about 1 time / 60msec, but in a storage device of one embodiment of the present invention, the refresh operating frequency can be 1 time / 10sec, that is, more than 10 times or more than 100 times that of a general DRAM. By adopting a storage device of one embodiment of the present invention, the refresh operating frequency can be once every 1 second or more and less than 100 seconds, preferably once every 5 seconds or more and less than 50 seconds.

[0123] In this embodiment and the like, an OS transistor is preferably used as the transistor 100. The insulation withstand voltage between the source and the drain of the OS transistor is high, so the channel length can be reduced. Therefore, the on-state current can be increased. The OS transistor is suitable for a vertical channel transistor.

[0124] As metal oxides that can be used for the semiconductor layer of the OS transistor, for example, indium oxide, gallium oxide, and zinc oxide can be cited. The metal oxide preferably contains at least indium (In) or zinc (Zn). In addition, the metal oxide preferably contains two or three selected from indium, element M, and zinc. Note that element M is a metal element or a semi-metal element with a high bonding energy with oxygen, for example, a metal element or a semi-metal element with a higher bonding energy with oxygen than indium.

[0125] Element M specifically includes aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. Element M contained in the metal oxide is preferably any one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and further preferably gallium. Note that in this specification, etc., metal elements and semi-metal elements are sometimes collectively referred to as "metal elements", and sometimes the "metal elements" described in this specification, etc. include semi-metal elements.

[0126] For example, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also referred to as "GZO"), aluminum zinc oxide (Al-Zn oxide, also referred to as "AZO"), indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as "IAZO"), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as "IGZO"), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as "IGZTO"), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as "IGAZO" or "IAGZO"), etc. can be used. Alternatively, indium tin oxide, gallium tin oxide (Ga—Sn oxide), aluminum tin oxide (Al—Sn oxide), or the like containing silicon may be used.

[0127] By increasing the ratio of the number of atoms of indium contained in the metal oxide relative to the total number of atoms of all metal elements, the field effect mobility of the transistor can be increased.

[0128] Note that the metal oxide may also replace indium or contain one or more metal elements with a large period number in addition to indium. Alternatively, the metal oxide may also replace indium or contain one or more metal elements with a large period number in addition to indium. Metal oxides have a tendency that the greater the overlap of the orbits of the metal elements, the greater the carrier conduction in the metal oxide. Therefore, by including a metal element with a large period number, the field effect mobility of the transistor can sometimes be improved. As metal elements with a large period number, metal elements belonging to the 5th period and metal elements belonging to the 6th period can be cited. As the metal element, specifically, yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium can be cited. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium are called light rare earth elements.

[0129] The metal oxide may also contain one or more non-metallic elements. The inclusion of non-metallic elements in the metal oxide may sometimes improve the field effect mobility of the transistor. Examples of the non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0130] By increasing the ratio of the number of zinc atoms in the main component elements contained in the metal oxide to the total number of metal element atoms, a highly crystalline metal oxide is obtained, thereby suppressing the diffusion of impurities in the metal oxide. Therefore, the variation of the electrical characteristics of the transistor is suppressed and the reliability can be improved.

[0131] By increasing the ratio of the number of atoms of the element M in the main component elements contained in the metal oxide relative to the total number of atoms of the metal elements, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, the generation of carriers caused by oxygen vacancies is suppressed, thereby realizing a transistor with a small off-state current. In addition, the variation of the electrical characteristics of the transistor is suppressed, thereby improving reliability.

[0132] The electrical characteristics and reliability of the transistor vary depending on the composition of the metal oxide used for the semiconductor layer. Therefore, by varying the composition of the metal oxide according to the electrical characteristics and reliability required for the transistor, a semiconductor device having both excellent electrical characteristics and high reliability can be realized.

[0133] When In-Zn oxide is used as the semiconductor layer of the OS transistor, a metal oxide in which the atomic ratio of indium is greater than the atomic ratio of zinc may be used. For example, a metal oxide in which the atomic ratio of the metal elements is In:Zn=1:1, In:Zn=2:1, In:Zn=3:1, In:Zn=4:1, In:Zn=5:1, In:Zn=7:1, In:Zn=10:1 or a metal oxide in the vicinity thereof may be used.

[0134] When In-Sn oxide is used as the semiconductor layer of the OS transistor, a metal oxide in which the atomic ratio of indium is greater than the atomic ratio of tin may be used. For example, a metal oxide in which the atomic ratio of the metal elements is In:Sn=1:1, In:Sn=2:1, In:Sn=3:1, In:Sn=4:1, In:Sn=5:1, In:Sn=7:1, In:Sn=10:1 or a metal oxide in the vicinity thereof may be used.

[0135] When In-Sn-Zn oxide is used as the semiconductor layer of the OS transistor, a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of tin may also be used. Furthermore, it is preferred to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of tin. For example, the atomic ratios of metal elements In:Sn:Zn=2:1:3, In:Sn:Zn=3:1:2, In:Sn:Zn=4:2:3, In:Sn:Zn=4:2:4.1, In:Sn:Zn=5:1:3, In:Sn:Zn=5:1:6, In:Sn:Zn=5:1:7, In:Sn:Zn=5:1:8, In:Sn:Zn =6:1:6、In:Sn:Zn=10:1:3、In:Sn:Zn=10:1:6、In:Sn:Zn=10:1:7、In:Sn:Zn=10:1:8、In :Sn:Zn=5:2:5, In:Sn:Zn=10:1:10, In:Sn:Zn=20:1:10, In:Sn:Zn=40:1:10 or metal oxides in their vicinity.

[0136] When In-Al-Zn oxide is used as the semiconductor layer of the OS transistor, a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of aluminum may be used. Furthermore, it is preferred to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of aluminum. For example, the atomic ratios of the metal elements In:Al:Zn=2:1:3, In:Al:Zn=3:1:2, In:Al:Zn=4:2:3, In:Al:Zn=4:2:4.1, In:Al:Zn=5:1:3, In:Al:Zn=5:1:6, In:Al:Zn=5:1:7, In:Al:Zn=5:1:8, In:Al:Zn=5:1:9, In:Al:Zn=5:1:10, In:Al:Zn=5:1:11, In:Al:Zn=5:1:12, In:Al:Zn=5:1:13, In:Al:Zn=5:1:14, In:Al:Zn=5:1:15, In:Al:Zn=5:1:16, In:Al:Zn=5:1:17, In:Al:Zn=5:1:18, In:Al:Zn=5:1:19, In:Al:Zn=5:1:10, In:Al:Zn=5:1:11, In:Al:Zn=5:1:12 n=6:1:6, In:Al:Zn=10:1:3, In:Al:Zn=10:1:6, In:Al:Zn=10:1:7, In:Al:Zn=10:1:8, In:Al:Zn=5:2:5, In:Al:Zn=10:1:10, In:Al:Zn=20:1:10, In:Al:Zn=40:1:10 or metal oxides thereabouts.

[0137] When In-Ga-Zn oxide is used as the semiconductor layer of the OS transistor, a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of gallium relative to the sum of the atomic numbers of metal elements in the In-Ga-Zn oxide may be used. Furthermore, it is preferred to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of gallium. For example, the semiconductor layer may also use a metal element atomic ratio of In:Ga:Zn=2:1:3, In:Ga:Zn=3:1:2, In:Ga:Zn=4:2:3, In:Ga:Zn=4:2:4.1, In:Ga:Zn=5:1:3, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:7, In:Ga:Zn=5:1:8, In:Ga :Zn=6:1:6, In:Ga:Zn=10:1:3, In:Ga:Zn=10:1:6, In:Ga:Zn=10:1:7, In:Ga:Zn=10:1:8, In:Ga:Zn=5:2:5, In:Ga:Zn=10:1:10, In:Ga:Zn=20:1:10, In:Ga:Zn=40:1:10 or metal oxides thereof.

[0138] When In-M-Zn oxide is used as the semiconductor layer of the OS transistor, a metal oxide in which the atomic ratio of indium relative to the sum of the atomic numbers of metal elements in the In-M-Zn oxide is higher than the atomic ratio of the element M may be used. Furthermore, it is preferred to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of the element M. For example, the semiconductor layer may also use a metal element atomic ratio of In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M: Zn=6:1:6, In:M:Zn=10:1:3, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=5:2:5, In:M:Zn=10:1:10, In:M:Zn=20:1:10, In:M:Zn=40:1:10 or metal oxides thereabouts.

[0139] When In-M-Zn oxide is used as a semiconductor layer, the following metal oxide may be used: the atomic ratio of the metal elements is In:M:Zn=1:3:2 [atomic ratio] or a composition close thereto, In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:0.5 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:1.2 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:2 [atomic ratio] or a composition close thereto, or In:M:Zn=4:2:3 [atomic ratio] or a composition close thereto. Note that the nearby composition includes a range of ±30% of the desired atomic ratio. In addition, gallium is preferably used as the element M.

[0140] Note that when a plurality of metal elements are included as the element M, the sum of the atomic ratios of the metal elements may be the atomic ratio of the element M. For example, when an In-Ga-Al-Zn oxide including gallium and aluminum is used as the element M, the sum of the atomic ratio of gallium and the atomic ratio of aluminum may be the atomic ratio of the element M. In addition, the atomic ratio of indium, the element M, and zinc is preferably within the above range.

[0141] It is preferable to use a metal oxide in which the ratio of the number of atoms of indium in the main component elements contained in the metal oxide to the total number of atoms of the metal elements is 30 atomic % or more and 100 atomic % or less, preferably 30 atomic % or more and 95 atomic % or less, more preferably 35 atomic % or more and 95 atomic % or less, more preferably 35 atomic % or more and 90 atomic % or less, more preferably 40 atomic % or more and 90 atomic % or less, more preferably 45 atomic % or more and 90 atomic % or less, more preferably 50 atomic % or more and 80 atomic % or less, more preferably 60 atomic % or more and 80 atomic % or less, more preferably 70 atomic % or more and 80 atomic % or less. For example, in the case of using In-M-Zn oxide as a semiconductor layer, the ratio of the number of atoms of indium to the total number of atoms of indium, element M and zinc is preferably within the above range.

[0142] As described above, when the ratio of the number of atoms of indium in the main component elements contained in the metal oxide to the total number of atoms of the metal elements is increased, the field effect mobility of the transistor can be increased. By using this transistor, a circuit capable of high-speed operation can be manufactured. Furthermore, the area occupied by the circuit can be reduced.

[0143] The composition of metal oxides can be analyzed, for example, using energy dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), inductively coupled plasma mass spectrometry (ICP-MS) or inductively coupled plasma atomic emission spectrometry (ICP-AES). Alternatively, multiple of the above methods can be combined for analysis. Note that the actual content of elements with low content is sometimes different from the content obtained by analysis due to the influence of analysis accuracy. For example, when the content of element M is low, the content of element M obtained by analysis is sometimes lower than the actual content.

[0144] The metal oxide can be formed by sputtering or atomic layer deposition as appropriate. Note that when the metal oxide is formed by sputtering, the atomic ratio of the target material is sometimes different from the atomic ratio of the metal oxide. In particular, the atomic ratio of zinc in the metal oxide is sometimes smaller than the atomic ratio of zinc in the target material. Specifically, the atomic ratio of zinc is sometimes about 40% or more and 90% or less of the atomic ratio of zinc in the target material.

[0145] Furthermore, when the metal oxide is deposited by sputtering, the above atomic ratio is not limited to the atomic ratio of the deposited metal oxide, but may also be the atomic ratio of the sputtering target used for the deposition of the metal oxide.

[0146] Here, the reliability of the transistor is explained. As one of the indicators for evaluating the reliability of the transistor, there is a GBT (Gate Bias Temperature) stress test in which an electric field is applied to the gate. Among them, the test of maintaining the gate at a high temperature while applying a positive potential (positive bias) relative to the source potential and the drain potential is called a PBTS (Positive BiasTemperature Stress) test, and the test of maintaining the gate at a high temperature while applying a negative potential (negative bias) is called an NBTS (Negative Bias Temperature Stress) test. In addition, the PBTS test and the NBTS test performed under the state of irradiation with light are respectively called the PBTIS (Positive Bias Temperature Illumination Stress) test and the NBTIS (Negative Bias Temperature Illumination Stress) test.

[0147] In an n-channel transistor, a positive potential is applied to the gate when the transistor is turned on, so the variation of the threshold voltage in the PBTS test is one of the important factors to be focused on as a reliability index of the transistor.

[0148] By using a metal oxide that does not contain gallium or has a low gallium content in the semiconductor layer, a transistor with high reliability for forward bias application can be realized. In other words, a transistor with a small change in threshold voltage in a PBTS test can be realized. In addition, when a metal oxide containing gallium is used, the gallium content is preferably lower than the indium content. Thus, a transistor with high reliability can be realized.

[0149] One of the reasons for the change in threshold voltage in the PBTS test is the defect state at or near the interface between the semiconductor layer and the gate insulating layer. The greater the defect state density, the more significant the degradation in the PBTS test. The generation of the defect state can be suppressed by reducing the gallium content in the region of the semiconductor layer that contacts the gate insulating layer.

[0150] The reason why the change in threshold voltage in the PBTS test can be suppressed by using a metal oxide that does not contain gallium or has a low gallium content for the semiconductor layer is, for example, as follows. Gallium contained in the metal oxide is more likely to absorb oxygen than other metal elements (such as indium or zinc). Therefore, it can be inferred that at the interface between the metal oxide containing more gallium and the gate insulating layer, carrier (here, electron) trap sites are easily generated by bonding between gallium and excess oxygen in the gate insulating layer. Therefore, when a positive potential is applied to the gate, carriers are captured at the interface between the semiconductor layer and the gate insulating layer, and the threshold voltage will change.

[0151] More specifically, when In-Ga-Zn oxide is used as the semiconductor layer, a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of gallium can be used for the semiconductor layer. It is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of gallium. In other words, a metal oxide in which the atomic ratio of metal elements satisfies In>Ga and Zn>Ga is used for the semiconductor layer.

[0152] For example, the semiconductor layer of the OS transistor may use metal elements with atomic ratios of In:Ga:Zn=2:1:3, In:Ga:Zn=3:1:2, In:Ga:Zn=4:2:3, In:Ga:Zn=4:2:4.1, In:Ga:Zn=5:1:3, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:7, In:Ga:Zn=5:1:8, In: Ga:Zn=6:1:6, In:Ga:Zn=10:1:3, In:Ga:Zn=10:1:6, In:Ga:Zn=10:1:7, In:Ga:Zn=10:1:8, In:Ga:Zn=5:2:5, In:Ga:Zn=10:1:10, In:Ga:Zn=20:1:10, In:Ga:Zn=40:1:10 or metal oxides thereabouts.

[0153] The semiconductor layer of the OS transistor preferably uses a metal oxide in which the ratio of the number of atoms of gallium to the number of atoms of the metal element contained is higher than 0 atomic % and is less than 50 atomic %, preferably greater than 0.1 atomic % and less than 40 atomic %, more preferably greater than 0.1 atomic % and less than 35 atomic %, more preferably greater than 0.1 atomic % and less than 30 atomic %, more preferably greater than 0.1 atomic % and less than 25 atomic %, more preferably greater than 0.1 atomic % and less than 20 atomic %, more preferably greater than 0.1 atomic % and less than 15 atomic %, more preferably greater than 0.1 atomic % and less than 10 atomic %. By reducing the gallium content in the semiconductor layer, a transistor with high resistance to the PBTS test can be realized. Note that by including gallium in the metal oxide, it is less likely to generate oxygen vacancies (V O : Oxygen Vacancy) effect.

[0154] As the semiconductor layer of the OS transistor, a metal oxide that does not contain gallium can also be used. For example, In-Zn oxide can be used for the semiconductor layer. At this time, when the atomic number ratio of indium contained in the metal oxide relative to the atomic number of the metal element is increased, the field effect mobility of the transistor can be improved. On the other hand, when the atomic number ratio of zinc contained in the metal oxide relative to the atomic number of the metal element is increased, the metal oxide has high crystallinity, so the variation of the electrical characteristics of the transistor is suppressed, and the reliability can be improved. In addition, as the semiconductor layer, a metal oxide such as indium oxide that does not contain gallium and zinc can also be used. By using a metal oxide that does not contain gallium, the variation of the threshold voltage in the PBTS test can be made extremely small, especially.

[0155] For example, an oxide containing indium and zinc can be used as the semiconductor layer. In this case, for example, a metal oxide having an atomic ratio of metal elements of In:Zn=2:3, In:Zn=4:1 or a ratio close to this can be used.

[0156] Note that although gallium is used as an example for the description, the invention can also be applied to the case where element M is used instead of gallium. It is preferable to use a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of element M for the semiconductor layer. It is also preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of element M.

[0157] A transistor having high reliability in case of forward bias application can be realized by using a metal oxide having a low content of element M as a semiconductor layer. A semiconductor device having high reliability can be realized by using this transistor as a transistor that needs to have high reliability in case of forward bias application.

[0158] The semiconductor layer may also have a stacked structure including two or more metal oxide layers. The compositions of the two or more metal oxide layers included in the semiconductor layer may also be the same or substantially the same as each other. By adopting a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used to form it, thereby reducing the manufacturing cost.

[0159] The compositions of the two or more metal oxide layers included in the semiconductor layer may also be different from each other. For example, a stacked structure of a first metal oxide layer having a composition of In:M:Zn=1:3:4 [atomic ratio] or thereabouts and a second metal oxide layer having a composition of In:M:Zn=1:1:1 [atomic ratio] or thereabouts disposed on the first metal oxide layer may be appropriately used. In addition, gallium or aluminum is particularly preferably used as the element M. For example, a stacked structure of any one selected from indium oxide, indium gallium oxide and IGZO and any one selected from IAZO, IAGZO and ITZO (registered trademark) may be used.

[0160] In addition, for example, a stacked structure of a first metal oxide layer with a composition of In:M:Zn=1:1:1 [atomic ratio] or thereabouts and a second metal oxide layer with a composition of In:Zn=4:1 [atomic ratio] or thereabouts provided on the first metal oxide layer can be appropriately used.

[0161] As the semiconductor layer, a crystalline metal oxide layer is preferably used. For example, a metal oxide layer having a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, a microcrystalline (nc: nano-crystal) structure, etc., which will be described later, can be used. By using a crystalline metal oxide layer for the semiconductor layer, the defect state density in the semiconductor layer can be reduced, thereby realizing a display device with high reliability.

[0162] The higher the crystallinity of the metal oxide layer used for the semiconductor layer, the lower the defect state density in the semiconductor layer can be. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of passing a large current can be realized.

[0163] When a metal oxide layer is formed by sputtering, the higher the substrate temperature (stage temperature) during formation, the more crystalline the metal oxide layer can be formed. In addition, the higher the flow rate ratio of the oxygen gas relative to the entire deposition gas used during formation (hereinafter also referred to as the oxygen flow rate ratio) is, the more crystalline the metal oxide layer can be formed.

[0164] The semiconductor layer of the OS transistor may also have a stacked structure of two or more metal oxide layers with different crystallinity. For example, a stacked structure may have a first metal oxide layer and a second metal oxide layer disposed on the first metal oxide layer, and the second metal oxide layer may have a region whose crystallinity is higher than that of the first metal oxide layer. Alternatively, the second metal oxide layer may have a region whose crystallinity is lower than that of the first metal oxide layer. The compositions of the two or more metal oxide layers included in the semiconductor layer may also be the same or substantially the same as each other. By adopting a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used to form them, thereby reducing manufacturing costs. For example, by using the same sputtering target to make the oxygen flow ratio different, a stacked structure of two or more metal oxide layers with different crystallinity can be formed. Note that the compositions of the two or more metal oxide layers included in the semiconductor layer may also be different from each other.

[0165] When an oxide semiconductor is used for the semiconductor layer 163, a material containing hydrogen is preferably used for the insulating layer 157 and the insulating layer 159. When the insulating layer containing hydrogen contacts the oxide semiconductor, the oxide semiconductor in the region in contact with the insulating layer is converted to n-type, and can be used as a source region or a drain region. As the insulating layer, for example, a material containing silicon, nitrogen and hydrogen can be used. Specifically, hydrogen-containing silicon nitride or hydrogen-containing silicon nitride oxide can be used.

[0166] The thickness of the insulating layer 157 and the insulating layer 159 is preferably 1 nm or more and 15 nm or less, more preferably 2 nm or more and 10 nm or less, further preferably 3 nm or more and 7 nm or less, and further preferably 3 nm or more and 5 nm or less. When an oxide semiconductor is used as the semiconductor layer 163, a region of the semiconductor layer 163 that contacts the insulating layer 157 containing hydrogen and a region that contacts the insulating layer 159 containing hydrogen serve as a source region or a drain region. By adjusting the thickness of the insulating layer 157 and the insulating layer 159, the size of the source region and the drain region formed in the semiconductor layer 163 can be controlled.

[0167] The thickness of the insulating layer 158 is preferably 1 nm to 50 nm, more preferably 2 nm to 30 nm, and further preferably 3 nm to 2 nm. By adjusting the thickness of the insulating layer 158, the size of the channel formation region of the semiconductor layer 163 can be controlled.

[0168] The thicknesses of the insulating layer 157 , the insulating layer 158 , and the insulating layer 159 can be appropriately set depending on the characteristics required for the transistor 100 .

[0169] In addition, the deposition of insulating layer 157, insulating layer 158, and insulating layer 159 is preferably performed continuously without being exposed to the atmosphere during the deposition. By performing the deposition of insulating layer 157, insulating layer 158, and insulating layer 159 continuously without being exposed to the atmosphere during the deposition, impurities and moisture from the atmosphere can be prevented from adhering to the interface between insulating layer 157 and insulating layer 158 and its vicinity, and the interface between insulating layer 158 and insulating layer 159 and its vicinity.

[0170] In addition, when an oxide semiconductor is used for the semiconductor layer 163, the conductive layer 155 in contact with the semiconductor layer 163 and the conductive layer 161 in contact with the semiconductor layer 163 preferably use a conductive material that converts the oxide semiconductor into an n-type. For example, a conductive material containing nitrogen can be used. For example, a conductive material containing titanium or tantalum and nitrogen can be used. In addition, other conductive materials can be provided in a manner overlapping with the conductive material containing nitrogen.

[0171] On the other hand, the insulating layer 158 preferably uses a material containing oxygen and having reduced hydrogen. For example, a material containing silicon and oxygen may be used. Specifically, silicon oxide or silicon oxynitride is used. Hydrogen is an impurity element in an oxide semiconductor, so when the semiconductor layer 163 of the oxide semiconductor contacts the insulating layer 158 in which hydrogen is reduced, the semiconductor layer 163 is not easily converted to an n-type. In addition, when the semiconductor layer 163 of the oxide semiconductor contacts the insulating layer 158 containing oxygen, the oxygen vacancies in the semiconductor layer 163 are reduced, the characteristics of the transistor 100 are stabilized, and the reliability is improved.

[0172] In addition, when an oxide semiconductor is used for the semiconductor layer 163, the insulating layer 158 preferably contains excess oxygen. In this specification, etc., excess oxygen refers to oxygen released by heating. In addition, when a material containing excess oxygen is used for the insulating layer 158, a material that is not easily permeable to oxygen is preferably used for the insulating layer 157 and the insulating layer 159. As a material that is not easily permeable to oxygen, for example, an oxide containing one or both of aluminum and hafnium, a nitride of silicon, or the like can be used. By using a material that is not easily permeable to oxygen for the insulating layer 157 and the insulating layer 159, the excess oxygen contained in the insulating layer 158 is not easily released to the lower layer or the upper layer. Therefore, sufficient oxygen can be supplied to the oxide semiconductor. For example, an insulating layer (insulating layer 158) containing silicon and oxygen can be included between two insulating layers (insulating layer 157, insulating layer 159) containing silicon and nitrogen.

[0173] In addition, by using an oxide semiconductor as the semiconductor layer 163 and using a material containing hydrogen as the insulating layer 157 and the insulating layer 159, hydrogen is supplied to the region of the semiconductor layer 163 in contact with the insulating layer 157 and the region of the semiconductor layer 163 in contact with the insulating layer 159, and each region in the semiconductor layer 163 is converted to an n-type. Therefore, the region of the semiconductor layer 163 in contact with the conductive layer 161 and the region of the semiconductor layer 163 in contact with the insulating layer 159 are used as one of the source (source region) and the drain (drain region). In addition, the region of the semiconductor layer 163 in contact with the conductive layer 155 and the region of the semiconductor layer 163 in contact with the insulating layer 157 are used as the other of the source (source region) and the drain (drain region).

[0174] In this case, the length of the side surface of the insulating layer 158 when viewed from the X direction or the Y direction is the channel length L (channel length L1) (see Figure 3A ). Therefore, the channel length L of the transistor 100 is determined by the thickness t of the insulating layer 158. Figure 3A Is magnification Figure 1B FIG. 1 is a cross-sectional view of transistor 100 shown in FIG. Figure 4A and Figure 4B yes Figure 3A A deformation example, equivalent to enlarging Figure 1BA cross-sectional view of transistor 100 is shown.

[0175] In addition, the insulating layer 157 and the insulating layer 159 may also use a material that does not contain hydrogen or contains very little hydrogen. For example, silicon nitride with very little hydrogen or silicon nitride oxide with very little hydrogen may also be used. At this time, the region where the semiconductor layer 163 contacts the insulating layer 157 and the region where the semiconductor layer 163 contacts the insulating layer 159 are not n-typed. Therefore, the region of the semiconductor layer 163 that contacts the conductive layer 161 is used as one of the source (source region) and the drain (drain region). In addition, the region of the semiconductor layer 163 that contacts the conductive layer 155 is used as the other of the source (source region) and the drain (drain region). In addition, the region of the semiconductor layer 163 that contacts the insulating layer 158 is used as a channel formation region.

[0176] In this case, the total length of the side surfaces of the insulating layer 157, the insulating layer 158, and the insulating layer 159 when viewed in the X direction or the Y direction is the channel length L (channel length L2). Therefore, the channel length L of the transistor 100 is determined by the total thickness ts of the insulating layer 157, the insulating layer 158, and the insulating layer 159.

[0177] Alternatively, the insulating layer 157 and the insulating layer 159 may be omitted and only the insulating layer 158 may be provided so that the insulating layer 158 is in contact with the conductive layer 155 and the conductive layer 161 (see Figure 4A ). In this case, the length of the side surface of the insulating layer 158 when viewed from the X direction or the Y direction is the channel length L. Therefore, the channel length L of the transistor 100 is determined by the thickness t of the insulating layer 158. Figure 4A In the structure shown, insulating layer 158 is sometimes referred to as insulating layer 156.

[0178] When an oxide semiconductor is used as the semiconductor layer 163, a material containing hydrogen is used as the insulating layers 157 and 159, and a material containing excess oxygen is used as the insulating layer 158, hydrogen in the insulating layers 157 and 159 is bonded to excess oxygen in the insulating layer 158, and a region of the semiconductor layer 163 in contact with the insulating layer 157 and a region of the semiconductor layer 163 in contact with the insulating layer 159 are not supplied with sufficient hydrogen and are not easily converted to n-type. Similarly, a region of the semiconductor layer 163 in contact with the insulating layer 158 is not supplied with sufficient oxygen.

[0179] In order to solve the above problem, the insulating layer 171 which is not easily permeable to oxygen and nitrogen may be provided between the insulating layer 157 and the insulating layer 158, and the insulating layer 172 which is not easily permeable to oxygen and nitrogen may be provided between the insulating layer 159 and the insulating layer 158 (see Figure 4B ). For example, a material that is not easily permeable to oxygen and nitrogen, such as silicon nitride, can be used. Figure 4B In the structure shown in FIG. 1 , the insulating layer 157 , the insulating layer 171 , the insulating layer 158 , the insulating layer 172 , and the insulating layer 159 are sometimes collectively referred to as the insulating layer 156 .

[0180] When a material that does not easily transmit oxygen is used as the insulating layers 171 and 172, bonding between hydrogen in the insulating layers 157 and 159 and excess oxygen in the insulating layer 158 is blocked. Therefore, a region of the semiconductor layer 163 in contact with the insulating layer 157 and a region of the semiconductor layer 163 in contact with the insulating layer 159 are sufficiently supplied with hydrogen. Similarly, a region of the semiconductor layer 163 in contact with the insulating layer 158 is sufficiently supplied with oxygen.

[0181] In this case, the total length of the side surfaces of the insulating layer 171 , the insulating layer 158 , and the insulating layer 172 when viewed in the X direction or the Y direction is the channel length L. Therefore, the channel length L of the transistor 100 is determined by the total thickness tm of the insulating layer 171 , the insulating layer 158 , and the insulating layer 172 .

[0182] The transistor 100 shown in this embodiment mode determines the channel length L according to the thickness of the insulating layer provided between the conductive layer 161 and the conductive layer 155. Therefore, a transistor having a short channel length L can be manufactured with high precision. In addition, the characteristic non-uniformity between the plurality of transistors 100 can be reduced. Therefore, the operation of the semiconductor device including the transistor 100 is stable, and the reliability can be improved. In addition, when the characteristic non-uniformity is reduced, the circuit design freedom of the semiconductor device is improved, and the operating voltage can also be reduced. Therefore, the power consumption of the semiconductor device can be reduced.

[0183] In this embodiment, three insulating layers (insulating layer 157, insulating layer 158, insulating layer 159) are included between conductive layer 155 and conductive layer 161, but the number of insulating layers between conductive layer 155 and conductive layer 161 is not limited thereto. The number of insulating layers between conductive layer 155 and conductive layer 161 may be one, two, or four or more layers.

[0184] In addition, in order to improve the coverage of the semiconductor layer 163, the insulating layer 164, and the conductive layer 165 formed in the opening 162, the taper angle θ of the side of the opening 162, that is, the taper angle θ of the side of each of the insulating layer 157, the insulating layer 158, and the insulating layer 159 is set to be greater than 45 degrees and less than 90 degrees, preferably greater than 50 degrees and less than 75 degrees. The taper angle θ of the side of a layer (insulating layer, conductive layer, or semiconductor layer) refers to the angle between the bottom surface of the layer and the side surface (refer to Figure 3A ).

[0185] Since the semiconductor layer 163 is disposed in the opening 162, the perimeter of the opening 162 when viewed from the Z direction is equal to the channel width W of the transistor 100 (see FIG. Figure 3B ). As the perimeter, for example, the perimeter at a position where the thickness t of the insulating layer 158 is half (t / 2) or the perimeter at a position where the thickness ts of the insulating layer 158 is half (ts / 2) can be calculated. Note that the perimeter at any position of the opening 162 can be set as the channel width W as needed. For example, the perimeter at the bottom of the opening 162 can be set as the channel width W, or the perimeter at the top of the opening 162 can be set as the channel width W.

[0186] In the memory device of one embodiment of the present invention, the channel length L is preferably at least smaller than the channel width W. The channel length L of one embodiment of the present invention is preferably 0.1 times or more and 0.99 times or less, and preferably 0.5 times or more and 0.8 times or less.

[0187] In addition, Figure 3B In FIG. 1 , the outline (planar shape) of the opening 162 when viewed from the Z direction is shown as a circle, but the present invention is not limited thereto. For example, the outline of the opening 162 when viewed from the Z direction may also be an ellipse (see FIG. 1 ). Figure 3C ) or rectangle (refer to Figure 3D ).Notice, Figure 3D In addition, for example, the outline of the opening 162 when viewed from the Z direction may also be a shape including one or both of a straight line portion and a curved line portion (see Figure 3E ).

[0188] In addition, the opening 162 is preferably small. For example, the maximum width of the opening 162 when viewed from the Z direction (the maximum diameter when the opening 162 is circular) is preferably less than 60nm, more preferably less than 50nm, further preferably less than 40nm, and particularly preferably less than 30nm. The maximum width of the opening 162 when viewed from the Z direction may also be less than 20nm. In addition, the minimum width of the opening 162 when viewed from the Z direction (the minimum diameter when the opening 162 is circular) is preferably greater than 1nm, more preferably greater than 5nm. In order to form the above-mentioned tiny opening 162, it is preferred to use a photolithography method using short-wavelength light such as EUV light or an electron beam.

[0189] Figure 5A and Figure 5B An example of a planar layout in which semiconductor devices 10A are arranged in a matrix is ​​shown. Figure 5A 1 shows a planar layout in which a region where the conductive layer 168 and the opening 162 (semiconductor device 10A) are alternately arranged along the X direction, a region where the conductive layer 168 is repeatedly arranged along the Y direction, and a region where the opening 162 (semiconductor device 10A) is repeatedly arranged along the Y direction. Figure 5A In the planar layout shown, the conductive layer 168 overlaps the opening 162 when viewed from the X direction.

[0190] Figure 5B A planar layout is shown in which a region where the conductive layer 168 is repeatedly arranged along the X direction, a region where the opening 162 (semiconductor device 10A) is repeatedly arranged along the X direction, a region where the conductive layer 168 is repeatedly arranged along the Y direction, and a region where the opening 162 (semiconductor device 10A) is repeatedly arranged along the Y direction.

[0191] exist Figure 5B In the planar layout shown, the conductive layer 168 and the opening 162 are arranged obliquely. Figure 5B In the embodiment, the conductive layer 161 that electrically connects the conductive layer 168 to the semiconductor device 10A is arranged obliquely. That is, when viewed from the Z direction, the straight line connecting the center of the conductive layer 168 and the center of the opening 162 is not perpendicular to the X direction and the Y direction. By arranging the conductive layer 168 and the opening 162 obliquely, the semiconductor device 10A can be efficiently arranged. Therefore, the integration degree of the semiconductor device 10A is improved, and the storage capacity per unit area of ​​the storage device including the semiconductor device 10A can be increased.

[0192] <Deformation Example 1> Fig. 6A and Figure 6B A semiconductor device 10B is shown as a modified example of the semiconductor device 10A. Fig. 6A It is a top view of the semiconductor device 10B. Figure 6B yes Fig. 6A A cross-sectional view of the portion indicated by the dot-dash line A1-A2. Figure 6C yes Fig. 6A A cross-sectional view of the portion indicated by the dot-dash line A3-A4.

[0193] By reducing the area of ​​the bottom of the opening 162, the taper angle θ of the side of the opening 162 can be increased without increasing the area occupied by the semiconductor device 10B. By increasing the taper angle θ of the side of the opening 162, the coverage of the semiconductor layer 163, the insulating layer 164, and the conductive layer 165 can be improved.

[0194] When the area of ​​the bottom of the opening 162 is reduced, the conductive layer 165 may become thinner toward the bottom of the opening 162 in the opening 162. The shape of the conductive layer 165 may be referred to as "needle-shaped" or "conical".

[0195] <Deformation Example 2> Fig. 7A and Figure 7B A semiconductor device 10C is shown as a modified example of the semiconductor device 10A. Fig. 7A It is a top view of the semiconductor device 10C. Figure 7B yes Fig. 7A A cross-sectional view of the portion indicated by the dot-dash line A1-A2. Figure 7C yes Fig. 7A A cross-sectional view of the portion indicated by the dot-dash line A3-A4.

[0196] The semiconductor device 10C does not have a taper angle on the side of the opening 162. If there is no problem with the coverage of the semiconductor layer 163, the insulating layer 164, and the conductive layer 165, the side of the opening 162 can be made vertical or substantially vertical. By making the side of the opening 162 vertical or substantially vertical, the occupied area of ​​the transistor 100 can be reduced. Therefore, the occupied area of ​​the semiconductor device including the transistor 100 can be reduced.

[0197] <Deformation Example 3> Fig. 8A and Figure 8B A semiconductor device 10D is shown as a modified example of the semiconductor device 10C. Fig. 8A It is a top view of the semiconductor device 10D. Figure 8B yes Fig. 8A A cross-sectional view of the portion indicated by the dot-dash line A1-A2. Figure 8C yes Fig. 8A A cross-sectional view of the portion indicated by the dot-dash line A3-A4.

[0198] The semiconductor device 10D shown in FIG8 has a structure in which the conductive layer 155 is removed from the semiconductor device 10A. Since the conductive layer 155 is not provided, the semiconductor device 10D can shorten its manufacturing process and improve productivity compared with the semiconductor device 10A. In addition, in the semiconductor device 10D, a part of the semiconductor layer 163 is used as one electrode of the capacitor 110. Specifically, at the bottom of the opening 162, the region of the semiconductor layer 163 overlapping the insulating layer 154 and the conductive layer 151 is used as one electrode of the capacitor 110.

[0199] <Deformation Example 4> Fig.9A 1 is a cross-sectional view showing a structural example in which two semiconductor devices 10A (semiconductor device 10Aa and semiconductor device 10Ab) are electrically connected to one wiring BL (conductive layer 168 and conductive layer 152). Fig. 9B From the Y direction Fig.9A A cross-sectional view of the portion indicated by the dot-dash line A1-A2. Fig. 9C yes Fig. 9B The equivalent circuit diagram of the cross-section diagram is shown.

[0200] The semiconductor device 10Aa is electrically connected to the wiring WLa, the wiring PLa, and the wiring BL. The semiconductor device 10Ab is electrically connected to the wiring WLb, the wiring PLb, and the wiring BL. By adopting a structure in which two semiconductor devices 10A are electrically connected to one wiring BL, the occupied area of ​​the semiconductor device including the semiconductor device 10A can be reduced.

[0201] The conductive layer 165 included in the semiconductor device 10Aa is used as a part of the wiring WLa. The conductive layer 151 included in the semiconductor device 10Aa is used as the wiring PLa. The conductive layer 165 included in the semiconductor device 10Ab is used as the wiring WLb. The conductive layer 151 included in the semiconductor device 10Ab is used as the wiring PLb.

[0202] In addition, when the same potential is supplied to the wiring PLa and the wiring PLb, they may be electrically connected.

[0203] In addition, the conductive layer 165 extending in the Y direction may be used as the conductive layer 165 of a plurality of semiconductor devices 10A arranged in the Y direction (see Fig.9A ). In other words, the conductive layer 165 included in the semiconductor device 10Aa may be electrically connected to the conductive layer 165 of another semiconductor device 10Aa arranged in the Y direction.

[0204] Furthermore, the conductive layer 151 extending in the Y direction may be used as the conductive layer 151 of a plurality of semiconductor devices 10A arranged in the Y direction. In other words, the conductive layer 151 included in the semiconductor device 10Aa may be electrically connected to the conductive layer 151 of another semiconductor device 10Aa arranged in the Y direction.

[0205] <Deformation Example 5> By stacking a plurality of semiconductor devices 10A, the area occupied by the semiconductor device 10A can be reduced. For example, by stacking two semiconductor devices 10A, the area occupied by each semiconductor device 10A is halved.

[0206] Fig.10 1 is a cross-sectional view showing a structural example in which four semiconductor devices 10A (semiconductor device 10A[ 1 ], semiconductor device 10A[ 2 ], semiconductor device 10A[ 3 ], and semiconductor device 10A[ 4 ]) are stacked in the Z direction. Fig.11 yes Fig.10 The equivalent circuit diagram of the stacked structure example shown in FIG. Fig.10 and Fig.11 In the present embodiment, the semiconductor devices 10A formed in the first layer, the second layer, the third layer, and the fourth layer are respectively referred to as semiconductor device 10A[1], semiconductor device 10A[2], semiconductor device 10A[3], and semiconductor device 10A[4]. In addition, in the present embodiment, the first layer, the second layer, the third layer, and the fourth layer are sometimes referred to as "first layer", "second layer", "third layer", and "fourth layer", respectively.

[0207] The semiconductor device 10A[1] is electrically connected to the wiring WL[1], the wiring PL[1], and the wiring BL (see Fig.11). The semiconductor device 10A[2] is electrically connected to the wiring WL[2], the wiring PL[2], and the wiring BL. The semiconductor device 10A[3] is electrically connected to the wiring WL[3], the wiring PL[3], and the wiring BL. The semiconductor device 10A[4] is electrically connected to the wiring WL[4], the wiring PL[4], and the wiring BL.

[0208] The conductive layer 165 included in the semiconductor device 10A[1] is electrically connected to the wiring WL[1]. In addition, the conductive layer 165 included in the semiconductor device 10A[1] is sometimes used as the wiring WL[1] or a part of the wiring WL[1]. The conductive layer 151 included in the semiconductor device 10A[1] is electrically connected to the wiring PL[1]. In addition, the conductive layer 151 included in the semiconductor device 10A[1] is sometimes used as the wiring PL[1] or a part of the wiring PL[1].

[0209] The conductive layer 165 included in the semiconductor device 10A[2] is electrically connected to the wiring WL[2]. In addition, the conductive layer 165 included in the semiconductor device 10A[2] is sometimes used as the wiring WL[2] or a part of the wiring WL[2]. The conductive layer 151 included in the semiconductor device 10A[2] is electrically connected to the wiring PL[2]. In addition, the conductive layer 151 included in the semiconductor device 10A[2] is sometimes used as the wiring PL[2] or a part of the wiring PL[2].

[0210] The conductive layer 165 included in the semiconductor device 10A[3] is electrically connected to the wiring WL[3]. In addition, the conductive layer 165 included in the semiconductor device 10A[3] is sometimes used as the wiring WL[3] or a part of the wiring WL[3]. The conductive layer 151 included in the semiconductor device 10A[3] is electrically connected to the wiring PL[3]. In addition, the conductive layer 151 included in the semiconductor device 10A[3] is sometimes used as the wiring PL[3] or a part of the wiring PL[3].

[0211] The conductive layer 165 included in the semiconductor device 10A[4] is electrically connected to the wiring WL[4]. In addition, the conductive layer 165 included in the semiconductor device 10A[4] is sometimes used as the wiring WL[4] or a part of the wiring WL[4]. The conductive layer 151 included in the semiconductor device 10A[4] is electrically connected to the wiring PL[4]. In addition, the conductive layer 151 included in the semiconductor device 10A[4] is sometimes used as the wiring PL[4] or a part of the wiring PL[4].

[0212] exist Fig.10 In the embodiment, a semiconductor device 10A[2] is provided on a semiconductor device 10A[1], a semiconductor device 10A[3] is provided on the semiconductor device 10A[2], and a semiconductor device 10A[4] is provided on the semiconductor device 10A[3]. Fig.10 The semiconductor devices 10A[ 1 ] to 10A[ 4 ] shown all include a conductive layer 152 and a conductive layer 168 . Fig.10 The conductive layer 168 included in each of the semiconductor devices 10A[ 1 ] to 10A[ 4 ] shown is electrically connected to each other through the conductive layer 152 included in each of the semiconductor devices 10A[ 1 ] to 10A[ 4 ].

[0213] Specifically, in Fig.10 In the embodiment, the conductive layer 152 included in the semiconductor device 10A[1] is electrically connected to the conductive layer 152 included in the semiconductor device 10A[2] via the conductive layer 168 included in the semiconductor device 10A[1]. In addition, the conductive layer 152 included in the semiconductor device 10A[2] is electrically connected to the conductive layer 152 included in the semiconductor device 10A[3] via the conductive layer 168 included in the semiconductor device 10A[2]. In addition, the conductive layer 152 included in the semiconductor device 10A[3] is electrically connected to the conductive layer 152 included in the semiconductor device 10A[4] via the conductive layer 168 included in the semiconductor device 10A[3]. Fig.10 As shown, when the plurality of conductive layers 168 and the plurality of conductive layers 152 are electrically connected, they function as one electrode extending in the Z direction. In other words, the plurality of conductive layers 168 and the plurality of conductive layers 152 function as one wiring BL.

[0214] like Fig.10 and Fig.11 As shown, the transistor 100 included in each of the semiconductor devices 10A[1] to 10A[4] is electrically connected to the wiring BL. Specifically, one of the source and drain of the transistor 100 included in the semiconductor device 10A[1], one of the source and drain of the transistor 100 included in the semiconductor device 10A[2], one of the source and drain of the transistor 100 included in the semiconductor device 10A[3], and one of the source and drain of the transistor 100 included in the semiconductor device 10A[4] are electrically connected to the wiring BL.

[0215] By electrically connecting a plurality of semiconductor devices 10A to one wiring BL, that is, by sharing one wiring BL, the occupied area of ​​the semiconductor device including the semiconductor device 10A can be reduced. In addition, by overlapping the plurality of semiconductor devices 10A in the Z direction, the occupied area of ​​the semiconductor device 10A can be reduced. Therefore, the occupied area of ​​the semiconductor device including the semiconductor device 10A can be further reduced. In addition, by overlapping the plurality of semiconductor devices 10A in the Z direction, the storage capacity per unit area of ​​the storage device including the semiconductor device 10A can be increased.

[0216] <Deformation Example 6> By combining Modification Example 4 and Modification Example 5, the occupied area of ​​each semiconductor device 10A can be further reduced.

[0217] Fig.12 1 is a cross-sectional view showing an example of a stacked structure of a plurality of semiconductor devices 10A. Fig.13 yes Fig.12 Equivalent circuit diagram of the stacked structure example shown. Fig.12 and Fig.13 An example is shown in which two semiconductor devices 10A (semiconductor device 10Aa and semiconductor device 10Ab) formed on the same plane form one set, and a set of semiconductor devices 10A is stacked in four layers (also referred to as “stages”).

[0218] exist Fig.12 and Fig.13 In the figure, the semiconductor device 10Aa and the semiconductor device 10Ab in the first layer are respectively referred to as semiconductor device 10Aa[1] and semiconductor device 10Ab[1]. In addition, the semiconductor device 10Aa and the semiconductor device 10Ab in the second layer are respectively referred to as semiconductor device 10Aa[2] and semiconductor device 10Ab[2]. In addition, the semiconductor device 10Aa and the semiconductor device 10Ab in the third layer are respectively referred to as semiconductor device 10Aa[3] and semiconductor device 10Ab[3]. In addition, the semiconductor device 10Aa and the semiconductor device 10Ab in the fourth layer are respectively referred to as semiconductor device 10Aa[4] and semiconductor device 10Ab[4].

[0219] In addition, the semiconductor device 10Aa[1] is electrically connected to the wiring WLa[1], the wiring PLa[1], and the wiring BL (see Fig.13 ). The semiconductor device 10Ab[1] is electrically connected to the wiring WLb[1], the wiring PLb[1], and the wiring BL. The semiconductor device 10Aa[2] is electrically connected to the wiring WLa[2], the wiring PLa[2], and the wiring BL. The semiconductor device 10Ab[2] is electrically connected to the wiring WLb[2], the wiring PLb[2], and the wiring BL. The semiconductor device 10Aa[3] is electrically connected to the wiring WLa[3], the wiring PLa[3], and the wiring BL. The semiconductor device 10Ab[3] is electrically connected to the wiring WLb[3], the wiring PLb[3], and the wiring BL. The semiconductor device 10Aa[4] is electrically connected to the wiring WLa[4], the wiring PLa[4], and the wiring BL. The semiconductor device 10Ab[4] is electrically connected to the wiring WLb[4], the wiring PLb[4], and the wiring BL.

[0220] By adopting Fig.12 and Fig.13The structure shown can further reduce the occupied area of ​​a semiconductor device including the semiconductor device 10A. In addition, the storage capacity per unit area of ​​a storage device using the semiconductor device 10A can be increased.

[0221] <Operation Example of Semiconductor Device 10> Next, an operation example of the semiconductor device 10 (the semiconductor device 10A, the semiconductor device 10C, and the semiconductor device 10D) will be described. Fig.14A An equivalent circuit diagram of the semiconductor device 10 is shown. Fig.14A The semiconductor device 10 shown is used as a storage element (memory cell) of a DRAM type (1Tr1C type) including one transistor M and one capacitor Cfe.

[0222] The capacitor Cfe is a ferroelectric capacitor including a material having ferroelectricity as a dielectric layer between two electrodes. Therefore, the semiconductor device 10 is used as a FeRAM. Fig.14A The transistor M shown corresponds to the transistor 100 , and the capacitor Cfe corresponds to the capacitor 110 .

[0223] As the semiconductor layer forming the channel of the transistor M, various semiconductor materials can be used. For example, as the semiconductor layer forming the channel of the transistor M, a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, or an amorphous semiconductor can be used alone or in combination. In addition, as the semiconductor material, for example, silicon or germanium can be used. In addition, compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductors, and nitride semiconductors can also be used.

[0224] In particular, an OS transistor is preferably used as the transistor M. The OS transistor has a characteristic of high insulation withstand voltage between the source and the drain. Therefore, by using the OS transistor as the transistor M, a high voltage can be applied to the transistor M even if the transistor M is miniaturized. By miniaturizing the transistor M, the occupied area of ​​the semiconductor device 10 can be reduced. For example, Fig.14A The area occupied by each semiconductor device 10 shown can be 1 / 3 to 1 / 6 of the area occupied by each cell of SRAM (Static Random Access Memory). Therefore, the semiconductor devices 10 can be arranged at a high density. Thus, a memory device with a large memory capacity can be realized.

[0225] When an OS transistor is used as a transistor constituting a memory cell, the memory cell may be referred to as an "OS memory". In particular, a DRAM-type OS memory is sometimes referred to as a DOSRAM (registered trademark). In addition, a FeRAM using an OS transistor as a transistor constituting a memory cell is sometimes referred to as a FeDOSRAM.

[0226] The wiring WL is used as a word line, and by controlling the potential of the wiring WL, it is possible to control the on state and the off state of the transistor M. For example, when the transistor M is an n-channel transistor, by making the potential of the wiring WL a high potential, the transistor M can be turned on, and by making the potential of the wiring WL a low potential, the transistor M can be turned off.

[0227] The wiring BL is used as a bit line, and the potential of the wiring BL is supplied to one electrode of the capacitor Cfe when the transistor M is in an on state.

[0228] The wiring PL is used as a plate line. The other electrode of the capacitor Cfe is supplied with a potential through the wiring PL.

[0229] <Hysteresis Characteristics of Ferroelectric Layer> The capacitor Cfe includes a ferroelectric layer having hysteresis characteristics. Fig. 14B is a graph showing an example of the hysteresis characteristic. Fig. 14B In FIG. 1 , the horizontal axis represents the voltage applied to the ferroelectric layer. The voltage may be, for example, the difference between the potential of one electrode of the capacitor Cfe and the potential of the other electrode of the capacitor Cfe.

[0230] In addition, Fig. 14B In FIG. 1 , the vertical axis represents the polarization of the ferroelectric layer. When the polarization is positive, it means that the positive charge is biased toward one electrode side of the capacitor Cfe and the negative charge is biased toward the other electrode side of the capacitor Cfe. On the other hand, when the polarization is negative, it means that the positive charge is biased toward the other electrode side of the capacitor Cfe and the negative charge is biased toward one electrode side of the capacitor Cfe.

[0231] in addition, Fig. 14B The voltage shown on the horizontal axis of the graph may also be the difference between the potential of the other electrode of the capacitor Cfe and the potential of one electrode of the capacitor Cfe. Fig. 14B The polarization shown on the vertical axis of the graph can also be positive when the positive charge is biased towards the other electrode side of the capacitor Cfe and the negative charge is biased towards one electrode side of the capacitor Cfe, and can be negative when the positive charge is biased towards one electrode side of the capacitor Cfe and the negative charge is biased towards the other electrode side of the capacitor Cfe.

[0232] like Fig. 14B As shown, the hysteresis characteristics of the ferroelectric layer can be represented by curves 51 and 52. The voltage at the intersection of curves 51 and 52 is VSP and -VSP. It can be said that VSP and -VSP have different polarities.

[0233] When the voltage applied to the ferroelectric layer is increased after a voltage below -VSP is applied to the ferroelectric layer, the polarization of the ferroelectric layer increases according to curve 51. On the other hand, when the voltage applied to the ferroelectric layer is decreased after a voltage above VSP is applied to the ferroelectric layer, the polarization of the ferroelectric layer decreases according to curve 52. Therefore, VSP and -VSP can be said to be saturation polarization voltages. Note that, for example, VSP is sometimes referred to as the first saturation polarization voltage and -VSP is sometimes referred to as the second saturation polarization voltage. In addition, Fig. 14B In the embodiment of the present invention, the absolute value of the first saturation polarization voltage and the absolute value of the second saturation polarization voltage are equal, but they may also be different.

[0234] Here, the voltage applied to the ferroelectric layer when the polarization of the ferroelectric layer is "0" when the polarization of the ferroelectric layer changes according to the curve 51 is recorded as Vc. In addition, the voltage applied to the ferroelectric layer when the polarization of the ferroelectric layer is "0" when the polarization of the ferroelectric layer changes according to the curve 52 is recorded as -Vc. Vc and -Vc can be said to be coercive voltages. It can be said that the Vc value and the -Vc value are values ​​between -VSP and VSP. Note that, for example, sometimes Vc is called the first coercive voltage and -Vc is called the second coercive voltage. In addition, Fig. 14B The absolute value of the first coercive voltage and the absolute value of the second coercive voltage are equal, but may not be equal.

[0235] The maximum value of polarization when no voltage is applied to the ferroelectric layer is called "remanent polarization Pr", and the minimum value is called "remanent polarization -Pr". The difference between remanent polarization Pr and remanent polarization -Pr is called "remanent polarization 2Pr".

[0236] As described above, the voltage applied to the ferroelectric layer included in the capacitor Cfe can be expressed as the difference between the potential of one electrode of the capacitor Cfe and the potential of the other electrode of the capacitor Cfe. In addition, as described above, the other electrode of the capacitor Cfe is electrically connected to the wiring PL. Therefore, by controlling the potential of the wiring PL, the voltage applied to the ferroelectric layer included in the capacitor Cfe can be controlled.

[0237] An example of a method for driving the semiconductor device 10 used as a memory cell is described. In the following description, the voltage applied to the ferroelectric layer of the capacitor Cfe represents the difference between the potential of one electrode of the capacitor Cfe and the potential of the other electrode (wiring PL) of the capacitor Cfe. The transistor M is an n-channel transistor.

[0238] Fig. 14C 2 is a timing chart showing an example of a driving method of the semiconductor device 10 . Fig. 14C An example of writing binary digital data to the semiconductor device 10 and reading binary digital data from the semiconductor device 10 is shown. Specifically, Fig. 14CThe following example is shown: data "1" is written to the semiconductor device 10 from time T01 to time T02, read and rewritten from time T03 to time T05, read and written to the semiconductor device 10 from time T11 to time T13, read and rewritten from time T14 to time T16, and read and written to the semiconductor device 10 from time T17 to time T19.

[0239] The sense amplifier electrically connected to the wiring BL is supplied with Vref as a reference potential. Fig. 14C In the read operation shown in FIG. 1 , when the potential of the wiring BL is higher than Vref, data "1" is read by the bit line driver circuit. On the other hand, when the potential of the wiring BL is lower than Vref, data "0" is read by the bit line driver circuit.

[0240] From time T01 to time T02, the potential of wiring WL is made high. Thus, transistor M is turned on. In addition, the potential of wiring BL is made Vw. Since transistor M is turned on, the potential of one electrode of capacitor Cfe is made Vw. And, the potential of wiring PL is made GND. Therefore, the voltage applied to the ferroelectric layer of capacitor Cfe becomes "Vw-GND". Thus, data "1" can be written to semiconductor device 10. Therefore, time T01 to time T02 can be said to be the period for writing operation.

[0241] Here, Vw is preferably greater than or equal to VSP, for example, preferably equal to VSP. Note that in this specification, GND is a ground potential, but GND does not necessarily need to be a ground potential as long as the semiconductor device 10 can be driven in a manner that satisfies the purpose of one embodiment of the present invention. For example, when the absolute value of the first saturation polarization voltage is different from the absolute value of the second saturation polarization voltage and the absolute value of the first coercive voltage is different from the absolute value of the second coercive voltage, GND can be a potential other than ground.

[0242] From time T02 to time T03, the potential of wiring BL and the potential of wiring PL are set to GND. As a result, the voltage applied to the ferroelectric layer of capacitor Cfe becomes 0V. From time T01 to time T02, the voltage "Vw-GND" applied to the ferroelectric layer of capacitor Cfe can be greater than VSP, so from time T02 to time T03, the polarization amount of the ferroelectric layer of capacitor Cfe is adjusted according to Fig. 14B The curve 52 shown changes. Therefore, from time T02 to time T03, no polarization reversal occurs in the ferroelectric layer of the capacitor Cfe.

[0243] The potential of the wiring BL and the potential of the wiring PL are set to GND, and then the potential of the wiring WL is set to a low potential. Therefore, the transistor M is turned off. Thus, the writing operation is completed, and the data "1" is retained in the semiconductor device 10. Note that if the polarization reversal does not occur in the ferroelectric layer of the capacitor Cfe, that is, the voltage applied to the ferroelectric layer of the capacitor Cfe is greater than -Vc of the second coercive voltage, the potential of the wiring BL and the wiring PL can be any potential.

[0244] From time T03 to time T04, the potential of wiring WL is made high. Thus, transistor M becomes turned on. In addition, the potential of wiring PL is made Vw. By making the potential of wiring PL Vw, the voltage applied to the ferroelectric layer of capacitor Cfe becomes "GND-Vw". As described above, the voltage applied to the ferroelectric layer of capacitor Cfe from time T01 to time T02 is "Vw-GND". Therefore, polarization reversal occurs in the ferroelectric layer of capacitor Cfe. During polarization reversal, current flows through wiring BL, and the potential of wiring BL is higher than Vref. Thus, the bit line driver circuit can read the data "1" maintained by semiconductor device 10. Therefore, time T03 to time T04 can be said to be a period of reading operation. Note that although it is assumed that Vref is higher than GND and lower than Vw, it can also be higher than Vw, for example.

[0245] Since the above-mentioned readout is a destructive readout, the data "1" held by the semiconductor device 10 disappears. Therefore, from time T04 to time T05, the potential of the wiring BL and the potential of the wiring PL are respectively set to Vw and GND. Therefore, the data "1" can be rewritten to the semiconductor device 10. Therefore, time T04 to time T05 can be said to be a period for rewriting.

[0246] From time T05 to time T11, the potential of the wiring BL and the potential of the wiring PL are set to GND. Then, the potential of the wiring WL is set to a low potential. Thus, the rewriting operation is completed, and the data "1" is retained in the semiconductor device 10.

[0247] From time T11 to time T12, the potential of the wiring WL and the potential of the wiring PL are set to high potential and Vw, respectively. Since the semiconductor device 10 holds data "1", the potential of the wiring BL is higher than Vref, and the data "1" held by the semiconductor device 10 is read out. Therefore, the time from time T11 to time T12 can be said to be a period for performing a read operation.

[0248] From time T12 to time T13, the potential of wiring BL is set to GND. Since transistor M is turned on, the potential of one electrode of capacitor Cfe is set to GND. In addition, the potential of wiring PL is set to Vw. Thus, the voltage applied to the ferroelectric layer of capacitor Cfe becomes "GND-Vw". Therefore, data "0" can be written to semiconductor device 10. Therefore, time T12 to time T13 can be said to be the period for writing.

[0249] From time T13 to time T14, the potential of wiring BL and the potential of wiring PL are set to GND. As a result, the voltage applied to the ferroelectric layer of capacitor Cfe becomes 0V. From time T12 to time T13, the voltage "GND-Vw" applied to the ferroelectric layer of capacitor Cfe can be less than -VSP, so from time T13 to time T14, the polarization amount of the ferroelectric layer of capacitor Cfe is adjusted according to Fig. 14B The curve 51 shown changes. Therefore, from time T13 to time T14, polarization reversal does not occur in the ferroelectric layer of the capacitor Cfe.

[0250] The potential of the wiring BL and the potential of the wiring PL are set to GND, and then the potential of the wiring WL is set to a low potential. Therefore, the transistor M is turned off. Thus, the writing operation is completed, and the data "0" is retained in the semiconductor device 10. Note that if the polarization reversal does not occur in the ferroelectric layer of the capacitor Cfe, that is, the voltage applied to the ferroelectric layer of the capacitor Cfe becomes less than the first coercive voltage Vc, the potential of the wiring BL and the wiring PL can be any potential.

[0251] From time T14 to time T15, the potential of wiring WL is made high. Thus, transistor M becomes turned on. In addition, the potential of wiring PL is made Vw. The potential of wiring PL is made Vw, and thus the voltage applied to the ferroelectric layer of capacitor Cfe becomes "GND-Vw". As described above, the voltage applied to the ferroelectric layer of capacitor Cfe from time T12 to time T13 is "GND-Vw". Therefore, polarization reversal does not occur in the ferroelectric layer of capacitor Cfe. Therefore, the amount of current flowing through wiring BL is smaller than the case where polarization reversal occurs in the ferroelectric layer of capacitor Cfe. Therefore, the rise in the potential of wiring BL is smaller than the case where polarization reversal occurs in the ferroelectric layer of capacitor Cfe, specifically, the potential of wiring BL becomes less than Vref. Thus, the bit line driving circuit can read the data "0" maintained by semiconductor device 10. Therefore, time T14 to time T15 can be said to be the period for reading operation.

[0252] From time T15 to time T16, the potential of the wiring BL and the potential of the wiring PL are set to GND and Vw, respectively. Thus, data "0" can be rewritten to the semiconductor device 10. Therefore, from time T15 to time T16, it can be said that the rewriting operation is performed.

[0253] From time T16 to time T17, the potential of the wiring BL and the potential of the wiring PL are set to GND. Then, the potential of the wiring WL is set to a low potential. Thus, the rewriting operation is completed, and the data “0” is retained in the semiconductor device 10 .

[0254] From time T17 to time T18, the potential of the wiring WL and the potential of the wiring PL are set to high potential and Vw, respectively. Since the semiconductor device 10 holds data "0", the potential of the wiring BL is lower than Vref, and the data "0" held by the semiconductor device 10 is read out. Therefore, the time from time T17 to time T18 can be said to be a period for performing a read operation.

[0255] From time T18 to time T19, the potential of wiring BL is set to Vw. Because transistor M is in the on state, the potential of one electrode of capacitor Cfe is set to Vw. In addition, the potential of wiring PL is set to GND. As a result, the voltage applied to the ferroelectric layer of capacitor Cfe becomes "Vw-GND". Therefore, data "1" can be written to semiconductor device 10. Therefore, time T18 to time T19 can be said to be the period for writing.

[0256] After time T19 , the potential of the wiring BL and the potential of the wiring PL are set to GND. Then, the potential of the wiring WL is set to a low potential. Thus, the writing operation is completed, and the data “1” is retained in the semiconductor device 10 .

[0257] The semiconductor device 10 using the ferroelectric layer for the capacitor Cfe is used as a nonvolatile memory element capable of retaining written information even when power supply is stopped.

[0258] In addition, DRAM (Dynamic Random Access Memory) requires a periodic refresh operation, which increases power consumption. The semiconductor device 10 using the ferroelectric layer for the capacitor Cfe does not require a refresh operation, thereby reducing power consumption.

[0259] In this specification, etc., a memory element or memory circuit including a ferroelectric layer is sometimes referred to as a "ferroelectric memory" or "FE memory". Therefore, the semiconductor device 10 is a ferroelectric memory and also a FE memory. The FE memory can be expected to achieve 1×10 10 More than 1×10 12 More preferably 1×10 15In addition, the FE memory can be expected to achieve an operating frequency of 10 MHz or more, preferably 1 GHz or more.

[0260] In addition, in the FE memory, the residual polarization 2Pr is related to the data retention capability. If the residual polarization 2Pr decreases, the data retention capability decreases. In this specification, etc., the period until the residual polarization 2Pr decreases by 5% (the data retention capability decreases by 5%) is referred to as the "storage retention period". The FE memory can be expected to achieve a storage retention period of more than 10 days, preferably more than 1 year, and more preferably more than 10 years in a temperature environment of 150°C or 200°C.

[0261] In addition, FE memory can also be applied to the cache memory and registers of CPU (Central Processing Unit), GPU (Graphics Processing Unit), etc. By combining the cache memory and registers of CPU with FE memory, Noff-CPU (Nomaly off CPU) can be realized. By combining the cache memory and registers of GPU with FE memory, Noff-GPU (Nomaly off GPU) can be realized.

[0262] This embodiment mode can be combined with other embodiment modes described in this specification as appropriate.

[0263] (Implementation Method 2) In this embodiment, a configuration example of a memory device 300 using the semiconductor device 10 as a memory cell will be described.

[0264] Fig.15A : is a block diagram showing a configuration example of a storage device 300 according to one embodiment of the present invention. Fig.15A The memory device 300 shown includes a driving circuit 21 and a memory array 20. The memory array 20 includes a plurality of semiconductor devices 10. Fig.15A An example is shown in which the memory array 20 includes a plurality of semiconductor devices 10 arranged in a matrix of m rows and n columns (m and n are integers greater than or equal to 2).

[0265] In addition, the rows and columns extend in directions perpendicular to each other. In this embodiment, the Y direction is set as the "row" and the X direction is set as the "column", but the Y direction may be set as the "column" and the X direction may be set as the "row".

[0266] exist Fig.15A, the semiconductor device 10 in the first row and the first column is referred to as semiconductor device 10[1,1], and the semiconductor device 10 in the mth row and the nth column is referred to as semiconductor device 10[m,n]. In addition, in the present embodiment, etc., an arbitrary row is sometimes referred to as "row i". In addition, an arbitrary column is sometimes referred to as "column j". Therefore, i is an integer greater than 1 and less than m, and j is an integer greater than 1 and less than n. In addition, in the present embodiment, etc., the semiconductor device 10 in the i-th row and the j-th column is referred to as semiconductor device 10[i,j]. In the present embodiment, etc., when represented as "i+α" (α is a positive integer or a negative integer), "i+α" is not less than 1 and not greater than m. Similarly, when represented as "j+α", "j+α" is not less than 1 and not greater than n.

[0267] In addition, the memory array 20 includes m wirings WL extending in the row direction (Y direction), m wirings PL extending in the row direction (Y direction), and n wirings BL extending in the Z direction. Note that the n wirings BL extend in the Z direction, but in order to simply illustrate the relationship between the wirings WL and the wirings PL and the wirings BL, Fig.15A It is shown that n wirings BL extend in the column direction (X direction).

[0268] In the present embodiment and the like, the first (first row) wiring WL is represented as wiring WL[1], and the m-th (m-th row) wiring WL is represented as wiring WL[m]. Similarly, the first (first row) wiring PL is represented as wiring PL[1], and the m-th (m-th row) wiring PL is represented as wiring PL[m]. Similarly, the first (first column) wiring BL is represented as wiring BL[1], and the n-th (n-th column) wiring BL is represented as wiring BL[n].

[0269] The semiconductor devices 10 arranged in the i-th row are electrically connected to the i-th row wiring WL (wiring WL[i]) and the i-th row wiring PL (wiring PL[i]). The semiconductor devices 10 arranged in the j-th column are electrically connected to the j-th column wiring BL (wiring BL[j]).

[0270] The drive circuit 21 includes a PSW 22 (power switch), a PSW 23 and a peripheral circuit 31. The peripheral circuit 31 includes a peripheral circuit 41, a control circuit 32 (control circuit) and a voltage generation circuit 33.

[0271] In the storage device 300, the above-mentioned circuits, signals and voltages can be appropriately selected as needed. Alternatively, other circuits or other signals can be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1 and PON2 are signals input from the outside, and signal RDA is a signal output to the outside. Signal CLK is a clock signal.

[0272] In addition, the signal BW, the signal CE and the signal GW are control signals. The signal CE is a chip enable signal, the signal GW is a global write enable signal, and the signal BW is a byte write enable signal. The signal ADDR is an address signal. The signal WDA is write data, and the signal RDA is read data. The signals PON1 and PON2 are power gating control signals. In addition, the signals PON1 and PON2 can also be generated in the control circuit 32.

[0273] The control circuit 32 is a logic circuit that has the function of controlling the overall operation of the storage device 300. For example, the control circuit performs a logic operation on the signal CE, the signal GW, and the signal BW to determine the operation mode (for example, writing operation, reading operation) of the storage device 300. Alternatively, the control circuit 32 generates a control signal for the peripheral circuit 41 to execute the above operation mode.

[0274] The voltage generating circuit 33 has a function of generating a voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 33. For example, when the signal WAKE is applied with an H level signal, the signal CLK is input to the voltage generating circuit 33, and the voltage generating circuit 33 generates a voltage.

[0275] The peripheral circuit 41 is a circuit for writing and reading data to and from the semiconductor device 10. The peripheral circuit 41 includes a row decoder 42, a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, an output circuit 48, and a sense amplifier 46.

[0276] The row decoder 42 and the column decoder 44 have the function of decoding the signal ADDR. The row decoder 42 is a circuit for specifying a row to be accessed, and the column decoder 44 is a circuit for specifying a column to be accessed. The row driver 43 has the function of selecting the wiring WL specified by the row decoder 42. The column driver 45 has the following functions: a function of writing data to the semiconductor device 10; a function of reading data from the semiconductor device 10; a function of holding the read data, etc.

[0277] The input circuit 47 has a function of holding a signal WDA. The data held in the input circuit 47 is output to the column driver 45. The output data of the input circuit 47 is the data (Din) written to the semiconductor device 10. The data (Dout) read from the semiconductor device 10 by the column driver 45 is output to the output circuit 48. The output circuit 48 has a function of holding Dout. In addition, the output circuit 48 has a function of outputting Dout to the outside of the memory device 300. The data output from the output circuit 48 is a signal RDA.

[0278] PSW22 has a function of controlling the supply of VDD to the peripheral circuit 31. PSW23 has a function of controlling the supply of VHM to the row driver 43. Here, the high power supply voltage of the memory device 300 is VDD, and the low power supply voltage is GND (ground potential). In addition, VHM is a high power supply voltage for making the word line high level, which is higher than VDD. The on / off of PSW22 is controlled by the signal PON1, and the on / off of PSW23 is controlled by the signal PON2. Fig.15A In the embodiment, the number of power domains to which VDD is supplied in the peripheral circuit 31 is one, but it may be more than one. In this case, a power switch may be provided for each power domain.

[0279] The driving circuit 21 and the memory array 20 may also be arranged on the same plane. Fig. 15B As shown, a layer including the memory array 20 may be overlapped and arranged directly on the layer including the driving circuit 21. By overlapping the driving circuit 21 and the memory array 20, the signal transmission distance between the driving circuit 21 and the memory array 20 can be shortened. Therefore, the resistance and parasitic capacitance between the driving circuit 21 and the memory array 20 are reduced, and the power consumption and signal delay can be reduced. In addition, the storage device 300 can be miniaturized.

[0280] In addition, Fig. 15B In the example, one layer of the memory array 20 is overlapped on the driving circuit 21 , but multiple layers of the memory array 20 may be overlapped on the driving circuit 21 . Fig. 15C FIG. 2 shows an example in which k layers (k is an integer greater than or equal to 2) of memory array 20 are stacked on drive circuit 21. Fig. 15C In the above, the memory array 20 provided in the first layer is referred to as the memory array 20[1], the memory array 20 provided in the second layer is referred to as the memory array 20[2], and the memory array 20 provided in the kth layer is referred to as the memory array 20[k].

[0281] Fig.16A is a schematic diagram illustrating a configuration example of the storage device 300 . Fig.16AThe memory device 300 shown includes a six-layer memory array 20 disposed on a driving circuit 21. As described above, Fig.16A In the present invention, the memory array 20 set in the third layer is referred to as the memory array 20[3], the memory array 20 set in the fourth layer is referred to as the memory array 20[4], the memory array 20 set in the fifth layer is referred to as the memory array 20[5], and the memory array 20 set in the sixth layer is referred to as the memory array 20[6].

[0282] Each memory array 20 includes a plurality of semiconductor devices 10 arranged in a matrix and wirings WL and PL extending in the Y direction. Note that for simplicity, the wirings WL and PL included in each of the first to fifth memory arrays 20 are omitted in the drawings.

[0283] in addition, Fig.16A The illustrated memory device 300 includes a plurality of wirings BL extending in the Z direction. The wirings BL are formed through the six-layer memory array 20 and are electrically connected to the drive circuit 21. When viewed from the Z direction, the plurality of wirings BL are arranged in a matrix.

[0284] By extending the wiring BL in the Z direction and electrically connecting to the drive circuit 21, the connection distance between the semiconductor device 10 and the drive circuit 21 can be shortened compared to the case where the wiring BL is extended in the X direction or the Y direction. Therefore, the signal transmission distance between the semiconductor device 10 and the drive circuit 21 is reduced, thereby increasing the operating speed of the storage device. In addition, the parasitic capacitance of the wiring BL is reduced, thereby reducing power consumption.

[0285] In addition, in each of the memory arrays 20 of each layer, one of the plurality of semiconductor devices 10 included in the memory array 20 is electrically connected to one of the plurality of wirings BL. Fig.16A In the illustrated memory device 300 , one wiring BL is electrically connected to one semiconductor device 10 in the memory array 20 of each layer, that is, a total of six semiconductor devices 10 .

[0286] In addition, a structure that electrically connects one wiring BL to a plurality of memory cells (semiconductor devices 10) is also called a "memory string". Fig.16A The illustrated memory device 300 includes a plurality of memory strings.

[0287] Fig. 16B yes Fig.16A FIG. 3 is a schematic diagram of a storage string included in the storage device 300 shown in FIG. Fig. 16B In the schematic diagram of the memory string shown in FIG. 1 , the wiring WL and the wiring PL electrically connected to the semiconductor device 10 are omitted. Fig. 16B A portion of the equivalent circuit of the memory string is also shown.

[0288] Fig.17A is a schematic diagram illustrating a configuration example of the storage device 300 . Fig.17A The storage device 300 shown is Fig.16A Therefore, in order to reduce repeated descriptions, the following mainly describes the modified example of the storage device 300. Fig.16A The storage device 300 shown is different.

[0289] Fig.17A The storage device 300 shown is Fig.16A The memory device 300 shown is different in that, in each of the memory arrays 20 of each layer, two of the plurality of semiconductor devices 10 included in the memory array 20 are electrically connected to one of the plurality of wirings BL. That is, one wiring BL is electrically connected to a total of twelve semiconductor devices 10.

[0290] Fig. 17B yes Fig.17A The schematic diagram of the storage string included in the storage device 300 shown in FIG. Fig. 17B A portion of the equivalent circuit of the memory string is also shown.

[0291] Fig.17A The number of wirings BL in the memory device 300 shown may be less than Fig.16A The number of wirings BL in the memory device 300 shown is 0. Therefore, the occupied area of ​​the memory device 300 is reduced.

[0292] In addition, the semiconductor device 10 according to one embodiment of the present invention is an FE memory, which can retain written information for a long period of time even when power is stopped. In addition, since a refresh operation required for DRAM is not required, a memory device 300 with low power consumption can be realized.

[0293] [Structural Example of Semiconductor Device] Fig.18 An example of a cross-sectional structure of a storage device 300 according to one embodiment of the present invention is shown. Fig.18 The memory device 300 shown includes a memory array 20 of k layers above a driving circuit 21. Fig.18 , the memory array 20 as the k-th layer is shown Fig.11 And the structure shown in Fig. 17. In order to reduce repeated description, the description of the memory array 20 of the k-th layer is omitted here.

[0294] also, Fig.182 shows a transistor 400 included in the driving circuit 21. The transistor 400 is provided on a semiconductor substrate 311 and includes: a conductive layer 316 used as a gate, an insulating layer 315 used as a gate insulator, a semiconductor region 313 formed by a portion of the substrate 311; and a low resistance region 314a and a low resistance region 314b used as a source region or a drain region. The transistor 400 can be a p-channel transistor or an n-channel transistor. As the substrate 311, for example, a single crystal silicon substrate can be used.

[0295] Here, in Fig.18 In the transistor 400 shown, the semiconductor region 313 (a part of the substrate 311) forming the channel has a convex shape. In addition, the conductive layer 316 covers the side and top surfaces of the semiconductor region 313 via the insulating layer 315. In addition, the conductive layer 316 can also use a material that adjusts the work function. Because the convex portion of the semiconductor substrate is utilized, this transistor 400 is also called a FIN-type transistor. In addition, an insulator used as a mask for forming the convex portion can also be provided in a manner that contacts the upper surface of the convex portion. In addition, although a case where a part of the semiconductor substrate is processed to form the convex portion is shown here, the SOI substrate can also be processed to form a semiconductor film having a convex shape.

[0296] Notice, Fig.18 The structure of the transistor 400 shown is only an example and is not limited to the above structure. An appropriate transistor may be used according to the circuit structure or driving method.

[0297] A wiring layer including an interlayer film, wiring, and plugs may be provided between the structures. In addition, the wiring layer may be provided in a plurality of layers according to the design. In addition, in this specification, wiring and a plug electrically connected to the wiring may also be one component. That is, a part of the conductor may be used as wiring, and a part of the conductor may be used as a plug.

[0298] For example, an insulating layer 320, an insulating layer 322, an insulating layer 324, and an insulating layer 326 are sequentially stacked as interlayer films over the transistor 400. In addition, conductive layers 328 and 330 electrically connected to the conductive layer 152 are embedded in the insulating layers 320, 322, 324, and 326. The conductive layers 328 and 330 are used as contact plugs or wirings.

[0299] In addition, the insulator used as the interlayer film can be used as a planarization film that covers the concavo-convex shape thereunder. For example, in order to improve the flatness of the top surface of the insulating layer 322, CMP treatment or the like may be performed.

[0300] Alternatively, a wiring layer may be provided over the insulating layer 326 and the conductive layer 330. Fig.18 In the embodiment, an insulating layer 350, an insulating layer 352, and an insulating layer 354 are sequentially stacked on the insulating layer 326 and the conductive layer 330. In addition, a conductive layer 356 is formed in the insulating layer 350, the insulating layer 352, and the insulating layer 354. The conductive layer 356 is used as a contact plug or wiring. The conductive layer 356 is electrically connected to the conductive layer 152.

[0301] This embodiment mode can be combined with other embodiment modes described in this specification as appropriate.

[0302] (Implementation method 3) In this embodiment, a metal oxide (hereinafter, also referred to as an oxide semiconductor) which can be used for the OS transistor described in the above embodiment will be described.

[0303] The metal oxide used for the OS transistor preferably contains at least indium or zinc, and more preferably contains indium and zinc. For example, the metal oxide preferably contains indium, M (M is one or more selected from gallium, aluminum, yttrium, tin, silicon, boron, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium and cobalt) and zinc. In particular, M is preferably one or more selected from gallium, aluminum, yttrium, antimony and tin, and more preferably gallium.

[0304] The metal oxide can be formed by a chemical vapor deposition method (CVD: Chemical Vapor Deposition) such as a sputtering method, a metal organic chemical vapor deposition (MOCVD: Metal Organic Chemical Vapor Deposition) method, or an atomic layer deposition method.

[0305] Hereinafter, an oxide containing indium (In), gallium (Ga), and zinc (Zn) will be described as an example of a metal oxide. Note that an oxide containing indium (In), gallium (Ga), and zinc (Zn) may be referred to as an In-Ga-Zn oxide.

[0306] <Classification of Crystal Structure> Examples of the crystalline structure of an oxide semiconductor include amorphous (including completely amorphous), CAAC (c-axis-aligned crystalline), nc (nanocrystalline), CAC (cloud-aligned composite), single crystal, and polycrystalline.

[0307] The crystalline structure of a film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum. For example, an XRD spectrum measured using GIXD (Grazing-Incidence XRD) can be used for evaluation. In addition, the GIXD method is also referred to as a thin film method or a Seemann-Bohlin method. Hereinafter, the XRD spectrum measured using GIXD is sometimes simply referred to as an XRD spectrum.

[0308] For example, the peak shape of the XRD spectrum of a quartz glass substrate is roughly bilaterally symmetrical. On the other hand, the peak shape of the XRD spectrum of an In-Ga-Zn oxide film having a crystalline structure is bilaterally asymmetrical. The fact that the peak shape of the XRD spectrum is bilaterally asymmetrical indicates that there is crystal in the film or substrate. In other words, unless the peak shape of the XRD spectrum is bilaterally symmetrical, it cannot be said that the film or substrate is in an amorphous state.

[0309] In addition, the crystal structure of the film or substrate can be evaluated using a diffraction pattern observed by nanobeam electron diffraction (NBED: Nano Beam Electron Diffraction) (also called a nanobeam electron diffraction pattern). For example, a halo is observed in the diffraction pattern of a quartz glass substrate, and it can be confirmed that the quartz glass is in an amorphous state. In addition, a spot-like pattern is observed in the diffraction pattern of an In-Ga-Zn oxide film deposited at room temperature, but no halo is observed. Therefore, it can be inferred that the In-Ga-Zn oxide deposited at room temperature is in an intermediate state that is neither single crystal or polycrystalline nor amorphous, and it cannot be concluded that the In-Ga-Zn oxide is amorphous.

[0310] [Structure of oxide semiconductor] In addition, when focusing on the structure of oxide semiconductors, the classification of oxide semiconductors is sometimes different from the above. For example, oxide semiconductors can be classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors other than single-crystal oxide semiconductors. As non-single-crystal oxide semiconductors, for example, the above-mentioned CAAC-OS and nc-OS can be cited. In addition, non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, a-like OS (amorphous-like oxide semiconductor) and amorphous oxide semiconductors.

[0311] Here, the details of the above-mentioned CAAC-OS, nc-OS and a-like OS are explained.

[0312] [CAAC-OS] CAAC-OS is an oxide semiconductor having a plurality of crystalline regions, wherein the c-axis of the plurality of crystalline regions is oriented in a specific direction. In addition, the specific direction refers to the thickness direction of the CAAC-OS film, the normal direction of the formed surface of the CAAC-OS film, or the normal direction of the surface of the CAAC-OS film. In addition, the crystalline region is a region having a periodic atomic arrangement. Note that when the atomic arrangement is regarded as a lattice arrangement, the crystalline region is also a region having a consistent lattice arrangement. Furthermore, CAAC-OS has a region where a plurality of crystalline regions are connected in the ab plane direction, and sometimes the region has distortion. In addition, distortion refers to a portion where the direction of the lattice arrangement changes between a region having a consistent lattice arrangement and other regions having a consistent lattice arrangement in a region where a plurality of crystalline regions are connected. In other words, CAAC-OS refers to an oxide semiconductor having a c-axis orientation and having no obvious orientation in the ab plane direction.

[0313] In addition, each of the above-mentioned multiple crystallization regions is composed of one or more tiny crystals (crystallizations with a maximum diameter less than 10 nm). In the case where a crystallization region is composed of one tiny crystal, the maximum diameter of the crystallization region is less than 10 nm. In addition, in the case where a crystallization region is composed of multiple tiny crystals, the maximum diameter of the crystallization region is sometimes about tens of nm.

[0314] In addition, in In-Ga-Zn oxide, CAAC-OS has a tendency to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter, In layer) and a layer containing gallium (Ga), zinc (Zn) and oxygen (hereinafter, (Ga, Zn) layer) are stacked. In addition, indium and gallium can replace each other. Therefore, sometimes the (Ga, Zn) layer contains indium. In addition, sometimes the In layer contains gallium. Note that sometimes the In layer contains zinc. This layered structure is observed as a lattice image in a high-resolution TEM (Transmission Electron Microscope) image, for example.

[0315] For example, when the CAAC-OS film is structurally analyzed using an XRD device, a peak indicating c-axis orientation is detected at or near 2θ = 31 degrees in Out-of-plane XRD measurement using θ / 2θ scanning. Note that the position (2θ value) of the peak indicating c-axis orientation sometimes varies depending on the type and composition of the metal elements constituting the CAAC-OS.

[0316] In addition, for example, multiple bright spots (spots) are observed in the electron diffraction pattern of the CAAC-OS film. In addition, when the spot of the incident electron beam passing through the sample (also called the direct spot) is used as the symmetry center, a certain spot and other spots are observed at point-symmetrical positions.

[0317] When observing the crystallized region from the above-mentioned specific direction, although the lattice arrangement in the crystallized region is basically a hexagonal lattice, the unit lattice is not limited to a regular hexagon, and there are cases where it is a non-regular hexagon. In addition, in the above-mentioned distortion, sometimes there is a pentagonal, heptagonal, and other lattice arrangement. In addition, no clear grain boundary is observed near the distortion of CAAC-OS. In other words, the distortion of the lattice arrangement inhibits the formation of grain boundaries. This may be because CAAC-OS can accommodate distortion due to the low density of the arrangement of oxygen atoms in the ab plane direction or the change in the bonding distance between atoms due to the substitution of metal atoms.

[0318] In addition, a crystalline structure in which clear grain boundaries are confirmed is called a so-called polycrystalline. The grain boundaries become recombination centers and carriers are captured, which may lead to a decrease in the on-state current of the transistor, a decrease in field effect mobility, etc. Therefore, CAAC-OS, in which no clear grain boundaries are confirmed, is one of the crystalline oxides that give the semiconductor layer of the transistor an excellent crystalline structure. Note that in order to form CAAC-OS, a structure containing Zn is preferably used. For example, In-Zn oxide and In-Ga-Zn oxide can suppress the generation of grain boundaries more than In oxide, so they are preferred.

[0319] CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries can be confirmed. Therefore, it can be said that in CAAC-OS, a decrease in electron mobility due to grain boundaries is not likely to occur. In addition, the crystallinity of an oxide semiconductor is sometimes reduced due to the mixing of impurities and / or the generation of defects, so it can be said that CAAC-OS is an oxide semiconductor with few impurities and defects (oxygen vacancies, etc.). Therefore, the physical properties of the oxide semiconductor including CAAC-OS are stable. Therefore, the oxide semiconductor including CAAC-OS has high heat resistance and high reliability. In addition, CAAC-OS is also stable to high temperatures (so-called thermal budget) in the manufacturing process. Therefore, when CAAC-OS is used for OS transistors, the degree of freedom of the manufacturing process can be expanded.

[0320] [nc-OS] In nc-OS, the atomic arrangement in a tiny region (for example, a region of 1 nm or more and 10 nm or less, especially a region of 1 nm or more and 3 nm or less) is periodic. In other words, nc-OS has tiny crystals. In addition, for example, the size of the tiny crystal is 1 nm or more and 10 nm or less, especially 1 nm or more and 3 nm or less, and the tiny crystal is called a nanocrystal. In addition, no regularity of crystal orientation is observed between different nanocrystals in nc-OS. Therefore, no orientation is observed in the entire film. Therefore, sometimes nc-OS is no different from a-like OS and amorphous oxide semiconductors in certain analysis methods. For example, when an XRD device is used to perform structural analysis on an nc-OS film, no peak indicating crystallinity is detected in the Out-of-plane XRD measurement using θ / 2θ scanning. In addition, when an electron diffraction (also called selected area electron diffraction) is performed on the nc-OS film using an electron beam whose beam diameter is larger than that of a nanocrystal (for example, 50 nm or more), a diffraction pattern similar to a halo pattern is observed. On the other hand, when the nc-OS film is subjected to electron diffraction using an electron beam whose beam diameter is close to or smaller than the size of the nanocrystal (for example, greater than 1 nm and less than 30 nm) (also called nanobeam electron diffraction), an electron diffraction pattern is sometimes obtained in which multiple spots are observed in a ring-shaped area centered on the direct spot.

[0321] [a-like OS] A-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductor. A-like OS contains voids or low-density regions. In other words, the crystallinity of a-like OS is lower than that of nc-OS and CAAC-OS. In addition, the hydrogen concentration in the film of a-like OS is higher than that in the film of nc-OS and CAAC-OS.

[0322] [Composition of oxide semiconductor] Next, the details of the above-mentioned CAC-OS will be described. In addition, CAC-OS is related to the material composition.

[0323] [CAC-OS] CAC-OS refers to, for example, a structure in which elements contained in a metal oxide are unevenly distributed, wherein the size of the material containing the unevenly distributed elements is greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 3 nm, or a similar size. Note that in the following, a state in which one or more metal elements are unevenly distributed in a metal oxide and regions containing the metal elements are mixed is also referred to as a mosaic or patch shape, and the size of the region is greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 3 nm, or a similar size.

[0324] Furthermore, CAC-OS refers to a composite metal oxide having a structure in which the material is divided into a first region and a second region to form a mosaic shape and the first region is distributed in the film (hereinafter also referred to as a cloud shape). That is, CAC-OS refers to a composite metal oxide having a structure in which the first region and the second region are mixed.

[0325] Here, each of the atomic ratios of In, Ga, and Zn relative to the metal elements constituting the CAC-OS of the In-Ga-Zn oxide is recorded as [In], [Ga], and [Zn]. For example, in the CAC-OS of the In-Ga-Zn oxide, the first region is a region where [In] is greater than [In] in the composition of the CAC-OS film. In addition, the second region is a region where [Ga] is greater than [Ga] in the composition of the CAC-OS film. In addition, for example, the first region is a region where [In] is greater than [In] in the second region and [Ga] is less than [Ga] in the second region. In addition, the second region is a region where [Ga] is greater than [Ga] in the first region and [In] is less than [In] in the first region.

[0326] Specifically, the first region is a region with indium oxide or indium zinc oxide as a main component. In addition, the second region is a region with gallium oxide or gallium zinc oxide as a main component. In other words, the first region can be referred to as a region with In as a main component. In addition, the second region can be referred to as a region with Ga as a main component.

[0327] Note that a clear boundary between the first region and the second region may not be observed.

[0328] In addition, CAC-OS in In-Ga-Zn oxide refers to a structure in which a part of the main component of Ga and a part of the main component of In exist irregularly in a mosaic shape in a material structure containing In, Ga, Zn, and O. Therefore, it can be inferred that CAC-OS has a structure in which metal elements are unevenly distributed.

[0329] CAC-OS can be formed, for example, by sputtering without intentionally heating the substrate. When CAC-OS is formed by sputtering, as the deposition gas, any one or more selected from an inert gas (typically argon), an oxygen gas, and a nitrogen gas can be used. In addition, the lower the flow rate ratio of the oxygen gas in the total flow rate of the deposition gas during deposition, the better. For example, the flow rate ratio of the oxygen gas in the total flow rate of the deposition gas during deposition is made greater than 0% and less than 30%, preferably greater than 0% and less than 10%.

[0330] For example, in the CAC-OS of In-Ga-Zn oxide, according to the EDX surface analysis (mapping) image obtained by energy dispersive X-ray spectroscopy (EDX), a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed can be confirmed.

[0331] Here, the first region is a region with higher conductivity than the second region. That is, when carriers flow through the first region, it exhibits the conductivity of a metal oxide. Therefore, when the first region is distributed in a cloud shape in the metal oxide, a high field-effect mobility (μ) can be achieved.

[0332] On the other hand, the second region is a region with higher insulation than the first region. That is, when the second region is distributed in the metal oxide, leakage current can be suppressed.

[0333] When CAC-OS is used for a transistor, through the complementary action due to the conductivity of the first region and the insulation of the second region, CAC-OS can be made to have a switching function (a function of controlling on / off). In other words, a part of the material of CAC-OS has a conductive function and another part has an insulating function, and the whole material has the function of a semiconductor. By separating the conductive function and the insulating function, each function can be maximized. Therefore, by using CAC-OS for a transistor, a large on-state current (I on )、high field-effect mobility (μ) and good switching operation can be achieved.

[0334] In addition, a transistor using CAC-OS has high reliability. Therefore, CAC-OS is most suitable for various semiconductor devices such as display devices.

[0335] Oxide semiconductors have various structures and various properties. The oxide semiconductor of one aspect of the present invention may also include two or more of amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0336] <OS Transistor> By using the metal oxide (oxide semiconductor) of one aspect of the present invention for a transistor, a transistor with high field-effect mobility can be achieved. In addition, a transistor with high reliability can be achieved. In addition, a miniaturized or highly integrated transistor can be achieved. For example, a transistor with a channel length of 2 nm or more and 30 nm or less can be manufactured.

[0337] In addition, it is preferable to use an oxide semiconductor with a low carrier concentration in the channel formation region of the transistor. For example, the carrier concentration in the channel formation region of the oxide semiconductor can be 1×10 18 cm -3 Below, preferably 1×10 17 cm -3 Less than, more preferably 1×10 15 cm -3 Below, more preferably 1×10 13 cm -3 Below, more preferably 1×10 11 cm -3 Below, and more preferably below 1×10 10 cm -3 , and is 1×10 -9 cm -3 In the case of reducing the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film can be reduced to reduce the defect state density. In this specification, etc., a state in which the impurity concentration is low and the defect state density is low is referred to as high-purity intrinsic or substantially high-purity intrinsic. In addition, an oxide semiconductor with a low carrier concentration is sometimes referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0338] Since a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has a lower defect state density, it is possible to have a lower trap state density.

[0339] Furthermore, it takes a long time for charges trapped in trap states of an oxide semiconductor to disappear, and they may behave like fixed charges. Therefore, the electrical characteristics of a transistor having a channel formation region formed in an oxide semiconductor with a high trap state density may be unstable.

[0340] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the nearby film. As impurities, hydrogen, carbon, nitrogen, etc. can be cited. Note that impurities in oxide semiconductors refer to, for example, elements other than the main components that constitute the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be said to be an impurity.

[0341] The band gap of the oxide semiconductor is preferably larger than the band gap of silicon (typically 1.1 eV), preferably 2 eV or more, more preferably 2.5 eV or more, and further preferably 3.0 eV or more. By using an oxide semiconductor with a large band gap, the off-state current (also called Ioff) of the transistor can be reduced.

[0342] In addition, in Si transistors (transistors using silicon in the semiconductor layer forming the channel), the short channel effect (Short Channel Effect, also known as SCE) appears as the miniaturization of transistors develops. Therefore, the miniaturization of Si transistors is difficult. One of the reasons for the short channel effect is that the band gap of silicon is small. On the other hand, in OS transistors, oxide semiconductors are used as semiconductor materials with a large band gap, so the short channel effect can be suppressed. In other words, OS transistors are transistors with no short channel effect or very little short channel effect.

[0343] The short channel effect refers to the degradation of electrical characteristics that occurs with the miniaturization of transistors (reduction of channel length). Specific examples of the short channel effect include a reduction in threshold voltage, an increase in subthreshold swing value (sometimes recorded as S value), and an increase in leakage current. Here, the S value refers to the change in gate voltage in the subthreshold region that changes the drain current value by one digit with a fixed drain voltage.

[0344] As an indicator of resistance to short channel effects, characteristic length is widely used. Characteristic length refers to an indicator of the curvature of the potential in the channel formation region. The smaller the characteristic length, the more rapidly the potential rises, so it can be said that the resistance to short channel effects is high.

[0345] OS transistors are accumulation-type transistors, and Si transistors are inversion-type transistors. Therefore, compared with Si transistors, the characteristic length between the source region and the channel formation region and the characteristic length between the drain region and the channel formation region in OS transistors are smaller. Therefore, OS transistors have a higher ability to resist short channel effects than Si transistors. That is, when you want to manufacture transistors with a small channel length, OS transistors are more suitable than Si transistors.

[0346] Even when the carrier concentration of the oxide semiconductor is reduced to the point where the channel formation region is i-type or substantially i-type, the conduction band bottom of the channel formation region is lowered due to the conduction-band-lowering (CBL) effect in the short channel transistor, so the energy difference of the conduction band bottom between the source region or the drain region and the channel formation region is likely to be reduced to more than 0.1 eV and less than 0.2 eV. Thus, the OS transistor can be regarded as having n + / n - / n + The accumulation type junctionless transistor structure or n + / n - / n + The accumulation type non-junction transistor structure, in which the channel formation region is n - Type region, source region and drain region are n+ Type region.

[0347] When the above structure is adopted for the OS transistor, good electrical characteristics can be achieved even when the semiconductor device is miniaturized or highly integrated. For example, even when the channel length or gate length of the OS transistor is 20 nm or less, 15 nm or less, 10 nm or less, 7 nm or less, or 6 nm or less and 1 nm or more, 3 nm or more, or 5 nm or more, good electrical characteristics can be obtained. On the other hand, in the Si transistor, it is sometimes difficult to have a gate length of 20 nm or less or 15 nm or less because of the short-channel effect. Therefore, compared with the Si transistor, the OS transistor is more suitable for use as a transistor with a small channel length. Note that the gate length refers to the gate electrode length in the direction in which carriers migrate in the channel formation region during transistor operation.

[0348] In addition, by miniaturizing the OS transistor, the high-frequency characteristics of the transistor can be improved. Specifically, the cut-off frequency of the transistor can be increased. When the gate length of the OS transistor is within the above range, for example, at room temperature, the cut-off frequency of the transistor can be 50 GHz or more, preferably 100 GHz or more, and more preferably 150 GHz or more.

[0349] As described above, the OS transistor has excellent effects compared with the Si transistor, such as a small off-state current and the ability to fabricate a transistor with a small channel length.

[0350] <Impurities in OS> Here, the effects of various impurities in the metal oxide (oxide semiconductor) are described.

[0351] When the oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect states are formed in the oxide semiconductor. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 20 atoms / cm 3 or less, preferably 5×10 19 atoms / cm 3 or less, more preferably 3×10 19 atoms / cm 3 or less, further preferably 1×10 19 atoms / cm 3 or less, even more preferably 3×10 18 atoms / cm 3 or less, still further preferably 1×10 18 atoms / cm 3 or less. In addition, the silicon concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×1020 atoms / cm 3 Below, preferably 5×10 19 atoms / cm 3 Less than, more preferably 3×10 19 atoms / cm 3 Below, more preferably 1×10 19 atoms / cm 3 Below, more preferably 3×10 18 atoms / cm 3 Below, and more preferably 1×10 18 atoms / cm 3 the following.

[0352] When an oxide semiconductor contains nitrogen, electrons are generated as carriers, which increases the carrier concentration and is easily converted to n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have a normally-on characteristic. Alternatively, when an oxide semiconductor contains nitrogen, a trap state is sometimes formed. As a result, the electrical characteristics of the transistor are sometimes unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 20 atoms / cm 3 Below, preferably 5×10 19 atoms / cm 3 Less than, more preferably 1×10 19 atoms / cm 3 Below, more preferably 5×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 Below, and more preferably 5×10 17 atoms / cm 3 the following.

[0353] In addition, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to generate water, so oxygen vacancies are sometimes formed. When hydrogen enters the oxygen vacancy, electrons as carriers are sometimes generated. In addition, sometimes electrons as carriers are generated because part of the hydrogen is bonded to oxygen bonded to metal atoms. Therefore, transistors using oxide semiconductors containing hydrogen tend to have normally-on characteristics. Therefore, it is preferred to reduce the hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to less than 1×10 20 atoms / cm 3 , preferably less than 5×10 19atoms / cm 3 , more preferably less than 1×10 19 atoms / cm 3 , and more preferably less than 5×10 18 atoms / cm 3 , and further preferably less than 1×10 18 atoms / cm 3 .

[0354] In addition, when the oxide semiconductor contains an alkali metal or an alkaline earth metal, a defect state is sometimes formed to form a carrier. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have a normally-on characteristic. Thus, the concentration of the alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor measured by SIMS analysis is set to 1×10 18 atoms / cm 3 Below, preferably 2×10 16 atoms / cm 3 the following.

[0355] By using an oxide semiconductor in which impurities are sufficiently reduced for a channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0356] This embodiment mode can be combined with other embodiment modes described in this specification as appropriate.

[0357] (Implementation 4) In this embodiment, refer to Fig.19A and Fig.19B An example of a chip 1200 on which the semiconductor device of the present invention is mounted will be described. A plurality of circuits (systems) are mounted on the chip 1200. In this way, a technology of integrating a plurality of circuits (systems) on one chip is sometimes referred to as a system on chip (SoC).

[0358] like Fig.19A As shown, the chip 1200 includes a CPU 1211, a GPU 1212, one or more simulation operation units 1213, one or more storage controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0359] Bumps (not shown) are provided on the chip 1200. Fig.19B As shown in FIG. 1 , the first surface of the package substrate 1201 is connected to the first surface of the package substrate 1201 . In addition, a plurality of bumps 1202 are provided on the back side of the first surface of the package substrate 1201 , and the bumps 1202 are connected to the motherboard 1203 .

[0360] Furthermore, a storage device such as a storage device 1221 or a flash memory 1222 may be provided on the motherboard 1203. For example, the semiconductor device 10 may be applied to the storage device 1221. Alternatively, for example, the semiconductor device 10 may be used instead of the flash memory 1222.

[0361] The CPU 1211 preferably has a plurality of CPU cores. In addition, the GPU 1212 preferably has a plurality of GPU cores. In addition, the CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory commonly used by the CPU 1211 and the GPU 1212 may be provided on the chip 1200. The semiconductor device 10 may be applied to the memory. In addition, the GPU 1212 is suitable for parallel calculation of a plurality of data, which may be used for image processing or product-sum operations. By providing an image processing circuit or a product-sum operation circuit using an oxide semiconductor as the GPU 1212, image processing and product-sum operations may be performed with low power consumption.

[0362] In addition, since CPU1211 and GPU1212 are provided on the same chip, the wiring between CPU1211 and GPU1212 can be shortened, and data can be transferred from CPU1211 to GPU1212, data can be transferred between memories possessed by CPU1211 and GPU1212, and calculation results can be transferred from GPU1212 to CPU1211 after calculations in GPU1212 are completed at high speed.

[0363] The analog operation unit 1213 includes one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. In addition, the analog operation unit 1213 may also include the above-mentioned product-sum operation circuit.

[0364] The storage controller 1214 has a circuit that functions as a controller of the storage device 1221 and a circuit that functions as an interface of the flash memory 1222 .

[0365] The interface 1215 has an interface circuit with external connection devices such as a display device, a speaker, a microphone, a camera, a controller, etc. The controller includes a mouse, a keyboard, a game console controller, etc. As the above-mentioned interface, USB (Universal Serial Bus), HDMI (High-Definition Multimedia Interface) (registered trademark), etc. can be used.

[0366] The network circuit 1216 includes a network circuit such as a LAN (Local Area Network) and may also include a network security circuit.

[0367] The above circuits (systems) can be formed on the chip 1200 through the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at a low cost.

[0368] The motherboard 1203 including the package substrate 1201 provided with the chip 1200 having the GPU 1212 , the storage device 1221 , and the flash memory 1222 may be referred to as a GPU module 1204 .

[0369] The GPU module 1204 can reduce its size due to having the chip 1200 using SoC technology. In addition, the GPU module 1204 is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop personal computers, and portable (portable) game consoles due to its high image processing capabilities. In addition, by utilizing a product-sum operation circuit using the GPU 1212, methods such as deep neural networks (DNNs), convolutional neural networks (CNNs), recursive neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep belief networks (DBNs) can be performed, thereby enabling the chip 1200 to be used as an AI chip, or the GPU module 1204 can be used as an AI system module.

[0370] This embodiment mode can be combined with other embodiment modes described in this specification as appropriate.

[0371] (Implementation method 5) This embodiment mode shows an example of an electronic component in which the semiconductor device or the like described in the above embodiment modes is mounted.

[0372] <Electronic components> Fig. 20A The electronic component 700 and a substrate (circuit board 704 ) on which the electronic component 700 is mounted are shown in a perspective view. Fig. 20A The electronic component 700 shown includes a storage device 720 within a mold 711. Fig. 20A 700 is partially omitted to show the inside thereof. The electronic component 700 includes a land 712 on the outside of the mold 711. The land 712 is electrically connected to an electrode pad 713, and the electrode pad 713 is electrically connected to a storage device 720 via a lead 714. The electronic component 700 is mounted on, for example, a printed circuit board 702. By combining a plurality of the electronic components and electrically connecting them on the printed circuit board 702, a circuit board 704 is completed.

[0373] The storage device 720 includes a drive circuit layer 721 and a storage circuit layer 722. The storage device 720 can use the storage device 300 according to one embodiment of the present invention. Therefore, it can be said that the drive circuit layer 721 is a layer including the drive circuit 21. In addition, the storage circuit layer 722 can use a single-layer or multi-layer memory array 20. Therefore, it can be said that the drive circuit layer 721 is a layer including the memory array 20.

[0374] Fig. 20B The figure shows a perspective view of an electronic component 730. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi Chip Module). In the electronic component 730, an interposer 731 is provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of storage devices 720 are provided on the interposer 731.

[0375] The electronic component 730 shows an example in which the storage device 720 is used as a high bandwidth memory (HBM). In addition, the semiconductor device 735 can use an integrated circuit (semiconductor device) such as a CPU, a GPU, or an FPGA.

[0376] The package substrate 732 may be a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like. The interposer 731 may be a silicon interposer, a resin interposer, or the like.

[0377] The plug board 731 has a plurality of wirings and has the function of electrically connecting a plurality of integrated circuits with different terminal spacings. The plurality of wirings are composed of a single layer or a plurality of layers. In addition, the plug board 731 has the function of electrically connecting the integrated circuit disposed on the plug board 731 to the electrode disposed on the package substrate 732. Therefore, the plug board is sometimes also referred to as a "rewiring substrate" or "intermediate substrate". In addition, sometimes a through electrode is provided in the plug board 731, and the integrated circuit is electrically connected to the package substrate 732 through the through electrode. In addition, in the case of using a silicon plug board, TSV (Through Silicon Via: silicon through hole) can also be used as a through electrode.

[0378] A silicon interposer is preferably used as the interposer 731. Since a silicon interposer does not need to be provided with active elements, it can be manufactured at a lower cost than an integrated circuit. On the other hand, the wiring formation of the silicon interposer can be performed in a semiconductor process, so it is easy to form fine wiring that is difficult to form when using a resin interposer.

[0379] In HBM, many wirings need to be connected to achieve a wide memory bandwidth. For this reason, it is required that fine wirings can be formed at a high density on the interposer on which the HBM is mounted. Therefore, a silicon interposer is preferably used as the interposer on which the HBM is mounted.

[0380] In addition, in SiP or MCM using a silicon interposer, the reliability degradation caused by the difference in expansion coefficient between the integrated circuit and the interposer is not likely to occur. In addition, since the surface flatness of the silicon interposer is high, poor connection is not likely to occur between the integrated circuit disposed on the silicon interposer and the silicon interposer. It is particularly preferred to use the silicon interposer for 2.5D packaging (2.5D mounting) in which a plurality of integrated circuits are arranged horizontally and disposed on the interposer.

[0381] In addition, a heat sink (heat sink plate) may be provided so as to overlap with the electronic component 730. When a heat sink is provided, it is preferable to make the height of the integrated circuits provided on the interposer 731 consistent. For example, in the electronic component 730 shown in this embodiment, it is preferable to make the height of the storage device 720 and the semiconductor device 735 consistent.

[0382] In order to mount the electronic component 730 on another substrate, an electrode 733 may be provided on the bottom of the package substrate 732 . Fig. 20B An example of forming the electrode 733 using solder balls is shown. By arranging solder balls in a matrix at the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrode 733 can be formed using conductive pins. By arranging conductive pins in a matrix at the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0383] The electronic component 730 can be mounted on other substrates by various mounting methods, not limited to BGA and PGA. For example, a mounting method such as SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), or QFN (Quad Flat Non-leaded package) can be used.

[0384] This embodiment mode can be combined with other embodiment modes described in this specification as appropriate.

[0385] (Implementation method 6) In this embodiment, application examples of a semiconductor device according to one embodiment of the present invention are described.

[0386] The semiconductor device according to one embodiment of the present invention can be applied to storage devices of various electronic devices (e.g., information terminals, computers, smart phones, e-book reader terminals, digital still cameras, video cameras, video playback devices, navigation systems, game consoles, etc.). In addition, it can also be applied to image sensors, IoT (Internet of Things), and medical equipment. Here, computers include tablet computers, notebook computers, desktop computers, and large computers such as server systems.

[0387] An example of an electronic device including a semiconductor device according to one embodiment of the present invention will be described. FIG. 21A to FIG. 21J , FIG. 22A to FIG. 22E The electronic component 700 or the electronic component 730 including the semiconductor device is shown as being included in each electronic device.

[0388] [Mobile phone] Fig.21A The information terminal 5500 shown is a mobile phone (smartphone) which is one of the information terminals. The information terminal 5500 includes a housing 5510 and a display portion 5511 . The display portion 5511 includes a touch panel as an input interface, and buttons are provided on the housing 5510 .

[0389] By using the semiconductor device according to one embodiment of the present invention in the information terminal 5500 , temporary files generated when a program is executed (for example, cache when a web browser is used) can be stored.

[0390] [Wearable terminal] also, Fig. 21B An information terminal 5900 as an example of a wearable terminal is shown. The information terminal 5900 includes a housing 5901, a display portion 5902, an operation switch 5903, an operation switch 5904, a strap 5905, and the like.

[0391] Similar to the above-described information terminal 5500 , by applying the semiconductor device according to one embodiment of the present invention to a wearable terminal, a temporary file generated when a program is executed can be retained.

[0392] [Information Terminal] Fig. 21C 1 shows a desktop information terminal 5300. The desktop information terminal 5300 includes an information terminal body 5301, a display portion 5302, and a keyboard 5303.

[0393] Similar to the above-described information terminal 5500 , by applying the semiconductor device according to one embodiment of the present invention to the desktop information terminal 5300 , temporary files generated when a program is executed can be stored.

[0394] Note that in the above description, FIG. 21A to FIG. 21C A smartphone, a wearable terminal, and a desktop information terminal are shown as examples of electronic devices, but information terminals other than smartphones, wearable terminals, and desktop information terminals may also be applied. Examples of information terminals other than smartphones, wearable terminals, and desktop information terminals include PDAs (Personal Digital Assistants), notebook information terminals, and workstations.

[0395] [Electrical products] also, Fig.21D An electric refrigerator-freezer 5800 is shown as an example of an electric appliance. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, etc. For example, the electric refrigerator-freezer 5800 is an electric refrigerator-freezer that supports IoT (Internet of Things).

[0396] The semiconductor device according to one embodiment of the present invention can be applied to an electric refrigerator-freezer 5800. By using the Internet or the like, the electric refrigerator-freezer 5800 can send information such as food stored in the electric refrigerator-freezer 5800 or the expiration date of the food to an information terminal or the like. The electric refrigerator-freezer 5800 can store a temporary file generated when sending the information in the semiconductor device.

[0397] In the above example, an electric refrigerator-freezer is described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, IH cookers, water dispensers, air conditioners including heating and cooling units, washing machines, dryers, audio-visual equipment, etc.

[0398] [Game console] also, Fig.21E A portable game machine 5200 as an example of a game machine is shown. The portable game machine 5200 includes a housing 5201, a display portion 5202, buttons 5203, and the like.

[0399] also, Fig.21F The fixed game machine 7500 is an example of a game machine. The fixed game machine 7500 includes a main body 7520 and a controller 7522. The main body 7520 can be connected to the controller 7522 in a wireless manner or a wired manner. Fig.21F Although not shown in the figure, the controller 7522 may include a display unit for displaying game images, a touch panel and a joystick as an input interface other than buttons, a rotating grip or a sliding grip, etc. In addition, the controller 7522 is not limited to Fig.21FThe shape of the controller 7522 can be changed according to the type of game. For example, in shooting games such as FPS (First Person Shooter), a controller that imitates the shape of a gun can be used as a trigger button. In addition, for example, in music games, a controller that imitates the shape of a musical instrument or a musical device can be used. Furthermore, a fixed game machine can also be provided with a camera, a depth sensor, a microphone, etc., and the game player's gestures or voice operations can replace the controller operation.

[0400] In addition, the images of the above-mentioned game machines can be output by display devices such as television devices, personal computer monitors, game monitors, head-mounted displays, etc.

[0401] By using the semiconductor device described in the above embodiment mode for the portable game console 5200 or the stationary game console 7500, a low-power portable game console 5200 or a stationary game console 7500 can be realized. In addition, the heat generated by the circuit can be reduced by means of low power consumption, thereby reducing the negative impact of heat on the circuit itself, peripheral circuits, and modules.

[0402] Furthermore, by using the semiconductor device described in the above embodiment mode in the portable game machine 5200 or the stationary game machine 7500, temporary files used for calculations generated when a game is executed can be stored.

[0403] exist Fig.21E In the example of the game console, a portable game console is shown. Fig.21F A home-use fixed game machine is shown. The electronic device of one embodiment of the present invention is not limited thereto. As an electronic device of one embodiment of the present invention, for example, an arcade game machine installed in an entertainment facility (game center, amusement park, etc.), a pitching machine for batting practice installed in a sports facility, etc. can be cited.

[0404] [Mobile body] The semiconductor devices described in the above embodiments can be applied to a vehicle as a moving object and the vicinity of a driver's seat of the vehicle.

[0405] Figure 21G A car 5700 is shown as an example of a moving object.

[0406] A dashboard that can display a speedometer, a tachometer, a travel distance, a refueling amount, a gear state, an air-conditioning setting, etc. to provide various information is provided near the driver's seat of the automobile 5700. In addition, a display device that displays the above information may also be provided near the driver's seat.

[0407] In particular, by displaying the image captured by the camera device (not shown) installed on the automobile 5700 on the above-mentioned display device, the field of vision blocked by pillars, etc., the blind spot of the driver's seat, etc. can be supplemented, thereby improving safety. In other words, by displaying the image captured by the camera device installed outside the automobile 5700, the field of vision can be supplemented to avoid the blind spot, thereby improving safety.

[0408] The semiconductor device described in the above embodiment can store information. For example, the semiconductor device can be applied to a system for automatic driving, navigation, danger prediction, etc. of the automobile 5700 to temporarily store necessary information. In addition, navigation, danger prediction, etc. information can be temporarily displayed on the display device. In addition, the recording of the driving recorder installed in the automobile 5700 can also be stored.

[0409] Although the above examples describe a car as an example of a mobile body, the mobile body is not limited to the car. For example, a tram, a monorail, a ship, a flying object (a helicopter, an unmanned aerial vehicle (UAV), an airplane, a rocket), etc. can also be cited as a mobile body.

[0410] [camera] The semiconductor devices described in the above embodiments can be applied to cameras.

[0411] Fig.21H A digital camera 6240 is shown as an example of an image pickup device. The digital camera 6240 includes a housing 6241, a display unit 6242, an operation switch 6243, a shutter button 6244, etc., and is equipped with a detachable lens 6246. Here, the digital camera 6240 adopts a structure in which the lens 6246 can be detached from the housing 6241, but the lens 6246 and the housing 6241 may be formed as one body. In addition, the digital camera 6240 may further include a flash device and a viewfinder, etc., which are separately installed.

[0412] By using the semiconductor device described in the above embodiment mode for the digital camera 6240, a low-power digital camera 6240 can be realized. In addition, low power consumption can reduce heat generated by the circuit, thereby reducing negative effects on the circuit itself, peripheral circuits, and modules due to heat.

[0413] [Video Camera] The semiconductor devices described in the above embodiments can be applied to video cameras.

[0414] Fig.21IA video camera 6300 as an example of a camera device is shown. The video camera 6300 includes a first housing 6301, a second housing 6302, a display unit 6303, an operation switch 6304, a lens 6305, a connection unit 6306, and the like. The operation switch 6304 and the lens 6305 are provided on the first housing 6301, and the display unit 6303 is provided on the second housing 6302. The first housing 6301 and the second housing 6302 are connected by the connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306. The image of the display unit 6303 can also be switched according to the angle between the first housing 6301 and the second housing 6302 in the connection unit 6306.

[0415] When recording an image captured by the video camera 6300, encoding is required according to a data recording method. With the semiconductor device described above, the video camera 6300 can store a temporary file generated when encoding is performed.

[0416] [ICD] The semiconductor device described in the above embodiment can be applied to an implantable cardioverter-defibrillator (ICD).

[0417] Fig.21J 1 is a schematic cross-sectional view showing an example of an ICD. An ICD main body 5400 includes at least a battery 5401, an electronic component 700, a regulator, a control circuit, an antenna 5404, a wire 5402 to the right atrium, and a wire 5403 to the right ventricle.

[0418] The ICD body 5400 is surgically placed in the body, and two metal wires pass through the subclavian vein 5405 and the superior vena cava 5406 of the human body, and the tip of one of the metal wires is placed in the right ventricle, and the tip of the other metal wire is placed in the right atrium.

[0419] ICD main body 5400 has the function of a pacemaker, and paces the heart when the heart rhythm is out of a predetermined range. In addition, when the heart rhythm does not improve even with pacing (ventricular tachycardia, ventricular fibrillation, etc.), treatment using defibrillation is performed.

[0420] In order to perform pacing and defibrillation appropriately, the ICD main body 5400 needs to monitor the heart rhythm frequently. Therefore, the ICD main body 5400 includes a sensor for detecting the heart rhythm. In addition, the ICD main body 5400 can store the heart rhythm data measured by the sensor, the number of times and time of treatment using pacing, etc. in the electronic component 700.

[0421] In addition, since power is received by antenna 5404, the power is charged to battery 5401. In addition, safety can be improved by including a plurality of batteries in ICD main body 5400. Specifically, even if some batteries in ICD main body 5400 fail, other batteries can function and be used as auxiliary power sources.

[0422] In addition, in addition to the antenna 5404 capable of receiving power, an antenna capable of sending physiological signals may also be included. For example, a system for monitoring cardiac activity in which physiological signals such as pulse, respiratory rate, heart rhythm, and body temperature can be confirmed by an external monitoring device may be constructed.

[0423] [Expansion unit for PC] The semiconductor device described in the above embodiment can be applied to a computer such as a PC (Personal Computer) or an expansion device for an information terminal.

[0424] Fig.22A An example of such an expansion device is shown as an expansion device 6100 that is portable and has a chip that can store information installed outside a PC. The expansion device 6100 can store information using the chip by connecting it to a PC via a USB or the like. Fig.22A A portable expansion device 6100 is shown, but the expansion device according to one embodiment of the present invention is not limited thereto. For example, a larger expansion device with a cooling fan or the like installed may be used.

[0425] The expansion device 6100 includes a housing 6101, a cover 6102, a USB connector 6103, and a substrate 6104. The substrate 6104 is accommodated in the housing 6101. The substrate 6104 is provided with a circuit for driving the semiconductor device described in the above embodiment. For example, the electronic component 700 and the controller chip 6106 are mounted on the substrate 6104. The USB connector 6103 is used as an interface for connecting to an external device.

[0426] [SD card] The semiconductor device described in the above embodiment can be applied to an SD card that can be mounted in electronic devices such as an information terminal and a digital camera.

[0427] Fig. 22B This is a schematic diagram of the appearance of an SD card. Fig. 22C51 is a schematic diagram of the internal structure of the SD card. The SD card 5110 includes a housing 5111, a connector 5112 and a substrate 5113. The connector 5112 has the function of connecting to an interface of an external device. The substrate 5113 is accommodated in the housing 5111. The substrate 5113 is provided with a semiconductor device and a circuit for driving the semiconductor device. For example, the substrate 5113 is installed with an electronic component 700 and a controller chip 5115. In addition, the circuit structures of the electronic component 700 and the controller chip 5115 are not limited to the above description, and the circuit structure can be appropriately changed according to the situation. For example, the write circuit, row driver, read circuit, etc. included in the electronic component can also be installed on the controller chip 5115 instead of the electronic component 700.

[0428] The capacity of the SD card 5110 can be increased by also providing the electronic component 700 on the back side of the substrate 5113. In addition, a wireless chip having a wireless communication function can be provided on the substrate 5113. Thus, wireless communication between an external device and the SD card 5110 can be performed, and data of the electronic component 700 can be read and written.

[0429] [SSD] The semiconductor device described in the above embodiment can be applied to an SSD (Solid State Drive) that can be mounted in electronic devices such as information terminals.

[0430] Fig.22D This is a schematic diagram of the appearance of SSD. Fig.22E 5150 is a schematic diagram of the internal structure of the SSD. The SSD5150 includes a housing 5151, a connector 5152, and a substrate 5153. The connector 5152 has the function of connecting to an interface of an external device. The substrate 5153 is accommodated in the housing 5151. The substrate 5153 is provided with a storage device and a circuit for driving the storage device. For example, the substrate 5153 is installed with an electronic component 700, a memory chip 5155, and a controller chip 5156. By also providing the electronic component 700 on the back side of the substrate 5153, the capacity of the SSD5150 can be increased. A working memory is installed in the memory chip 5155. For example, a DRAM chip can be used for the memory chip 5155. A processor, an ECC circuit, etc. are installed in the controller chip 5156. Note that the circuit structures of the electronic component 700, the memory chip 5155, and the controller chip 5155 are not limited to the above description, and the circuit structure can be appropriately changed according to the situation. For example, a memory used as a working memory can also be provided in the controller chip 5156.

[0431] [computer] Fig.23AThe illustrated computer 5600 is an example of a large computer (supercomputer) mainly used for scientific computing. Scientific computing requires performing huge operations at high speed, so it consumes a large amount of power and generates high heat in the chips. For example, in a data center including multiple computers 5600, the amount of digital data used is extremely large. Specifically, it is estimated that: the global digital data volume exceeds 10 24 (yotta) bytes or 10 30 (quetta) bytes.

[0432] By using the semiconductor device of one aspect of the present invention in the computer 5600, a low-power supercomputer can be realized. In addition, by virtue of the low power consumption, the heat generated from the circuit can be reduced, whereby the negative impacts on the circuit itself, the peripheral circuit, and the module caused by heat can be reduced. In addition, by using the semiconductor device of one aspect of the present invention, a low-power supercomputer can be realized. Thus, it can be expected to reduce the global digital data volume and greatly contribute to measures against global warming.

[0433] In the computer 5600, multiple rack-mounted computers 5620 are housed in the rack 5610. The computer 5620 can have, for example, Fig. 23B the structure of the illustrated perspective view. In Fig. 23B , the computer 5620 includes a motherboard 5630, and the motherboard 5630 includes a plurality of slots 5631 and a plurality of connection terminals. A personal computer card 5621 is inserted into the slot 5631. And the personal computer card 5621 includes connection terminals 5623, 5624, 5625, which are connected to the motherboard 5630.

[0434] Fig.23C The illustrated personal computer card 5621 is an example of a processing board including a CPU, a GPU, a storage device, etc. The personal computer card 5621 has a board 5622. In addition, the board 5622 includes connection terminals 5623, 5624, 5625, semiconductor devices 5626, 5627, 5628, and a connection terminal 5629. Note that Fig.23C semiconductor devices other than the semiconductor devices 5626, 5627, and 5628 are shown, and for the description of these semiconductor devices, reference can be made to the description of the semiconductor devices 5626, 5627, and 5628 described below.

[0435] The connection terminal 5629 has a shape that can be inserted into the slot 5631 of the motherboard 5630, and the connection terminal 5629 is used as an interface for connecting the personal computer card 5621 and the motherboard 5630. For example, PCIe, etc. can be cited as the specification of the connection terminal 5629.

[0436] The connection terminals 5623, 5624, and 5625 can be used as interfaces for supplying power to the personal computer card 5621 or inputting signals, for example. In addition, for example, they can be used as interfaces for outputting signals calculated by the personal computer card 5621, for example. Examples of the specifications of the connection terminals 5623, 5624, and 5625 include USB, SATA (Serial ATA), and SCSI (Small Computer System Interface). In addition, when video signals are output from the connection terminals 5623, 5624, and 5625, HDMI (registered trademark) and the like can be cited as the specifications.

[0437] The semiconductor device 5626 includes a terminal (not shown) for inputting and outputting a signal. By inserting the terminal into a socket (not shown) included in the board 5622 , the semiconductor device 5626 and the board 5622 can be electrically connected.

[0438] The semiconductor device 5627 includes a plurality of terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected by soldering the terminals to wiring included in the board 5622 by reflow soldering. As the semiconductor device 5627, for example, an FPGA (Field Programmable Gate Array), a GPU, a CPU, etc. can be cited. As the semiconductor device 5627, for example, an electronic component 730 can be used.

[0439] The semiconductor device 5628 includes a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by soldering the terminals to wiring included in the board 5622, for example, by reflow soldering. As the semiconductor device 5628, for example, a memory device can be cited. As the semiconductor device 5628, for example, the electronic component 700 can be used.

[0440] The computer 5600 can be used as a parallel computer. By using the computer 5600 as a parallel computer, for example, large-scale calculations required for learning and inference of artificial intelligence can be performed.

[0441] By using a semiconductor device of one embodiment of the present invention in the above-mentioned various electronic devices, miniaturization and low power consumption of the electronic devices can be achieved. In addition, the power consumption of the semiconductor device of one embodiment of the present invention is low, thereby reducing the heat generation of the circuit. Thus, the negative impact of the heat generation on the circuit itself, the peripheral circuit and the module can be reduced. In addition, by using a semiconductor device of one embodiment of the present invention, an electronic device that can also work stably in a high temperature environment can be realized. Thus, the reliability of the electronic device can be improved.

[0442] This embodiment mode can be combined with other embodiment modes described in this specification as appropriate.

[0443] (Implementation 7) A semiconductor device according to one embodiment of the present invention includes an OS transistor. The OS transistor has a small change in electrical characteristics due to radiation exposure. In other words, it has high resistance to radiation and can be appropriately used in an environment where radiation may be incident. For example, an OS transistor can be appropriately used in space. In this embodiment, an OS transistor is used. Fig.24 A specific example in which a semiconductor device according to one embodiment of the present invention is applied to space equipment will be described.

[0444] exist Fig.24 In FIG. 6 , an artificial satellite 6800 is shown as an example of a space device. The artificial satellite 6800 includes a main body 6801, a solar cell panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Fig.24 An example is shown in which the outer space includes the planet 6804. Note that the outer space refers to, for example, an altitude of 100 km or more, but the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.

[0445] In addition, outer space is an environment where the radiation dose is more than 100 times that of the ground. Examples of radiation include: electromagnetic waves (electromagnetic radiation) represented by X-rays and gamma rays; and particle radiation represented by alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, muon rays, etc.

[0446] When sunlight shines on the solar cell panel 6802, the power required for the artificial satellite 6800 to operate is generated. However, for example, when sunlight does not shine on the solar cell panel or when the amount of sunlight shining on the solar cell panel is small, the amount of power generated is reduced. Therefore, there is a possibility that the power required for the artificial satellite 6800 to operate may not be generated. In order to operate the artificial satellite 6800 even when the generated power is small, it is preferable to provide a secondary battery 6805 in the artificial satellite 6800. In addition, the solar cell panel is sometimes referred to as a solar cell module.

[0447] The artificial satellite 6800 can generate a signal. The signal is transmitted through the antenna 6803, and a receiver on the ground or other artificial satellites can receive the signal. By receiving the signal transmitted by the artificial satellite 6800, the position of the receiver receiving the signal can be measured. Thus, the artificial satellite 6800 can constitute a satellite positioning system.

[0448] In addition, the control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is composed of, for example, one or more selected from a CPU, a GPU, and a storage device. In addition, as the control device 6807, a semiconductor device including an OS transistor of one embodiment of the present invention is preferably used. Compared with Si transistors, the electrical characteristics of OS transistors due to radiation exposure change is small. That is, OS transistors have high reliability and can be used appropriately even in an environment where radiation may be incident.

[0449] In addition, the artificial satellite 6800 may include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 may have a function of detecting sunlight reflected from an object on the ground. Or, by including a thermal infrared sensor, the artificial satellite 6800 may have a function of detecting thermal infrared rays released from the ground. Thus, the artificial satellite 6800 may be used as an earth observation satellite, for example.

[0450] Note that although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited to this. For example, a semiconductor device according to one embodiment of the present invention can be suitably applied to space equipment such as a spacecraft, a space capsule, and a space probe.

[0451] This embodiment mode can be combined with other embodiment modes described in this specification as appropriate. [Explanation of symbols]

[0452] 100: transistor, 110: capacitor, 151: conductive layer, 152: conductive layer, 153: insulating layer, 154: insulating layer, 155: conductive layer, 157: insulating layer, 158: insulating layer, 159: insulating layer, 161: conductive layer, 162: opening, 163: semiconductor layer.

Claims

1. A semiconductor device comprising: Capacitors; as well as The transistor on the capacitor, Wherein, the capacitor comprises: a first conductive layer; a first insulating layer on the first conductive layer; and a second conductive layer on the first insulating layer, The transistor comprises: a second insulating layer on the second conductive layer; a third conductive layer on the second insulating layer; openings disposed in the second insulating layer and the third conductive layer; a semiconductor layer covering the opening; A third insulating layer on the semiconductor layer; and a fourth conductive layer on the third insulating layer, The opening overlaps with the second conductive layer, Furthermore, the first insulating layer includes ferroelectric.

2. The semiconductor device according to claim 1, The angle formed by the side surface of the second insulating layer in the opening and the bottom surface of the second insulating layer is greater than or equal to 45 degrees and less than or equal to 90 degrees.

3. The semiconductor device according to claim 1 or 2, The storage period at an ambient temperature of 150° C. is 10 days or more.

4. The semiconductor device according to claim 1 or 2, The second insulating layer includes a fourth insulating layer, a fifth insulating layer on the fourth insulating layer, and a sixth insulating layer on the fifth insulating layer, The fourth insulating layer and the sixth insulating layer both contain nitrogen and silicon, And the fifth insulating layer contains oxygen and silicon.

5. The semiconductor device according to claim 4, The fourth insulating layer and the sixth insulating layer both contain hydrogen.

6. The semiconductor device according to claim 1 or 2, The semiconductor layer includes an oxide semiconductor.

7. The semiconductor device according to claim 1 or 2, The first insulating layer includes hafnium, zirconium and oxygen.

8. The semiconductor device according to claim 1 or 2, The first conductive layer and the second conductive layer contain titanium and nitrogen.

9. The semiconductor device according to claim 1 or 2, wherein the fourth conductive layer is used as a gate electrode of the transistor, The third conductive layer is used as one of a source electrode and a drain electrode of the transistor, And the second conductive layer is used as the other of the source electrode and the drain electrode of the transistor.

10. A semiconductor device comprising: Multiple layers stacked together; as well as a first electrode passing through the plurality of layers, Wherein, each of the multiple layers comprises: capacitors; and The transistor on the capacitor, Wherein, the capacitor comprises: a first conductive layer; a first insulating layer on the first conductive layer; and a second conductive layer on the first insulating layer, The transistor comprises: a second insulating layer on the second conductive layer; a third conductive layer on the second insulating layer; openings disposed in the second insulating layer and the third conductive layer; a semiconductor layer covering the opening; A third insulating layer on the semiconductor layer; and a fourth conductive layer on the third insulating layer, The opening overlaps with the second conductive layer, The first insulating layer has a ferroelectric. Furthermore, the third conductive layer is electrically connected to the first electrode.

11. The semiconductor device according to claim 10, The angle formed by the side surface of the second insulating layer in the opening and the bottom surface of the second insulating layer is greater than or equal to 45 degrees and less than or equal to 90 degrees.

12. The semiconductor device according to claim 10 or 11, The storage period at an ambient temperature of 150° C. is 10 days or more.

13. The semiconductor device according to claim 10 or 11, The first electrode includes a plurality of conductive layers.

14. The semiconductor device according to claim 10 or 11, The second insulating layer includes a fourth insulating layer, a fifth insulating layer on the fourth insulating layer, and a sixth insulating layer on the fifth insulating layer, The fourth insulating layer and the sixth insulating layer both contain nitrogen and silicon, And the fifth insulating layer contains oxygen and silicon.

15. The semiconductor device according to claim 14, The fourth insulating layer and the sixth insulating layer both contain hydrogen.

16. The semiconductor device according to claim 10 or 11, The semiconductor layer includes an oxide semiconductor.

17. The semiconductor device according to claim 10 or 11, The first insulating layer includes hafnium, zirconium and oxygen.

18. The semiconductor device according to claim 10 or 11, The first conductive layer and the second conductive layer contain titanium and nitrogen.

19. The semiconductor device according to claim 10 or 11, wherein the fourth conductive layer is used as a gate electrode of the transistor, The third conductive layer is used as one of a source electrode and a drain electrode of the transistor, And the second conductive layer is used as the other of the source electrode and the drain electrode of the transistor.

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