Semiconductor device, semiconductor module, and wireless communication apparatus

Abstract

The semiconductor device includes: a substrate; a channel layer provided on one surface side of the substrate and including a first nitride semiconductor having a first band gap; a barrier layer provided on an opposite side of the channel layer with respect to the substrate, and including a second nitride semiconductor formed of Alx1Iny1Ga (1-x1-y1) N (0 < x1 < 1, 0 < y1 < 1), and having a second band gap larger than the first band gap of the first nitride semiconductor; and an intermediate layer provided in the barrier layer and including a third nitride semiconductor formed of Alx2Iny2Ga (1-x2-y2) N (0 < = x2 < 1, 0 < = y2 < 1), where (1-x1-y1) lt is satisfied; and (1-x2-y2).

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, a semiconductor module, and a wireless communication device. Background Art

[0002] For example, Patent Document 1 discloses an epitaxial substrate for a semiconductor device, which can obtain a good ohmic contact in a high electron mobility transistor (HEMT). The epitaxial substrate for a semiconductor device includes a base substrate, a channel layer including GaN, a spacer layer including AlN, and a barrier layer including In, Al or Ga as a group III element. The barrier layer is basically formed by x Al 1-x The Ga atoms are doped into the base layer of N (0<x<1) and the concentration of Ga atoms in the barrier layer is 1.2×10 20 cm -3 the following.

[0003] Reference List

[0004] Patent Literature

[0005] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2011-222964 Summary of the invention

[0006] At the same time, it is desired to improve the heat resistance in HEMTs.

[0007] Therefore, it is desirable to provide a semiconductor device, a semiconductor module, and a wireless communication device capable of improving heat resistance.

[0008] A semiconductor device according to an embodiment of the present disclosure includes: a substrate; a channel layer provided on one surface side of the substrate, the channel layer including a first nitride semiconductor having a first band gap; a barrier layer provided on an opposite side of the channel layer relative to the substrate and including a second nitride semiconductor including Al x1 In y1 Ga (1-x1-y1) N(0<x1<1, 0<y1<1) and having a second band gap larger than the first band gap of the first nitride semiconductor; and an intermediate layer, disposed in the barrier layer, and including a third nitride semiconductor, the third nitride semiconductor including Al x2 In y2 Ga (1-x2-y2) N(0≤x2<1, 0≤y2<1), where (1-x1-y1)<(1-x2-y2) is satisfied.

[0009] A semiconductor module according to one embodiment of the present disclosure includes the semiconductor device according to one embodiment of the present disclosure described above.

[0010] A wireless communication device according to one embodiment of the present disclosure includes the semiconductor device according to one embodiment of the present disclosure described above.

[0011] In a semiconductor device according to an embodiment of the present disclosure, a semiconductor module according to an embodiment of the present disclosure, and a wireless communication device according to an embodiment of the present disclosure, an intermediate layer including a third nitride semiconductor is provided in a barrier layer including a second nitride semiconductor, the third nitride semiconductor including Al x2 In y2 Ga (1-x2-y2) N (0≤x2<1, 0≤y2<1) and satisfying (1-x1-y1)<(1-x2-y2), the second nitride semiconductor includes Al x1 In y1 Ga (1-x1-y1) N(0<x1<1, 0<y1<1) and has a second band gap larger than a first band gap of a first nitride semiconductor included in the channel layer. This improves the crystallinity of the barrier layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a schematic cross-sectional view showing an example of a configuration of a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 2A It shows Figure 1 Schematic cross-sectional views of an embodiment of a process for manufacturing a semiconductor device shown in FIG.

[0014] Figure 2B It shows that Figure 2A Schematic cross-sectional view of the subsequent steps.

[0015] Figure 2C It shows that Figure 2B Schematic cross-sectional view of the subsequent steps.

[0016] Figure 2D It shows that Figure 2C Schematic cross-sectional view of the subsequent steps.

[0017] Figure 2E It shows that Figure 2D Schematic cross-sectional view of the subsequent steps.

[0018] Figure 2F It shows that Figure 2E Schematic cross-sectional view of the subsequent steps.

[0019] Figure 3 is a schematic cross-sectional view showing an example of a configuration of a semiconductor device according to Modification 1 of the present disclosure.

[0020] Figure 4 is a schematic cross-sectional view showing another example of the configuration of the semiconductor device according to Modification 1 of the present disclosure.

[0021] Figure 5 is a schematic cross-sectional view showing an example of a configuration of a semiconductor device according to Modification 2 of the present disclosure.

[0022] Figure 6 is a schematic cross-sectional view showing an example of a configuration of a semiconductor device according to Modification 3 of the present disclosure.

[0023] Figure 7 is a schematic cross-sectional view showing another example of the configuration of the semiconductor device according to Modification 3 of the present disclosure.

[0024] Figure 8 is a schematic cross-sectional view showing an example of a configuration of a semiconductor device according to Modification 4 of the present disclosure.

[0025] Fig. 9 is a schematic cross-sectional view showing an example of a configuration of a semiconductor device according to Modification 5 of the present disclosure.

[0026] Fig.10 is a schematic cross-sectional view showing the configuration of a semiconductor device of Reference Example 1.

[0027] Fig.11 is a schematic cross-sectional view showing the configuration of a semiconductor device of Reference Example 2.

[0028] Fig.12 is a schematic cross-sectional view showing the configuration of a semiconductor device of Reference Example 3.

[0029] Fig.13 is a schematic cross-sectional view showing the configuration of a semiconductor device of Reference Example 4.

[0030] Fig.14 3 is a characteristic diagram showing the off-leakage current in Reference Example 4.

[0031] Fig.15 is a characteristic diagram showing the off-leakage current in the embodiment.

[0032] Fig.16 The current-voltage characteristics in Reference Example 2 are shown.

[0033] Fig.17 The current-voltage characteristics in the embodiment are shown.

[0034] Fig.18 is a schematic perspective view showing the configuration of a semiconductor module.

[0035] Fig.19 is a block diagram showing the configuration of a wireless communication device. DETAILED DESCRIPTION

[0036] Hereinafter, some embodiments of the present disclosure are described in detail with reference to the accompanying drawings. The following embodiments are specific examples of the present disclosure, and the present disclosure is not limited to the following embodiments. In addition, the arrangement, size, size ratio, etc. of the components in the present disclosure are not limited to the arrangement, size, size ratio, etc. shown in each of the accompanying drawings.

[0037] It should be noted that the explanation is made in the following order.

[0038] 1. Implementation (Example of a semiconductor device having a Schottky-type gate configuration in which an intermediate layer is inserted into a barrier layer)

[0039] 1-1. Configuration of semiconductor devices

[0040] 1-2. Method for manufacturing semiconductor device

[0041] 1-3. Actions and effects

[0042] 2. Modifications

[0043] 2-1. Modification 1

[0044] 2-2. Modification 2

[0045] 2-3. Modification 3

[0046] 2-4. Modification 4

[0047] 2-5. Modification 5

[0048] 3. Example

[0049] 4. Application examples

[0050] 4-1. Application examples of semiconductor modules

[0051] 4-2. Application examples of wireless communication equipment

[0052] <1. Implementation Method>

[0053] [1-1. Configuration of semiconductor device]

[0054] Figure 1 An example of a cross-sectional configuration of a semiconductor device (semiconductor device 1 ) according to an embodiment of the present disclosure is schematically shown.

[0055] The semiconductor device 1 has a stacked configuration, in which a substrate 11, a first buffer layer 12, a second buffer layer 13, a channel layer 14, a first spacer layer 15, a second spacer layer 16, a barrier layer 17, an intermediate layer 18 disposed in the barrier layer 17, and a protective layer 19 are sequentially stacked. The semiconductor device 1 also includes a source electrode S, a drain electrode D, an insulating film Z, and a gate electrode G located on the protective layer 19. The semiconductor device 1 has, for example, a Schottky-type gate configuration.

[0056] The semiconductor device 1 according to the present embodiment is a high electron mobility transistor (HEMT) having a two-dimensional electron gas layer 2DEG as a channel. The two-dimensional electron gas layer 2DEG is formed due to the difference in polarization magnitude between the channel layer 14 and the barrier layer 17. The two-dimensional electron gas layer 2DEG is formed in the channel layer 14, for example, adjacent to the interface K45 between the channel layer 14 and the first spacer layer 15.

[0057] The substrate 11 is a support member of the semiconductor device 1. For example, the substrate 11 is a Si (silicon) substrate, a SiC (silicon carbide) substrate, a sapphire substrate, a GaN (gallium nitride) substrate, an AlN (aluminum nitride) substrate, etc. As the Si substrate, for example, a single crystal Si (111) substrate having a (111) plane as a main surface is preferred. In the semiconductor device 1, as described above, a first buffer layer 12 and a second buffer layer 13 are provided. The first buffer layer 12 and the second buffer layer 13 make it possible to reduce the mismatch between the lattice constant of the substrate 11 and the lattice constant of the channel layer 14. To this end, the substrate 11 may include a material having a lattice constant different from that of the channel layer 14.

[0058] It should be noted that the use of the substrate 11 of the above-mentioned material makes it possible to obtain the effects of the semiconductor device of the present disclosure described below. The following embodiments and reference examples 1 to 4 are each the results obtained when using the substrate 11 including Si(111). In the semiconductor device 1 using a substrate including SiC or a substrate including GaN having higher single crystallinity and lower through-dislocation density than Si(111), further reduction in off-leakage current and higher breakdown voltage can be expected. To this end, the substrate 11 can be configured by selecting a preferred material according to the application, etc.

[0059] The first buffer layer 12 and the second buffer layer 13 each include an epitaxially grown nitride semiconductor. The first buffer layer 12 and the second buffer layer 13 make it possible to reduce the lattice mismatch between the substrate 11 and the channel layer 14 by controlling the lattice constant of the surface provided with the channel layer 14. This allows the first buffer layer 12 and the second buffer layer 13 to further improve the crystallization state of the channel layer 14 while suppressing the warping of the substrate 11.

[0060] For example, in the case where the substrate 11 is a single crystal Si substrate having a (111) plane as a main surface and the channel layer 14 is a GaN layer, the first buffer layer 12 includes AlN and the second buffer layer 13 includes AlGaN. However, depending on the configuration of the substrate 11 and the channel layer 14, the first buffer layer 12 and the second buffer layer may not exist. Alternatively, of the first buffer layer 12 and the second buffer layer, only the first buffer layer 12 may be provided.

[0061] The channel layer 14 includes a nitride semiconductor having a band gap smaller than the band gap of the first spacer layer 15 and the band gap of the barrier layer 17. The channel layer 14 is disposed on the second buffer layer 13. The channel layer 14 allows carriers to accumulate at an interface on the barrier layer 17 side due to a difference in polarization magnitude between the channel layer 14 and the barrier layer 17.

[0062] The channel layer 14 includes Al as an epitaxially grown nitride semiconductor. x6 In y6 Ga (1-x6-y6) N(0≤x6≤1, 0≤y6≤1, 0≤x6+y6≤1). For example, the channel layer 14 includes epitaxially grown GaN (gallium nitride). The channel layer 14 may include undoped u-GaN to which no impurities are added. In addition, the channel layer 14 may include at least one of InGaN (indium gallium nitride), InN (indium nitride), AlGaN (aluminum gallium nitride), or AlInGaN (aluminum indium gallium nitride). In addition, the channel layer 14 may have a stacked configuration including a plurality of layers each having a different composition. In this case, the channel layer 14 makes it possible to suppress impurity scattering of carriers. This allows the channel layer 14 to further increase carrier mobility.

[0063] The first spacer layer 15 includes a nitride semiconductor having a band gap greater than that of the channel layer 14. The first spacer layer 15 is disposed above the channel layer 14. The first spacer layer 15 is disposed to reduce alloy scattering between the barrier layer 17 and the channel layer 14, and to suppress a reduction in carrier mobility of the two-dimensional electron gas layer 2DEG due to the alloy scattering.

[0064] The first spacer layer 15 includes epitaxially grown Al x4 In y4 Ga (1-x4-y4) N(0<x4≤1, 0≤y4<1, 0≤x4+y4≤1) For example, the first spacer layer 151 may include AlN or may include AlGaN or AlInGaN.

[0065] The first spacer layer 15 preferably has a thickness of, for example, 0.26 nm or more and 3.0 nm or less, and particularly preferably has a thickness of 0.5 nm or more and 1.5 nm or less. In the case where the first spacer layer 15 has a thickness of 0.26 nm or more, it can be expected that the first spacer layer 15 more effectively suppresses alloy scattering. On the other hand, in the case where the first spacer layer 15 has a thickness of 3.0 nm or less, the first spacer layer 15 can more appropriately control the band gap distribution of the semiconductor device 1. This makes it possible to further increase the carrier density of the two-dimensional electron gas layer 2DEG formed in the channel layer 14.

[0066] The second spacer layer 16 includes Al as an epitaxially grown nitride semiconductor. x5 In y5 Ga (1-x5-y5) N(0<x5<1, 0≤y5<1, 0<x5+y5<1). The second spacer layer 16 is disposed on the first spacer layer 15. The Al x5 In y5 Ga (1-x5-y5) N and Al as a nitride semiconductor included in the barrier layer 17 described below x1 In y1 Ga (1-x1-y1) N(0<x1≤1, 0≤y1<1) has a relationship of x5<x1. This makes it easier to obtain a mixed crystal with higher single crystallinity than the barrier layer 17. Therefore, the second spacer layer 16 can more clearly define the interface between the barrier layer 17 and the first spacer layer 15 while suppressing interface disorder due to heat, thereby making it possible to suppress the degradation of the configuration of the layers of the channel layer 14 and the barrier layer 17 due to heat.

[0067] For example, the second spacer layer 16 may include GaN, and the second spacer layer 16 includes AlGaN or AlInGaN. For example, the second spacer layer 16 including GaN may be disposed on the first spacer layer 15 including AlN. Alternatively, the second spacer layer 16 including AlGaN may be disposed on the first spacer layer 15 including AlGaN. In the case of stacking the AlN layer and the GaN layer, diffusion of Al from the AlN layer to the GaN layer or diffusion of Ga from the GaN layer to the AlN layer may be caused. This provides a manufacturing advantage for a configuration in which both the first spacer layer 15 and the second spacer layer 16 include AlGaN. In addition, the second spacer layer 16 including AlInGaN may be disposed on the first spacer layer 15 including AlInGaN. In addition, because the AlInGaN layer including In allows lattice distortion to be reduced, the effect of suppressing the generation of defects in the first spacer layer 15 and defects in the second spacer layer 16 can be obtained.

[0068] It is preferred that Al included in the second spacer layer 16x5 In y5 Ga (1-x5-y5) The Ga composition (1-x5-y5) of N is greater than 0.3. In the case where the Ga composition (1-x5-y5) of the second spacer layer 16 is greater than 0.3, the crystallinity of the second spacer layer 16 is further improved, allowing the interface disorder caused by heat to be suppressed. Thus, the degradation of the layer configuration of the channel layer 14 and the barrier layer 17 caused by heat can be suppressed. The Al composition ratio in the second spacer layer 16 is lower than the Al composition ratio in the first spacer layer 15 and the Al composition ratio in the barrier layer 17. Inserting the second spacer layer 16 having a relatively low Al composition ratio between the first spacer layer 15 and the barrier layer 17 allows the single crystallinity of the barrier layer 17 including AlInGaN to be improved. That is, inserting the second spacer layer 16 having a Ga concentration higher than the Ga concentration in the first spacer layer 15 and the Ga concentration in the barrier layer 17 between the first spacer layer 15 and the barrier layer 17 allows the single crystallinity of the barrier layer 17 including AlInGaN to be improved. Furthermore, in other words, the semiconductor device 1 has a configuration in which the second spacer layer 16 having a band gap lower than the band gap of the first spacer layer 15 and the band gap of the barrier layer 17 is provided between the first spacer layer 15 and the barrier layer 17. This achieves suppression of local electric field concentration and high-speed on / off operation, making it possible to obtain a higher breakdown voltage as well as high mutual conductance.

[0069] The second spacer layer 16 preferably has a thickness of 0.26 nm or more and 3.0 nm or less, and particularly preferably has a thickness of 0.5 nm or more and 1.5 nm or less. In the case where the second spacer layer 16 has a thickness of 0.26 nm or more, the layer formation of the second spacer layer 16 can be performed more easily. On the other hand, in the case where the second spacer layer 16 has a thickness of 3.0 nm or less, the second spacer layer 16 can more appropriately control the band gap distribution of the semiconductor device 1. This makes it possible to further increase the carrier density of the two-dimensional electron gas layer 2DEG formed in the channel layer 14.

[0070] The barrier layer 17 includes a nitride semiconductor having a band gap greater than that of the channel layer 14. The barrier layer 17 is disposed on the second spacer layer 16. The barrier layer 17 allows carriers to accumulate in the channel layer 14 in a region near the barrier layer 17 by spontaneous polarization or piezoelectric polarization. In the semiconductor device 1, this allows a two-dimensional electron gas layer 2DEG having high mobility and high carrier concentration to be formed in a region of the channel layer 14 adjacent to the interface K45.

[0071] The barrier layer 17 includes Al as an epitaxially grown nitride semiconductor. x1 In y1 Ga (1-x1-y1)N(0<x1<1, 0<y1<1). Here, x1>0.7 and y1<0.3 may also be satisfied. For example, the barrier layer 17 may include undoped u-Al without adding impurities. x1 In (1-x1) N. In this case, the barrier layer 17 allows the lattice mismatch with GaN to be reduced, thereby making it possible to obtain a crystal having high single crystallinity.

[0072] For example, the carrier density of the two-dimensional electron gas layer 2DEG can be controlled by the band gap distribution of each layer from the barrier layer 17 to the channel layer 14. One factor determining the carrier density of the two-dimensional electron gas layer 2DEG is the height of the conduction band minimum of the barrier layer 17.

[0073] For example, the higher the Al composition of each layer, the greater the polarization of each layer. This results in a greater slope of the conduction band minimum. In addition, the greater the thickness of each layer, the greater the height of the conduction band minimum. Thus, by appropriately controlling the thickness and composition of each layer from the barrier layer 17 to the channel layer 14 and controlling the height of the conduction band minimum of the barrier layer 17, the carrier density of the two-dimensional electron gas layer 2DEG can be increased.

[0074] For example, the barrier layer 17 includes an Al composition having a higher percentage than that included in the second spacer layer 16. x5 In y5 Ga (1-x5-y5) N Al x1 In (1-x1) N(0<x1<1, 0<y1<1). That is, the barrier layer 17 includes a nitride semiconductor that satisfies x5<x1 with the second spacer layer 16, thereby allowing a larger polarization to be obtained. This makes it possible to further increase the carrier concentration of the two-dimensional electron gas layer 2DEG. For example, since the barrier layer 17 includes a nitride semiconductor with x1 greater than 0.7, a larger polarization can be obtained. This allows a higher carrier concentration of the two-dimensional electron gas layer 2DEG. For example, the barrier layer 17 includes AlInN. The barrier layer 17 may include AlInGaN, AlGaN, or AlN. In the case where the barrier layer 17 includes AlInGaN, a constant design margin for band gap and strain can be obtained. In addition, since the barrier layer 17 includes Ga, the single crystallinity of the barrier layer 17 is improved.

[0075] The barrier layer 17 preferably has a thickness of 2.0 nm or more and 20 nm or less. In this case, the barrier layer 17 can more appropriately control the band gap distribution of the semiconductor device 1. This makes it possible to further increase the carrier density of the two-dimensional electron gas layer 2DEG formed in the channel layer 14. It should be noted that the thickness of the barrier layer 17 here is the thickness excluding the intermediate layer 18. In addition, the barrier layer 17 more preferably has a thickness of 3.0 nm or more and 10 nm or less.

[0076] In the present embodiment, the barrier layer 17 includes therein an intermediate layer 18 which divides the barrier layer 17 into a lower layer (first barrier layer 17A) and an upper layer (second barrier layer 17B). The intermediate layer 18 includes Al as an epitaxially grown nitride semiconductor. x2 In y2 Ga (1-x2-y2) N(0≤x2≤1,0≤y2<1), and (1-x1-y1)<(1-x2-y2). x2 In y2 Ga (1-x2-y2) N (0≤x2≤1, 0≤y2<1) and Al as the nitride semiconductor included in the barrier layer 17 x1 In y1 Ga (1-x1-y1) N(x5<x1≤1,0≤y1<1) satisfies x2<x1. In addition, Al x2 In y2 Ga (1-x2-y2) N(0≤x2≤1, 0≤y2<1) also satisfies 1-x2-y2>0.01. For example, the intermediate layer 18 includes GaN. Since the intermediate layer 18 including Ga has excellent single crystallinity and morphology, the crystallinity of the barrier layer 17 is improved by inserting the intermediate layer 18 having a higher Ga composition than the barrier layer 17 into the barrier layer 17.

[0077] The intermediate layer 18 preferably has a thickness of 0.26 nm or more and 2.0 nm or less. When the thickness of the intermediate layer 18 is greater than 2.0 nm, the density of the two-dimensional electron gas concentration in the channel layer 14 decreases, resulting in generation of carriers in the intermediate layer 18 .

[0078] The barrier layer 17 including AlInN is particularly likely to oxidize due to the high composition ratio of Al. In order to suppress such oxidation, a protective layer 19 may be provided on the barrier layer 17. The protective layer 19 protects the surface of the barrier layer 17 from impurities such as agents or various types of ions while maintaining the surface of the barrier layer 17 in a preferred state, thereby making it possible to suppress degradation of the operating characteristics of the semiconductor device 1. The protective layer 19 includes, for example, Al as an epitaxially grown nitride semiconductor. x3 In y3 Ga (1-x3-y3)N(0≤x3<1, 0≤y3<1). It should be noted that with respect to the nitride semiconductor included in the barrier layer 17, it is sufficient to satisfy (1-x1-y1)<(1-x3-y3). For this reason, the protective layer 19 includes, for example, GaN. The protective layer 19 may include AlInGaN, AlGaN or InGaN. GaN has the highest single crystallinity. InGaN promotes n-type contact. By selecting an Al composition lower than that of the barrier layer 17, AlInGaN and AlGaN make it possible to obtain a mixed crystal having a band gap greater than that of GaN and InGaN while serving as a protective layer. The advantage conferred by the large band gap is that a high two-dimensional electron gas concentration is obtained.

[0079] The gate electrode G, the source electrode S, and the drain electrode D each include a conductive material. The gate electrode G, the source electrode S, and the drain electrode D are each disposed on a semiconductor layer. The gate electrode G is disposed between the source electrode S and the drain electrode D. The gate electrode G is a Schottky gate that forms a Schottky junction by contacting the nitride semiconductor included in the protective layer 19 without via the insulating film Z. The gate electrode G may have, for example, a two-layer configuration in which a Ni (nickel) layer and an Au (gold) layer are sequentially stacked on the protective layer 19. In addition, the source electrode S and the drain electrode D may be configured to have, for example, a configuration in which a Ti (titanium) layer, an Al (aluminum) layer, a Ni (nickel) layer, and an Au (gold) layer are sequentially stacked on the protective layer 19.

[0080] The insulating film Z includes an insulating material. The insulating film Z is provided to cover a region included in the protective layer 19 and not covered by any of the gate electrode G, the source electrode S, and the drain electrode D. The insulating film Z includes, for example, Al2O3 (aluminum oxide), SiO2 (silicon dioxide), Si3N4 (silicon nitride), HfO2 (hafnium oxide), etc. as constituent materials. The insulating film Z may be a single-layer film including the above-mentioned constituent materials or a multilayer film in which a plurality of layers each including the above-mentioned constituent materials are stacked.

[0081] [1-2. Method for manufacturing semiconductor device]

[0082] Next, refer to FIG. 2A to FIG. 2F An example of a method of manufacturing the semiconductor device 1 according to the present embodiment is described. FIG. 2A to FIG. 2F Each is a schematic cross-sectional view showing each process in a method of manufacturing the semiconductor device 1 .

[0083] First, if Figure 2AAs shown in, for example, a first buffer layer 12, a second buffer layer 13, a channel layer 14, a first spacer layer 15, a second spacer layer 16, a first barrier layer 17A, an intermediate layer 18, a second barrier layer 17B and a protective layer 19 are sequentially epitaxially grown on a substrate 11. It should be noted that the substrate 11 can use a Si substrate, a sapphire substrate, a SiC substrate, a GaN substrate, an AlN substrate, a GaAs substrate, a ZnO substrate, a ScAlMgO substrate, etc. However, the following describes a case where a Si substrate is used as an embodiment.

[0084] For example, first, a Si substrate having a (111) position as a main surface is introduced into a MOCVD (metal organic chemical vapor deposition) device, and thermal cleaning is performed for about 10 minutes at 1000° C. Then, the first buffer layer 12 is formed by epitaxially growing AlN at about 700° C. to a thickness of about 100 nm to 300 nm at about 1100° C.

[0085] Next, the second buffer layer 13 is formed on the first buffer layer 12 by, for example, epitaxially growing AlGaN having an Al composition of about 0.20 at about 900° C. to 1100° C. to a thickness of 100 nm to 500 nm.

[0086] Subsequently, the channel layer 14 is formed on the second buffer layer 13 , for example, by epitaxially growing GaN at approximately 900° C. to 1100° C. to a thickness of 500 nm to 2000 nm.

[0087] Then, the first spacer layer 15 is formed on the channel layer 14 by, for example, epitaxially growing AlN at 900° C. to 1100° C. to a thickness of about 0.5 nm to 1.5 nm.

[0088] Next, the second spacer layer 16 is formed on the first spacer layer 15 by, for example, epitaxially growing GaN at 900° C. to 1100° C. to about 0.5 nm to 1.5 nm.

[0089] Subsequently, the first barrier layer 17A is formed, for example, by epitaxially growing AlInN to about 1 nm to 10 nm at 700° C. to 900° C. Next, the intermediate layer 18 is formed on the first barrier layer 17A, for example, by epitaxially growing GaN to about 0.26 nm to 2.0 nm at 900° C. to 1100° C. Then, the second barrier layer 17B is formed on the intermediate layer 18, for example, by epitaxially growing AlInN to about 1 nm to 10 nm at 700° C. to 900° C.

[0090] Furthermore, the protective layer 19 is formed on the barrier layer 17 by, for example, epitaxially growing GaN to about 1 nm to 5 nm at 700° C. to 1000° C.

[0091] Next, if Figure 2BAs shown in , the insulating film Z is formed by forming a film of SiN, SiO2, Al2O3, or the like on the protective layer 19. Subsequently, the insulating film Z is selectively removed using a resist pattern having an opening in a region corresponding to each of the source electrode S and the drain electrode D. In other words, only a portion of the insulating film Z (which is a region where each of the source electrode S and the drain electrode D is to be formed) is selectively removed. As a result, the openings ZS and ZD are formed to expose a portion of the upper surface of the protective layer 19.

[0092] Then, if Figure 2C As shown in , the opening ZS and the opening ZD are extended to the middle of the channel layer 14 by dry etching using the insulating film Z as a mask.

[0093] Next, if Figure 2D As shown in , for example, a GaN layer 20 having n-type conductivity is grown by MOCVD, sputtering, etc. At this time, Si or Ge (germanium) can be used as a dopant. Since the GaN layer 20 in contact with the channel layer 14 is provided, a device with low on-resistance (Ron) can be obtained.

[0094] Then, if Figure 2E As shown in , the source electrode S and the drain electrode D are each formed by selectively stacking a Ti layer, an Al layer, a Ni layer, and an Au layer in order on the upper surface of the GaN layer 20 .

[0095] Then, if Figure 2F As shown, the insulating film Z is selectively removed using a resist pattern having an opening in a region corresponding to the gate electrode G. In other words, only a portion of the insulating film Z (which is a region where the gate electrode G is to be formed) is selectively removed. As a result, an opening ZG is formed to expose a portion of the upper surface of the protective layer 19. Then, the gate electrode G is formed by selectively stacking a Ni layer and an Au layer in sequence on the exposed upper surface of the protective layer 19.

[0096] Following the above process, we can form Figure 1 A semiconductor device 1 according to the present embodiment is shown in FIG.

[0097] [1-3. Action and Effect]

[0098] Nitride semiconductors including AlInGaN are materials that enable light emission from the ultraviolet region to the infrared region by controlling the composition ratio of Al, Ga and In. After the commercialization of blue light-emitting diodes (LEDs) using InGaN for light-emitting layers, LEDs and semiconductor lasers (LDs) from the ultraviolet region to the green region are now in practical use. These light-emitting devices are used for lighting, backlights of LCD panels, projection light sources, etc.

[0099] Meanwhile, research and development of HEMTs using nitride semiconductors have been actively conducted in recent years. Nitride has a larger band gap than Si, GaAs, etc., and has polarization characteristics unique to hexagonal crystals. For this reason, HEMTs using nitride semiconductors are expected to be transistors that allow low resistance, high breakdown voltage, and high-speed operation.

[0100] Specifically, HEMT is expected to be applied to power devices or radio frequency (RF) devices, etc. For example, HEMT using AlGaN for a barrier layer is in practical use in a base station for satellite communication or wireless communication. Compared with HEMT using AlGaN for a barrier layer, HEMT using AlInN for a barrier layer makes it possible to obtain an even higher two-dimensional electron gas concentration, and thus is expected to allow even higher power.

[0101] In a HEMT in which a barrier layer including AlInN is directly stacked on a channel layer including GaN, there is a high probability of scattering due to fluctuations in the In composition of AlInN at the AlInN / GaN interface. Therefore, in a HEMT in which a barrier layer including AlInN is directly stacked on a channel layer including GaN, the mobility of the two-dimensional electron gas is lower by more than one digit than the value predicted by theoretical calculation.

[0102] It has been found that inserting a spacer layer including AlN by about 1 nm between a channel layer including GaN and a barrier layer including AlInN makes it possible to suppress scattering due to AlInN, allowing a significant improvement in mobility.

[0103] In addition, compared with a HEMT having a double-layer configuration (GaN / AlGaN) including a channel layer including GaN and a barrier layer including AlGaN, a HEMT having a triple-layer configuration (GaN / AlN / AlInN) including a channel layer including GaN, a spacer layer including AlN, and a barrier layer including AlInN has a problem of low process resistance, such as low heat resistance or chemical resistance, or susceptibility to etching damage. This difficulty limits the degree of freedom of the process flow and process conditions, thereby causing difficulties in practical application.

[0104] In addition, the AlInN mixed crystal is a ternary mixed crystal including AlN and InN, but there is a significant difference in the physical property values ​​such as saturated vapor pressure between AlN and InN, and it has low miscibility. For this reason, AlInN has lower single crystallinity, higher impurity concentration, and more difficulty in obtaining a smooth surface compared to GaN, AlGaN, etc. During processing, these properties may cause oxidation or etching in a HEMT including a barrier layer containing AlInN in the outermost layer. In addition, after heat treatment, the sheet resistance tends to deteriorate due to a decrease in the concentration of the two-dimensional electron gas or a decrease in mobility, making it difficult to obtain the device characteristics desired according to the material properties. In addition, it is also difficult to manufacture a device with high reliability. In addition, for Schottky gate HEMTs, there is a problem of large off-leakage current.

[0105] In order to solve these problems, HEMTs have been proposed in which the outermost surface of a barrier layer including AlInN is protected by a protective layer including GaN. However, even HEMTs provided with a protective layer are not sufficient to solve the root cause of the low crystallinity of AlInN. In addition, the protective layer is an unnecessary layer in terms of the function of the RF device. Therefore, providing the protective layer increases the thickness of the epitaxial growth layer as the upper layer of the two-dimensional electron gas, thereby reducing transconductance (gm) and high-frequency characteristics.

[0106] In contrast, in the semiconductor device 1 according to the present embodiment, the semiconductor device 1 includes Al x2 In y2 Ga (1-x2-y2) The intermediate layer 18 of the nitride semiconductor N (0≤x2<1, 0≤y2<1) and satisfying (1-x1-y1)<(1-x2-y2) is provided on the nitride semiconductor (Al2O3) having a band gap larger than the band gap of the channel layer 14. x1 In y1 Ga (1-x1-y1) N(0<x1<1, 0<y1<1)) is formed in the barrier layer 17, thereby improving the crystallinity of the barrier layer 17.

[0107] Thereby, the semiconductor device 1 allows improvement in heat resistance.

[0108] In addition, the barrier layer 17 having excellent crystallinity makes it possible to obtain an effect of suppressing surface oxidation of the barrier layer 17. In other words, the thickness of the protective layer 19 can be reduced, and thus high gm or high frequency characteristics can be obtained without deteriorating the sheet resistance of the two-dimensional electron gas. In addition, although the semiconductor device 1 has a Schottky-type gate configuration, the improved crystallinity of the barrier layer 17 makes it possible to reduce the so-called off-leakage current compared to a semiconductor device having a configuration without the intermediate layer 18.

[0109] Next, Modifications 1 to 5, Examples, and Application Examples of the present disclosure are described. Note that components corresponding to those of the semiconductor device of the above-described embodiment are denoted by the same reference numerals, and description thereof is omitted.

[0110] <2. Modifications>

[0111] (2-1. Modification 1)

[0112] Figure 3 An example of a cross-sectional configuration of a semiconductor device (semiconductor device 1A) according to Modification 1 of the present disclosure is schematically shown. Figure 4 Another example of the cross-sectional configuration of the semiconductor device 1A according to Modification 1 of the present disclosure is schematically shown.

[0113] In the above-described embodiment, the intermediate layer 18 that divides the barrier layer 17 into the first barrier layer 17A and the second barrier layer 17B is inserted into the barrier layer 17. In contrast, in the semiconductor device 1A in the present variation, a plurality of intermediate layers that divide the barrier layer 17 into a plurality of layers in the stacking direction (Y-axis direction) are inserted into the barrier layer 17.

[0114] In other words, the semiconductor device 1A has a stacked configuration in which the substrate 11, the first buffer layer 12, the second buffer layer 13, the channel layer 14, the first spacer layer 15, the second spacer layer 16, the barrier layer 17, and two intermediate layers 18 and a protective layer 19, for example, dividing the barrier layer 17 into, for example, three layers (the first barrier layer 17A, the second barrier layer 17B, and the third barrier layer 17C), are stacked in sequence. In addition, the semiconductor device 1A has the following stacked configuration: the substrate 11, the first buffer layer 12, the second buffer layer 13, the channel layer 14, the first spacer layer 15, the second spacer layer 16, the barrier layer 17, and three intermediate layers 18 and a protective layer 19, for example, dividing the barrier layer 17 into, for example, four layers (the first barrier layer 17A, the second barrier layer 17B, the third barrier layer 17C, and the fourth barrier layer 17D), are stacked in sequence. Except for these points, the semiconductor device 1A has a configuration substantially similar to that of the semiconductor device 1.

[0115] Likewise, in the semiconductor device 1A of the present modification, each of the semiconductor devices includes Al x2 In y2 Ga (1-x2-y2) A plurality of intermediate layers 18 of nitride semiconductors N (0≤x2<1, 0≤y2<1) and satisfying (1-x1-y1)<(1-x2-y2) are provided on a nitride semiconductor (Al2O3) having a band gap larger than that of the channel layer 14. x1 In y1 Ga (1-x1-y1)N(0<x1<1, 0<y1<1)) in the barrier layer 17, thereby improving the crystallinity of the barrier layer 17. Thus, the semiconductor device 1 makes it possible to improve heat resistance, as in the above-mentioned embodiment. In addition, high gm and high frequency characteristics can be obtained without deteriorating the sheet resistance of the two-dimensional electron gas. In addition, although the semiconductor device 1 has a Schottky-type gate configuration, the improved crystallinity of the barrier layer 17 makes it possible to reduce the so-called off-leakage current compared to a semiconductor device having a configuration without the intermediate layer 18.

[0116] (2-2. Modification 2)

[0117] Figure 5 An example of a cross-sectional configuration of a semiconductor device (semiconductor device 1B) according to Modification 2 of the present disclosure is schematically shown.

[0118] In the above embodiment, as the Al x2 In y2 Ga (1-x2-y2) N (0≤x2≤1, 0≤y2<1) nitride semiconductor, the intermediate layer 18 including GaN is inserted into the barrier layer 17. In contrast, in the semiconductor device 1B in the present modification, as the intermediate layer including Al x2 In y2 Ga (1-x2-y2) The intermediate layer 28 of the nitride semiconductor of N (0≤x2≤1, 0≤y2<1), including AlGaN or AlInGaN having a Ga composition greater than the Ga composition of the barrier layer 17, is inserted into the barrier layer 17. For the AlGaN mixed crystal or the AlInGaN mixed crystal, it is preferred that the Ga composition is at least 1% or more, and it is particularly preferred that the Ga composition is 30% or more. Except for this, the semiconductor device 1B has a configuration substantially similar to that of the semiconductor device 1.

[0119] Likewise, in the semiconductor device 1B of this modification, the semiconductor device 1B includes Al x2 In y2 Ga (1-x2-y2) The intermediate layer 28 of the nitride semiconductor N (0≤x2<1, 0≤y2<1) and satisfying (1-x1-y1)<(1-x2-y2) is provided on the nitride semiconductor (Al2O3) having a band gap larger than the band gap of the channel layer 14. x1 In y1 Ga (1-x1-y1)N(0<x1<1, 0<y1<1)) in the barrier layer 17, thereby improving the crystallinity of the barrier layer 17. Thus, the semiconductor device 1 makes it possible to improve heat resistance, as in the above-mentioned embodiment. In addition, high gm and high frequency characteristics can be obtained without deteriorating the sheet resistance of the two-dimensional electron gas. In addition, although the semiconductor device 1 has a Schottky-type gate configuration, the improved crystallinity of the barrier layer 17 makes it possible to reduce the so-called off-leakage current compared to a semiconductor device having a structure without the intermediate layer 28.

[0120] (2-3. Modification 3)

[0121] Figure 6 An example of a cross-sectional configuration of a semiconductor device (semiconductor device 1C) according to Modification 3 of the present disclosure is schematically shown. Figure 7 Another example of a cross-sectional configuration of a semiconductor device 1C according to Modification 3 of the present disclosure is schematically shown.

[0122] In the above embodiment, the intermediate layer 18 is inserted at the position where the barrier layer 17 is divided into the first barrier layer 17A and the second barrier layer 17B each having substantially the same thickness. Figure 6 The thickness of the lower layer (first barrier layer 27A) is greater than that of the upper layer (second barrier layer 27B), and Figure 7 The upper layer (second barrier layer 27AB) is shown to have a greater thickness than the lower layer (first barrier layer 27A). Except for these points, the semiconductor device 1C has a configuration substantially similar to that of the semiconductor device 1 .

[0123] Likewise, in the semiconductor device 1C of this modification, the x2 In y2 Ga (1-x2-y2) The intermediate layer 18 of the nitride semiconductor N (0≤x2<1, 0≤y2<1) and satisfying (1-x1-y1)<(1-x2-y2) is provided on the nitride semiconductor (Al2O3) having a band gap larger than the band gap of the channel layer 14. x1 In y1 Ga (1-x1-y1) N(0<x1<1, 0<y1<1)) in the barrier layer 27, thereby improving the crystallinity of the barrier layer 27. As a result, the semiconductor device 1 can improve heat resistance, as in the above-mentioned embodiment. In addition, high gm and high frequency characteristics can be obtained without deteriorating the sheet resistance of the two-dimensional electron gas. In addition, although the semiconductor device 1 has a Schottky-type gate configuration, the improved crystallinity of the barrier layer 27 makes it possible to reduce the so-called off-leakage current compared to a semiconductor device having a configuration without the intermediate layer 28.

[0124] (2-4. Modification 4)

[0125] Figure 8 An example of a cross-sectional configuration of a semiconductor device (semiconductor device 1D) according to Modification 4 of the present disclosure is schematically shown.

[0126] In the above embodiment, the intermediate layer 18 is inserted into the x1 In y1 Ga (1-x1-y1) In contrast, in the semiconductor device 1D in the present modification, one of the first barrier layer 37A and the second barrier layer 37B separated by the intermediate layer 18 includes AlInGaN as the barrier layer containing Al. x1 In y1 Ga (1-x1-y1) The semiconductor device 1D has a configuration basically similar to that of the semiconductor device 1 except for this.

[0127] Likewise, in the semiconductor device 1D of this modification, the x2 In y2 Ga (1-x2-y2) The intermediate layer 18 of the nitride semiconductor N (0≤x2<1, 0≤y2<1) and satisfying (1-x1-y1)<(1-x2-y2) is provided on the nitride semiconductor (Al2O3) having a band gap larger than the band gap of the channel layer 14. x1 In y1 Ga (1-x1-y1) N(0<x1<1, 0<y1<1)) in the barrier layer 37, thereby improving the crystallinity of the barrier layer 37. As a result, the semiconductor device 1 can improve heat resistance, as in the above-mentioned embodiment. In addition, high gm and high frequency characteristics can be obtained without deteriorating the sheet resistance of the two-dimensional electron gas. In addition, although the semiconductor device 1 has a Schottky-type gate configuration, the improved crystallinity of the barrier layer 37 makes it possible to reduce the so-called off-leakage current compared to a semiconductor device having a configuration without the intermediate layer 18.

[0128] (2-5. Modification 5)

[0129] Fig. 9 An example of a cross-sectional configuration of a semiconductor device (semiconductor device 1E) according to Modification 5 of the present disclosure is schematically shown.

[0130] In the above embodiment, the intermediate layer 18 is inserted into the x1 In y1 Ga (1-x1-y1)In contrast, in the semiconductor device 1E in the present modification, the AlInN mixed crystals have different Al compositions. x1 In y1 Ga (1-x1-y1) The semiconductor device 1E is a nitride semiconductor of N (0<x1<1, 0<y1<1) and is included in the first barrier layer 47A and the second barrier layer 47B separated by the intermediate layer 18. The semiconductor device 1E has a substantially similar structure to the semiconductor device 1 except for this.

[0131] Likewise, in the semiconductor device 1E of this modification, the semiconductor device 1E includes Al x2 In y2 Ga (1-x2-y2) The intermediate layer 18 of a semiconductor N (0≤x2<1, 0≤y2<1) and satisfying (1-x1-y1)<(1-x2-y2) is provided on a nitride semiconductor (Al2O3) having a band gap larger than that of the channel layer 14. x1 In y1 Ga (1-x1-y1) N(0<x1<1, 0<y1<1)) in the barrier layer 47, thereby improving the crystallinity of the barrier layer 47. As a result, the semiconductor device 1 can improve heat resistance, as in the above-mentioned embodiment. In addition, high gm and high frequency characteristics can be obtained without deteriorating the sheet resistance of the two-dimensional electron gas. In addition, although the semiconductor device 1 has a Schottky-type gate configuration, the improved crystallinity of the barrier layer 47 makes it possible to reduce the so-called off-leakage current compared to a semiconductor device having a configuration without the intermediate layer 18.

[0132] <3. Example>

[0133] Figures 10 to 13 Each schematically shows a cross-sectional configuration of a general semiconductor device (semiconductor device 100A, 100B, 100C, or 100D) as a reference example. Figure 1 Samples of the semiconductor device 1 of the illustrated embodiment and samples of semiconductor devices 100A, 100B, 100C, and 100D as reference examples were prepared and evaluated for heat resistance, off-leakage current, barrier layer oxidation inhibition, and gm characteristics.

[0134] [Evaluation of heat resistance]

[0135] (Example)

[0136] test Figure 1 The heat resistance of the semiconductor device 1 shown in FIG. Figure 1The sample of the channel layer 14, the first spacer layer 15, the second spacer layer 16, the barrier layer 17, the intermediate layer 18 disposed in the barrier layer 17, and the protective layer 19 of the semiconductor device 1 shown in the figure was annealed at 900° C. for 2 minutes in a nitrogen atmosphere to compare the change in sheet resistance before and after annealing. Here, the sheet resistance of the two-dimensional electron gas layer 2DEG formed in the channel layer was measured by an eddy current method.

[0137] It should be noted that in the semiconductor device 1 as a sample of the embodiment, the channel layer 14 includes GaN with a film thickness of 200nm. The first spacer layer 15 includes AlN with a film thickness of 1.0nm. The second spacer layer 16 includes GaN with a film thickness of 1.0nm. For the barrier layer 17, the first barrier layer 17A includes AlInN with a film thickness of 1.8nm, and the second barrier layer 17B includes AlInN with a film thickness of 1.8nm. The intermediate layer 18 includes GaN with a film thickness of 0.25nm. The protective layer 19 includes GaN with a film thickness of 2.5nm.

[0138] (Refer to Examples 1 to 4)

[0139] For comparison, a sample of each of the semiconductor devices 100A, 100B, 100C, and 100D as reference examples 1 to 4 was prepared in a manner similar to the embodiment, and the heat resistance was tested. The sample of the semiconductor device 100A as reference example 1 had the same configuration as the sample of the semiconductor device 1 of the embodiment, except that the barrier layer 107 included AlInN with a film thickness of 4 nm, and did not include the intermediate layer 108 and the protective layer 109. The sample of the semiconductor device 100B as reference example 2 had the same configuration as the sample of the semiconductor device 1 of the embodiment, except that the barrier layer 107 included AlInN with a film thickness of 4 nm, the protective layer 109 included GaN with a film thickness of 2.5 nm, and did not include the intermediate layer 108. The sample of the semiconductor device 100C as reference example 3 had the same configuration as the sample of the semiconductor device 1 of the embodiment, except that the barrier layer 107 included AlInN with a film thickness of 4 nm, the protective layer 109 included GaN with a film thickness of 1.0 nm, and did not include the intermediate layer 108. The sample of the semiconductor device 100D as Reference Example 4 has the same configuration as the sample of the semiconductor device 1 of the embodiment, except that the barrier layer 107 includes AlInN with a film thickness of 4 nm, the protective layer 109 includes GaN with a film thickness of 0.5 nm, and the intermediate layer 108 is not included.

[0140] In the example and reference examples 1 to 4, the change in sheet resistance before and after annealing was 27% in the example, 154% in reference example 1, 24% in reference example 2, 42% in reference example 3, and 40% in reference example 4.

[0141] From this result, it can be found that, in the case where the thickness of the protective layer 109 is changed, the heat resistance is improved as the thickness increases. However, as described above, for the protective layers 19 and 109 including GaN, the high-frequency characteristics decrease as the thickness increases. Therefore, it is desirable that the thickness of the protective layers 19 and 109 is as small as possible. In the semiconductor device 1 of the embodiment, the heat resistance is improved compared to the reference example 4 having the same thickness of 0.5 nm as the protective layer 19, and its heat resistance is equivalent to the heat resistance of the reference example 2 including the protective layer 109 having a thickness of 5 times (2.5 nm).

[0142] [Evaluation of Off-Leakage Current]

[0143] For Reference Example 4 and the embodiment, the Id (drain current)-Vg (gate voltage) characteristics were measured, and the results are shown in Fig.14 (See Example 4) and Fig.15 (Example) It was found that the sample of the example can reduce the off-leakage current by about 0.6 times compared with the sample of reference example 4. This is considered to be due to the improvement of the crystallinity of the barrier layer 17 in the semiconductor device 1 of the example compared with the semiconductor device 100D of reference example 4.

[0144] [Evaluation of oxidation inhibition]

[0145] The oxygen contamination of the outermost layer in each sample of the embodiment, reference example 1 and reference example 4 was analyzed by transmission electron microscopy (TEM) and energy dispersive X-ray analysis (EDX). As a result, 4 nm of oxygen contamination (i.e., across the entire barrier layer) was observed in the sample of reference example 1 that did not include the protective layer 109, and oxygen contamination at a depth of 1.5 nm from the upper surface of the barrier layer 104 was observed in the sample of reference example 4 that included the protective layer 109 having a thickness of 0.5 nm. In contrast, in the sample of the embodiment, oxygen contamination at a depth of 0.5 nm from the upper surface of the barrier layer 104 was observed. In addition, similar results were obtained using electron energy loss spectroscopy (EELS). This indicates that the semiconductor device 1 of the embodiment is effective in suppressing surface oxidation of the barrier layer 17.

[0146] [Evaluation of gm characteristics]

[0147] The current-voltage characteristics of Reference Example 2 and the embodiment were measured, and Fig.16 (See Example 2) and Fig.17 The results are shown in (Example). In the sample of Example, a gm of about 1.3 times higher than that of the sample of Reference Example 2 was obtained, and a steeper derivative of the IV curve was also obtained. This is considered to be due to the improvement of the crystallinity of the barrier layer 17 in the semiconductor device 1 of the example compared with the semiconductor device 100B of Reference Example 2.

[0148] <4. Application Examples>

[0149] (4-1. Semiconductor module)

[0150] Then, refer to Fig.18 A semiconductor module is described as a first application example of the technology according to the present disclosure. Fig.18 is a schematic perspective view showing the configuration of the semiconductor module 1000 .

[0151] like Fig.18 As shown, the semiconductor module 1000 is an antenna-integrated module in which, for example, an edge antenna 1020 and a plurality of front-end components are mounted as a module on a chip 1050. For example, the edge antenna 1020 is formed in a plurality of arrays on the chip 1050. The front-end components are, for example, a switch 1010, a low noise amplifier 1041, a bandpass filter 1042, and a power amplifier 1043. For example, the semiconductor module 1000 can be used as a transceiver for wireless communication.

[0152] The semiconductor module 1000 includes, for example, a semiconductor device (e.g., semiconductor device 1) of the above-described embodiment as a transistor included in a switch 1010, a low noise amplifier 1041, a power amplifier 1043, etc. For example, in the fifth generation mobile communication (5G) using radio waves in a higher frequency band, there is a large propagation loss of radio waves. Therefore, it is expected that the semiconductor module 1000 compatible with 5G transmits radio waves with higher power. Because the semiconductor module 1000 including the semiconductor device 1 can improve device characteristics, wireless communication can be performed with high power, low power consumption and high reliability. In other words, the semiconductor module 1000 can be more appropriately used for the fifth generation mobile communication (5G).

[0153] (4-2. Wireless communication equipment)

[0154] Next, refer to Fig.19 A wireless communication device is described as a second application example of the technology according to the present disclosure. Fig.19 2000 is a block diagram showing the configuration of the wireless communication device 2000 .

[0155] like Fig.19 As shown in , the wireless communication device 2000 includes an antenna ANT, an antenna switch circuit 2003, a high power amplifier HPA, a radio frequency integrated circuit RFIC (Radio Frequency Integrated Circuit), a baseband unit BB, a voice output unit MIC, a data output unit DT, and an interface unit I / F (for example, a wireless LAN (Wireless Local Area Network: W-LAN) or Bluetooth (registered trademark)). For example, the wireless communication device 2000 is a cellular phone system having multiple functions such as voice communication, data communication, or LAN connection.

[0156] In the wireless communication device 2000, when transmitting, the transmission signal is output from the baseband unit BB to the antenna ANT via the radio frequency integrated circuit RFIC, the high power amplifier HPA and the antenna switch circuit 203. In addition, in the wireless communication device 2000, when receiving, the reception signal is input from the antenna ANT to the baseband unit BB via the antenna switch circuit 2003 and the radio frequency integrated circuit RFIC. The reception signal processed in the baseband unit BB is output to the outside of the wireless communication device 2000 from, for example, the voice output unit MIC, the data output unit DT or the interface unit I / F.

[0157] The wireless communication device 2000 includes the semiconductor device of the above-described embodiment and the like (e.g., the semiconductor device 1) as a transistor included in the antenna switch circuit 2003, the high power amplifier HPA, the radio frequency integrated circuit RFIC, or the baseband section BB, etc. This makes it possible to further improve the device characteristics, thereby enabling the wireless communication device 2000 to perform high-output, low-power consumption, and high-reliability wireless communication.

[0158] The technology according to the present disclosure has been described above with reference to some embodiments, Modifications 1 to 5, Examples, and Application Examples. However, the technology according to the present disclosure is not limited to the above-described embodiments and the like, and various modifications are possible.

[0159] In addition, not all configurations and operations described in the embodiments are indispensable to the configurations and operations of the present disclosure. For example, among the components of each embodiment, any component not stated in the independent claim representing the most general concept of the present disclosure should be understood as an optional component.

[0160] The terms used throughout this specification and the appended claims should be interpreted as "non-limiting" terms. For example, the terms "include" or "comprises" should be interpreted as "not limited to what is described as including". The term "has" should be interpreted as "not limited to what is described as having".

[0161] The terms used herein include terms that are used only for convenience of description and are not intended to limit the purpose of configuration and operation. For example, terms such as "right", "left", "upper", and "lower" only indicate directions in the drawings to which reference is made. In addition, the terms "inner" and "outer" only indicate directions toward the center of the component of interest and directions away from the center of the component of interest, respectively. The same applies to terms similar to these terms and terms of similar intent.

[0162] It should be noted that the effects described here are merely embodiments and are not limiting, and other effects may exist.

[0163] It should be noted that the present technology may have the following configuration. According to the present technology having the following configuration, the intermediate layer including the second nitride semiconductor is provided within the barrier layer including the second nitride semiconductor including Al x2 In y2 Ga (1-x2-y2) N (0≤x2<1, 0≤y2<1) and satisfying (1-x1-y1)<(1-x2-y2), the second nitride semiconductor includes Al x1 In y1 Ga (1-x1-y1) N(0<x1<1, 0<y1<1) and has a second band gap larger than the first band gap of the first nitride semiconductor included in the channel layer, thereby improving the crystallinity of the barrier layer. This makes it possible to improve heat resistance. (1)

[0165] A semiconductor device, comprising:

[0166] substrate;

[0167] A channel layer is disposed on one surface side of the substrate, and the channel layer includes a first nitride semiconductor having a first band gap;

[0168] The barrier layer is provided on the opposite side of the channel layer relative to the substrate and includes a second nitride semiconductor including Al x1 In y1 Ga (1-x1-y1) N(0<x1<1, 0<y1<1), and having a second band gap larger than the first band gap of the first nitride semiconductor; and

[0169] The intermediate layer is disposed in the barrier layer and includes a third nitride semiconductor including Al x2 In y2 Ga (1-x2-y2) N(0≤x2<1,0≤y2<1), where

[0170] Satisfies (1-x1-y1)<(1-x2-y2). (2)

[0172] The semiconductor device according to (1), wherein x2<x1 is satisfied. (3)

[0174] The semiconductor device according to (1) or (2), wherein 1-x2-y2>0.01 is satisfied. (4)

[0176] The semiconductor device according to any one of (1) to (3), wherein the intermediate layer has a thickness of 0.26 nm or more and 2.0 nm or less. (5)

[0178] The semiconductor device according to any one of (1) to (4), wherein:

[0179] The barrier layer includes a first barrier layer and a second barrier layer, the first barrier layer is disposed on the channel layer side, the intermediate layer is located between the first barrier layer and the second barrier layer, and the second barrier layer is disposed on the opposite side relative to the channel layer, and

[0180] The first barrier layer and the second barrier layer have different Al compositions from each other. (6)

[0182] The semiconductor device according to any one of (1) to (5), wherein x1 is greater than 0.7 and y1 is less than 0.3. (7)

[0184] The semiconductor device according to any one of (1) to (6), wherein the barrier layer has a thickness of 2.0 nm or more and 20 nm or less. (8)

[0186] The semiconductor device according to any one of (1) to (7), further comprising a protective layer located on the opposite side of the barrier layer relative to the channel layer, the protective layer comprising Al x3 In y3 Ga (1-x3-y3) N(0≤x3<1, 0≤y3<1), and satisfies (1-x1-y1)<(1-x3-y3). (9)

[0188] The semiconductor device according to any one of (1) to (8), further comprising a first spacer layer and a second spacer layer, wherein the first spacer layer and the second spacer layer are sequentially stacked between the channel layer and the barrier layer, and the first spacer layer comprises Al x4 In y4 Ga (1-x4-y4) N(0<x4≤1,0≤y4<1,0≤x4+y4≤1), and the second spacer layer includes Al x5 In y5 Ga (1-x5-y5) N(0<x5<x4≤1, 0≤y5<1, 0<x5+y5<1). (10)

[0190] A semiconductor device according to any one of (1) to (9), wherein the channel layer includes at least one of GaN (gallium nitride), InGaN (indium gallium nitride), InN (indium nitride), AlGaN (aluminum gallium nitride), or AlInGaN (aluminum indium gallium nitride). (11)

[0192] The semiconductor device according to any one of (1) to (10), wherein the substrate includes at least one of Si (silicon), sapphire, SiC (silicon carbide), GaN (gallium nitride), or AlN (aluminum nitride). (12)

[0194] The semiconductor device according to any one of (9) to (11), further comprising:

[0195] Insulating film;

[0196] a gate electrode;

[0197] a source electrode; and

[0198] Drain electrode,

[0199] An insulating film, a gate electrode, a source electrode, and a drain electrode are provided on the opposite side of the barrier layer with respect to the second spacer layer. (13)

[0201] The semiconductor device according to any one of (8) to (12), further comprising:

[0202] Insulating film;

[0203] a gate electrode;

[0204] a source electrode; and

[0205] Drain electrode,

[0206] An insulating film, a gate electrode, a source electrode, and a drain electrode are provided on the protective layer. (14)

[0208] The semiconductor device according to (13), wherein the semiconductor device has a Schottky type gate configuration in which the protective layer and the gate electrode have a Schottky junction. (15)

[0210] A semiconductor module including a semiconductor device, the semiconductor device including:

[0211] substrate;

[0212] A channel layer is disposed on one surface side of the substrate, and the channel layer includes a first nitride semiconductor having a first band gap;

[0213] The barrier layer is provided on the opposite side of the channel layer relative to the substrate and includes a second nitride semiconductor including Al x1 In y1 Ga (1-x1-y1) N(0<x1<1, 0<y1<1), and having a second band gap larger than the first band gap of the first nitride semiconductor; and

[0214] The intermediate layer is disposed in the barrier layer and includes a third nitride semiconductor including Al x2 In y2 Ga (1-x2-y2) N(0≤x2<1,0≤y2<1), where,

[0215] The semiconductor device satisfies (1-x1-y1)<(1-x2-y2). (16)

[0217] A wireless communication device includes a semiconductor device, wherein the semiconductor device includes:

[0218] substrate;

[0219] A channel layer is disposed on one surface side of the substrate, and the channel layer includes a first nitride semiconductor having a first band gap;

[0220] The barrier layer is provided on the opposite side of the channel layer relative to the substrate and includes a second nitride semiconductor including Al x1 In y1 Ga (1-x1-y1) N(0<x1<1, 0<y1<1), and having a second band gap larger than the first band gap of the first nitride semiconductor; and

[0221] The intermediate layer is disposed in the barrier layer and includes a third nitride semiconductor including Al x2 In y2 Ga (1-x2-y2) N(0≤x2<1,0≤y2<1), where,

[0222] The semiconductor device satisfies (1-x1-y1)<(1-x2-y2).

[0223] This application claims the benefit of Japanese Priority Patent Application JP2022-139301 filed with the Japan Patent Office on September 1, 2022, the entire contents of which are incorporated herein by reference.

[0224] Those skilled in the art should understand that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.

Claims

1. A semiconductor device, comprising: substrate; A channel layer is disposed on a surface side of the substrate, wherein the channel layer includes a first nitride semiconductor having a first band gap; A barrier layer is provided on the opposite side of the channel layer relative to the substrate and includes a second nitride semiconductor including Al x1 In y1 Ga (1-x1-y1) N(0<x1<1, 0<y1<1), and having a second band gap larger than the first band gap of the first nitride semiconductor; as well as The intermediate layer is disposed in the barrier layer and includes a third nitride semiconductor including Al x2 In y2 Ga (1-x2-y2) N(0≤x2<1,0≤y2<1), where, Satisfies (1-x1-y1)<(1-x2-y2).

2. The semiconductor device according to claim 1, wherein Satisfies x2<x1.

3. The semiconductor device according to claim 1, wherein Satisfies 1-x2-y2>0.

01.

4. The semiconductor device according to claim 1, wherein: The intermediate layer has a thickness of 0.26 nm or more and 2.0 nm or less.

5. The semiconductor device according to claim 1, wherein The barrier layer includes a first barrier layer and a second barrier layer, the first barrier layer is disposed on the channel layer side, the intermediate layer is located between the first barrier layer and the second barrier layer, and the second barrier layer is disposed on the opposite side relative to the channel layer, and The first barrier layer and the second barrier layer have different Al compositions from each other.

6. The semiconductor device according to claim 1, wherein x1 is greater than 0.7 and y1 is less than 0.

3.

7. The semiconductor device according to claim 1, wherein The barrier layer has a thickness of 2.0 nm or more and 20 nm or less.

8. The semiconductor device according to claim 1, further comprising a protective layer, the protective layer being located on an opposite side of the barrier layer relative to the channel layer, the protective layer comprising Al x3 In y3 Ga (1-x3-y3) N(0≤x3<1, 0≤y3<1), and satisfies (1-x1-y1)<(1-x3-y3).

9. The semiconductor device according to claim 1, further comprising a first spacer layer and a second spacer layer, wherein the first spacer layer and the second spacer layer are sequentially stacked between the channel layer and the barrier layer, and the first spacer layer comprises Al x4 In y4 Ga (1-x4-y4) N(0<x4≤1, 0≤y4<1, 0≤x4+y4≤1), and the second spacer layer includes Al x5 In y5 Ga (1-x5-y5) N(0<x5<x4≤1, 0≤y5<1, 0<x5+y5<1).

10. The semiconductor device according to claim 1, wherein The channel layer includes at least one of GaN (gallium nitride), InGaN (indium gallium nitride), InN (indium nitride), AlGaN (aluminum gallium nitride) or AlInGaN (aluminum indium gallium nitride).

11. The semiconductor device according to claim 1, wherein The substrate includes at least one of Si (silicon), sapphire, SiC (silicon carbide), GaN (gallium nitride) or AlN (aluminum nitride).

12. The semiconductor device according to claim 9, further comprising: Insulating film; a gate electrode; source electrode; as well as Drain electrode, The insulating film, the gate electrode, the source electrode, and the drain electrode are provided on the opposite side of the barrier layer with respect to the second spacer layer.

13. The semiconductor device according to claim 8, further comprising: Insulating film; a gate electrode; source electrode; as well as Drain electrode, The insulating film, the gate electrode, the source electrode, and the drain electrode are provided on the protective layer.

14. The semiconductor device according to claim 13, wherein: The semiconductor device has a Schottky-type gate configuration in which the protection layer and the gate electrode have a Schottky junction.

15. A semiconductor module comprising a semiconductor device, the semiconductor device comprising: substrate; A channel layer is disposed on a surface side of the substrate, wherein the channel layer includes a first nitride semiconductor having a first band gap; A barrier layer is provided on the opposite side of the channel layer relative to the substrate and includes a second nitride semiconductor including Al x1 In y1 Ga (1-x1-y1) N(0<x1<1, 0<y1<1), and having a second band gap larger than the first band gap of the first nitride semiconductor; as well as The intermediate layer is disposed in the barrier layer and includes a third nitride semiconductor including Al x2 In y2 Ga (1-x2-y2) N(0≤x2<1,0≤y2<1), where, The semiconductor device satisfies (1-x1-y1)<(1-x2-y2).

16. A wireless communication device, comprising a semiconductor device, wherein the semiconductor device comprises: substrate; a channel layer disposed on a surface side of the substrate, the channel layer comprising a first nitride semiconductor having a first band gap, A barrier layer is provided on the opposite side of the channel layer relative to the substrate and includes a second nitride semiconductor including Al x1 In y1 Ga (1-x1-y1) N(0<x1<1, 0<y1<1), and having a second band gap larger than the first band gap of the first nitride semiconductor; as well as The intermediate layer is disposed in the barrier layer and includes a third nitride semiconductor including Al x2 In y2 Ga (1-x2-y2) N(0≤x2<1,0≤y2<1), where, The semiconductor device satisfies (1-x1-y1)<(1-x2-y2).

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