A referenceless over / under voltage protection detection device and method

Abstract

This invention discloses a referenceless over / undervoltage protection detection device and method, comprising: a power supply voltage detection network, a single-input trigger circuit, a feedback circuit, and a buffer; the power supply voltage detection network detects real-time information of the chip's power supply voltage and transmits the detected voltage to the single-input trigger circuit; the single-input trigger circuit determines whether the chip's power supply voltage is over-voltage or under-voltage based on the detected voltage and generates a switching voltage; the feedback circuit adjusts the output coefficient of the power supply voltage detection network based on the switching voltage feedback from the single-input trigger circuit to achieve over-voltage or under-voltage protection of the chip's power supply voltage; the buffer is used to enhance the driving capability of the power supply voltage for over-voltage or under-voltage protection. This invention uses a single-input trigger circuit for chip power supply voltage detection, which can better protect the chip's operation.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit technology, specifically, it relates to a reference-free over / under voltage protection detection device and method. Background Technology

[0002] In automotive and consumer electronics applications, chips often contain high-voltage signals or multiple power signals. When overvoltage or undervoltage occurs, the over / undervoltage protection detection device, which serves as the power source for the main functional module devices, can prevent chip damage, thereby ensuring the chip operates safely and efficiently.

[0003] Currently, typical over / under voltage protection detection devices generally utilize a reference voltage V provided by other modules. ref As a stable reference source, the power supply voltage information is detected through a power supply voltage sensing network, and the reference voltage V is then used. ref The detection results from the power supply voltage detection network are compared with those from a comparator, and the comparison result is used as an indicator of whether there is an over / under voltage, which is then transmitted to the subsequent functional module. However, this method requires a reference voltage source that directly uses an external high voltage as the power supply, which is a challenge for many high-voltage applications. Therefore, it cannot be used directly and will incur additional power consumption, which is also a burden for low-power devices. Summary of the Invention

[0004] To address the problems existing in the prior art, the present invention provides a reference-free over / under voltage protection detection device and method, which uses a single-input trigger circuit to detect the power supply voltage of the chip, thereby better protecting the chip's operation.

[0005] To achieve the above technical objectives, the present invention adopts the following technical solution: a reference-free over / under voltage protection detection device, comprising: a power supply voltage detection network, a single-input trigger circuit, a feedback circuit, and a buffer;

[0006] The power supply voltage detection network is used to detect the real-time information of the chip power supply voltage and transmit the detected voltage to the single-input trigger circuit.

[0007] The single-input trigger circuit determines whether the chip power supply voltage is over-voltage or under-voltage based on the detected voltage, and generates a switching voltage.

[0008] The feedback circuit adjusts the output coefficient of the power supply voltage detection network based on the flip voltage feedback from the single-input trigger circuit to achieve overvoltage or undervoltage protection of the chip power supply voltage.

[0009] The buffer is used to enhance the driving capability of the power supply voltage for overvoltage or undervoltage protection.

[0010] Furthermore, the power supply voltage detection network includes: a first resistor R1, a second resistor R2, and a third resistor R3, wherein one end of the first resistor R1 is connected to the power supply voltage V of the chip. DD The first resistor R1 and the second resistor R2 are connected together as the output terminal of the power supply voltage detection network and connected to the input terminal of the single-input trigger circuit. The other end of the second resistor R2 is connected to the output terminal of the feedback circuit and one end of the third resistor R3, and the other end of the third resistor R3 is grounded.

[0011] Further, the single-input trigger circuit includes: a first bipolar transistor Q1, a second bipolar transistor Q2, a first PMOS transistor PM1, a second PMOS transistor PM2, a fourth resistor R4, a fifth resistor R5, and a current comparator. The bases of the first bipolar transistor Q1 and the second bipolar transistor Q2 together serve as the input terminals of the single-input trigger circuit. The emitter of the first bipolar transistor Q1 is connected to one end of the fourth resistor R4 and one end of the fifth resistor R5, respectively. The emitter of the second bipolar transistor Q2 is connected to the other end of the fourth resistor R4, and the other end of the fifth resistor R5 is grounded. The collector of the first bipolar transistor Q1, the drain of the first PMOS transistor PM1, and the gate of the first PMOS transistor PM1 are all connected to the first input terminal of the current comparator. The collector of the second bipolar transistor Q2, the drain of the second PMOS transistor PM2, and the gate of the second PMOS transistor PM2 are all connected to the second input terminal of the current comparator. The sources of the first PMOS transistor PM1 and the second PMOS transistor PM2 are both connected to the chip's power supply voltage V. DD Connection; the output terminal of the current comparator is connected to the input terminal of the feedback circuit.

[0012] Further, the current comparator includes: a third PMOS transistor PM3, a fourth PMOS transistor PM4, a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, and a fourth NMOS transistor NM4. The gate of the fourth PMOS transistor PM4 serves as the first input terminal of the current comparator, and the gate of the third PMOS transistor PM3 serves as the second input terminal of the current comparator. The sources of both the third PMOS transistor PM3 and the fourth PMOS transistor PM4 are connected to the chip's power supply voltage V. DDThe third PMOS transistor PM3 is connected to the gate of the first NMOS transistor NM1, the drain of the first NMOS transistor NM1, the drain of the second NMOS transistor NM2, and the gate of the third NMOS transistor NM3. The sources of the first NMOS transistor NM1, the second NMOS transistor NM2, the third NMOS transistor NM3, and the fourth NMOS transistor NM4 are all grounded. The drain of the fourth PMOS transistor PM4, the gate of the second NMOS transistor NM2, the drain of the third NMOS transistor NM3, the gate of the fourth NMOS transistor NM4, and the drain of the fourth NMOS transistor NM4 together serve as the output terminal of the current comparator.

[0013] Furthermore, the feedback circuit includes a Schmitt trigger and a feedback switch. The input terminal of the Schmitt trigger serves as the input terminal of the feedback circuit, and the output terminal of the Schmitt trigger is connected to the control terminal of the feedback switch and the input terminal of the buffer, respectively. The feedback switch is connected to the power supply voltage detection network.

[0014] Furthermore, the feedback switch is a fifth NMOS transistor, the gate of the fifth NMOS transistor is connected to the output terminal of the Schmitt trigger, the drain of the fifth NMOS transistor is connected to one end of the second resistor R2 and the third resistor R3, and the source of the fifth NMOS transistor is grounded.

[0015] Furthermore, when it is an overvoltage protection detection device, the buffer is composed of an odd number of cascaded inverters; when it is an undervoltage protection detection device, the buffer is composed of an even number of cascaded inverters.

[0016] Furthermore, the power supply voltage detection network outputs the detection voltage V to the single-input trigger circuit. IN for:

[0017] V IN =M*V S

[0018] Where M is the output coefficient of the power supply voltage detection network, when the third resistor R3 is short-circuited. When the third resistor R3 is connected to the power supply voltage detection network R1 represents the resistance value of the first resistor R1, R2 represents the resistance value of the second resistor R2, and R3 represents the resistance value of the third resistor R3; V S This indicates the real-time value of the power supply voltage.

[0019] Furthermore, the resistance values ​​of the first resistor R1, the second resistor R2, and the third resistor R3 satisfy the following:

[0020]

[0021] Among them, V IHThe voltage at the inflection point during the rise of the power supply voltage, V BE1 V represents the difference between the base and emitter voltages of the first bipolar transistor Q1, N represents the ratio of the number of second bipolar transistors Q2 to the number of first bipolar transistors Q1, and V represents the difference between the base and emitter voltages of the first bipolar transistor Q1. T The voltage equivalent of temperature; R4 represents the resistance of the fourth resistor; R5 represents the resistance of the fifth resistor; V IL This indicates the reversal point voltage during the power supply voltage drop process.

[0022] Furthermore, the present invention also provides an over / under voltage protection method for the aforementioned referenceless over / under voltage protection detection device. When it is an overvoltage protection device, the specific process of overvoltage protection of the chip power supply voltage is as follows:

[0023] When the power supply voltage detection network detects the chip power supply voltage V DD Exceeding the first high-level switching voltage V IH_OR At this time, the input voltage of the single-input trigger circuit is... Subsequently, the output of the single-input trigger circuit toggles to a high level, the feedback switch in the feedback circuit turns off, enabling the third resistor R3. The buffer drives the subsequent circuit, causing the overvoltage protection device to output a high level, triggering overvoltage protection. When the power supply voltage toggles from the first high level to the voltage V... IH_OR The voltage V drops back to the first low-level switching voltage after the overvoltage is canceled. IL_OF At this time, the input voltage of the single-input trigger circuit is... When the feedback switch of the feedback circuit is turned on, the third resistor R3 is shielded. The buffer drives the subsequent circuit, causing the overvoltage protection device to output a low level, thus canceling the overvoltage protection. Here, V... IH_OR >V IL_OF >Chip power supply voltage V DD .

[0024] Furthermore, the present invention also provides an over / under voltage protection method for the aforementioned referenceless over / under voltage protection detection device. When it is an undervoltage protection device, the specific process of performing undervoltage protection on the chip voltage is as follows:

[0025] When the power supply voltage detection network detects the chip power supply voltage V DD Below the second low-level switching voltage V IL_UF At this time, the input voltage of the single-input trigger circuit is... Subsequently, the output of the single-input trigger circuit toggles to a low level, the feedback switch in the feedback circuit is turned on, shielding the third resistor R3. The buffer drives the subsequent circuit, causing the undervoltage protection device to output a high level, triggering the undervoltage protection; when the power supply voltage toggles from the second low level to the voltage V... IL_UF Rebound to the second high-level switching voltage UIH_UR At this time, the input voltage of the single-input trigger circuit is... When the feedback switch of the feedback circuit is turned off, the third resistor R3 is enabled. The buffer drives the subsequent circuit, causing the undervoltage protection device to output a low level, thus canceling the undervoltage protection. Here, V... IL_UF <V IH_UR <Chip power supply voltage V DD .

[0026] Compared with the prior art, the present invention has the following beneficial effects: The single-input trigger circuit of the reference-free over / under voltage protection detection device and method of the present invention adopts the detection method of bipolar transistor pairs, which changes the traditional detection method that requires bias current and reference voltage. It is suitable for more design scenarios that cannot provide bias voltage, such as bias modules that control the same power supply or modules that cannot be directly designed with a reference voltage source for high voltage power supplies. The real-time status of the power supply voltage can be obtained based solely on the power supply voltage information, thus protecting the safe operation of the chip. In addition, the present invention also uses a current comparator with hysteresis and a Schmitt trigger to prevent false flips and glitches, resulting in lower overall power consumption than traditional over / under voltage protection detection devices. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the over / under voltage protection detection device without a reference according to the present invention;

[0028] Figure 2 This is a circuit diagram of the overvoltage protection detection device without a reference according to the present invention;

[0029] Figure 3 This is a circuit diagram of the undervoltage protection detection device without a reference according to the present invention. Detailed Implementation

[0030] The technical solution of the present invention will be further explained and described below with reference to the accompanying drawings.

[0031] like Figure 1 This is a schematic diagram of the referenceless over / undervoltage protection detection device of the present invention. The referenceless over / undervoltage protection detection device includes: a power supply voltage detection network 101, a single-input trigger circuit 201, a feedback circuit 301, and a buffer 401. The power supply voltage detection network 101 detects real-time information of the chip power supply voltage and transmits the detected voltage to the single-input trigger circuit 201. The single-input trigger circuit 201 determines whether the chip power supply voltage is over-voltage or under-voltage based on the detected voltage and generates a switching voltage. Specifically, the single-input trigger circuit 201 only needs to input the detected voltage without bias current or a reference voltage, utilizing the switching voltage V of the chip power supply voltage. IH and V IL The offset current between the two branches in the single-input trigger circuit 201 is generated, and the chip power supply voltage is at the normal level V.DD The initial current and accompanying chip power supply voltage V at that time DD The different rates of current change during the change are used to design the switching equilibrium point, thereby changing the output of the over / under voltage protection detection device. The feedback circuit 301 adjusts the output coefficient of the power supply voltage detection network 101 based on the switching voltage feedback from the single-input trigger circuit 201, achieving over / under voltage protection for the chip's power supply. The buffer 401 is used to enhance the driving capability of the power supply voltage for over / under voltage protection. This invention's reference-free over / under voltage protection detection device can obtain the real-time status of the power supply voltage based solely on the power supply voltage information, protecting the safe operation of the chip and reducing power consumption.

[0032] like Figure 2-3 In this invention, the power supply voltage detection network 101 includes: a first resistor R1, a second resistor R2, and a third resistor R3. One end of the first resistor R1 is connected to the power supply voltage V of the chip. DD The other end of the first resistor R1 and one end of the second resistor R2 are connected together as the output terminal of the power supply voltage detection network 101, which is connected to the input terminal of the single-input trigger circuit 201. The other end of the second resistor R2 is connected to the output terminal of the feedback circuit 301 and one end of the third resistor R3. The other end of the third resistor R3 is grounded. The detection voltage VIN is generated by voltage division through the series connection of the first resistor R1, the second resistor R2 and the third resistor R3.

[0033] The single-input trigger circuit 201 of this invention includes: a first bipolar transistor Q1, a second bipolar transistor Q2, a first PMOS transistor PM1, a second PMOS transistor PM2, a fourth resistor R4, a fifth resistor R5, and a current comparator. The ratio of the base of the first bipolar transistor Q1 to the number of the second bipolar transistor Q2 is 1:N. The bases of the first bipolar transistor Q1 and the bases of the second bipolar transistor Q2 together serve as the input terminal of the single-input trigger circuit 201, obtaining the power supply voltage V. DDThe current comparator monitors real-time over / under voltage conditions. The emitter of the first bipolar transistor Q1 is connected to one end of the fourth resistor R4 and one end of the fifth resistor R5, respectively. The emitter of the second bipolar transistor Q2 is connected to the other end of the fourth resistor R4, thus forming an offset current. The other end of the fifth resistor R5 is grounded. The collector of the first bipolar transistor Q1, the drain of the first PMOS transistor PM1, and the gate of the first PMOS transistor PM1 are all connected to the first input terminal of the current comparator, forming the left branch. The collector of the second bipolar transistor Q2, the drain of the second PMOS transistor PM2, and the gate of the second PMOS transistor PM2 are all connected to the second input terminal of the current comparator, forming the right branch. The current offset from the two branches is passed to the current comparator, which picks up the difference between the two collector currents and converts it into a 1-bit high / low level output for over / under voltage signal use. The sources of the first PMOS transistor PM1 and the second PMOS transistor PM2 are both connected to the chip's power supply voltage V. DD Connections: The output of the current comparator is connected to the input of the feedback circuit 301. The value of the ratio N depends on the trade-off between area, power consumption, and accuracy requirements; the larger N is, the larger the area or power consumption, and the lower the accuracy.

[0034] To prevent the base current of the bipolar transistor from affecting the normal operation of the power supply voltage detection network 101, the series resistance of the second resistor R2 and the third resistor R3 in this invention satisfies the following resistance relationship with the fifth resistor R5:

[0035] R2+R3>>R5*β1

[0036] Where β1 is the current amplification factor of the first bipolar transistor Q1.

[0037] The magnitude of the current of the first PMOS transistor PM1 is related to the collector current I of the first bipolar transistor Q1. C1 The second PMOS transistor PM2 has the same current magnitude as the collector current I of the second bipolar transistor Q2. C2 The currents are the same. During over / under voltage switching and during their respective recovery processes, the currents in the two branches reach equilibrium and are equal.

[0038] I C1 =I C2 =I tail / 2

[0039] When the currents are equal, the collector current of the first bipolar transistor Q1 and the collector current of the second bipolar transistor Q2 are equal, therefore:

[0040]

[0041] Among them, I tailV is the current flowing through the fifth resistor R5. BE1 ΔV is the difference between the base and emitter voltages of the first bipolar transistor Q1. BE =V BE1 -V BE2 V BE2 This is the difference between the base and emitter voltages of the second bipolar transistor Q2.

[0042] To convert the collected current information into a single-bit voltage signal common to subsequent modules, the single-input flip-flop 201 is equipped with a current comparator, which includes: a third PMOS transistor PM3, a fourth PMOS transistor PM4, a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, and a fourth NMOS transistor NM4. The gate of the fourth PMOS transistor PM4 serves as the first input terminal of the current comparator, and the gate of the third PMOS transistor PM3 serves as the second input terminal. The sources of both the third PMOS transistor PM3 and the fourth PMOS transistor PM4 are connected to the chip's power supply voltage V. DD Connections: The drain of the third PMOS transistor PM3 is connected to the gate of the first NMOS transistor NM1, the drain of the first NMOS transistor NM1, the drain of the second NMOS transistor NM2, and the gate of the third NMOS transistor NM3, respectively. The sources of the first NMOS transistor NM1, the second NMOS transistor NM2, the third NMOS transistor NM3, and the fourth NMOS transistor NM4 are all grounded. The drain of the fourth PMOS transistor PM4, the gate of the second NMOS transistor NM2, the drain of the third NMOS transistor NM3, the gate of the fourth NMOS transistor NM4, and the drain of the fourth NMOS transistor NM4 together serve as the output terminal of the current comparator.

[0043] The single-input trigger circuit 201 of this invention uses a bipolar transistor to generate different collector currents I on two branches based on the input detection voltage information. C1 and I C2 This results in current error I. C1 -I C2Before the power supply voltage rises to an overvoltage level, the current in the left branch is less than the current in the right branch; after the overvoltage occurs, the current in the left branch becomes greater than the current in the right branch. Before the power supply voltage rises to an undervoltage level, the current in the left branch is greater than the current in the right branch; after the overvoltage occurs, the current in the left branch becomes less than the current in the right branch. These two currents are input to a current comparator with hysteresis to determine the overvoltage. The hysteresis function ensures that even with a certain degree of mismatch between the third PMOS transistor PM3, the fourth PMOS transistor PM4, the first NMOS transistor NM1, the second NMOS transistor NM2, the third NMOS transistor NM3, and the fourth NMOS transistor NM4, there will be no false flipping. Furthermore, the second NMOS transistor NM2 or the third NMOS transistor NM3 in the branch with the larger current is in the off state, while the second NMOS transistor NM2 or the third NMOS transistor NM3 in the branch with the smaller current is in the on state, which will further accelerate and ensure correct triggering of the flipping.

[0044] The feedback circuit 301 includes a Schmitt trigger 302 and a feedback switch 303. The input terminal of the Schmitt trigger 302 serves as the input terminal of the feedback circuit 301. The output terminal of the Schmitt trigger 301 is connected to the control terminal of the feedback switch 303 and the input terminal of the buffer 401, respectively. The feedback switch 303 is connected to the power supply voltage detection network 101. The Schmitt trigger 302 can prevent output signal glitches in the single-input trigger circuit 201 and prevent the feedback switch 303 from mis-conducting and causing the third resistor R3 to change the current correct voltage division ratio, thereby improving the robustness of the switching function and the driving capability of the signal. In the overvoltage device, the input and output of the Schmitt trigger 301 are out of phase; in the undervoltage device, the input and output of the Schmitt trigger 301 are in phase.

[0045] Feedback switch 303 is a fifth NMOS transistor. The gate of the fifth NMOS transistor is connected to the output of Schmitt trigger 302, the drain of the fifth NMOS transistor is connected to the end of the second resistor R2 and the third resistor R3, and the source of the fifth NMOS transistor is grounded. When the chip's power supply voltage V... DD When overvoltage or undervoltage occurs, the power supply voltage detection network 101 outputs different voltages due to the opening and closing of the feedback switch 303.

[0046] In this invention, the power supply voltage detection network 101 outputs the detection voltage V to the single-input trigger circuit 201. IN for:

[0047] V IN =M*V S

[0048] Where M is the output coefficient of the power supply voltage detection network 101, and the value of M is affected by whether the third resistor R3 is connected. H This is the output coefficient when the third resistor R3 is short-circuited and shielded. M L This is the output coefficient when the third resistor R3 is connected to the power supply voltage detection network 101. R1 represents the resistance value of the first resistor R1, R2 represents the resistance value of the second resistor R2, and R3 represents the resistance value of the third resistor R3; V S This indicates the real-time value of the power supply voltage.

[0049] The third resistor R3 is shielded by the feedback circuit 301, M H The larger the value, the smaller the power supply voltage required to reach the flip point during detection and sensing. This makes the power supply more sensitive to overvoltage or undervoltage conditions, facilitating the detection and sensing of power supply voltage status. When the power supply returns to normal, it needs to recover to a voltage value further away from the flip point to cancel the overvoltage or undervoltage condition. Therefore, the feedback circuit 301 connects the third resistor R3 to the power supply voltage detection network 101, making M... L Smaller.

[0050] In this invention, the resistance values ​​of the first resistor R1, the second resistor R2, and the third resistor R3 satisfy the following:

[0051]

[0052] Among them, V IH The voltage at the inflection point during the rise of the power supply voltage, V BE1 V represents the difference between the base and emitter voltages of the first bipolar transistor Q1, N represents the ratio of the number of second bipolar transistors Q2 to the number of first bipolar transistors Q1, and V represents the difference between the base and emitter voltages of the first bipolar transistor Q1. T The voltage equivalent of temperature; R4 represents the resistance of the fourth resistor; R5 represents the resistance of the fifth resistor; V IL This indicates the reversal point voltage during the power supply voltage drop process.

[0053] like Figure 2 When used as an overvoltage protection detection device, buffer 401 consists of an odd number of cascaded inverters, resulting in opposite input and output polarities. This enhances the driving capability of the output signal, facilitating the complete transmission of the output signal to the digital module or enabling subsequent circuits, such as bandgap references and oscillators, to protect the chip. Figure 3 When used as an undervoltage protection detection device, buffer 401 is composed of an even number of cascaded inverters, so that the input and output polarities are the same, thereby enhancing the driving capability of the output signal and facilitating the complete transmission of the output signal to the digital module or enabling subsequent circuits, such as bandgap references and oscillators, to protect the chip.

[0054] In one technical solution of the present invention, an over / under voltage protection method for a referenceless over / under voltage protection detection device is also provided, the specific process of which is as follows:

[0055] When the chip power supply is undervoltage protected, in order to prevent the chip power supply from being over-energized or suddenly abnormal, the overvoltage protection detection device of this invention will shut down the downstream module in time to prevent overheating and damage. When the chip power supply is undervoltage protected, in order to prevent the chip power supply from being powered down or suddenly abnormal, the undervoltage protection detection device of this invention will shut down the downstream module in time to prevent the downstream module from malfunctioning.

[0056] Chip power supply voltage V DD The design of the overvoltage or undervoltage switching voltage relies on the power supply voltage detection network 101 changing the output coefficient M. For the single-input trigger circuit 201, each input voltage is mapped one-to-one with its respective circuit state. Therefore, the detection voltage VIN value corresponding to the switching voltage is the same, and the current I flowing through the fifth resistor R5 is... tail They are all the same value:

[0057] I tail_OR =I tail_OF =I tail_UR =I tail_UF

[0058] V IN_OR =V IN_IF =V IN_UR =V IN_UF

[0059] Among them, I tail_OR This indicates the current flowing through the fifth resistor R5 when the chip's power supply voltage rises due to overvoltage, I. tail_OF This indicates the current flowing through the fifth resistor R5 when the chip's power supply voltage experiences an overvoltage shunt. tail_UR This indicates the current flowing through the fifth resistor R5 when the chip's power supply voltage drops due to undervoltage, I. tail_UF This indicates the current flowing through the fifth resistor R5 when the chip's power supply voltage recovers from undervoltage, in V. IN_OR This indicates the input voltage (V) of the single-input trigger circuit 201 when the chip's power supply voltage rises due to overvoltage. IN_OF This indicates the input voltage (V) of the single-input trigger circuit 201 when the chip power supply voltage experiences an overvoltage sag. IN_UR This indicates the input voltage (V) of the single-input trigger circuit 201 when the chip's power supply voltage drops below the low voltage threshold. IN_UF This indicates the input voltage of the single-input trigger circuit 201 when the chip power supply voltage is undervoltage and recovers.

[0060] When used as an overvoltage protection device, the specific process for overvoltage protection of the chip power supply voltage is as follows: When the power supply voltage detection network 101 detects the chip power supply voltage V... DD Rise above the first high-level switching voltage V IH_OR At that time, the first resistor R1 and the second resistor R2 are used to divide the voltage of the chip power supply V. DDThe detection and sensing are performed; specifically, the input voltage of the single-input trigger circuit 201 at this time... The currents in the left and right branches inside the single-input trigger circuit 201 are equal. Then, the output of the single-input trigger circuit 201 flips to a high level, causing the output of the Schmitt trigger 302 to go low, turning off the feedback switch 303, enabling the third resistor R3, and driving the buffer 401 to drive the subsequent circuit, making the overvoltage protection device output high and triggering overvoltage protection. When the power supply voltage flips from the first high level to the voltage V... IH_OR The voltage V drops back to the first low-level switching voltage after the overvoltage is canceled. IL_OF At that time, the first resistor R1, the second resistor R2, and the third resistor R3 are used to divide the voltage of the chip power supply V. DD The detection and sensing are performed; specifically, the input voltage of the single-input trigger circuit 201 at this time... The currents in the left and right branches of the single-input trigger circuit 201 are equal. Afterwards, the output of the single-input trigger circuit 201 flips to a low level, causing the output of the Schmitt trigger 302 to go high, turning on the feedback switch 303, shielding the third resistor R3, and the buffer 401 to drive the subsequent circuit, causing the overvoltage protection device output to return to a low level, thus canceling the overvoltage protection. Here, V... IH_OR >V IL_OF >Chip power supply voltage V DD .

[0061] When used as an undervoltage protection device, the specific process for undervoltage protection of the chip voltage is as follows: When the power supply voltage detection network 101 detects the chip power supply voltage V... DD Drops below the second low-level switching voltage V IL_UF At that time, the first resistor R1, the second resistor R2, and the third resistor R3 are used to divide the voltage of the chip power supply V. DD The detection and sensing are performed; specifically, the input voltage of the single-input trigger circuit 201 at this time... The currents in the left and right branches inside the single-input trigger circuit 201 are equal. Then, the output of the single-input trigger circuit 201 flips to a low level, causing the output of the Schmitt trigger 302 to become high, turning on the feedback switch 303, shielding the third resistor R3, and the buffer 401 to drive the subsequent circuit, causing the undervoltage protection device to output a high level, triggering the undervoltage protection. When the power supply voltage flips from the second low level to the voltage V... IL_UF Rise back to the second high-level switching voltage V IH_UR At that time, the first resistor R1 and the second resistor R2 are used to divide the voltage of the chip power supply V. DD The detection and sensing are performed; specifically, the input voltage of the single-input trigger circuit 201 at this time... The currents in the left and right branches inside the single-input trigger circuit 201 are equal. Afterwards, the output of the single-input trigger circuit 201 flips to a high level, causing the output of the Schmitt trigger 302 to become low, turning off the feedback switch 303, enabling the third resistor R3, and the buffer 401 to drive the subsequent circuit, causing the output of the undervoltage protection device to return to a low level, thus canceling the undervoltage protection; where V IL_UF <V IH_UR <Chip power supply voltage V DD .

[0062] The reference-free over / under voltage protection detection device and method of this invention uses a bipolar transistor pair detection method in the single-input trigger circuit, which changes the traditional detection method that requires bias current and reference voltage. It is suitable for more design scenarios where bias voltage cannot be provided, such as bias modules that control the same power supply or modules that cannot be directly designed with a reference voltage source for high-voltage power supplies. The real-time status of the power supply voltage can be obtained based solely on the power supply voltage information, protecting the safe operation of the chip. In addition, this invention also uses a current comparator with hysteresis and a Schmitt trigger to prevent false flips and glitches, resulting in lower overall power consumption than traditional over / under voltage protection detection devices.

[0063] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should be considered within the scope of protection of the present invention.

Claims

1. A referenceless over / under voltage protection detection device, characterized in that, include: The power supply voltage detection network (101), single-input trigger circuit (201), feedback circuit (301) and buffer (401); The power supply voltage detection network (101) is used to detect the real-time information of the chip power supply voltage and transmit the detected voltage to the single-input trigger circuit (201). The power supply voltage detection network (101) includes: a first resistor R1, a second resistor R2, and a third resistor R3, wherein one end of the first resistor R1 is connected to the power supply voltage V of the chip. DD The other end of the first resistor R1 and one end of the second resistor R2 are connected together as the output terminal of the power supply voltage detection network (101), and connected to the input terminal of the single input trigger circuit (201). The other end of the second resistor R2 is connected to the output terminal of the feedback circuit (301) and one end of the third resistor R3, respectively. The other end of the third resistor R3 is grounded. The single-input trigger circuit (201) determines whether the chip power supply voltage is over-voltage or under-voltage based on the detected voltage and generates a switching voltage. The single-input trigger circuit (201) includes: a first bipolar transistor Q1, a second bipolar transistor Q2, a first PMOS transistor PM1, a second PMOS transistor PM2, a fourth resistor R4, a fifth resistor R5, and a current comparator. The bases of the first bipolar transistor Q1 and the second bipolar transistor Q2 together serve as the input terminals of the single-input trigger circuit (201). The emitter of the first bipolar transistor Q1 is connected to one end of the fourth resistor R4 and one end of the fifth resistor R5, respectively. The emitter of the second bipolar transistor Q2... The other end of the fourth resistor R4 is connected to the ground; the collector, drain, and gate of the first PMOS transistor PM1 are all connected to the first input terminal of the current comparator; the collector, drain, and gate of the second PMOS transistor PM2 are all connected to the second input terminal of the current comparator; the source of the first PMOS transistor PM1 and the source of the second PMOS transistor PM2 are both connected to the chip's power supply voltage V. DD Connection; the output terminal of the current comparator is connected to the input terminal of the feedback circuit (301); The feedback circuit (301) adjusts the output coefficient of the power supply voltage detection network (101) according to the flip voltage feedback from the single input trigger circuit (201) to realize overvoltage or undervoltage protection of the chip power supply voltage. The buffer (401) is used to enhance the driving capability of the power supply voltage for overvoltage or undervoltage protection; The resistance values ​​of the first resistor R1, the second resistor R2, and the third resistor R3 satisfy the following: in, This represents the reversal point voltage during the rise of the power supply voltage. This represents the difference between the base and emitter voltages of the first bipolar transistor Q1. This indicates the ratio of the number of second bipolar transistors Q2 to the number of first bipolar transistors Q1. Voltage equivalent representing temperature. This indicates the resistance value of the fourth resistor, R4. This indicates the resistance value of the fifth resistor, R5. This indicates the reversal point voltage during the power supply voltage drop process.

2. The over / under voltage protection detection device without a reference as described in claim 1, characterized in that, The current comparator includes: a third PMOS transistor PM3, a fourth PMOS transistor PM4, a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, and a fourth NMOS transistor NM4. The gate of the fourth PMOS transistor PM4 serves as the first input terminal of the current comparator, and the gate of the third PMOS transistor PM3 serves as the second input terminal of the current comparator. The sources of both the third PMOS transistor PM3 and the fourth PMOS transistor PM4 are connected to the chip's power supply voltage V. DD The third PMOS transistor PM3 is connected to the gate of the first NMOS transistor NM1, the drain of the first NMOS transistor NM1, the drain of the second NMOS transistor NM2, and the gate of the third NMOS transistor NM3. The sources of the first NMOS transistor NM1, the second NMOS transistor NM2, the third NMOS transistor NM3, and the fourth NMOS transistor NM4 are all grounded. The drain of the fourth PMOS transistor PM4, the gate of the second NMOS transistor NM2, the drain of the third NMOS transistor NM3, the gate of the fourth NMOS transistor NM4, and the drain of the fourth NMOS transistor NM4 together serve as the output terminal of the current comparator.

3. The over / under voltage protection detection device without a reference as described in claim 2, characterized in that, The feedback circuit (301) includes a Schmitt trigger (302) and a feedback switch (303). The input terminal of the Schmitt trigger (302) serves as the input terminal of the feedback circuit (301). The output terminal of the Schmitt trigger (301) is connected to the control terminal of the feedback switch (303) and the input terminal of the buffer (401), respectively. The feedback switch (303) is connected to the power supply voltage detection network (101).

4. The over / under voltage protection detection device without a reference as described in claim 3, characterized in that, The feedback switch (303) is a fifth NMOS transistor. The gate of the fifth NMOS transistor is connected to the output terminal of the Schmitt trigger (302). The drain of the fifth NMOS transistor is connected to one end of the second resistor R2 and the third resistor R3. The source of the fifth NMOS transistor is grounded.

5. The over / under voltage protection detection device without a reference according to claim 4, characterized in that, When it is an overvoltage protection detection device, the buffer (401) is composed of an odd number of inverters cascaded together; when it is an undervoltage protection detection device, the buffer (401) is composed of an even number of inverters cascaded together.

6. The over / under voltage protection detection device without a reference as described in claim 5, characterized in that, The power supply voltage detection network (101) outputs the detected voltage to the single-input trigger circuit (201). for: in, M The output coefficient of the power supply voltage detection network (101) is given when the third resistor R3 is short-circuited. When the third resistor R3 is connected to the power supply voltage detection network (101), ; This indicates the resistance value of the first resistor R1. This indicates the resistance value of the second resistor, R2. This indicates the resistance value of the third resistor, R3. V S This indicates the real-time value of the power supply voltage.

7. An over / under voltage protection method for a referenceless over / under voltage protection detection device according to any one of claims 1-6, characterized in that, When used as an overvoltage protection device, the specific process for overvoltage protection of the chip power supply voltage is as follows: When the power supply voltage detection network (101) detects the chip power supply voltage V DD Exceeding the first high-level switching voltage At this time, the input voltage of the single-input trigger circuit (201) is... Afterwards, the output of the single-input trigger circuit (201) flips to a high level, the feedback switch (303) in the feedback circuit (301) turns off, enabling the third resistor R3, and the buffer (401) drives the subsequent circuit, causing the overvoltage protection device to output a high level, triggering the overvoltage protection; when the power supply voltage flips from the first high level voltage... Falling back to the first low-level switching voltage to cancel overvoltage At this time, the input voltage of the single-input trigger circuit (201) is... The feedback switch (303) of the feedback circuit (301) is turned on, shielding the third resistor R3. The buffer (401) drives the subsequent circuit, causing the overvoltage protection device to output a low level, thus canceling the overvoltage protection. > >Chip power supply voltage V DD .

8. An over / under voltage protection method for a referenceless over / under voltage protection detection device according to any one of claims 1-6, characterized in that, When used as an undervoltage protection device, the specific process for undervoltage protection of the chip voltage is as follows: When the power supply voltage detection network (101) detects the chip power supply voltage V DD Below the second low-level switching voltage At this time, the input voltage of the single-input trigger circuit (201) is... Afterwards, the output of the single-input trigger circuit (201) flips to a low level, the feedback switch (303) in the feedback circuit (301) is turned on, shielding the third resistor R3, and the buffer (401) drives the subsequent circuit, making the output of the undervoltage protection device high level, triggering the undervoltage protection; when the power supply voltage flips from the second low level voltage... Rebound to the second high-level switching voltage At this time, the input voltage of the single-input trigger circuit (201) is... The feedback switch (303) of the feedback circuit (301) is turned off, enabling the third resistor R3. The buffer (401) drives the subsequent circuit, causing the undervoltage protection device to output a low level, thus canceling the undervoltage protection. < <Chip power supply voltage V DD .

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