Automatic test vector generation method and system based on decision tree

Abstract

The invention discloses an automatic test vector generation method and system based on a decision tree, and the method comprises the steps: firstly extracting the node feature data of a to-be-tested circuit, and then obtaining and calculating the backtracking confidence coefficient of each logic gate through a trained decision tree model; the backtracking confidence is a prediction probability value of the decision tree model for successful fault propagation of the logic gate in the backtracking path; and finally, selecting a logic gate with high backtracking confidence as a node to be added into a backtracking path, and generating a test vector according to the backtracking path. According to the method, the number of test vectors can be effectively reduced, the time complexity of fault detection is reduced, and the problems of high backtracking frequency, high resource consumption, noise data interference and the like in a traditional method are solved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit testability design, in particular to a decision tree-based automatic test vector generation method and system. Background Art

[0002] ATPG (Automatic Test Pattern Generation) is the process of automatically generating test vectors used in integrated circuit testing. As the complexity of circuit logic increases, ATPG has problems such as too many backtracking times and high computational overhead when processing large-scale circuits. In addition, the characteristic data generated in the backtracking path is easily affected by noise, making the selection of fault propagation paths inaccurate, resulting in low quality of test vector generation and affecting overall test efficiency.

[0003] In recent years, artificial intelligence technology has been gradually applied to the field of automatic test vector generation to improve the efficiency and accuracy of fault detection. Artificial neural networks are used to assist in path selection during the backtracking process. However, traditional artificial neural networks are prone to overfitting problems when processing complex circuit structures and noisy data, resulting in unstable backtracking path selection, increasing the number of test vectors, and reducing test efficiency and coverage. Therefore, how to reduce the number of backtracking times and test vectors while ensuring test accuracy and improve the efficiency of automatic test vector generation is an urgent problem to be solved. Summary of the invention

[0004] Purpose of the invention: The purpose of the present invention is to provide a decision tree-based automatic test vector generation method and system to solve the problems of high number of backtracking times and low test vector generation efficiency in the traditional automatic test vector generation process.

[0005] Technical solution: The automatic test vector generation method based on a decision tree of the present invention comprises the following steps: Extract node feature data of the circuit to be tested, and use the trained decision tree model to calculate the backtracking confidence of each logic gate. The backtracking confidence is the predicted probability value of the decision tree model for the logic gate to successfully propagate the fault in the backtracking path; select the logic gate with high backtracking confidence as a node to add to the backtracking path, and generate a test vector based on the backtracking path; Among them, the training method of the decision tree model includes: Parse the circuit netlist file, extract the node feature data on the backtracking path during the backtracking process, add real labels to the backtracking path, and establish a circuit feature data set; establish a decision tree model, input the circuit feature data set into the decision tree model for training and verification, and obtain the predicted label of each node.

[0006] Furthermore, the node characteristic data includes logic gate type, controllability, observability, circuit level and decision tendency.

[0007] Furthermore, the logic gate types include AND gates, NOT gates, and OR gates; the controllability is divided into high controllability and low controllability according to a controllability risk reduction threshold; the observability is divided into high observability and low observability according to an observability risk reduction threshold; the circuit level is divided into high level and low level according to a circuit level risk reduction threshold; the decision tendency is divided into tendency to select 1 and tendency to select 0 according to a decision tendency risk reduction threshold.

[0008] Further, the selecting logic gates with high backtracking confidence as nodes to be added to the backtracking path includes: selecting the fault source node as the backtracking starting point, and selecting the logic gate with the highest backtracking confidence from the logic gates connected to the current node each time backtracking to add to the backtracking path.

[0009] Furthermore, the loss function of the decision tree model is a negative exponential loss function.

[0010] The automatic test vector generation system based on a decision tree of the present invention comprises: A feature extraction unit, used to extract node feature data of the circuit to be tested; A backtracking confidence calculation unit is used to calculate the backtracking confidence of each logic gate using the trained decision tree model. The backtracking confidence is the predicted probability value of the decision tree model for the logic gate to successfully propagate a fault in the backtracking path. Among them, the training method of the decision tree model includes: Parse the circuit netlist file, extract the node feature data on the backtracking path during the backtracking process, add real labels to the backtracking path, and establish a circuit feature data set; establish a decision tree model, input the circuit feature data set into the decision tree model for training and verification, and obtain the predicted label of each node The test vector generation unit is used to select logic gates with high backtracking confidence as nodes to be added to the backtracking path, and generate test vectors according to the backtracking path.

[0011] Further, the node characteristic data includes logic gate type, controllability, observability, circuit level and decision tendency; The logic gate types include AND gates, NOT gates, and OR gates; the controllability is divided into high controllability and low controllability according to the controllability risk reduction threshold; the observability is divided into high observability and low observability according to the observability risk reduction threshold; the circuit level is divided into high level and low level according to the circuit level risk reduction threshold; the decision tendency is divided into tendency to select 1 and tendency to select 0 according to the decision tendency risk reduction threshold.

[0012] Furthermore, in the test vector generation unit, the selection of logic gates with high backtracking confidence as nodes to be added to the backtracking path includes: selecting the fault source node as the backtracking starting point, and selecting the logic gate with the highest backtracking confidence from the logic gates connected to the current node each time backtracking is performed and adding it to the backtracking path.

[0013] The electronic device described in the present invention includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the computer program is loaded into the processor, the automatic test vector generation method based on the decision tree is implemented.

[0014] The computer-readable storage medium of the present invention stores a computer program, and when the computer program is executed by a processor, the automatic test vector generation method based on a decision tree is implemented.

[0015] Beneficial effects: Compared with the prior art, the advantages of the present invention are: (1) The present invention establishes a decision tree model to effectively learn and analyze the circuit feature data generated in the backtracking process, thereby optimizing the backtracking path selection in fault detection; (2) The present invention uses information such as logic gate type, controllability, observability, circuit hierarchy and decision tendency to establish a circuit feature data set, and trains the decision tree model so that it can accurately learn the complex relationship between the backtracking path and circuit features; (3) The present invention designs a robustness loss function, calculates the backtracking confidence through a negative exponential loss function, effectively smoothes the prediction output, enhances the model's anti-interference ability to noise data, and ensures that the backtracking confidence of the logic gate can still be stably predicted in complex circuits. In summary, the present invention can effectively reduce the number of test vectors, reduce the time complexity of fault detection, and greatly improve the efficiency of automatic test vector generation while ensuring fault coverage, solving the problems of high backtracking frequency, large resource consumption and noise data interference in traditional methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a flow chart of the automatic test vector generation method of the present invention.

[0017] Figure 2 A schematic diagram is generated for a circuit characteristic data set according to an embodiment of the present invention.

[0018] Figure 3 Schematic diagram of a circuit characteristic data set file according to an embodiment of the present invention.

[0019] Figure 4 Schematic diagram of recursive partitioning of decision tree features according to an embodiment of the present invention.

[0020] Figure 5 The figure is a flow chart of the decision tree training process according to an embodiment of the present invention.

[0021] Figure 6 A schematic diagram of a statistical report generated by automatic test vectors according to an embodiment of the present invention.

[0022] Figure 7 Detailed data diagram of the test vector according to an embodiment of the present invention. DETAILED DESCRIPTION

[0023] The technical solution of the present invention is further described below in conjunction with the accompanying drawings.

[0024] like Figure 1 As shown, this embodiment is described by taking a basic combinational circuit as an example, and the circuit includes: three NAND gates G1, G2, G3, two AND gates G5, G6 and two OR gates G4, G7. The lines of adjacent logic gates are represented by h, i, j, k, l, m, n, o, p. The automatic test vector generation method based on the decision tree of the present invention includes the following steps.

[0025] Step 1, read in the netlist file, collect five types of feature data generated by each logic gate corresponding to the backtracking path, including logic gate type, controllability, observability, circuit hierarchy and decision tendency; create a circuit feature data set, and randomly divide the circuit feature data set into a training set, a validation set and a test set according to a preset ratio.

[0026] Step 2: construct a decision tree model, input the training set and the validation set into the decision tree model for training and validation, obtain a training model file, and adjust robustness parameters to optimize the decision tree model.

[0027] The decision tree model includes four core parameters: loss function, maximum tree depth, maximum number of leaf nodes, and minimum number of samples contained in a leaf node, and four core steps: training, reasoning, evaluation, and feature importance analysis. The training steps include data preprocessing, parameter initialization, recursive tree structure construction, recursive partitioning of leaf nodes, and storage of node depth information; The reasoning step includes traversing samples, indexing leaf nodes, and calculating the prediction results of category distribution according to a negative exponential loss function; The evaluation step includes the matching degree between the predicted label and the true label, and calculating the total loss according to the risk of the leaf node.

[0028] The feature importance step involves calculating the risk reduction for each node, measuring the tree's dependence on the input features.

[0029] The loss function of the decision tree model is the negative exponential loss function (NE), which is expressed as follows: represents the value of the loss function, y represents the true label, represents the confidence or output value predicted by the model, represents the robustness parameter that can be adjusted, Represents the exponential loss between the predicted value and the true label: ; The recursive partitioning expression of leaf nodes in the training step is as follows, where D represents the sample set on the current node, and S represents the sample set on the parent node. represents the purity or impurity measure of the set S, Express satisfaction A subset of samples, Express satisfaction A subset of samples, Representation Subset A measure of purity or impurity, Representation Subset A measure of purity or impurity: ; The expression for calculating the category distribution in the inference step is as follows, where Indicates The probability distribution of the class, Indicates The numerical value of the class label, Represents the confidence or output value predicted by the model, represents the robustness parameter, Represents the set of all categories: ; The total loss expression for risk calculation in the feature importance step is as follows, where represents the risk reduction brought by the split, represents the risk value of the current node, represents the risk value of the left child node, represents the risk value of the right child node, Represents the minimum threshold for risk reduction: .

[0030] Step 3: read the netlist file of the circuit to be tested, extract its circuit feature data and input it into the optimized robust decision tree model, calculate the backtracking confidence of each logic gate, and the backtracking confidence is the model's predicted probability value of the logic gate successfully propagating the fault in the backtracking path. Store the predicted backtracking confidence results, mark the circuit nodes, and form a backtracking confidence mapping table.

[0031] Step 4: Select the fault source node as the backtracking starting point. When generating the backtracking path, for each node, select the logic gate with the highest backtracking confidence value among the logic gates connected to it and add it to the backtracking path.

[0032] Step 5: Finally, a backtracking path that can effectively propagate faults is generated. Under the guidance of the backtracking path, a test vector with the highest fault coverage and the least redundancy is generated.

[0033] In order to facilitate the understanding of the present invention, the following four aspects are explained separately.

[0034] (1) The overall process of the automatic test vector generation method based on decision tree.

[0035] A complete automatic test vector generation process is divided into four stages, namely, reading the netlist, generating a fault list, generating a test vector, and detecting faults; however, in the traditional automatic test vector generation method, there are problems such as many backtracking times and low test vector generation efficiency when facing complex large-scale circuits. To solve this problem, the present invention proposes an automatic test vector generation method based on a decision tree, which collects feature data generated in the backtracking process of automatic test vector generation; constructs a dedicated circuit feature data set and divides it into a training set, a validation set, and a test set according to a preset ratio; designs a robustness loss function, constructs and trains a decision tree model; applies the optimized decision tree model to the circuit netlist file of the circuit to be tested, and predicts the confidence of each logic gate; guides the selection of the backtracking path based on the prediction results, and finally generates a test vector.

[0036] The present invention reduces the waste of computing resources caused by backtracing by optimizing the backtracing path selection, reduces the automatic testing cost while maintaining the fault coverage, and significantly reduces the number of backtracing times and the number of test vectors.

[0037] (2) Circuit feature dataset generation process.

[0038] Reference Figure 2 , parse the netlist file, and extract the path information and node feature data generated during the backtracking process. The ATPG algorithm collects node features on multiple backtracking paths. For example, when detecting a fault on an output line in a sample circuit, the ATPG algorithm will generate multiple backtracking paths. These paths include paths that successfully propagate faults (marked as "success") and paths that fail to propagate faults (marked as "failure"). For example, a successful path can be represented as path njg, and a failed path can be represented as path mlha. By analyzing these paths, feature information related to logic gates is extracted, including logic gate type, controllability, observability, circuit hierarchy, and decision tendency.

[0039] Each node on the backtracking path will contain the above feature information, which is collected from the start of the ATPG program to the completion of all fault detection. In the circuit feature dataset, the nodes on the successful backtracking path are marked as "1" and the nodes on the failed backtracking path are marked as "0", forming a dataset with clear labels.

[0040] Reference Figure 3 , the circuit feature dataset of this backtracking path shows a successful decision path, with the starting decision point being GateID 16. The path lists the relevant logic gate information, including the attribute values ​​of each gate and its depth relationship with the main output terminal. Specifically, each logic gate has the following fields: GateID is the unique identifier of the logic gate, numFO represents the number of output fan-outs of the logic gate, which is 2 in this data, indicating that the output of each logic gate is connected to two subsequent logic gates; cc0 and cc1 represent the control 0 condition and control 1 condition of the logic gate, respectively, with values ​​of 2 and 3; co represents controllability and observability, with a value of 1; the depthFromPo field represents the depth of the logic gate from the main output terminal. In this path, the cc0, cc1, and co values ​​of all logic gates remain consistent, while the depthFromPo field gradually decreases, indicating that the logic gate gradually approaches the main output terminal from the deep layer.

[0041] It should be noted that by annotating and preprocessing these backtracking feature data, the generated circuit feature data set is randomly divided into training set, validation set and test set in the ratio of 80%, 10% and 10% for model training, validation and evaluation. The ratio of training set, validation set and test set can be adjusted in actual use. The generation process of the circuit feature data set not only retains the circuit structure information in the backtracking path, but also captures the characteristics of dynamic changes in the fault propagation process, providing high-quality data input for the robust decision tree model.

[0042] (3) Robust decision tree model training process.

[0043] Reference Figure 4 ,The training process of the decision tree starts from the root node and ,gradually divides the nodes based on the circuit feature data. The dataset is ,recursively divided into subsets based on the selected features. This ,process continues until the stopping condition is met, such as reaching the maximum depth, the node purity is ,high enough, or the number of samples is below a threshold. ,When stopped, the node becomes a leaf node, storing the category ,distribution and predicted value.

[0044] For example, if “gate type” is selected as the partitioning feature, the data set will be divided into three subsets: AND gate, NOT gate, and OR gate; If "controllability" is selected as the partitioning feature, the data set will be divided into two subsets: high controllability and low controllability; the partitioning standard is based on the minimum threshold of controllability risk reduction. To decide, those above this threshold will be classified into the high controllability subset, and those below this threshold will be classified into the low controllability subset; If "observability" is selected as the partitioning feature, the data set will be divided into two subsets: high observability and low observability; the partitioning criterion is the minimum threshold for reducing observability risk. To decide, those above this threshold will be classified into the high observability subset, and those below this threshold will be classified into the low observability subset; If "decision tendency" is selected as the partitioning feature, the data set will be divided into two subsets: tendency selection 1 and tendency selection 0; the partitioning standard is based on the minimum threshold of decision tendency risk reduction. To determine, those above this threshold will be divided into the tendency selection 1 subset, and those below this threshold will be divided into the tendency selection 0 subset; If "circuit level" is selected as the partitioning feature, the data set will be divided into two subsets: high-level and low-level. The partitioning criteria are: The minimum threshold for risk reduction based on the circuit level To determine, those above this threshold will be divided into the high-level subset, and those below this threshold will be divided into the low-level subset.

[0045] Reference Figure 5 Specifically, the model initializes an empty decision tree T, sets the maximum depth, minimum number of samples, and robustness parameter μ. The training process starts from the root node and recursively calls the BuildTree function to build a decision tree. At each node, the model selects the optimal feature and split threshold through FindBestSplit, calculates the split quality based on the negative exponential loss function, evaluates the risk reduction of the left and right child nodes, and updates the split rules of the decision node. During the splitting process, the model dynamically adjusts the threshold to optimize the feature segmentation to ensure that each split can maximize the purity of the child node. By limiting the marginal loss, the loss function can effectively handle the noise in the training data and improve the robustness of the model on complex backtracking path data. When the number of samples in the node is lower than the set threshold or reaches the maximum depth, the splitting stops, the node is marked as a leaf node, and the distribution of the category samples is recorded as the prediction output.

[0046] The advantage of optimizing the splitting quality through a robust loss function is that the model can smooth the impact of noisy data, making the splitting rules more robust, which is particularly suitable for processing backtracking path data with dynamic weight characteristics and complex feature distribution. The recursive construction process of the tree ensures that the model can gradually capture the nonlinear relationship between features, thereby deeply learning the key characteristics of the backtracking path. By optimizing the splitting rules, the model can not only effectively distinguish between successful paths and failed paths, but also quantify the relative importance of circuit features, providing a reliable basis for optimizing automatic test vector generation.

[0047] Furthermore, the decision tree model has good interpretability. By analyzing the decision path, it is clear which features play a key role in node splitting. For example, certain specific gate types or dynamic backtracking propensity values ​​appear frequently in the splitting rules of the model, indicating that they have a greater impact on path selection. In addition, the adjustment of the robustness parameter μ enables the model to adapt to the characteristics of different circuits. Especially when dealing with complex circuit structures, the optimized decision tree can significantly reduce the number of backtracking times and the number of test vectors.

[0048] (4) Model evaluation and feature importance analysis.

[0049] The evaluation process of the robust decision tree model is mainly carried out by comparing the degree of match between the prediction results and the true labels. The evaluation of the model includes not only the accuracy rate, but also the loss calculation. First, the model calculates the accuracy of the prediction to evaluate the decision tree's ability to correctly classify the backtracking path. The prediction accuracy is calculated by comparing the matching of the model's predicted label with the actual label for each backtracking path, and calculating the proportion of correct predictions. For the test set, the model is able to distinguish between successful paths and failed paths. The high accuracy rate means that the decision tree has a high reliability in the selection of backtracking paths. Secondly, the robust decision tree also calculates the loss function value and uses the negative exponential loss function to evaluate the splitting quality of the model. This loss function effectively smooths the impact of noisy data, allowing the model to maintain good stability when facing complex or noisy data. During the evaluation process, the robust decision tree model can automatically handle the nonlinear characteristics in the circuit data, ensuring that each split maximizes the accuracy of the prediction while reducing the risk of misclassification.

[0050] Furthermore, the performance of the model was verified by testing different circuits. Through experiments on multiple circuits, the model demonstrated strong generalization capabilities and good application results in different circuit designs, with high accuracy and low loss function values, indicating that the model can maintain good prediction capabilities in various test circuits. In this way, the evaluation process not only verified the accuracy of the robust decision tree, but also confirmed its adaptability and robustness, especially when faced with complex circuit structures, the model can effectively avoid overfitting.

[0051] It should also be noted that in the present embodiment, during the feature importance analysis process, the robust decision tree model calculates the importance of the feature by evaluating the risk reduction when each node is split. Each time a split occurs, the model evaluates the contribution of the current feature to the purity of the split, calculates the contribution value of each feature, accumulates the contribution amount at all splits, and finally obtains the weight value of each feature. These weight values ​​reflect the degree of influence of each feature in the backtracking path selection. That is, features such as logic gate type, controllability, observability, circuit hierarchy, and decision-making tendency will play different roles in the splitting process of the decision tree.

[0052] In order to verify the method of the present invention, the method of the present invention is compared with the traditional automatic test vector generation and the automatic test vector generation method based on the artificial neural network model, wherein the automatic test vector generation method based on the artificial neural network model is recorded in: "S. Roy, SK Millican and VD Agrawal, "Machine Intelligence for Efficient Test Pattern Generation," 2020 IEEE International Test Conference(ITC), Washington, DC, USA, 2020, pp. 1-5, doi: 10.1109 / ITC44778.2020.9325250."

[0053] The experiment uses a benchmark circuit, referring to Figure 6 , showing the statistical reports of C2670, C6288, S15850, S38584 circuits, including key information such as fault classification, coverage, number of test modes, and test running time. The test uses the SAF (Stuck-At Fault) fault model, with a total number of 86,824 faults, and the number of faults obtained after simplification is 61,840. Among these faults, the number of undetected faults is 3,272, the number of ATPG untestable faults is 200, the number of ATPG aborted faults is 5, the number of redundant faults and pending faults are both 0, and the number of detected faults reaches 83,347. The test coverage is 96.22% and the ATPG efficiency is 96.23%. The test uses 105 test vectors and the running time is 21.27 seconds.

[0054] Reference Figure 7 , shows detailed test vector data. The input and output signal names of the circuit are listed at the top, such as G0, G1, G2, etc. Each row represents a test pattern, and the pattern names are such as pattern_1, pattern_2, etc. Each test pattern contains multiple binary vectors, which are separated by vertical lines and may correspond to the states of different signals in the circuit. For example, the test data in pattern_1 is "1111011011110010|1100110011100011|...". The total number of test vectors is 207, and each vector provides the states of multiple signals to verify the behavior of the circuit under different input conditions.

[0055] Referring to Table 1, for combinational circuits, the method of the present invention performs outstandingly on the C6288 circuit compared to the traditional method, with the number of vectors reduced by 75.2%, the number of backtracking reduced by 74.1%, and the test coverage increased by 1.34%. In the C2670 circuit, the number of vectors decreased by 60.9%, the number of backtracking decreased by 53.3%, and the test coverage increased by 1.67%. For sequential circuits, the method of the present invention reduced the number of vectors on the S15850 circuit by 24.8%, the number of backtracking decreased by 9.1%, and the test coverage increased by 0.58%. On the S38584 circuit, the number of vectors decreased by 3.8%, the number of backtracking decreased by 24.1%, and the test coverage was maintained comparable to that of the traditional method. Therefore, the method of the present invention can effectively reduce the number of test vectors, reduce the number of backtracking times, and optimize the overall test efficiency while maintaining the test coverage.

[0056] Table 1 Benchmark circuit test sample data statistics

[0057]

[0058] The automatic test vector generation system based on a decision tree of the present invention comprises: A feature extraction unit, used to extract node feature data of the circuit to be tested; A backtracking confidence calculation unit is used to calculate the backtracking confidence of each logic gate using the trained decision tree model. The backtracking confidence is the predicted probability value of the decision tree model for the logic gate to successfully propagate a fault in the backtracking path. Among them, the training method of the decision tree model includes: Parse the circuit netlist file, extract node feature data on the backtracking path during the backtracking process, add real labels to the backtracking path, and establish a circuit feature data set; establish a decision tree model, input the circuit feature data set into the decision tree model for training and verification, and obtain a predicted label for each node; The test vector generation unit is used to select logic gates with high backtracking confidence as nodes to be added to the backtracking path, and generate test vectors according to the backtracking path.

[0059] The electronic device described in the present invention includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the computer program is loaded into the processor, the automatic test vector generation method based on the decision tree is implemented.

[0060] The computer-readable storage medium of the present invention stores a computer program, and when the computer program is executed by a processor, the automatic test vector generation method based on a decision tree is implemented.

[0061] The computer-readable storage media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, flash memory, or any other medium that can be used to store program code in the form of instructions or data structures and that can be accessed by a computer.

[0062] The processor is used to execute the computer program stored in the memory to implement each step of the method involved in the above embodiment.

Claims

1. A method for automatically generating test vectors based on a decision tree, characterized in that: The steps include: Extract node feature data of the circuit to be tested, and use the trained decision tree model to calculate the backtracking confidence of each logic gate. The backtracking confidence is the predicted probability value of the decision tree model for the successful propagation of faults by the logic gate in the backtracking path. Select logic gates with high backtracking confidence as nodes and add them to the backtracking path, and generate test vectors according to the backtracking path; Among them, the training method of the decision tree model includes: Parse the circuit netlist file, extract the node feature data on the backtracking path during the backtracking process, add real labels to the backtracking path, and establish a circuit feature data set; establish a decision tree model, input the circuit feature data set into the decision tree model for training and verification, and obtain the predicted label of each node.

2. The automatic test vector generation method based on decision tree according to claim 1 is characterized in that: The node characteristic data includes logic gate type, controllability, observability, circuit level and decision tendency.

3. The automatic test vector generation method based on decision tree according to claim 2 is characterized in that: The logic gate types include AND gates, NOT gates, and OR gates; the controllability is divided into high controllability and low controllability according to the controllability risk reduction threshold; the observability is divided into high observability and low observability according to the observability risk reduction threshold; the circuit level is divided into high level and low level according to the circuit level risk reduction threshold; the decision tendency is divided into tendency to select 1 and tendency to select 0 according to the decision tendency risk reduction threshold.

4. The automatic test vector generation method based on decision tree according to claim 1 is characterized in that: The selecting logic gates with high backtracking confidence as nodes to be added to the backtracking path includes: selecting the fault source node as the backtracking starting point, and selecting the logic gate with the highest backtracking confidence from the logic gates connected to the current node each time backtracking to add to the backtracking path.

5. The automatic test vector generation method based on decision tree according to claim 1 is characterized in that: The loss function of the decision tree model is a negative exponential loss function.

6. An automatic test vector generation system based on a decision tree, characterized in that: include: A feature extraction unit, used to extract node feature data of the circuit to be tested; A backtracking confidence calculation unit is used to calculate the backtracking confidence of each logic gate using the trained decision tree model. The backtracking confidence is the predicted probability value of the decision tree model for the logic gate to successfully propagate a fault in the backtracking path. Among them, the training method of the decision tree model includes: Parse the circuit netlist file, extract node feature data on the backtracking path during the backtracking process, add real labels to the backtracking path, and establish a circuit feature data set; establish a decision tree model, input the circuit feature data set into the decision tree model for training and verification, and obtain a predicted label for each node; The test vector generation unit is used to select logic gates with high backtracking confidence as nodes to be added to the backtracking path, and generate test vectors according to the backtracking path.

7. The automatic test vector generation system based on decision tree according to claim 6, characterized in that: The node characteristic data includes logic gate type, controllability, observability, circuit level and decision tendency; The logic gate types include AND gates, NOT gates, and OR gates; the controllability is divided into high controllability and low controllability according to the controllability risk reduction threshold; the observability is divided into high observability and low observability according to the observability risk reduction threshold; the circuit level is divided into high level and low level according to the circuit level risk reduction threshold; the decision tendency is divided into tendency to select 1 and tendency to select 0 according to the decision tendency risk reduction threshold.

8. The automatic test vector generation system based on decision tree according to claim 6, characterized in that: In the test vector generation unit, the selection of logic gates with high backtracking confidence as nodes to be added to the backtracking path includes: selecting the fault source node as the backtracking starting point, and selecting the logic gate with the highest backtracking confidence from the logic gates connected to the current node each time backtracking to add it to the backtracking path.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the computer program is loaded into a processor, the automatic test vector generation method based on a decision tree is implemented according to any one of claims 1 to 5.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the decision tree-based automatic test vector generation method according to any one of claims 1 to 5 is implemented.

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