Array substrate, driving method and low-temperature polysilicon liquid crystal display panel

Abstract

The present application discloses an array substrate, a driving method and a low-temperature polysilicon liquid crystal display panel, wherein the light shielding layer of the array substrate is made on the base substrate, the buffer layer is made on the buffer layer, the second gate layer and the bottom gate insulating layer are made on the buffer layer, and the second gate layer is made in the bottom gate insulating layer and is arranged corresponding to the lightly doped region of the polysilicon layer, the polysilicon layer is made on the bottom gate insulating layer, the top gate insulating layer is made on the polysilicon layer, the first gate layer and the interlayer insulating layer are made on the top gate insulating layer, and the first gate layer is made in the interlayer insulating layer, and the source and the drain are respectively connected to the two ends of the polysilicon layer through the via hole. When the transistor is turned on, the electrons in the channel region are concentrated in the front channel region, and the on-state current is instantly increased. When the transistor is turned off, the electrons in the channel region are concentrated in the back channel region, and the off-state current is instantly reduced, which greatly reduces the leakage current of the transistor.

Description

Technical Field

[0001] The present invention relates to the technical field of transmittance of low-temperature polysilicon displays, and in particular to an array substrate, a driving method and a low-temperature polysilicon liquid crystal display surface. Background Art

[0002] The liquid crystal panel includes a color filter substrate, a thin film transistor array substrate and a liquid crystal layer arranged between the two substrates. Its working principle is to control the rotation of the liquid crystal molecules in the liquid crystal layer by applying a driving voltage on the two glass substrates, thereby refracting the light from the backlight module to produce a picture.

[0003] Low-temperature polysilicon (LTPS) technology is a new generation of TFT substrate manufacturing technology. The biggest difference from traditional amorphous silicon (aSi) technology is that low-temperature polysilicon displays have faster response speeds and have the advantages of high brightness, high resolution and low power consumption.

[0004] Since the electron mobility is 2-3 times that of the hole mobility, most of the LTPS liquid crystal display products on the market are of Nmos TFT type. However, the problem that comes with it is that as the drain-source voltage (Vds) of the transistor (TFT) increases (0.1V→10.1V), the reverse bias voltage (VGL) of the gate is loaded on the transistor (TFT), and the leakage current increases sharply, seriously affecting the product image quality, and having a negative effect on the product's afterimage and crosstalk (Crossta lk). Summary of the invention

[0005] When a reverse bias voltage is applied to an existing low-temperature polysilicon liquid crystal display transistor, the leakage current increases sharply, which seriously affects the display quality of the low-temperature polysilicon liquid crystal display product and aggravates the product's afterimage and crosstalk problems.

[0006] In view of the above problems, an array substrate, a driving method and a low-temperature polysilicon liquid crystal display panel are proposed. By setting a second gate layer and a bottom gate insulating layer under the polysilicon layer, when the transistor is turned on, the electrons in the channel region are concentrated in the front channel region, and the on-state current is instantly increased. When the transistor is turned off, the electrons in the channel region are concentrated in the back channel region, and the off-state current is instantly reduced, thereby greatly reducing the leakage current of the transistor.

[0007] In a first aspect, an array substrate includes:

[0008] A substrate, a light shielding layer, a buffer layer, a polysilicon layer, a top gate insulating layer, a first gate layer, an interlayer insulating layer, a source electrode and a drain electrode;

[0009] Among them, it also includes a second gate layer and a bottom gate insulating layer;

[0010] The light-shielding layer is made on the substrate, the buffer layer is made on the buffer layer, the second gate layer and the bottom gate insulating layer are made on the buffer layer, and the second gate layer is made in the bottom gate insulating layer and is arranged corresponding to the lightly doped area of ​​the polysilicon layer, the polysilicon layer is made on the bottom gate insulating layer, the top gate insulating layer is made on the polysilicon layer, the first gate layer and the interlayer insulating layer are made on the top gate insulating layer, and the first gate layer is made in the interlayer insulating layer, and the source and the drain are connected to the two ends of the polysilicon layer through vias respectively.

[0011] In conjunction with the array substrate described in the first aspect of the present invention, in a first possible implementation manner, the polysilicon layer includes:

[0012] Two heavily doped regions, two lightly doped regions and

[0013] Channel area;

[0014] The two lightly doped regions are respectively formed on both sides of the channel region, and the two heavily doped regions are respectively formed outside the lightly doped regions.

[0015] In combination with the first possible implementation manner of the first aspect of the present invention, in a second possible implementation manner, the second gate layer at least includes:

[0016] Independent first bottom gate and second bottom gate;

[0017] The first bottom gate and the second bottom gate are respectively arranged corresponding to the two lightly doped regions.

[0018] In combination with the second possible implementation manner of the first aspect of the present invention, in a third possible implementation manner, the channel region includes:

[0019] anterior channel region and dorsal channel region;

[0020] The front channel region and the back channel region are respectively close to the top gate insulating layer and the bottom gate insulating layer.

[0021] In combination with the third possible implementation manner of the first aspect of the present invention, in a fourth possible implementation manner, the first bottom gate and the second bottom gate are used to input a positive voltage signal or a negative voltage signal, so that the electrons in the lightly doped region are concentrated in the front channel region or the back channel region.

[0022] In combination with the fourth possible implementation manner of the first aspect of the present invention, in a fifth possible implementation manner, the source electrode is connected to the heavily doped region at one end of the polysilicon layer through a via, and the drain electrode is connected to the heavily doped region at the other end of the polysilicon layer through a via.

[0023] In a second aspect, a driving method is provided for driving the array substrate according to the first aspect, comprising:

[0024] Step 10: input a positive voltage signal to the first gate layer and input a negative voltage signal to the second gate layer, so that the on-state current is instantly increased and the transistor is turned on;

[0025] Step 20: input a negative voltage signal to the first gate layer and input a positive voltage signal to the second gate layer, so that the on-state current is instantly reduced and the transistor is turned off.

[0026] In conjunction with the driving method described in the second aspect of the present invention, in a first possible implementation manner, step 10 includes:

[0027] Step 11, obtaining the gate positive voltage and threshold voltage;

[0028] Step 12: When the gate positive voltage is greater than the threshold voltage, negative voltage signals are input to the first bottom gate and the second bottom gate respectively, so that the electrons in the channel region are concentrated in the front channel region.

[0029] In combination with the driving method described in the second aspect of the present invention, in a second possible implementation manner, step 20 includes:

[0030] Step 21, obtaining a negative gate voltage;

[0031] Step 22: When the gate voltage is a negative voltage, a positive voltage signal is input to the first bottom gate and the second bottom gate respectively, so that the electrons in the channel region are concentrated in the back channel region.

[0032] In a third aspect, a low-temperature polysilicon liquid crystal display panel includes the array substrate described in the first aspect and is driven by the driving method described in the second aspect.

[0033] An array substrate, a driving method and a low-temperature polysilicon liquid crystal display panel in the present invention are implemented. By setting a second gate layer and a bottom gate insulating layer below the polysilicon layer, when the transistor is turned on, the electrons in the channel region are concentrated in the front channel region, instantly increasing the on-state current. When the transistor is turned off, the electrons in the channel region are concentrated in the back channel region, instantly reducing the off-state current, thereby greatly reducing the leakage current of the transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the scheme in the present application, a brief introduction is given below to the drawings required for use in the description of the embodiments of the present application. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0035] Figure 1is a structural schematic diagram of an array substrate in the prior art;

[0036] Figure 2 is a schematic structural diagram of the array substrate in this application;

[0037] Figure 3 It is a schematic diagram of electron transfer in the lightly doped region when a negative voltage signal is applied to the second gate layer of the array substrate in the present application;

[0038] Figure 4 It is a schematic diagram of electron transfer in the lightly doped region when a positive voltage signal is applied to the second gate layer of the array substrate in the present application;

[0039] Figure 5 It is a schematic diagram of the process steps of a specific implementation of the driving method in the present application;

[0040] Figure 6 yes Figure 5 A schematic diagram of a process step of a specific implementation method of step 10;

[0041] Figure 7 yes Figure 5 A schematic diagram of the process steps of a specific implementation method of step 20. DETAILED DESCRIPTION

[0042] The following will be combined with the accompanying drawings in the invention to clearly and completely describe the technical solutions in the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, other embodiments obtained by ordinary technicians in this field without creative work are all within the scope of protection of the present invention.

[0043] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by technicians in the technical field to which this application belongs; the terms used in the specification of the application are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" in the specification and claims of this application and the above-mentioned figure descriptions and any variations thereof are intended to cover non-exclusive inclusions.

[0045] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0046] Name Explanation

[0047] Nmos TFT: a thin film transistor that uses electrons as carriers to conduct the channel

[0048] Vth: Gate threshold voltage (critical voltage where the electron concentration in the front channel of polysilicon is greater than or equal to the hole concentration)

[0049] When a reverse bias voltage is applied to the existing low-temperature polysilicon liquid crystal display transistor, the leakage current increases sharply, which seriously affects the display quality of the low-temperature polysilicon liquid crystal display product and aggravates the product's afterimage and crosstalk problems. Figure 1 , Figure 1 It is a schematic diagram of the structure of an array substrate in the prior art.

[0050] In view of the above problems, an array substrate, a driving method and a low-temperature polysilicon liquid crystal display panel are proposed.

[0051] First, as Figure 2 , Figure 21 is a schematic diagram of the structure of the array substrate in the present application; an array substrate comprises: a base substrate 100, a light shielding layer 200, a buffer layer 300, a polysilicon layer 400, a top gate insulating layer 500, a first gate layer 700, an interlayer insulating layer 600, a source 101 and a drain 102; wherein, it also comprises a second gate layer and a bottom gate insulating layer 900; the light shielding layer 200 is made on the base substrate 100, the buffer layer 300 is made on the buffer layer 300, the second gate layer and the bottom gate insulating layer 900 are made on the buffer layer The first gate layer 700 and the second gate layer 900 are formed on the bottom gate insulating layer 900, and the second gate layer is formed in the bottom gate insulating layer 900 and is arranged corresponding to the lightly doped region (LDD) of the polysilicon layer 400. The polysilicon layer 400 is formed on the bottom gate insulating layer 900, the top gate insulating layer 500 is formed on the polysilicon layer 400, the first gate layer 700 and the interlayer insulating layer 600 are formed on the top gate insulating layer 500, and the first gate layer 700 is formed in the interlayer insulating layer 600. The source 101 and the drain 102 are connected to the two ends of the polysilicon layer 400 through the via holes respectively. By arranging the second gate layer and the bottom gate insulating layer 900 below the polysilicon layer 400, when the transistor is turned on, the electrons in the channel region are concentrated in the front channel region (P1+), and the on-state current (I on) is instantly increased. When the transistor is turned off, the electrons in the channel region are concentrated in the back channel region (P2+), and the off-state current (I on) is instantly reduced, which greatly reduces the leakage current of the transistor.

[0052] In this embodiment, the first gate layer 700 controls the opening and closing of the transistor, the polysilicon layer 400 includes a heavily doped region (N-), a lightly doped region (LDD) and a channel region, and the second gate layer is used to control the electron direction of the lightly doped region (LDD), thereby instantly increasing the on-state current (I on) and instantly reducing the off-state current (I off).

[0053] Furthermore, the polysilicon layer 400 includes two heavily doped regions (N-), two lightly doped regions (LDD) and a channel region; the two lightly doped regions (LDD) are respectively formed on both sides of the channel region, and the two heavily doped regions (N-) are respectively formed on the outside of the lightly doped regions (LDD).

[0054] Furthermore, the channel region includes a front channel region (P1+) and a back channel region; the front channel region (P1+) and the back channel region are respectively close to the top gate insulating layer 500 and the bottom gate insulating layer 900. The source 101 is connected to the heavily doped region (N-) at one end of the polysilicon layer 400 through a via hole, and the drain 102 is connected to the heavily doped region (N-) at the other end of the polysilicon layer 400 through a via hole.

[0055] Preferably, the second gate layer includes at least an independent first bottom gate 810 and a second bottom gate 820; the first bottom gate 810 and the second bottom gate 820 are respectively arranged corresponding to the two lightly doped regions (LDD). The first bottom gate 810 and the second bottom gate 820 are used to input a positive voltage (VGH) signal or a negative voltage (VGL) signal, so that the electrons of the lightly doped region (LDD) are concentrated in the front channel region (P1+) or the back channel region (P2+).

[0056] In this embodiment, the transistor type is Nmos TFT, and the PH3 doped in the LDD region is intended to suppress the hot carrier effect and reduce the leakage current. However, in the actual operation process, LDD cannot achieve this purpose, so by adding a second gate layer (bottom gate) and a bottom gate insulating layer 900, the timing signal of the second gate layer (bottom gate) can be adjusted, as follows:

[0057] like Figure 3 , Figure 3 It is a schematic diagram of electron transfer in the lightly doped region (LDD) when a negative voltage (VGL) signal is applied to the second gate layer of the array substrate 100 in the present application; when a positive voltage (VGH) signal is input to the first gate layer 700 (top gate), especially when Vgs>Vth, the channel electrons are all in the front channel due to the principle of opposites attracting each other, and the TFT is gradually turned on. At this time, the bottom gate can give a VGL signal, and by using like charges repelling each other, the electrons in the LDD region will be the same as the channel region, so that all electrons are in the front channel, the LDD resistance is reduced, and the on-state current (I on) is instantly increased.

[0058] On the contrary, if Figure 4 , Figure 4 It is a schematic diagram of electron transfer in the lightly doped region (LDD) when a positive voltage (VGH) signal is applied to the second gate layer of the array substrate 100 in the present application; when the top gate is at the VGL signal, the channel electrons are all in the back channel due to the principle of like charges repelling each other, and the TFT is gradually closed. At this time, the bottom gate can give a VGH signal, and using the principle of opposite charges attracting each other, the electrons in the LDD region will be the same as the channel region, so that all electrons are in the back channel, the LDD resistance is increased, and the off-state current (I off) is instantly reduced.

[0059] In a second aspect, a driving method is provided for driving the array substrate 100 of the first aspect, such as Figure 5 , Figure 5 It is a schematic diagram of the process steps of a specific implementation of the driving method in this application; including:

[0060] Step 10, input a positive voltage (VGH) signal to the first gate layer 700, and input a negative voltage (VGL) signal to the second gate layer, so that the on-state current (I on) is instantly increased and the transistor is turned on; Step 20, input a negative voltage (VGL) signal to the first gate layer 700, and input a positive voltage (VGH) signal to the second gate layer, so that the on-state current (I on) is instantly reduced and the transistor is turned off.

[0061] Preferably, if Figure 6 , Figure 6 yes Figure 5 A schematic diagram of the process steps of a specific implementation of step 10 in the figure; step 10 includes: step 11, obtaining a gate positive voltage (VGH) and a threshold voltage (Vth); step 12, when the gate positive voltage (VGH) is greater than the threshold voltage (Vth), inputting a negative voltage (VGL) signal to the first bottom gate 810 and the second bottom gate 820 respectively, so that the electrons in the channel region are concentrated in the front channel region (P1+).

[0062] Preferably, if Figure 7 , Figure 7 yes Figure 5 Schematic diagram of a specific implementation of step 20 in the process. Step 20 includes: step 21, obtaining a gate voltage; step 22, when the gate voltage is a negative voltage (VGL), inputting a positive voltage (VGH) signal to the first bottom gate 810 and the second bottom gate 820 respectively, so that the electrons in the channel region are concentrated in the back channel region (P2+).

[0063] In a third aspect, a low-temperature polysilicon liquid crystal display panel comprises the array substrate of the first aspect and is driven by the driving method of the second aspect.

[0064] An array substrate, a driving method and a low-temperature polysilicon liquid crystal display panel in the present invention are implemented. By setting a second gate layer and a bottom gate insulating layer 900 below the polysilicon layer 400, when the transistor is turned on, the electrons in the channel region are concentrated in the front channel region (P1+), and the on-state current (I on) is instantly increased. When the transistor is turned off, the electrons in the channel region are concentrated in the back channel region (P2+), and the off-state current (I on) is instantly reduced, thereby greatly reducing the leakage current of the transistor.

[0065] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. An array substrate, characterized in that: include: A substrate, a light shielding layer, a buffer layer, a polysilicon layer, a top gate insulating layer, a first gate layer, an interlayer insulating layer, a source electrode and a drain electrode; Among them, it also includes a second gate layer and a bottom gate insulating layer; The light-shielding layer is made on the substrate, the buffer layer is made on the buffer layer, the second gate layer and the bottom gate insulating layer are made on the buffer layer, and the second gate layer is made in the bottom gate insulating layer and is arranged corresponding to the lightly doped area of ​​the polysilicon layer, the polysilicon layer is made on the bottom gate insulating layer, the top gate insulating layer is made on the polysilicon layer, the first gate layer and the interlayer insulating layer are made on the top gate insulating layer, and the first gate layer is made in the interlayer insulating layer, and the source and the drain are respectively connected to the two ends of the polysilicon layer through vias.

2. The array substrate according to claim 1, characterized in that: The polysilicon layer comprises: Two heavily doped regions, two lightly doped regions and Channel area; The two lightly doped regions are respectively formed on both sides of the channel region, and the two heavily doped regions are respectively formed outside the lightly doped regions.

3. The array substrate according to claim 2, characterized in that: The second gate layer at least comprises: Independent first bottom gate and second bottom gate; The first bottom gate and the second bottom gate are respectively arranged corresponding to the two lightly doped regions.

4. The array substrate according to claim 3, characterized in that: The channel region comprises: anterior channel region and dorsal channel region; The front channel region and the back channel region are respectively close to the top gate insulating layer and the bottom gate insulating layer.

5. The array substrate according to claim 4, characterized in that: The first bottom gate and the second bottom gate are used to input a positive voltage signal or a negative voltage signal, so that the electrons in the lightly doped region are concentrated in the front channel region or the back channel region.

6. The array substrate according to claim 5, characterized in that: The source electrode is connected to the heavily doped region at one end of the polysilicon layer through a via hole, and the drain electrode is connected to the heavily doped region at the other end of the polysilicon layer through a via hole.

7. A driving method for driving the array substrate according to any one of claims 1 to 6, characterized in that: include: Step 10: input a positive voltage signal to the first gate layer and input a negative voltage signal to the second gate layer, so that the on-state current is instantly increased and the transistor is turned on; Step 20: input a negative voltage signal to the first gate layer and input a positive voltage signal to the second gate layer, so that the on-state current is instantly reduced and the transistor is turned off.

8. The driving method according to claim 7, characterized in that: The step 10 comprises: Step 11, obtaining the gate positive voltage and threshold voltage; Step 12: When the gate positive voltage is greater than the threshold voltage, negative voltage signals are input to the first bottom gate and the second bottom gate respectively, so that the electrons in the channel region are concentrated in the front channel region.

9. The driving method according to claim 7, characterized in that: The step 20 comprises: Step 21, obtaining a negative gate voltage; Step 22: When the gate voltage is a negative voltage, a positive voltage signal is input to the first bottom gate and the second bottom gate respectively, so that the electrons in the channel region are concentrated in the back channel region.

10. A low temperature polysilicon liquid crystal display panel, characterized in that: It comprises the array substrate according to any one of claims 1 to 6 and is driven by the driving method according to any one of claims 7 to 9.

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